TWI416692B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI416692B
TWI416692B TW098115087A TW98115087A TWI416692B TW I416692 B TWI416692 B TW I416692B TW 098115087 A TW098115087 A TW 098115087A TW 98115087 A TW98115087 A TW 98115087A TW I416692 B TWI416692 B TW I416692B
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Taiwan
Prior art keywords
layer
semiconductor substrate
isolation layer
semiconductor device
conductive member
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TW098115087A
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English (en)
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TW201023331A (en
Inventor
Hung Pin Chang
Kuo Ching Hsu
Chen Shien Chen
Wen Chih Chiou
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201023331A publication Critical patent/TW201023331A/zh
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Publication of TWI416692B publication Critical patent/TWI416692B/zh

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Description

半導體裝置及其製造方法
本發明係有關於一種積體電路，特別是有關於一種用於半導體晶片的凸塊(bump)結構，其具有用於疊置晶片的矽通孔電極(through-silicon via,TSV)。
自積體電路的發明創造以來，由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進，使半導體業持續不斷的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
這些集積度的改進實質上是朝二維(two-dimensional,2D)方面的，因為積體部件所佔的體積實際上位於半導體晶圓的表面。儘管微影(lithography)技術的精進為2D積體電路製作帶來相當大的助益，二維空間所能擁有的密度還是有其物理限制。這些限制之一在於製作這些部件所需的最小尺寸。再者，當更多的裝置放入一晶片中，需具有更複雜的電路設計。
為了進一步增加積體電路密度，已開始研究三維(3D)積體電路(three-dimensional integrated circuit,3DIC)。在典型的3DIC製程中，二個晶片彼此接合，且在每一晶片與基底上的接觸墊之間形成電性連接。例如，在彼此上方接合二個晶片。疊置的晶片接著與一承載基底(carrier substrate)接合，而接線將每一晶片上的接觸墊電性耦接至承載基底上的接觸墊。然而，上述做法需要一個大於晶片的承載基底來進行打線製程(wire bonding)。
近來，已開始注意所謂的矽通孔電極(TSV)。一般而言，矽通孔電極是透過蝕刻在基底中形成一垂直通孔並於其中填入導電材料而成，例如銅。對基底背側進行薄化，以露出TSV，而另一晶片則與露出的TSV接合，進而形成堆疊晶片封裝(stacked die package)。若基底使用不同技術或腳位(pin-out)來與另一晶片/晶圓接合，則需要一重佈(redistribution)線層。
由於基底在薄化及接合之前是接合至一臨時載板，因此熱預算通常會是個考量點。為了能夠進行低溫接合製程，會使用焊球將另一基底接合至矽通孔電極。然而，由於需要一重佈線層，必須進行額外的膜層製作來形成重佈線層，而對於在熱預算內形成重佈線層來說是相當困難的。
因此，有必要尋求一種新的接合TSV的結構及方法。
本發明一實施例提供一種半導體裝置。半導體裝置具有一半導體基底，其具有複數矽通孔電極延伸穿過並突出於半導體基底的一背側。一第一隔離層，位於相鄰的矽通孔電極之間半導體基底的背側，且未延伸超過突出的矽通孔電極。複數導電部件具有漸細側壁且分別電性耦接至矽通孔電極。一第二隔離層，位於第一隔離層上。在其他實施例中，導電部件包括一重佈線且具有漸細側壁。重佈線可位於第一隔離層與第二隔離層之間。
本發明另一實施例提供一種半導體裝置之製造方法。提供一半導體基底，具有一矽通孔電極自半導體基底的一第一側延伸於其內。在半導體基底的一第二側露出矽通孔電極。在半導體基底的第二側形成一第一隔離層，且使矽通孔電極露出。在矽通孔電極上形成具有漸細側壁的一導電部件。在第一隔離層上形成材料不同於第一隔離層的一第二隔離層。在導電部件上形成一接觸阻障層。導電部件可包括一重佈線。
本發明又另一實施例提供一種半導體裝置之製造方法。提供一第一半導體基底，其具有複數矽通孔電極自第一半導體基底的一電路側延伸至第一半導體基底的一背側以及位於背側上的每一矽通孔電極上具有漸細側壁的一導電接墊。第一半導體基底的背側具有一第一隔離層以及位於第一隔離層上的一第二隔離層。提供一第二半導體基底，其具有複數上接觸點。將第一半導體基底接合至第二半導體基底，使第二半導體基底的每一上接觸點電性耦接至第一半導體基底上對應的導電接墊。
以下說明本發明實施例之製作與使用。然而，必須了解的是本發明提供許多適當的實施例的發明概念，可實施於不同的特定背景。述及的特定實施例僅用於說明以特定的方法來製作及使用本發明，而並非用以侷限本發明的範圍。
本發明實施例示有關於使用具有矽通孔電極的基底的金屬焊墊。以下所說明的實施例係關於金屬焊墊與重佈線層的整合，使其能夠同時製造重佈線層與金屬焊墊。再者，金屬焊墊較佳為具有漸細(tapered)側壁，藉以在晶圓及/或晶片堆疊製程中提供較大的接合界面。
第1至14圖使用於三維積體電路(3DIC)或疊置晶片中具有凸塊(bump)結構及/或重佈線層的晶片的局部製造過程剖面示意圖。而在本發明各個實施例中，相同的部件係使用相同的標號。
請參照第1圖，一半導體基底100具有電路112形成於上。半導體基底100可包括摻雜或未摻雜的矽塊材或是絕緣層上覆半導體(semiconductor-on-insulator,SOI)基底的主動(active)層。一般而言，SOI基底包括形成於一絕緣層上的一半導體材料層，例如矽。絕緣層可為埋入式氧化(buried oxide,BOX)層或是氧化矽層。絕緣層形成於一基底上，通常為矽基底或玻璃基底。另外也可使用其他基底，例如多層或漸層(gradient)基底。
形成於半導體基底110上的電路112可為適用於特定應用的任一類型電路。在一實施例中，電路112包括形成於基底上的電子裝置，而電子裝置上具有一層或多層的介電層。金屬層可形成於介電層之間，以作為電子裝置之間傳送電子信號的路徑。電子裝置也可形成於一層或多層的介電層內。
舉例而言，電路112可包括各個不同的N型金屬氧化物半導體(N-type metal-oxide semiconductor,NMOS)裝置及/或P型金屬氧化物半導體(PMOS)裝置，例如電晶體、電容、電阻、二極體、光電二極體、熔絲等等，其相互連接以實施單一或多種功能。這些功能可包括記憶結構、製程結構、感測器、放大器、電源分配、輸入/輸出電路等等。所屬技術領域中具有通常知識者可以理解上述範例說明僅在於進一步解釋本發明之應用而並非用以侷限本發明。對於特定應用來說，也可使用其他電路。
第1圖亦繪示出一蝕刻終止層114及一層間介電(inter-layer dielectric,ILD)層116。蝕刻終止層114較佳由一介電材料所構成且與相鄰的膜層，例如下方的半導體基底110及上方的ILD層116，具有不同的蝕刻選擇比。在一實施例中，蝕刻終止層114可由SiN、SiCN、SiCO、CN、或其組合等等所構成，且可藉由化學氣相沉積(chemical vapor deposition,CVD)或電將輔助化學氣相沉積(plasma-enhanced CVD,PECVD)技術而形成。
ILD層116可由低介電常數(low-k)介電材料所形成，例如氧化矽、磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG)、氟矽玻璃(fluorinated silicate glass,FSG)、SiOx Cy 、旋塗玻璃(spin-on glass,SOG)、旋塗高分子、碳化矽材料、其化合物、其複合材料、或其組合等等，並藉由適當的習知方法製造而成，例如旋塗法、CVD或PECVD。須注意的是蝕刻終止層114及ILD層116可各自包括複數介電層，其中相鄰的介電層之間可具有或不具有蝕刻終止層。
接觸窗118貫穿ILD層116以提供電路112電性接觸之用。接觸窗118的製作可藉由使用微影技術在ILD層116上沉積及圖案化一光阻材料而露出部分的ILD層116來形成接觸窗118。可使用蝕刻製程，例如異向性(anisotropic)乾蝕刻製程，在ILD層116內形成開口。最好在開口內沿表面形成擴散阻障層及/或黏著層(未繪示)，並填入導電材料。擴散阻障層可包括一層或多層的TaN、Ta、TiN、Ti、或CoW等等，且導電材料可包括銅、鎢、鋁、銀、或其組合，藉以形成第1圖所示的接觸窗118。
在ILD層116上形成一層或多層的金屬層間介電(inter-metal dielectric,IMD)層120及配置的金屬化層(未繪示)。一般而言，IMD層120及所配置的金屬化層係用於彼此電路的連接，並提供外部電性連接之用。IMD層120較佳由low-k介電材料所構成，例如由PECVD或是高密度電漿化學氣相沉積(high-density plasma CVD,HDPCVD)技術所形成的氟矽玻璃(FSG)，IMD層120也可包括中間蝕刻終止層，其與蝕刻終止層114相似。在最上層的IMD層中具有上金屬接點122，以提供外部電性連接之用。
第1圖亦繪示出矽通孔電極(through-silicon via,TSV)124。矽通孔電極124可由任何合適的方法所形成。舉例而言，在形成ILD層116之前，藉由單一或多重蝕刻製程、鑽孔、及雷射技術等等，形成延伸於半導體基底110內的開口。最好在開口內沿表面形成一襯層，如作為隔離層的襯層126，且在開口內填入一導電材料。襯層126較佳由一層或多層的SiN、氧化物、或高分子等等所構成，而導電材料較佳為包括銅、鎢、鋁、銀、或其組合等等，藉以形成矽通孔電極124。另外也可使用其他材料，包括導電擴散阻障層，如TaN、Ta、TiN、Ti、或CoW等等。
須注意的是圖式中矽通孔電極124是從半導體基底110的上表面延伸於其內，此處僅作為說明之目的，然而也可使用其他的配置。舉例而言，在另一實施例中，矽通孔電極124可從ILD層116或是其中一IMD層120的上表面延伸。舉例而言，在一實施例中，矽通孔電極124的製造可在形成接觸窗118之後，藉由單一或多重蝕刻製程、鑽孔、或雷射技術等等，形成延伸於半導體基底110內的開口。最好在開口內沿表面形成一襯層，如作為隔離層的襯層126，且在開口內填入如之前所述的導電材料。
在上金屬接點122上形成導電凸塊128，例如由Cu、W、CuSn、AuSn、InAu、或PbSn等等所構成的金屬凸塊，且利用一黏著層132使一承載基底130貼附於IMD層120的上表面。一般而言，承載基底130係提供後續製程步驟期間物理或結構上的支撐之用。藉由此方式可降低或防止半導體基底110的損害。
承載基底130可包括玻璃、氧化矽、或氧化鋁等等。黏著層132可為任何適合的黏著材料，例如UV膠，其接觸到紫外(UV)光後會失去黏性。承載基底130的厚度較佳在幾密爾(mil)到幾十密爾的範圍。
第2圖係繪示出根據本發明實施例之對半導體基底110的背側進行薄化(thinning)製程，以露出矽通孔電極124/襯層126。可使用機械研磨製程、化學機械研磨(chemical mechanical polishing,CMP)製程、蝕刻製程及/或其組合來進行薄化製程。舉例而言，可進行初步平坦化製程，如研磨或CMP，以初步露出矽通孔電極124。之後，進行濕式或乾式蝕刻，其對於襯層126的材料與半導體基底110的材料之間具有高蝕刻選擇比而使半導體基底110向下凹陷，因而矽通孔電極124及襯層126突出於半導體基底110的下側，如第2圖所示。在一實施例中，矽通孔電極124由銅所構成，且襯層126由TaN所構成。而可使用HBr/O2 、HBr/Cl2 /O2 、SF6 /Cl2 、或SF6 等電漿來進行乾蝕刻而使半導體基底110向下凹陷。矽通孔電極124及襯層126所露出的長度在次微米(sub-μm)至幾微米的範圍。
第3圖係繪示出根據本發明實施例之在半導體基底110(半導體基底110表面上可形成一原生氧化層(native oxide))的背側形成一第一隔離層310。在一實施例中，第一隔離層310為介電材料，例如SiN、氧化物、SiC、SiON、或高分子等等，且可藉由旋塗法、印刷、或CVD等方式而形成。第一隔離層310較佳為藉由低溫製程而形成，如使用溫度小於250℃的PECVD製程，以防止接合用的黏著層劣化，而確保整合製程始終的機械強度。第一隔離層310的厚度最好足以覆蓋露出的矽通孔電極124。
取決於形成第一隔離層310所使用的製程，可能需要進行平坦化製程。比較特別的是在一些沉積方法中會形成一平整表面，如旋塗法。然而，在其他的方法中則會形成一順應層，如CVD，因而需進行平坦化製程，如研磨或CMP，以形成一平整表面，如第3圖所示。
第4圖係繪示出根據本發明實施例之二次露出矽通孔電極124。可使用機械研磨製程、CMP製程、蝕刻製程及/或其組合來進行薄化製程。舉例而言，可進行初步平坦化製程，如研磨或CMP，以初步露出矽通孔電極124。之後，進行濕式或乾式蝕刻，其對於矽通孔電極124及襯層126的材料與第一隔離層310的材料之間具有高蝕刻選擇比而使第一隔離層310向下凹陷，因而使矽通孔電極124突出於第一隔離層310的下側，如第4圖所示。在一實施例中，矽通孔電極124由銅所構成，且第一隔離層310由二氧化矽所構成。可使用氫氟酸來進行濕蝕刻或使用乾蝕刻，而使第一隔離層310向下凹陷。另外也可使用其他的製程及材料。矽通孔電極124所露出的長度在次微米(sub-μm)至幾微米的範圍。
除了向下凹陷第一隔離層310之外，第4圖也同時繪示出自矽通孔電極124所露出的部分去除襯層126。
請參照第5圖，在第一隔離層310的表面上及矽通孔電極124所露出的部分上順應性沉積一晶種層510。晶種層510係由導電材料所構成的薄膜層，用以在後續製程步驟期間輔助形成一厚膜層。在一實施例中，可藉由使用CVD或物理氣相沉積(physical vapor deposition,PVD)技術來沉積一薄導電層，例如Cu、Ti、Ta、TiN、或TaN等薄膜層而形成晶種層510。舉例而言，藉由PVD製程來沉積Ti層，以形成一阻障層，並藉由PVD製程來沉積Cu層，以形成一晶種層。
第6圖係繪示出根據本發明實施例之在晶種層510上形成一第一罩幕圖案層610。第一罩幕圖案層610係作為後續製程步驟中用於形成導電接墊的模具。第一罩幕圖案層610可為圖案化的光阻層或硬式罩幕(hard mask)等等。在一實施例中，光阻材料的厚度約在次微米至幾微米的範圍，且經由圖案化而在矽通孔電極124上方形成開口612。
須注意的是第6圖的實施例中較佳為利用一內凹(re-entrant)輪廓，使開口612在沿著晶種層510的開口612的底部寬於開口612的頂部。可藉由任何適宜的技術來形成內凹輪廓，例如使用具有不同圖案化特性及可一次或多次曝光的多重光阻層、擴散技術、或是影像反轉製程等等。然而，在其他實施例中，第一罩幕圖案層610可利用一漸細輪廓，使開口612在沿著晶種層510的開口612的底部窄於開口612的頂部。
之後，請參照第7圖，導電部件710形成於開口612(繪示於第6圖)內。導電部件710較佳為金屬，例如銅、鎢、或其他導電金屬，且可藉由電鍍或無電電鍍等製程而形成。在一實施例中，係採用電鍍製程，其中晶圓沒入(submerged)或浸入(immersed)於電鍍溶液中。晶圓表面電性連接至外部直流(DC)電源供應器的負電極側，使晶圓在電鍍製程中作為陰極。一固體陽極，例如銅陽極，也浸入於溶液中且連接至電源供應器的正電極側。原子自陽極分解至溶液中，而陰極，例如晶圓，則自溶液中獲取原子，以在晶圓中露出的導電區域進行電鍍，例如開口612內所露出的晶種層510部分。
須注意的是導電部件710可為接觸墊及/或重佈線。請參照第14圖，其為第1至13圖中實施例的平面示意圖，第7圖中左側的導電部件710為一接觸墊，而第7圖中右側的導電部件710為一接觸墊及一重佈線。重佈線容許電性連接至位於TSV以外位置的另一裝置，例如晶片、晶圓或是封裝基底等等。此對於TSV、基底上的電路、及腳位(pin-out)的放置具有較大的彈性及較高的自主性。
請參照第8圖，其繪示出根據本發明實施例之去除第一罩幕圖案層610(繪示於第6及7圖)。在一實施例中，第一罩幕圖案層610為一光阻罩幕，且可藉由電漿灰化(ashing)或濕式剝除(wet strip)製程來去除第一罩幕圖案層610。較佳的電漿灰化製程係使用O2 ，舉例而言，其流量約在1000sccm至2000sccm的範圍。製程壓力約在300mTorr至600mTorr的範圍。製程功率約在500Watts至2000Watts的範圍。製程溫度約在80℃至200℃的範圍。另外，進行電漿灰化製程之後也可浸入硫酸(H2 SO4 )溶液中，清洗晶圓並去除殘留的光阻材料。
第9圖係繪示出去除晶種層510所露出的部分。舉例而言，晶種層510所露出的部分可藉由濕式蝕刻製程來去除。
第10圖係繪示出根據本發明實施例之形成一第二隔離層1010。第二隔離層1010的形成方法及材料可使用相似於第一隔離層310的形成方法及材料。然而，使用於形成第二隔離層1010的材料較佳為與使用於第一隔離層310的材料之間具有高蝕刻選擇比。在上述方法中，第一隔離層310(及導電部件710)可作為後續製程步驟中圖案化第二隔離層1010的蝕刻終止層。第二隔離層1010的厚度較佳在2000埃()至8000埃的範圍。以下所要說明的是圖案化第二隔離層1010，以隔離部分的重佈線，同時露出接觸墊的所在位置。
第11圖係繪示出根據本發明實施例之形成一第二罩幕圖案層1110。第二罩幕圖案層1110的材料可使用相似於第一罩幕圖案層610的材料，例如光阻或是硬式罩幕材料，而形成方法可使用相似於第一罩幕圖案層610的形成方法。然而，須注意的是第一罩幕圖案層610所採用的技術在於形成一內凹圖案，而第二罩幕圖案層1110則是具有垂直圖案。因此，任何適合的微影技術都可用來形成第二罩幕圖案層1110。
第12圖係繪示出根據本發明實施例之圖案化第二隔離層1010以及去除第二罩幕圖案層1110。舉例而言，在一實施例中，第二隔離層1010由氮化矽所構成，而第一隔離層310則由氧化矽所構成。第二隔離層1010可藉由乾式蝕刻製程來進行圖案化，其在第二隔離層1010的氮化矽與第一隔離層310的氧化矽之間具有高蝕刻選擇比。
在圖案化第二隔離層1010之後，可去除第二罩幕圖案層1110，如第12圖所示。舉例而言，第二罩幕圖案層1110可藉由電漿灰化製程或是濕式剝除製程將其去除，如上述關於第8圖的說明。另外，去除第二罩幕圖案層1110之後也可進行一清潔步驟，例如浸入硫酸溶液中，以去除表面上任何的污染物。
第13圖係繪示出根據本發明實施例之形成一接觸阻障層1310。接觸阻障層1310係作為與外部裝置形成電性連接的導電接觸點，例如另一晶片、晶圓、電路板、或封裝板等等。接觸阻障層1310與矽通孔電極124作電性接觸，再依次與形成於基底上的電路(如，電路112)或是另一外部裝置(如，另一晶片、晶圓、電路板、或封裝板等等)作電性接觸。
在一實施例中，接觸阻障層1310由金屬或金屬合金所構成，例如Ni、AuSu、或Au等等，並採用無電電鍍(electroless plating)技術。然而，也可採用其他的方法及技術。接觸阻障層1310的材料選擇上必須能夠加強導電部件710與外部裝置上的接觸部件之間的黏著性。須注意的是導電部件710與接觸阻障層1310共同構成接觸墊，其上可連接其他裝置，例如晶片、晶圓、或基底等等。
第14圖係繪示出根據本發明實施例之排置接觸墊1410與重佈線1412的平面示意圖，而第1至13圖係沿第14圖中A-A線的剖面示意圖。第二隔離層1010係作為保護(passivation)層並覆蓋露出接觸墊1410(如，接觸阻障層1310及其下方的導電部件710)以外的基底背側。第二隔離層1010形成於重佈線1412(以虛線繪示之)上方。
可以理解的是上述實施例容許可同時形成接觸電及重佈線。重佈線的使用容許在不同腳位及技術中使用相同的設計。具有漸細側壁的導電凸塊也在晶圓及/或晶片堆疊製程中提供較大的接合界面。
第15至17圖係繪示出根據本發明實施例之將上述關於第1至14圖的結構接合至另一結構。特別的是一基底1510，其具有上金屬接點1512及連接部件1514。舉例而言，連接部件1514可為錫球(solder ball)。藉由對準連接部件1514與接觸墊1410以及施加壓力及/或熱，以將基底1510貼附於半導體基底110，使連接部件1514黏附於接觸阻障層1310而形成電性連接，如第16圖所示。由於接觸阻障層1310與導電部件710具有漸細外型，因此可使接合界面具有較大的潤濕(wetting)表面，進而形成較佳的電性連接以及提供額外結構上的支撐。
請參照第17圖，可去除臨時的承載基板130，使半導體基底110的電路側上的導電凸塊128可接合至另一晶片、晶圓、基底、或板子等等。之後，可進行適用於特定應用的其他後段(back-end-of-line)製程。舉例而言，在堆疊的晶片之間注入填充材料、形成封膠(encapsulant)、及進行切割(singulation)製程以形成各自的堆疊晶片封裝等等。然而，須注意的是本發明實施例可使用於諸多不同的情況。舉例而言，本發明實施例可使用於晶片對晶片(die-to-die)接合結構配置、晶片對晶圓(die-to-wafer)接合結構配置、或晶圓對晶圓(wafer-to-wafer)接合結構配置。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
110．．．半導體基底
112．．．電路
114．．．蝕刻終止層
116．．．內層介電層
118．．．接觸窗
120．．．金屬層間介電層
122、1512．．．上金屬接點
124．．．矽通孔電極
126．．．襯層
128．．．導電凸塊
130．．．承載基底
310．．．第一隔離層
510．．．晶種層
610．．．第一罩幕圖案層
612．．．開口
710．．．導電部件
1010．．．第二隔離層
1110．．．第二罩幕圖案層
1310．．．接觸阻障層
1410．．．接觸墊
1412．．．重佈線
1510．．．基底
1514．．．連接部件
第1至13圖係繪示出根據本發明實施例之具有用於疊置晶片的凸塊結構的半導體裝置局部製造過程剖面示意圖。
第14圖係繪示出根據本發明實施例之腳位配置平面示意圖。
第15至17圖係繪示出根據本發明另一實施例之疊置晶片的局部製造過程剖面示意圖。
110．．．半導體基底
112．．．電路
114．．．蝕刻終止層
116．．．內層介電層
118．．．接觸窗
120．．．金屬層間介電層
122、1512．．．上金屬接點
124．．．矽通孔電極
126．．．襯層
128．．．導電凸塊
310．．．第一隔離層
510．．．晶種層
710．．．導電部件
1010．．．第二隔離層
1310．．．接觸阻障層
1510．．．基底
1514．．．連接部件

Claims (20)

  1. 一種半導體裝置，包括：一第一半導體基底；複數矽通孔電極，延伸穿過該第一半導體基底，且該等矽通孔電極突出於該第一半導體基底的一背側；一第一隔離層，位於相鄰的該等矽通孔電極之間該第一半導體基底的該背側，且該第一隔離層未延伸超過該等突出的矽通孔電極；一導電部件，具有一漸細側壁且電性耦接至該等矽通孔電極中的至少一個；以及一第二隔離層，位於該第一隔離層上以及一部分的該導電部件上。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該導電部件包括一重佈線。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該第二隔離層位於至少一部分的該重佈線上。
  4. 如申請專利範圍第2項所述之半導體裝置，其中該第一隔離層的材料不同於該第二隔離層的材料。
  5. 如申請專利範圍第1項所述之半導體裝置，更包括一接觸阻障層，位於至少一部分的該導電部件上。
  6. 如申請專利範圍第1項所述之半導體裝置，更包括一襯層，沿著該等矽通孔電極的側壁。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該襯層未延伸超過該第一隔離層的一上表面。
  8. 如申請專利範圍第1項所述之半導體裝置，更包 括：一接觸阻障層，位於該導電部件上；一第二半導體基底，具有一上金屬接點；以及一導電連接部件，夾設於該接觸阻障層與該上金屬接點之間。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該導電連接部件向下延伸至該導電部件的該漸細側壁。
  10. 一種半導體裝置之製造方法，包括：提供一第一半導體基底，該第一半導體基底具有一矽通孔電極自該第一半導體基底的一第一側延伸於其內，在該第一半導體基底的一第二側露出該矽通孔電極；沿著該第一半導體基底的該第二側形成一第一隔離層，且使該矽通孔電極露出；在該矽通孔電極上形成具有一漸細側壁的一導電部件；在該第一隔離層上形成一第二隔離層，其中該第一隔離層的材料不同於該第二隔離層的材料；以及在該導電部件的至少一部分上形成一接觸阻障層。
  11. 如申請專利範圍第10項所述之半導體裝置之製造方法，其中形成該導電部件包括使用具有凹口的罩幕圖案層作為形成該導電部件的模具。
  12. 如申請專利範圍第10項所述之半導體裝置之製造方法，其中露出該矽通孔電極包括蝕刻該第一半導體 基底至低於該矽通孔電極的一表面，使該矽通孔電極突出於該第一半導體基底。
  13. 如申請專利範圍第10項所述之半導體裝置之製造方法，其中形成該第一隔離層包括：形成一絕緣材料層；對該絕緣材料層進行平坦化；以及蝕刻該絕緣材料層，以露出該矽通孔電極。
  14. 如申請專利範圍第10項所述之半導體裝置之製造方法，其中該矽通孔電極突出於該第一隔離層。
  15. 如申請專利範圍第10項所述之半導體裝置之製造方法，其中形成該導電部件包括：在該第一隔離層及該矽通孔電極上方形成一晶種層；在該晶種層上形成一罩幕圖案層，該罩幕圖案層具有複數凹口而露出位於該矽通孔電極上方的該晶種層；在該晶種層的露出部分上形成一金屬接墊；去除該罩幕圖案層；以及去除未被該金屬接墊覆蓋的該晶種層。
  16. 如申請專利範圍第10項所述之半導體裝置之製造方法，更包括自該矽通孔電極露出的部分去除一襯層。
  17. 一種半導體裝置之製造方法，包括：提供一第一半導體基底，其具有複數矽通孔電極自該第一半導體基底的一電路側延伸至該第一半導體基底的一背側以及位於該背側上的每一矽通孔電極上具有漸細側壁的一導電接墊，且該第一半導體基底的該背側具 有一第一隔離層以及位於該第一隔離層上的一第二隔離層；提供一第二半導體基底，其具有複數上接觸點；以及將該第一半導體基底接合至該第二半導體基底，使該第二半導體基底的每一上接觸點電性耦接至該第一半導體基底上對應的該等導電接墊。
  18. 如申請專利範圍第17項所述之半導體裝置之製造方法，其中該等導電接墊中至少有一些包括一重佈線。
  19. 如申請專利範圍第18項所述之半導體裝置之製造方法，其中該重佈線位於該第一隔離層與該第二隔離層之間。
  20. 如申請專利範圍第17項所述之半導體裝置之製造方法，其中至少有透過一金屬凸塊來進行該第一半導體基底與該第二半導體基底的接合。
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