TWI387006B - 半導體裝置中之漏電性能的改善及電遷移最小化的方法 - Google Patents

半導體裝置中之漏電性能的改善及電遷移最小化的方法 Download PDF

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TWI387006B
TWI387006B TW097137287A TW97137287A TWI387006B TW I387006 B TWI387006 B TW I387006B TW 097137287 A TW097137287 A TW 097137287A TW 97137287 A TW97137287 A TW 97137287A TW I387006 B TWI387006 B TW I387006B
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Noel Russell
Steven R Sherman
John J Hautala
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Tel Epion Inc
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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Description

半導體裝置中之漏電性能的改善及電遷移最小化的方法
本發明一般係關於用以改善半導體積體電路的雙鑲嵌整合結構的方法與處理系統。
半導體產業透過利用尺寸微縮而成功地將更具成本效益的晶片帶入市場。然而，儘管尺寸縮小適用於裝置或前端半導體處理，裝置線路並不適於尺寸縮小且導致惡化的互連電阻與/或電容。為減輕此問題，產業已傾向使用如銅(Cu)之較低阻值的導體，也引進較低介電常數(lower-k，k為介電常數)的絕緣體以降低在鑲嵌互連結構中的電容。近期在超低介電常數(ultra-low-k，ULK，k<2.5)範圍中所發展的絕緣體常具有大量的多孔性(例如：30-50%)的特性。這些材料係極易碎且因其易受來自其它來源之污染的影響而難以整合。
在雙鑲嵌結構(dual-damascene(DD)structure)中，單一金屬沉積步驟係用以同時地形成Cu金屬線路與穿孔。藉由填塞在電介質層或基板中如阱、穿孔，或其它互連結構的凹紋而形成此Cu金屬線路與穿孔。填塞之後，藉由化學機械研磨法(CMP process)移除沉積於此凹紋以外的過剩Cu金屬，從而形成帶有金屬互連鑲嵌的平坦結構。
一種在工作件的傳導路徑中使電遷移減至最小量與在工作件的電介質區域中吸除金屬污染物的方法。此方法包括使工作件的頂端表面平坦化，以形成帶有複數個傳導路徑與複數個電介質區域的實質平坦表面、使工作件的頂端表面裸露於磷源，以在此複數個傳導路徑與此複數個電介質區域中形成摻磷層，及在摻磷層上方形成障壁層。
普遍需要改善包含銅與電介質特徵部的裝置之信賴性，特別是，傳導路徑與介於傳導路徑之間經由平坦化所裸露的電介質區域。一種改善裝置信賴性的方法為吸除出現在傳導路徑之間的金屬不純物，此可導致兩線間崩潰之邊限及漏電性能被改善。可藉由裸露表面於含磷之源且使用一或多種方法在如銅線的傳導路徑之間吸除金屬不純物，例如裸露表面於含磷(P)氣體或蒸氣之分壓時的熱處理、電漿處理、直接或經由覆蓋層而離子佈植入此表面，與/或使用氣體團簇離子束(GCIB)的注入(infusion)處理。此外，可藉由在傳導路徑中加入P來降低傳導路徑的電遷移而改善信賴性，從而把因傳導電子與擴散金屬原子之間的動量轉換所引起的傳導材料的運移減至最小量。
在傳導路徑與介於傳導路徑之間經由平坦化所裸露的電介質區域中加入摻磷層而降低電遷移，及提供改善的兩線間崩潰之邊限與漏電性能，導致如裝置或電路特性之改善的輸出參數。
參照圖1，GCIB處理設備100包括被分為三個連通腔的真空槽102，包括源腔104、游離/加速腔106，與處理腔108。藉由真空泵浦系統146a、146b與146c使腔室分別地抽至適當的操作壓力。加壓下，氣體儲存瓶111所儲的可壓縮源氣112(例如：氬氣或N2 )經由氣體節流閥113與氣體進給管114而送入滯留腔116，且經由適當形狀的噴嘴110而噴射至實質上較低壓的真空中。產生了超音氣體噴柱118。可壓縮源氣112可為一大氣壓下在溫度大於30度凱式溫度(Kelvin)時凝結的氣體，反之非可壓縮源氣可為一大氣壓下在溫度低於或等於30度凱式溫度時凝結的氣體。適當的可壓縮源氣112包括，但非必然限於膦(phosphine)、氬氣、氮氣、二氧化碳、氧氣，與其他氣體及其混合氣體。適當的非可壓縮源氣包括，但非必然限於氦氣、氖氣、氫氣，與其混合氣體。
因噴柱的膨脹而造成的冷卻引起此氣體噴柱118之一部分凝聚成團簇，每一個團簇包括數個至數千弱鍵結原子或分子。氣體分離器孔120自團簇噴柱中部份地分離出未凝聚成團簇噴柱的氣體分子，而把在如此高的壓力係不利的下游區域(例如：離子器122、高壓電極126，與處理腔108)中的壓力減至最少量。
形成包含氣體團簇的超音氣體噴柱118後，在離子器122中游離此團簇。此離子器122通常係一電子撞擊離子器，其自一或多個白熱燈絲124中產生熱電子、加速，及引導電子使其與通過離子器122的氣體噴柱118中的氣體團簇發生碰撞。此電子撞擊自團簇中逐出電子，引起此團簇中的一部分成帶正電離子化。若干團簇可具有一個以上被逐出的電子且可為倍數離子化。一組施加適當偏壓的高壓電極126自離子器中篩選團簇離子、形成波束，接著使其加速至所需的能量(通常以數佰伏特(V)至數十仟伏特(kV)的加速電勢)且使其聚焦以形成GCIB 128。燈絲電源供應器136提供燈絲電壓VF 以加熱此離子器燈絲124。陽極電源供應器134提供陽極電壓VA 以加速自燈絲124中所發射的熱電子而使其照射包含氣體噴柱118的團簇以產生離子。篩選電源供應器138提供篩選電壓VE 以對高壓電極施加偏壓而自離子器122的游離區域中篩選離子及形成GCIB 128。加速器電源供應器140提供加速電壓VAcc 以對高壓電極施加相對於離子器122的偏壓而導致等於VAcc 的全GCIB加速電勢。一或多個透鏡電源供應器(例如所示的142與144)可供以對高壓電極施加聚焦電壓的偏壓(例如VL1 與VL2 )而聚焦此GCIB 128。
將工作件152置於設在GCIB 128路徑上的工作件支撐物150上，此工作件可為半導體晶圓或藉由GCIB處理加工的其它工作件。因為大多數應用以空間地均勻結果考慮大型工作件的處理，一掃描系統係合適於使此GCIB 128在整個大區域上均勻地掃描而產生空間均勻的結果。
此GCIB 128係靜止的，具有GCIB軸心129，且經由GCIB128機械式地掃描此工作件152以使GCIB的效應分佈於工作件152的表面上。
X-掃描致動器202提供工作件支撐物150在X-掃描移動208方向(進出此紙張面)的線性移動。Y-掃描致動器204提供工作件支撐物150在Y-掃描移動210方向的線性移動，其通常垂直於X-掃描移動208。經由GCIB 128，X-掃描與Y-掃描移動的組合以柵狀掃描移動方式移動工作件支撐物150所支撐的工作件152，以藉由GCIB128用以處理工作件152而引起工作件152表面的均勻(或另外的編程方法)照射。此工作件支撐物150以相對於GCIB 128軸心的一角度設置工作件152而使GCIB 128具有相對於工作件152表面的波束入射角206。此波束入射角206可為任何適當的角度，但通常為90度或接近90度。在Y-掃描期間，工作件152與工作件支撐物150自所示的位置移動至交替的位置〝A〞，此位置分別由符號152A與150A代表。注意到，當於這兩位置之間移動時，經由GCIB 128掃描此工作件152，及在極點位置兩處，工作件152係完全地移出GCIB 128的路徑(過度掃描)。雖然在圖1中未明白地顯示出，在(通常)垂直的X-掃描移動208的方向(進出此紙張面)中執行相似的掃描與過度掃描。
波束電流感應器218係設置在GCIB 128路徑上且於工作件支撐物150後方，而當掃描工作件支撐物150超出GCIB 128路徑時，截取GCIB 128的取樣。波束電流感應器218通常為法拉第杯(faraday cup)或相似物，除波束進入時打開之外係關閉的，且通常以電性絕緣架座212固定於真空槽102的壁上。
控制器220，其可為微電腦控制器，經由電纜216連接X-掃描致動器202與Y-掃描致動器204，及控制X-掃描致動器202與Y-掃描致動器204而使工作件152進出GCIB 128，且相對於GCIB 128均勻地掃描工作件152以藉由GCIB 128執行工作件152的所需處理。控制器220以電引線214接收藉由波束電流感應器218所收集的取樣波束電流，從而監控GCIB及控制藉由工作件152所接收的GCIB劑量，且當已傳送預定的所需劑量時，自GCIB 128中移開工作件152。
參照圖2A及依據一代表性實施例，顯示帶有平坦頂端表面203的工作件152的橫剖面圖，說明在凹紋中所形成的傳導路徑225。平坦化處理提供平坦頂端表面203以產生均勻的表面，同時可改善後續微影步驟的光學解析度。可藉由偵測電介質區域235頂端的出現而終止平坦化處理。藉由蝕刻複數個互連孔洞(稱為穿孔)，接著藉由工作件152、前金屬電介質(pre-metal dielectric，PMD)、或金屬層間電介質(inter-layer dielectric，ILD)中的阱蝕刻，自鑲嵌製程或雙鑲嵌製程中形成傳導路徑225。工作件152可包含矽、鍺(Ge)或如砷化鎵(GaAs)或銻化銦(InSb)的III-V族半導體。可自磊晶層、單晶基板或絕緣層上覆矽(silicon-on-insulator，SOI)層中形成工作件152的頂層。
經由一或多種蝕刻處理所形成的互連孔洞與阱系列可稱為凹紋。使用電鍍(electroplating)或物理氣相沉積法(PVD)以如銅的金屬填塞此凹紋，後續使用如化學機械研磨法(CMP)、電解拋光(electropolishing)，或離子銑削法(ion milling)的處理使凹紋平坦化以裸露工作件152、PMD、與/或ILD的電介質，，及傳導路徑225。
可使傳導路徑225加上障壁材料232的襯底以限制傳導路徑225與電介質區域235之間的材料轉移量。障壁材料232可由一或多層鉭、氮化鉭、鈦、氮化鈦、鎢，與/或氮化鎢所形成。可使用成層技術形成此障壁材料，包括物理氣相沉積(PVD)、原子層沉積(ALD)、化學氣相沉積(CVD)、電漿增強型化學氣相沈積(plasma enhanced chemical vapor deposition，PECVD)、熱沉積，與蒸鍍。
圖2B係說明圖2A中工作件152在以磷源245處理工作件152的平坦頂端表面230後，形成摻磷層240。此磷源245可為以分子或離子形式的含磷氣體之分壓、以原子或離子形式的離子流或包括數百或數千P原子或含P分子的離子氣體團簇流。磷(P)可與平坦頂端表面230起反應且/或擴散進工作件152，或可使磷佈植或注入此頂端表面230。可藉由一系統傳送劑量約5x1012 原子/cm2 至約1x1014 原子/cm2 的磷源245，此系統係自熱處理系統、電漿處理系統、離子佈植系統，與氣體離子團簇離子束系統組成的群體中選出。可使平坦頂端表面230摻雜以形成包含介於0.1與10原子百分比(atomic %)之間的磷之摻磷層240。
在本發明的一實施例中，P係被佈植以形成帶有尖峰磷濃度深度的摻磷層240，其中此尖峰磷濃度深度係在平坦頂端表面230下方介於100與500埃(angstrom)之間。可使用熟悉本技藝者所知悉的方法使工作件152退火以降低因離子佈植處理所產生之傷害。
在本發明之較佳實施例中，GCIB係用以注入P，提供摻磷層240介於50與200埃之間的深度。在另一實施例中，GCIB係用以注入P達約300埃的深度。
磷源245可包含如膦(PH3 )的單一物種或可包含複數個物種，包括膦與如氦氣、氖氣，與/或氫氣的非可壓縮源氣。
圖2C係說明在摻磷層240上方形成障壁層250後的圖2B中工作件152。可自障壁原料255中形成此障壁層250。使用具有本技藝一般技能者所知悉的方法在摻磷層240上沉積障壁層250作為保形層，此方法如化學氣相沉積(CVD)、電漿增強型化學氣相沈積(PECVD)、高密度電漿化學氣相沉積(high density plasma chemical vapor deposition，HDPCVD)、有機金屬化學氣相磊晶法(metal organic chemical vapor deposition，MOCVD)、原子層沉積(ALD)，與物理氣相沉積(PVD)。障壁原料255可包含如氮化矽的電介質材料或一或多種障壁層材料，如碳化矽、摻氮的碳化矽、碳氮化硼，與氮化硼。
圖3係一流程圖，顯示以磷源245使工作件152之平坦頂端表面230改性的一種方法之一實施例。在構件300中，使工作件152平坦化以形成帶有傳導路徑225與電介質區域235的實質平坦表面。在構件310中，預處理平坦頂端表面230以降低或使來自平坦頂端表面230的汙染減至最小量。在一範例中，此預處理可為濕式化學清洗處理以移除在平坦頂端表面230所吸附的殘留粒子與材料。此濕式化學清洗處理可使用包括去離子水、苯並三嗪(benzotriazine)，與檸檬酸的化學機械研磨後清洗化學劑，或為化學機械研磨後清洗特別設計的溶液，如ATMI製造的ESC-700系列產品。在另一範例中，此預處理可為藉由GCIB工具所執行的注入蝕刻步驟以自平坦頂端表面230中處理或移除材料的一部分。在另一範例中，此預處理可為藉由PVD工具所執行的濺射步驟以自平坦頂端表面230中處理或移除材料的一部分。儘管此實施例包括預處理，構件310係選擇性的。在構件320中，以磷源245處理此平坦頂端表面230以形成摻磷層240而吸除在電介質區域235中的金屬污染物，與使傳導路徑225中的電遷移減低到最小量。在構件330中，在摻磷層上方形成障壁層，其包括如氮化矽、碳化矽、摻氮的碳化矽、碳氮化硼與氮化硼的障壁材料。
已描述半導體裝置中之漏電性能的改善及電遷移最小化的方法之複數個實施例。針對說明與描述之目的提出本發明之實施例的上述內容。其並不旨在涵蓋所有事項或使本發明限於所揭露的精確形式。本說明與下述的申請專利範圍包括如左、右、頂、底、在上方、在下方、較高、較低、第一、第二等術語，其僅用於描述性目的且不應理解為限制性。例如，若指明相對垂直位置的術語提及一狀況，其中基板的裝置側(或有效表面)係此基板的〝頂〞表面，此基板實際上可位於任何方向而使得在標準地面參考系中基板的〝頂〞端可低於〝底〞端且仍落於〝頂〞一詞的意義內。本文(包括在申請專利範圍中)所用的〝在...之上〞一詞，除非特別說明，否則不代表在第二層上的第一層係直接及立即與第二層接觸，可有第三層或其它結構介於第一層與在第一層上的第二層之間。可在若干狀況與目標中製造、使用或運送此述的裝置或物品的實施例。
在本描述與申請專利範圍請求項中，會使用〝耦合〞與〝相連接〞一詞及其衍生字。應了解到，這些字詞不意味彼此為同義字。相反地，在特殊的實施例中，〝相連接〞可用以指明兩個以上元件彼此係直接物理或電性上接觸，而〝耦合〞更意味兩個以上元件彼此係不直接接觸，但仍彼此相合作或交互作用。
照此具體說明的全文，〝一個實施例〞或〝一實施例〞意味在本發明之至少一實施例中包括關於本實施例所描述的特殊形體、結構、材料，或特徵，但不表示在每一實施例中都會存在。因此，在此詳細說明的全文種種地方中，詞組〝在一個實施例中〞或〝在一實施例中〞的出現未必涉及本發明的相同實施例。此外，在一或多個實施例中可以任何適當的方式結合特殊形體、結構、材料，或特徵。在其他實施例中可包括各式額外層別與/或結構，與/或省略所描述的形體。
以最有助於了解本發明的方法把各式操作依序描述為多種離散的操作。然而，不應把描述的順序理解為暗示這些操作係必定順序相依。特別是，這些操作係不需依表達順序而執行。可以不同於所述實施例的順序執行所述的操作。在額外的實施例中可執行各式額外的操作，與/或省略所述的操作。
在上述教示的指引下，熟悉相關技藝者可理解許多修正或變化係可能的。熟悉本技藝者將認可圖中所示的種種組件的各種等價的結合與替換。因此按計畫本發明的範圍係不為此詳細說明所限，而為隨附的申請專利範圍請求項所限。
100．．．GCIB處理設備
102．．．真空槽
104．．．源腔
106．．．加速/游離腔
108．．．處理腔
110．．．噴嘴
111．．．氣體儲存瓶
112．．．壓縮源氣
113．．．氣體節流閥
114．．．氣體進給管
116．．．滯留腔
118．．．超音氣體噴柱
120．．．氣體分離器孔
122．．．離子器
124．．．白熱燈絲
126．．．高壓電極
128．．．GCIB(氣體團簇離子束)
129．．．GCIB軸心
134．．．陽極電源供應器
136．．．燈絲電源供應器
138．．．篩選電源供應器
140．．．加速器電源供應器
142．．．透鏡電源供應器
144．．．透鏡電源供應器
146a．．．真空泵浦系統
146b．．．真空泵浦系統
146c．．．真空泵浦系統
150．．．工作件支撐物
150A．．．符號
152．．．工作件
152A．．．符號
202．．．X-掃描致動器
204．．．Y-掃描致動器
206．．．波束入射角
208．．．X-掃描移動
210．．．Y-掃描移動
212．．．電性絕緣架座
214．．．電引線
216．．．電纜
218．．．波束電流感應器
220．．．控制器
225．．．傳導路徑
230．．．平坦頂端表面
232．．．障壁材料
235．．．電介質材料
240．．．摻磷層
245．．．磷源
250．．．障壁層
255．．．障壁原料
VA ．．．陽極電壓
VACC ．．．加速電壓
VE ．．．篩選電壓
VF ．．．燈絲電壓
VL1 ．．．聚焦電壓
VL2 ．．．聚焦電壓
本發明係經由例子說明且不限於隨附圖示的圖表中。
圖1係一GCIB處理設備的略圖。
圖2A係一平坦化工作件的橫剖面圖，說明在凹紋中所形成的傳導路徑。
圖2B係說明圖2A中工作件在處理工作件的平坦表面後，形成摻磷層。
圖2C係說明在摻磷層上方形成障壁層後的圖2B中工作件。
圖3係一流程圖，顯示以磷源使工作件之平坦表面改性的一種方法之一實施例。
152．．．工作件
225．．．傳導路徑
232．．．障壁材料
235．．．電介質材料
240．．．摻磷層
250．．．障壁層
255．．．障壁原料

Claims (8)

  1. 一種形成一摻磷層的方法，該方法包括：使一工作件的一頂端表面平坦化，以形成帶有複數個銅傳導路徑與複數個電介質區域的實質平坦表面；使用一氣體團簇離子束系統將磷摻雜物注入至該工作件的該平坦化頂端表面之中及之下，以在該複數個銅傳導路徑與該複數個電介質區域中、從該頂端表面至該頂端表面下約50-200埃(angstrom)的一所需深度形成一摻磷層，其中在該摻磷層中存在的該磷摻雜物用於吸除在該複數個電介質區域中的金屬污染物、及使在該複數個銅傳導路徑中的電遷移減低到最小量；及在該摻磷層上方形成一障壁層，以使來自形成在該複數個銅傳導路徑及電介質區域中的該摻磷層的材料轉移減低到最小量。
  2. 如申請專利範圍第1項的形成一摻磷層的方法，更包括在使磷注入該工作件的該頂端表面之前的一預處理步驟。
  3. 如申請專利範圍第1項的形成一摻磷層的方法，其中該摻磷層包括介於0.1原子百分比(atomic%)與10原子百分比(atomic%)之間的磷摻雜物。
  4. 如申請專利範圍第1項的形成一摻磷層的方法，其中利用一化學機械研磨平坦法或一電解拋光法使該實質平坦表面平坦化。
  5. 如申請專利範圍第1項的形成一摻磷層的方法，其中使用包括膦與一非可壓縮氣體的一磷源使磷注入該工作件的該頂端表面。
  6. 如申請專利範圍第5項的形成一摻磷層的方法，其中該非可壓縮氣體係自氦氣、氖氣，與氫氣組成的群體中選取。
  7. 如申請專利範圍第5項的形成一摻磷層的方法，更包括一第二可壓縮氣源，該第二可壓縮氣源係自氬氣、氮氣、二氧化碳與氧氣組成的群體中選取。
  8. 如申請專利範圍第1項的形成一摻磷層的方法，其中該障壁層係自氮化矽、碳化矽、摻氮的碳化矽、碳氮化硼，與氮化硼組成的群體中選取。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7410890B2 (en) * 2002-12-12 2008-08-12 Tel Epion Inc. Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation
US7838428B2 (en) * 2006-03-23 2010-11-23 International Business Machines Corporation Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species
US7816253B2 (en) * 2006-03-23 2010-10-19 International Business Machines Corporation Surface treatment of inter-layer dielectric
US8192805B2 (en) * 2007-09-27 2012-06-05 Tel Epion Inc. Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices
JP6278591B2 (ja) * 2012-11-13 2018-02-14 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
US9899327B2 (en) * 2016-06-24 2018-02-20 International Business Machines Corporation Surface treatment for semiconductor structure
JP2017175143A (ja) * 2017-05-01 2017-09-28 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP2017175145A (ja) * 2017-05-01 2017-09-28 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP2019041054A (ja) * 2017-08-28 2019-03-14 東芝メモリ株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174793B1 (en) * 1999-10-11 2001-01-16 United Microelectronics Corp. Method for enhancing adhesion between copper and silicon nitride
US6784095B1 (en) * 2001-02-14 2004-08-31 Advanced Micro Devices, Inc. Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing
TW200419801A (en) * 2003-03-28 2004-10-01 Advanced Power Electronics Corp Trench power MOSFET and method thereof
US20050277246A1 (en) * 2002-12-12 2005-12-15 Epion Corporation Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4361762A (en) 1980-07-30 1982-11-30 Rca Corporation Apparatus and method for neutralizing the beam in an ion implanter
JPS62296357A (ja) 1986-06-16 1987-12-23 Fujitsu Ltd イオン注入装置の電荷中和装置
US4916311A (en) 1987-03-12 1990-04-10 Mitsubishi Denki Kabushiki Kaisha Ion beaming irradiating apparatus including ion neutralizer
US4886971A (en) 1987-03-13 1989-12-12 Mitsubishi Denki Kabushiki Kaisha Ion beam irradiating apparatus including ion neutralizer
US6268291B1 (en) 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
JP3013787B2 (ja) * 1996-09-20 2000-02-28 日本電気株式会社 半導体装置の製造方法
US6492282B1 (en) 1997-04-30 2002-12-10 Siemens Aktiengesellschaft Integrated circuits and manufacturing methods
US6124620A (en) * 1998-05-14 2000-09-26 Advanced Micro Devices, Inc. Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation
KR100385042B1 (ko) 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법
US6646277B2 (en) 2000-12-26 2003-11-11 Epion Corporation Charging control and dosimetry system for gas cluster ion beam
US7396745B2 (en) * 2004-12-03 2008-07-08 Tel Epion Inc. Formation of ultra-shallow junctions by gas-cluster ion irradiation
US7276441B1 (en) 2003-04-15 2007-10-02 Lsi Logic Corporation Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
US7259036B2 (en) 2004-02-14 2007-08-21 Tel Epion Inc. Methods of forming doped and un-doped strained semiconductor materials and semiconductor films by gas-cluster-ion-beam irradiation and materials and film products
CN100472739C (zh) 2004-11-08 2009-03-25 Tel艾派恩有限公司 铜互连布线和形成铜互连布线的方法
US7226875B2 (en) 2004-11-30 2007-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method for enhancing FSG film stability
JP2006165115A (ja) * 2004-12-03 2006-06-22 Toshiba Corp 半導体装置
EP1958245B1 (en) * 2005-12-09 2013-10-16 Semequip, Inc. Method for the manufacture of semiconductor devices by the implantation of carbon clusters
US8110815B2 (en) * 2006-06-12 2012-02-07 Semequip, Inc. Vapor delivery to devices under vacuum
KR20090029209A (ko) * 2006-06-13 2009-03-20 세미이큅, 인코포레이티드 이온 주입을 위한 이온 빔 장치 및 방법
US8192805B2 (en) * 2007-09-27 2012-06-05 Tel Epion Inc. Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices
US7737013B2 (en) * 2007-11-06 2010-06-15 Varian Semiconductor Equipment Associates, Inc. Implantation of multiple species to address copper reliability
US7871929B2 (en) * 2008-07-30 2011-01-18 Tel Epion Inc. Method of forming semiconductor devices containing metal cap layers
US7776743B2 (en) * 2008-07-30 2010-08-17 Tel Epion Inc. Method of forming semiconductor devices containing metal cap layers
JP2010114409A (ja) * 2008-10-10 2010-05-20 Sony Corp Ｓｏｉ基板とその製造方法、固体撮像装置とその製造方法、および撮像装置
US7977235B2 (en) * 2009-02-02 2011-07-12 Tokyo Electron Limited Method for manufacturing a semiconductor device with metal-containing cap layers
US8202783B2 (en) * 2009-09-29 2012-06-19 International Business Machines Corporation Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174793B1 (en) * 1999-10-11 2001-01-16 United Microelectronics Corp. Method for enhancing adhesion between copper and silicon nitride
US6784095B1 (en) * 2001-02-14 2004-08-31 Advanced Micro Devices, Inc. Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing
US20050277246A1 (en) * 2002-12-12 2005-12-15 Epion Corporation Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation
TW200419801A (en) * 2003-03-28 2004-10-01 Advanced Power Electronics Corp Trench power MOSFET and method thereof

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