TWI381464B - The bump structure and its making method - Google Patents

The bump structure and its making method Download PDF

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TWI381464B
TWI381464B TW097133263A TW97133263A TWI381464B TW I381464 B TWI381464 B TW I381464B TW 097133263 A TW097133263 A TW 097133263A TW 97133263 A TW97133263 A TW 97133263A TW I381464 B TWI381464 B TW I381464B
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elastic layer
layer
bump
elastic
bump structure
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TW097133263A
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Hannstar Display Corp
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Description

凸塊結構及其製作方法
本發明係有關一種金屬凸塊結構及其製作方法，特別是指一種凸塊結構及其製作方法。
液晶顯示器(Liquid Crystal display,LCD)的製程中包含有陣列(array)、晶胞(cell)以及模組(module)等三段製程，其中模組段製程的主要目的是封裝驅動IC，而模組段製程又分為三個部分，其係分別為COG(chip on glass)、OLB(outer lead bonding)與AOP(ACF on PCB)。
LCM(LCD Module)三大段製程中，以COG模組構裝技術具有高接合密度及低成本的優點，為降低成本的重點設計。而所謂的覆晶玻璃(Chip on Glass；COG)乃為高腳數(high pin count)及超細節距(fine pitch)平面顯示器(Flat Panel Display)之模組構裝技術。此模組構裝之技術特徵為驅動IC訊號源及面板玻璃基板間具有最少接合點且其不須使用可撓性基板，因此，可以克服捲帶式封裝(TCP)容易因彎摺而產生引腳斷裂的現象，進而提高產品之可靠度。
傳統的COG驅動IC中含有凸塊(bump)，目的是為了要與LCD導通，讓驅動IC的訊號能順利藉由凸塊傳送至LCD，以便作畫素訊號的傳輸與畫面的切換。請參閱第1圖，其係傳統的凸塊結構，如圖所示，傳統的凸塊結構包含有一表面上設置有一連接墊10的半導體基底12，其中，連接墊10係以鋁(Al)、金(Au)或其他合金等金屬材質形成；一覆蓋基底12與部分連接墊10的保護層(passivation)14，其係界定出連接墊10與外部電路電性連結的位置；一位於保護層14與自保護層14顯露出之連接墊10上的凸塊下金屬層16，其中，凸塊下金屬層16其材質可為鋁(Al)、鈦(Ti)、鎢(W)、金(Au)或其合金等金屬材質形成；以及一位於凸塊下金屬層16上的凸塊18，其一般材質為 金。在上述結構中，由於凸塊20整體為金屬材質，對材料特性上而言在COG非導電膠(non－conductive film,NCF)製程上彈性以及變形量會有明顯不足。
因此為解決上述之缺點，衍生出一種嶄新的智慧型凸塊結構(smart bump)20，如第2(a)~2(b)圖所示。此種智慧型凸塊結構20包含有一表面上設置有一連接墊21的半導體基底22；一覆蓋基底22與部分連接墊21的保護層(passivation)23；一覆蓋於保護層23與部分自保護層23顯露出之連接墊21上的PI層(彈性層)24，其係界定出連接墊21與外部電路電性連結的位置；一位於PI層24與自PI層24顯露出之連接墊21上的凸塊下金屬層25；以及一位於凸塊下金屬層25上的凸塊26。智慧型凸塊結構20係於每一凸塊26底端形成一圖案化島狀PI層24結構，以增加凸塊整體的彈性與COG NCF的製程穩定性。鑑此，智慧型凸塊結構20製作時，係需於對應凸塊26之欲設置位置上先形成島狀PI層24。
但隨著LCD畫素的提高與IC設計與製程的進步，IC上所需容納的pin數也大幅度增加，因此IC也必須持續往細微間距(fine pitch)的趨勢發展，相對地，凸塊的寬度必須縮減以容納更多的細微間距。一般而言，fine pitch IC凸塊間距通常低於20 μm，而現今因PI層材料的曝光、顯影能力之間距的極限值是20 μm，在這樣的間距極限下，將使得間距為a(a<20 μm)的島狀彈性層在製作上面臨一大瓶頸。
有鑑於此，本發明遂針對上述習知技術之缺失，提出一種嶄新的凸塊結構及其製作方法，以有效克服上述之該等問題。
本發明之主要目的在提供一種凸塊結構及其製作方法，其係利用一較大尺度(≧20 μm)的彈性層圖案化製程，以形成至少一彈性層，來提供凸塊適當的彈性與變形量，以使凸塊結構能夠適用於細微間距的IC。
本發明之另一目的在提供一種凸塊結構及其製作方法，其鋸齒狀彈性層有利於後續製程使用異方向性導電膠電性接合時，多餘的導電膠進行排膠。
為達上述之目的，本發明提供一種凸塊結構，其包含有一表面上形成有數個連接墊之半導體基底；一保護層，其係覆蓋於該基底上，保護層對應於每一該連接墊具有一開口，以露出部分連接墊，以供作為電性連接位置；一位於保護層上的彈性層；以及數個凸塊，其每一係設於對應該些電性連接位置上，且延伸至彈性層上。
本發明尚提供一種凸塊的製作方法，其包含有形成數個連接墊於一半導體基底上；形成一彈性層於一半導體基底上；以及形成數個凸塊對應於該些連接墊之上，且延伸至該彈性層。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明之第一實施例之智慧型凸塊結構的主要精神所在是架構在先前技術之智慧型結構設計下，為因應IC持續往細微間距的趨勢發展時，細微間距IC凸塊間距需低於20 μm，而彈性層間距之顯影蝕刻極限為20 μm之情況下，提供一種嶄新的智慧型凸塊結構讓凸塊代工廠(bumping house)有更多裕度，順利形成智慧型凸塊結構。
請一併參閱第3(a)圖~3(c)圖，其係為本發明之第一實施例的立體示意圖、截線bb’段的剖視圖與結構佈局(layout)示意圖。在這個實施例中與習知之smart bump的主要技術差異點在於本發明之一圖案化彈性層上承載著至少二個凸塊結構。
如圖所示，本發明之智慧型凸塊30的結構包含有：一表面上設置有數個連接墊32的半導體基底34；一覆蓋於基底34上的保護層36，此保護層36對應於每一該32具有一開口，以露出部分連接墊32，來形成數個電性連接位置38；一覆蓋於保護層36上之第一彈性層40， 第一彈性層40同時也延伸至電性連接位置38的第一側；一第二彈性層42，其同樣也覆蓋於保護層36上且延伸至電性連接位置38的第二側，第一彈性層40與第二彈性層42之材質為非導電材且具有優於金屬材之彈性特性，例如聚亞醯胺(PI)；以及數個凸塊44，其中每一凸塊44係設於對應電性連接位置38的位置上且兩端各延伸至第一彈性層40與第二彈性層42上。更者，上述凸塊44更包含有一凸塊下金屬45。
在上述之結構下，數個凸塊44之第一側端將會同時位於第一彈性層40上，而第二側端將同位於第二彈性層42上，也就是第一彈性層40將承受所有凸塊44第一側端之受力，而第二彈性層42則承受凸塊44第二側端之所有受力，由於第一彈性層40與第二彈性層42之材質選用以具有優於金屬材之彈性特性，因此可提供金屬材質之凸塊44在後續電性接合製程時增加彈性與變形的空間。在本發明之第一實施例中，彈性層僅需圖案化為長形之第一彈性層40與第二彈性層44結構，而無須曝光顯影形成如第2(b)圖之不連續島狀結構，而有效的避免了彈性層蝕刻極限間距(a)的限制。
而上述實施例的製作步驟，請參閱第4圖，其係上述實施例的步驟流程圖，首先如步驟S1所述，於一半導體基底34上形成數個連接墊32；接續如步驟S2所述，於基底34上形成一保護層36，此保護層36對應於每一該32具有一開口，以露出部分連接墊32，作為數個電性連接位置38；如步驟S3所述，於保護層36上形成一延伸至電性連接位置38第一側上的第一彈性層40，並且於保護層36上形成一延伸至電性連接位置38第二側上的第二彈性層42；最後，如步驟S4所述，於對應於連接墊32之位置上形成數個凸塊44，且凸塊44兩端各自延伸至該第一彈性層40與該第二彈性層42。
請一併參閱第5(a)圖~5(c)圖，其係為本發明之第二實施例的立體示意圖、截線cc’段的剖視圖與結構佈局示意圖。在此具體實施 例中係將習知smart bump結構的彈性層進行適當調整，以應後續凸塊在電性接合時所受之壓力變化與變形量的來設計。如圖所示，此實施例之金屬凸塊的結構包含有：一表面上設置有數個連接墊50的半導體基底52；一覆蓋於基底52上的保護層54，此保護層54對應於每一該連接墊50具有一開口，以露出部分連接墊，來形成數個電性連接位置56；一覆蓋於保護層上之圖案化彈性層58，此圖案化彈性層58同時也延伸至部分電性連接位置，圖案化彈性層58之材質可以為PI，且此彈性層58之圖案可定義為一鋸齒狀圖案；以及數個凸塊60，其中每一凸塊60係設於對應電性連接位置56的位置上且延伸至圖案化彈性層58，以使凸塊60與自圖案化彈性層58顯露出之電性連接位置56形成電性連接並利用延伸覆蓋的部分圖案化彈性層58，來提供每一凸塊彈性與變形空間。而凸塊60更包含有一凸塊下金屬層61。
在上述之結構下，僅需對彈性層進行相對於第2圖之不連續島狀結構為較大尺度的圖案化製程，鑑此避免了對彈性層進行過小間距(a)的蝕刻。
請參閱第6圖，其係本發明之彈性層的另一種鋸齒狀圖案化彈性層的示意圖，第5圖之彈性層58與第6圖之彈性層62之圖案差異，乃是應後續製程中凸塊在電性接合時所受之壓力變化來設計，以提高該凸塊整體的彈性。此外，鋸齒狀的圖案也利於後續製程時異方向性導電膠的排膠。
請參閱第7(a)與第7(b)圖，其係本發明又一實施例的結構示意圖與俯視示意圖。如圖所示，此實施例包含有一表面上形成有數個連接墊64的半導體基底66；一覆蓋於基底66上的保護層68，其對應於連接墊64具有一開口，以露出部分連接墊64，供作為數個電性連接位置65；一位於保護層68上的彈性層70；以及一位於電性連接位置上並延伸至彈性層的凸塊72。而上述凸塊72更包含有一凸塊下金屬層74。此實施例不同於先前實施例的特點是在於彈性層僅位於保 護層上，並無延伸至電性連接位置上。
綜上所述，本發明係提供一種嶄新的凸塊結構及其製作方法，其包含有一表面上形成有數個連接墊的半導體基底；一覆蓋於基底上的保護層，其對應於每一連接墊具有一開口，以露出部分連接墊，供作為數個電性連接位置；至少一位於保護層上的一彈性層；以及數個凸塊，其每一設於對應電性連接位置上，且延伸至彈性層上，以提供凸塊彈性與變形量的空間。本發明利用一較大尺度(≧20 μm)圖案化製程，以形成一圖案化彈性層(平行線狀、長條狀或鋸齒狀)，來提供凸塊適當的彈性與變形量，以使smart bump結構能夠適用於fine pitch的IC。
唯以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明實施之範圍。故即凡依本發明申請範圍所述之特徵及精神所為之均等變化或修飾，均應包括於本發明之申請專利範圍內。
10‧‧‧連接墊
12‧‧‧半導體基底
14‧‧‧保護層
16‧‧‧凸塊下金屬層
18‧‧‧凸塊
20‧‧‧智慧型凸塊結構
21‧‧‧連接墊
22‧‧‧基底
23‧‧‧保護層
24‧‧‧PI層
25‧‧‧凸塊下金屬層
26‧‧‧凸塊
30‧‧‧智慧型凸塊
32‧‧‧連接墊
34‧‧‧半導體基底
36‧‧‧保護層
38‧‧‧電性連接位置
40‧‧‧第一彈性層
42‧‧‧第二彈性層
44‧‧‧凸塊
45‧‧‧凸塊下金屬層
50‧‧‧連接墊
52‧‧‧基底
54‧‧‧保護層
56‧‧‧電性連接位置
58‧‧‧彈性層
60‧‧‧凸塊
61‧‧‧凸塊下金屬層
62‧‧‧彈性層
64‧‧‧連接墊
65‧‧‧電性連接位置
66‧‧‧基底
68‧‧‧保護層
70‧‧‧彈性層
72‧‧‧凸塊
74‧‧‧凸塊下金屬層
第1圖係習知之金屬凸塊的結構示意圖。
第2(a)圖係習知之智慧型凸塊的結構示意圖。
第2(b)圖係習知之智慧型凸塊的俯視示意圖。
第3(a)圖至3(c)圖係各為本發明之智慧型凸塊的第一具體實施例立體示意圖、剖視圖與結構佈局示意圖。
第4圖係本發明之第一具體實施例的製作步驟流程圖。
第5(a)圖至5(c)圖係各為本發明之智慧型凸塊的第二具體實施例立體示意圖、剖視圖與結構佈局示意圖。
第6圖係為本發明之智慧型凸塊的彈性層的另一種實施例示意圖。
第7(a)圖係本發明之智慧型凸塊的又一具體實施例示意圖。
第7(b)圖係為第7(a)圖之俯視圖。
30‧‧‧智慧型凸塊
36‧‧‧保護層
38‧‧‧電性連接位置
40‧‧‧第一彈性層
42‧‧‧第二彈性層
44‧‧‧凸塊

Claims (8)

  1. 一種凸塊結構，其包含有：一半導體基底，其上形成有數個連接墊；一保護層，其係覆蓋於該基底上，該保護層對應於每一該連接墊具有一開口，以露出部分該連接墊，作為數個電性連接位置；一彈性層，其係連續式覆蓋於部分的該保護層與部分的該連接墊上方，作為電性接合壓著時的彈性緩衝層；以及數個凸塊，其每一係設於對應該些電性連接位置上，且延伸至該彈性層。
  2. 如申請專利範圍第1項所述之凸塊結構，其中該彈性層之材質為聚亞醯胺(PI)。
  3. 如申請專利範圍第1項所述之凸塊結構，其中該凸塊還包含有一凸塊下金屬層。
  4. 如申請專利範圍第1項所述之凸塊結構，其中該彈性層係圖案化為鋸齒狀。
  5. 如申請專利範圍第1項所述之凸塊結構，其中該彈性層係為一第一彈性層與一第二彈性層，且該第一彈性層與該第二彈性層係分設於該凸塊底部兩側。
  6. 如申請專利範圍第1項所述之凸塊結構，其係用於液晶顯示器面板的覆晶玻璃(COG)製程。
  7. 如申請專利範圍第1項所述之凸塊結構，其中該彈性層是非導電性材料。
  8. 一種製作超細微間距的凸塊方法，其包含有：形成數個連接墊於一半導體基底上；於該半導體基底上形成一保護層，該保護層具有數個開口，以顯露出部分該連接墊形成一彈性層於一半導體基底上，該彈性層連續式覆蓋於部分的保 護層與部分的該連接墊上方，作為電性接合壓著時的彈性緩衝層；以及形成數個凸塊對應於該些連接墊之上，且延伸至該彈性層。
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