•1276212 . 九、發明說明： 【發明所屬之技術領域】 本發明係有關一電性連接墊結構，主要是針對玻璃覆 晶封裝（Chip on Glass，COG)中，使驅動集成電路(ic)上用 以電性連接之金凸塊具有一非常平坦之表面。 【先前技術】 液晶顯示器與傳統映像管（CRT)相比具有低電壓驅 ⑩ 動、微功耗、顯示容量大、低輻射及輕薄等特性，所以被 廣泛的應用於各種影音設備及通訊設備。該液晶顯示器的 驅動集成電路之封裝方式亦由早期的晶片直接封裝（chip on Board，COB)、捲帶式封裝（Tape Carrier Bonding，TAB) 發展到如今的玻璃覆晶（Chip on Glass，COG)、薄膜覆晶 (Chip on Film，COF)等封裝方式。 請參閱「第1圖」，係一種玻璃覆晶結構之壓接示意 圖。該玻璃覆晶結構包括一驅動集成電路(IC) U、一異向 φ 導電膜12及一玻璃基板13。該驅動集成電路η上具有 複數金凸塊(gold bump)lll，且該玻璃基板上具複數與 該些金凸塊(goldbump)lll對應數目及位置由導電薄膜形 成之電極 131’該異向導電膜(Anisotropic Conductive Film， ACF)12由黏合劑（binder)121及位於其中之導電粒子 (conductive particles)122組成。該玻璃覆晶封裝結構係藉 由該異向導電膜12使驅動集成電路η之金凸塊H1與玻 璃基板13上之電極131壓接導通。 該玻璃覆晶結構之壓接方式為，首先，提供該玻璃基 •1276212 : 板13，且該玻璃基板13上具複數導電薄膜形成之電極 131 ;將該異向導電膜12貼覆於該玻璃基板π上；將該 驅動集成電路11置於該異向導電膜12上，該驅動集成電 路11上具複數金凸塊111，該些金凸塊111分別與玻璃基 板13上之電極131相對應。然後於一定溫度、速度及壓 力條件下’對上述結構進行預壓及本壓（main bonding)操 作，使驅動集成電路u之金凸塊lu藉由該異向導電膜 • 12之導電粒子122與該玻璃基板13之電極131實現電性 連接，並藉由黏合劑121將驅動集成電路n與玻璃基板 U黏合（如「第2圖」所示）。 該異向導電膜丨2的主要特點在於Z軸(厚度）方向有電 性導通’而水平方向不相導通的特性，因此只要導電粒子 122夠小或相互絕緣得宜，即可達到各金凸塊ηι間細間 距（fine pitch)之接合效果。 由於目前液晶顯示器朝向更高解析度的顯示運用，將 • 面臨驅動集成電路11之引腳(pin)數越來越多，也就是不 僅驅動集成電路Π上電路的集積度愈來愈高，該些金凸 塊111的數目也越來越多。 所以設計者為減少各金凸塊m之間距(pitch)所占的 空間’可以動用的地方除了該些電性連接線的佈局考量 外’另一方面就是縮小各個金凸塊nl間的間距，因為若 各金凸塊111之間距無法有效的減小，將限制晶片尺寸越 趨縮小之方向。 但’現常見導電粒子122的粒徑範圍在3〜15//m之 6 (§) 1276212 :間’士，大的導電粒子122會降低每個電極接觸的粒子數， 同吋谷易造成相鄰電極因為導電粒子122接觸而短路Μ 的情形（如「第3圖」所示）。相同的，在縮小各個金凸塊 111間的間距後’也會有上述的問題，所以為了形成細間 距（fine pitch)，想必然就必須使用小粒徑的導電粒子122， 如粒徑3〜4// m的導電粒子122。 ^ 士 弟4圖」该驅動集成電路η之電性連接墊 φ 不思圖，在該驅動集成電路11上的連接墊112藉由一絕 緣t 113經由黃光製程形成一連接墊開口部(pad叩如)114 (请再參閱「第5圖」所示），再以電鍍製程形成—約15〜17 /zm厚度之金凸塊U1。 而在一般標準的金凸塊111與該玻璃基板13之電極 131的連接中需壓破五粒以上之導電粒子122，因為該金 凸塊111係形成於該連接墊開口部114及其週邊的絕緣層 U3上，所以在一般該金凸塊111之表面積約2000/Z m2 •的使情況下，因為該絕緣層133的厚度關係，該金凸塊in 之表面1141將會形成一向下凹陷約2//m之表面樣態，又 一般電鍍製程也會因為製程因素而於同一平面上產生表 面±l"m的電鍍落差。 綜合上述，該金凸塊U1之表面1141最高與最低將會 有4/z m的高度落差。如此3〜4// m的小粒徑導電粒子122 將會因為該表面U41的落差高度而導致該導電粒子丨22 壓的不夠破而與金凸塊ln間的接觸面積不夠，而無良好 的電性連接效果。 1276212 【發明内容】 爰是’本發明之主要目的在於解決該驅動集成電路上 該些金凸塊的表面平坦化問題，藉由該金凸塊表面的平坦 化，使玻璃覆晶封裝之壓接製程中，該小粒徑導電粒子將 不會有壓的不夠破，而有接觸面積不夠之問題，使連接的 電極間具有良好的電性連接效果。 本發明之另一目的在於對於任何用於玻璃覆晶封裝 _ 之驅動集成電路，在不需改變製程的情況下，可選用具小 粒徑之導電粒子的異向導電膜，而達到縮小各個金凸塊間 細間距(fine pitch)之目標，藉此可增加驅動集成電路上電 路的集積度。本發明係一種電性連接墊結構，係對於驅動 集成電路上做為對外之連接墊，當該絕緣層設置於該些連 接墊上方後，該絕緣層經由黃光製程形成複數個連接墊開 口部，藉由該些連接墊開口部露出該連接墊之小面積表 面；而該金凸塊形成該絕緣層上方，同時透過該連接塾開 口部與該連接墊電性連接。 1 I發明將原本大面積之連接墊開口部結構改為複數 個連接塾開口部’藉由調整該些連接塾開口部與具絕緣層 之未開口區域的面積比例，在兼顧電性連接之條件下 金凸塊形成於該些連接塾開口部及其週邊的絕緣層上 時’將：因為該些連接塾開口部之單—區域不大：而減少 如習知單一大面積之連接墊開口部產生嚴重凹陷之影 響，使本發明所形成之金凸塊具有一非常平坦^^_ 的表面。 1276212 【實施方式】 茲有關本發明之詳細内容及技術說明，現配合圖式說 明如下：• 1276212. IX. Description of the Invention: [Technical Field] The present invention relates to an electrical connection pad structure, mainly for a chip on glass (COG), to drive an integrated circuit (IC) The gold bumps for electrical connection have a very flat surface. [Prior Art] Compared with the conventional image tube (CRT), the liquid crystal display has low voltage driving, micro power consumption, large display capacity, low radiation and light weight, so it is widely used in various audio and video equipment and communication equipment. The packaging of the liquid crystal display driver integrated circuit has also been developed from the early chip on board (COB), tape carrier bonding (TAB) to today's chip on glass (COG). , such as chip on film (COF) packaging. Please refer to "Figure 1", which is a crimping diagram of a glass flip-chip structure. The glass flip-chip structure includes a driving integrated circuit (IC) U, an anisotropic φ conductive film 12, and a glass substrate 13. The driving integrated circuit η has a plurality of gold bumps l11, and the glass substrate has a plurality of electrodes 131' corresponding to the number of the gold bumps 111 and the conductive film formed thereon. The film (Anisotropic Conductive Film, ACF) 12 is composed of a binder 121 and conductive particles 122 located therein. The glass flip-chip package structure is used to press-contact the gold bumps H1 of the driving integrated circuit η with the electrodes 131 on the glass substrate 13 by the anisotropic conductive film 12. The glass flip-chip structure is crimped by first providing the glass substrate 1276212: a plate 13 having the electrode 131 formed of a plurality of conductive films thereon; the isotropic conductive film 12 is attached to the glass The driving integrated circuit 11 is disposed on the opposite conductive film 12, and the driving integrated circuit 11 has a plurality of gold bumps 111 corresponding to the electrodes 131 on the glass substrate 13, respectively. . Then, under a certain temperature, speed and pressure condition, the pre-compression and the main bonding operation are performed on the above structure, so that the gold bumps of the driving integrated circuit u are made of the conductive particles 122 of the anisotropic conductive film. The electrode 131 of the glass substrate 13 is electrically connected, and the driving integrated circuit n is bonded to the glass substrate U by the adhesive 121 (as shown in FIG. 2). The main feature of the anisotropic conductive film 丨2 is that the Z-axis (thickness) direction is electrically conductive and the horizontal direction is not conductive. Therefore, as long as the conductive particles 122 are small enough or insulated from each other, each gold bump can be achieved. The bonding effect of fine pitch between ηι. Due to the current use of liquid crystal displays for higher resolution display, the number of pins facing the driver integrated circuit 11 is increasing, that is, not only the integrated circuit of the driver integrated circuit is higher and higher, The number of gold bumps 111 is also increasing. Therefore, in order to reduce the space occupied by the pitch of each gold bump m, the designer can use the layout of the electrical connection lines in addition to the layout considerations of the electrical connection lines. On the other hand, the space between the gold bumps nl is narrowed. Because if the distance between the gold bumps 111 cannot be effectively reduced, the direction in which the wafer size is narrowed will be limited. However, the particle size of the common conductive particles 122 is in the range of 3 to 15//m 6 (§) 1276212: the large conductive particles 122 reduce the number of particles in contact with each electrode. The adjacent electrode is short-circuited due to the contact of the conductive particles 122 (as shown in "Fig. 3"). Similarly, after narrowing the pitch between the gold bumps 111, the above problem also occurs. Therefore, in order to form a fine pitch, it is necessary to use a small particle diameter of the conductive particles 122, such as a particle size of 3~ 4 / / m of conductive particles 122. ^士弟4图" The electrical connection pad φ of the driving integrated circuit η is not considered, and the connection pad 112 on the driving integrated circuit 11 forms a connection pad opening portion through a yellow light process by an insulating t 113 For example, 114 (please refer to "Fig. 5"), and then form a gold bump U1 of about 15~17 /zm thickness by an electroplating process. In the connection between the general standard gold bump 111 and the electrode 131 of the glass substrate 13, five or more conductive particles 122 are required to be crushed because the gold bump 111 is formed in the opening of the connection pad opening portion 114 and its periphery. On the layer U3, in the case where the surface area of the gold bump 111 is generally about 2000/Z m2 · , the surface 1141 of the gold bump in will form a downward recess of about 2 due to the thickness relationship of the insulating layer 133. / / m surface state, and the general plating process will also produce surface ± l " m electroplating drop on the same plane due to process factors. In summary, the surface 1141 of the gold bump U1 will have a height difference of 4/z m at the highest and lowest. Such a small particle size conductive particle 122 of 3 to 4 / / m will cause the conductive particle 丨 22 to be insufficiently broken due to the height difference of the surface U41, and the contact area with the gold bump ln is insufficient, and there is no good Electrical connection effect. 1276212 [Description of the Invention] The main purpose of the present invention is to solve the problem of surface flattening of the gold bumps on the driving integrated circuit, and the surface of the gold bumps is flattened to crimp the glass flip chip. In the process, the small-sized conductive particles will not have insufficient pressure to break, and there is a problem that the contact area is insufficient, so that the connected electrodes have a good electrical connection effect. Another object of the present invention is to reduce the thickness of each of the driving integrated circuits for the glass flip chip package by using an anisotropic conductive film of small particle size conductive particles without changing the process. The goal of fine pitch between bumps, thereby increasing the degree of integration of the circuitry on the driver integrated circuit. The invention relates to an electrical connection pad structure, which is used as an external connection pad for driving an integrated circuit. After the insulation layer is disposed above the connection pads, the insulation layer forms a plurality of connection pad openings through a yellow light process. The small opening surface of the connecting pad is exposed by the opening portions of the connecting pads; and the gold bumps are formed above the insulating layer, and are electrically connected to the connecting pads through the connecting opening. 1 I invention changes the original large-area connection pad opening structure to a plurality of connection openings" by adjusting the ratio of the area of the opening of the connection opening to the unopened area having the insulating layer, in consideration of the condition of electrical connection When the lower gold bump is formed on the insulating layer of the opening portion of the connecting port and the periphery thereof, it will be: because the single-region of the opening portion of the connecting port is not large: the opening of the connecting pad is reduced as a conventional single large area The effect of severe depressions is such that the gold bumps formed by the present invention have a very flat surface. 1276212 [Embodiment] The details and technical description of the present invention are as follows:
請參閱「第6圖」所示，係本發明之玻璃覆晶封裝示 意圖。該玻璃覆晶封裝包括一驅動集成電路(IC)21，且該 驅動集成電路21上具有複數金凸塊(g〇id bump)211 ;—破 璃基板23，且該玻璃基板23上具複數個與該些金凸塊 (goldbump)211對應數目及位置之導電薄膜形成之電極 231 , —異向導電膜22及，該異向導電膜(Anisotropic Conductive Film，ACF)22 由黏合劑（binder)221 及為於其 中粒徑約3〜4/zm之小粒徑之導電粒子(c〇nductive pardcleS)222組成。其中，該玻璃覆晶封裝係將驅動集成 電路21之金凸塊211藉由該導電粒子222與該玻璃基板 23之電極231實現電性連接，並由黏合劑221將驅動集成 電路21與玻璃基板23黏合。 本發明主要係一種電性連接塾結構，係對於該驅動集 成電路之電性連接塾結構做—改進，讓玻璃覆晶封裝 的過程中該些導電粒子222不會有壓的不夠破之情況，而 該玻璃基板23之電極231與金凸塊叫間的接觸面積夠， 具有良好的電性連接效果。 ' -月再多閱第7圖」該驅動集成電路以之電性連接 塾示意圖，該驅動集成電路21設有做為對外 212。一絕緣層213設置於該連接墊212 層213經由黃光製程形成複數個小 ，且u絕緣 乂设歡1 j面積之連接墊開口部 ⑧ 1276212 (padopen)214，藉由該些連接墊開口部2l 、 m表面(請再參閱「第8圖」所示)’其中:些二 口部214間互不相連接，且該些連接墊開口部區汗 總面積須使該金凸塊211與該電極231 L A 2之 電性 j具有標準之連接 而該金凸塊211形成該絕緣層213卜士 上方，透過該連接 墊開口部214與該連接墊212電性連接。其中該金凸塊2ΐι # 之材料係為銅、錄與金三者任選其一，或錫錯Λ合金，以電 鍍製程形成，厚度係介於15〜18em之間。 本發明之特徵在於將習知原本大面積之連接塾開口 部(pad〇pen)114 (如「第5圖」所示）結構改為複^個小 面積之連接塾開口部214 (如「第8圖」所示）。藉此舍該 .金凸塊2η形成於該些連接塾開口部214及其週缘 層213上時，因為單一小面積之連接墊開口部214之週邊 的絕緣層213厚度對該金凸塊231表面2141下凹陷之影 • 響將不到l//m。加上電鍍製程因素而於同—平面上產生 表面±l//m的電鑛落差，該金凸塊211之表面2141最高 與彔低處的高度落差將不到2 // m，也就是說該金凸塊211 之表面2141是非常平坦的（extra flat)。 本發明藉由複數個連接墊開口部214取代習之的單— 連接墊開口部（pad open)l 14改善習知下陷之現象，但因為 未開口之絕緣層213上表面依然是一平面樣態，在該金凸 塊211與該電極231間具有產業標準之連接電性原則下， 藉由調整總開口（複數個連接墊開口部214之區域面積）與 1276212 • 尚具絕緣層213之未開口之區域面積之比例，可兼顧該金 凸塊211與該電極231間之連接電性及改良該金凸塊211 表面2141之平坦化。 在一般產業標準中，該金凸塊211與該破璃基板23 之電極231的連接中需壓破五粒以上之導電粒子222，才 算是有足夠之電性接觸面積，具良好的電性連接效果。所 以本發明所形成於驅動集成電路21之電性連接墊，因為 複數個小面積之連接墊開口部214 ,使的該金凸塊211之 瞻表面2141非常平坦的（extraflat)，所以當該導電粒子222 為粒徑是3〜4/zm之小粒徑時，在玻璃覆晶封裝之壓接製 程中，該小粒徑導電粒子222將不會有壓的不夠破、接觸 面積不夠之習知缺失，使得連接的電極間具有良好的電性 連接效果。 而經過本發明之電性連接墊結構因為前述小粒徑導 電粒子222的壓破問題得以解決，所以在每一個金凸塊211 φ 間的間距(pitch)，以產業標準該間距需大於導電粒子222 粒徑三倍以上之標準。即在不需改變製程的情況下，本發 明就可選用具小粒徑之導電粒子222的異向導電膜22，以 粒徑3//m之導電粒子222而言，該各個金凸塊211間距 (pitch)可縮小到ι〇μιη，該也就是達到細間距（finepitch) 之目標，同時可增加驅動集成電路上電路的集積度。 惟上述僅為本發明之較佳實施例而已，並非用來限定 本發明實施之範圍。即凡依本發明申請專利範圍所做的均 等變化與修飾，皆為本發明專利範圍所涵蓋。 ⑧ 1276212 【圖式簡單說明】 第1圖，係一種先前技術之玻璃覆晶封裝之壓接示意圖。 第2圖，係玻璃覆晶封裝示意圖。 第3圖，係導電粒子接觸而短路之示意圖。 第4圖，係習知驅動集成電路之電性連接墊示意圖。 第5圖，係第4圖所示之連接墊開口結構示意圖。 第6圖，係本發明之玻璃覆晶封裝示意圖。 第7圖，係本發明之驅動集成電路之電性連接墊示意圖。 第8圖，係第7圖所示之連接墊開口結構示意圖。 【主要元件符號說明】 11、 21 ： 驅動集成電路 111 、211 :金凸塊 112 、212 :連接墊 113 、213 _·絕緣層 114 、214 :連接墊開口部 1141、2141 :表面 12、 22 ： 異向導電膜 121 、221 :黏合劑 122 、222 :導電粒子 13、 23 ： 玻璃基板 131 、231 :電極 14 ： 短路 ⑧Please refer to Fig. 6 for the purpose of the glass flip chip package of the present invention. The glass flip chip package includes a driving integrated circuit (IC) 21, and the driving integrated circuit 21 has a plurality of gold bumps 211; a glass substrate 23, and the glass substrate 23 has a plurality of An electrode 231 formed of a conductive film corresponding to the number and position of the gold bumps 211, an anisotropic conductive film 22, and an anisotropic conductive film (ACF) 22 are bonded by a binder 221 And consisting of conductive particles (c〇nductive pardcleS) 222 having a particle size of about 3 to 4/zm. The glass flip-chip package electrically connects the gold bumps 211 of the driving integrated circuit 21 with the electrodes 231 of the glass substrate 23 by the conductive particles 222, and drives the integrated circuit 21 and the glass substrate by the adhesive 221 23 bonding. The invention is mainly an electrical connection structure, which is improved for the electrical connection structure of the driving integrated circuit, so that the conductive particles 222 do not have insufficient pressure during the process of glass flip-chip packaging. The contact area between the electrode 231 of the glass substrate 23 and the gold bump is sufficient, and has a good electrical connection effect. '-More than the seventh month, the driver IC is electrically connected to the schematic diagram, and the driver integrated circuit 21 is provided as the external 212. An insulating layer 213 is disposed on the layer 213 of the connection pad 212 to form a plurality of connection pad openings 8 1276212 (padopen) 214 through the yellow light process, and the opening of the connection pads 2l, m surface (please refer to "Fig. 8")" where: the two ports 214 are not connected to each other, and the total area of the sweat in the opening area of the connection pad is such that the gold bump 211 and the The electrical connection j of the electrode 231 LA 2 has a standard connection, and the gold bump 211 forms the upper portion of the insulating layer 213, and is electrically connected to the connection pad 212 through the connection pad opening portion 214. The material of the gold bump 2ΐι# is selected from the group consisting of copper, recording and gold, or tin-tin alloy, formed by electroplating, and the thickness is between 15 and 18 cm. The present invention is characterized in that the structure of the conventional large-area connecting port opening portion 114 (as shown in FIG. 5) is changed to a plurality of small-area connecting port openings 214 (eg, Figure 8). Therefore, when the gold bumps 2n are formed on the connection opening portions 214 and the peripheral layer 213 thereof, the thickness of the insulating layer 213 around the periphery of the connection pad opening portion 214 of a single small area is the thickness of the gold bumps 231. The shadow of the depression on the surface 2141 • The sound will be less than l//m. In addition to the electroplating process factor, the surface of the gold bump 211 has a height difference of ±1/m, and the height of the surface 2141 of the gold bump 211 is less than 2 // m. The surface 2141 of the gold bump 211 is extra flat. The present invention improves the conventional sag phenomenon by replacing a plurality of pad openings 214 with a plurality of pad openings 214, but since the upper surface of the unopened insulating layer 213 is still a planar state Under the principle of the industry standard connection between the gold bump 211 and the electrode 231, by adjusting the total opening (area area of the plurality of connection pad openings 214) and 1276212, there is still no opening of the insulating layer 213. The ratio of the area of the area can balance the connection between the gold bump 211 and the electrode 231 and improve the planarization of the surface 2141 of the gold bump 211. In the general industry standard, in the connection between the gold bump 211 and the electrode 231 of the glass substrate 23, it is necessary to crush five or more conductive particles 222, so that it has sufficient electrical contact area and has good electrical connection effect. . Therefore, the present invention is formed on the electrical connection pad of the driving integrated circuit 21, because the plurality of small-area connection pad opening portions 214 make the surface 2141 of the gold bump 211 extremely flat, so when the conductive When the particle 222 is a small particle diameter of 3 to 4/zm, in the crimping process of the glass flip-chip package, the small-diameter conductive particle 222 will not be insufficiently broken and the contact area is insufficient. Missing, so that the connected electrodes have a good electrical connection effect. However, the electrical connection pad structure of the present invention is solved because the above-mentioned crushing problem of the small-diameter conductive particles 222 is solved, so the pitch between each gold bump 211 φ needs to be larger than the conductive particles by the industry standard. 222 The standard of more than three times the particle size. That is, in the case where the process is not changed, the present invention can select the anisotropic conductive film 22 of the small-sized conductive particles 222, and the conductive bumps 222 having a particle diameter of 3/m, the respective gold bumps 211 The pitch can be reduced to ι〇μιη, which is the goal of fine pitch, while increasing the accumulation of circuitry on the driver IC. The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. That is, the equivalent changes and modifications made by the scope of the patent application of the present invention are covered by the scope of the invention. 8 1276212 [Simple description of the drawings] Fig. 1 is a schematic view of a prior art glass flip chip package. Figure 2 is a schematic diagram of a glass flip chip package. Fig. 3 is a schematic view showing short-circuiting of conductive particles in contact. Figure 4 is a schematic diagram of an electrical connection pad of a conventional driver integrated circuit. Fig. 5 is a schematic view showing the structure of the opening of the connection pad shown in Fig. 4. Figure 6 is a schematic view of the glass flip chip package of the present invention. Figure 7 is a schematic view showing an electrical connection pad of the driving integrated circuit of the present invention. Fig. 8 is a schematic view showing the structure of the opening of the connection pad shown in Fig. 7. [Description of main component symbols] 11, 21: Driver integrated circuits 111, 211: gold bumps 112, 212: connection pads 113, 213 - insulating layers 114, 214: connection pad opening portions 1141, 2141: surfaces 12, 22: Anisotropic conductive films 121, 221: adhesives 122, 222: conductive particles 13, 23: glass substrates 131, 231: electrodes 14: short circuit 8