JP4075204B2 - Multilayer semiconductor device - Google Patents

Multilayer semiconductor device Download PDF

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Publication number
JP4075204B2
JP4075204B2 JP10227999A JP10227999A JP4075204B2 JP 4075204 B2 JP4075204 B2 JP 4075204B2 JP 10227999 A JP10227999 A JP 10227999A JP 10227999 A JP10227999 A JP 10227999A JP 4075204 B2 JP4075204 B2 JP 4075204B2
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semiconductor device
semiconductor
carrier substrate
semiconductor element
stacked
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JP2000294723A (en
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和弘 石川
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve a heat radiation characteristic by electrically connecting a first semiconductor device and a second semiconductor device, and sealing the outer surrounding of the first and second semiconductor devices with resin so that a metal plate installed on the second semiconductor device is exposed. SOLUTION: For electrically introducing an electric signal from a second semiconductor element 5 to a user substrate, an electrode terminal 16 at an outer peripheral part on the rear face of the semiconductor carrier substrate 8b of the second semiconductor element 5 is bonded to a bonding pad part 17 installed at the outer peripheral part of the surface face of a semiconductor carrier substrate 8a in a first semiconductor element 1 at a stacked lower side by metallic thin wire 13. A metallic plate 18 is arranged in the almost center part of the rear face 8b of a semiconductor carrier substrate 8b on the side of the second semiconductor element 5. The upper area of the semiconductor carrier substrate 8a is sealed with potting sealing resin 19 so that the metallic plate 18 is not covered.

Description

【０００１】
【発明の属する技術分野】
本発明は、フリップチップ実装工法で実装した半導体装置どうしまたは、フリップチップ実装工法の半導体装置と、もう一つ別の半導体装置（外周部に電気的接続が取れる電極端子部を有している半導体装置）とが放熱性接着剤を介して、接着させた積層型の半導体装置に関するもので、特に、積層化した半導体装置の放熱性の向上化を図り、半導体装置の大容量化・高機能化・高信頼性化を実現することができることを目的とした積層型半導体装置に関するものである。また、従来のフリップチップ実装構造の半導体装置を個々に実装することよりも、更に、高密度実装化を実現することができることを特徴とした積層型半導体装置とその製造方法に関するものである。
【０００２】
【従来の技術】
一般的に積層型半導体装置は、複数の半導体装置を積層化するため、技術的に放熱特性が重要課題となっている。従来の積層型半導体装置は、リードフレーム上下に、２種類の半導体素子を搭載し、ワイヤーボンディングにより電気的に接続し、半導体素子全体をモールド封止しているなどの構造であり、筐体を通じて、電子機器のシステム本体への熱放散させる機構が十分でない構造であった。
【０００３】
以下、図面を参照して従来の積層型半導体装置の構造例について説明する。図５および図６は、従来の積層型半導体装置を示す断面図である。
【０００４】
まず図５に示すような積層型半導体装置は、第１の半導体素子１の電極（図示せず）に金などのバンプ２を形成し、このバンプ２に銅材よりなるリード３をインナーボンディングし、続いて、そのリード３をリードフレーム４にアウターボンディングを施して接続する。さらに、リードフレーム４を裏返しにして、第２の半導体素子５に、再び前記の処理を施すことにより、第２の半導体素子５のバンプ２とリードフレーム４との間を銅材のリ−ド３で接続する。その後、封止樹脂６により樹脂モールドを施こし、リードフレーム４を必要な形状に成形加工し、樹脂封止型の積層型半導体装置を構成している。
【０００５】
次に、従来の積層型半導体装置として別の例を図６に示している。図６は従来の積層型半導体装置を示す断面図である。
【０００６】
図６に示すように、従来のフリップチップ実装型の積層型半導体装置は、その主面の電極パッド７にバンプ２が形成された第１の半導体素子１が、その主面を下にして（フリップチップ）、支持体であるセラミックを絶縁基体とした多層回路基板よりなる半導体キャリア基板８上の複数の電極９とが半田あるいは導電性接着剤等により接合されている。そして、接合された第１の半導体素子１と半導体キャリア基板８との隙間には、エポキシ系の封止樹脂６が充填封止されている。なお、半導体キャリア基板８は、その裏面に外部端子１０を有し、電極９と外部端子１０とは半導体キャリア基板８内に形成されたビア(図示せず）により、内部接続されている。そしてもう一つ別の第２の半導体素子５が、半田または導電性接着剤１１等を介して、第１の半導体素子１の裏面と接合されており、この第２の半導体素子５の表面の電極パッド７から、半導体キャリア基板８の表面外周部にあるボンディングパッド１２に金属細線１３でボンディングされている。そして第１の半導体素子１、第２の半導体素子５および金属細線１３を含む半導体キャリア基板８の上面側を封止樹脂６で樹脂モールドして積層型半導体装置を構成している。
【０００７】
【発明が解決しようとする課題】
しかしながら前記従来の積層型半導体装置の構造では、発熱体である半導体素子からの発熱を、電子機器システム内の筐体を通じて効率良く、且つ十分に放散させるための高放熱システム機能が組み込まれておらず、消費電力が高い仕様の半導体素子を積層化した半導体装置に組み込んだ場合、急激な半導体素子の温度上昇により半導体素子が破壊し、その積層型半導体装置が動作しなくなるといった不具合が発生する。そのため、高放熱仕様の積層型半導体装置の実現を図ることが重要であり、且つ大容量化し、高機能化した積層型半導体装置の実現が必要不可欠であった。
【０００８】
本発明は、前記従来の課題を解決するもので、複数の半導体素子より発生する熱の放熱特性を向上させ、積層型半導体装置の信頼性の向上化を図ることはもちろん、従来の２つの半導体素子を個々に実装する場合に比べ信号遅延が小さく、且つ実装面積を縮小化することもできる半導体装置を提供することを目的とする。
【０００９】
【課題を解決するための手段】
前記課題を解決するために本発明の積層型半導体装置は、以下のような構成を有している。すなわち、概念的には、少なくとも第１の半導体装置と第２の半導体装置とよりなり、互いの半導体装置どうしを放熱性接着剤を介して積層化して接合した積層型半導体装置であって、前記第１の半導体装置上に第２の半導体装置が積層され、前記第１の半導体装置と第２の半導体装置とが電気的に接続され、前記第２の半導体装置上に放熱用の金属製プレート板が設けられ、前記金属製プレート板が露出するように、前記第１の半導体装置と前記第２の半導体装置との外囲を封止樹脂で封止した積層型半導体装置である。
【００１０】
また、本発明の積層型半導体装置は、底面に外部端子を有し、上面に前記外部端子と基板内接続した電極を有した絶縁性回路基板よりなる第１の半導体キャリア基板と、前記電極に対応してその主面の電極パッドがバンプを介して接合された第１の半導体素子とよりなる第１の半導体装置と、底面に外部端子を有し、上面に前記外部端子と基板内接続した電極を有した絶縁性回路基板よりなる第２の半導体キャリア基板と、前記電極に対応してその主面の電極パッドがバンプを介して接合された第２の半導体素子とよりなる第２の半導体装置とが放熱性接着剤を介して積層化して接合した積層型半導体装置であって、前記第１の半導体素子の裏面と第２の半導体素子の裏面とが接合され、前記第２の半導体キャリア基板の底面の外部端子と前記第１の半導体キャリア基板の上面の電極とが金属細線で電気的に接続され、前記第２の半導体キャリア基板の底面上に放熱用の金属製プレート板が設けられ、前記金属製プレート板が露出するように、前記第１の半導体キャリア基板の上面領域の前記第２の半導体装置を含む領域を封止樹脂で封止した積層型半導体装置である。
【００１１】
また、底面に外部端子を有し、上面に前記外部端子と基板内接続した電極を有した絶縁性回路基板よりなる第１の半導体キャリア基板と、前記電極に対応してその主面の電極パッドがバンプを介して接合された第１の半導体素子とよりなる第１の半導体装置と、底面に外部端子を有し、上面に前記外部端子と基板内接続した電極を有した絶縁性回路基板よりなる第２の半導体キャリア基板と、前記電極に対応してその主面の電極パッドがバンプを介して接合された第２の半導体素子とよりなる第２の半導体装置とが放熱性接着剤を介して積層化して接合した積層型半導体装置であって、前記第１の半導体素子の裏面と第２の半導体キャリア基板の底面とが金属製プレート板を介して前記放熱性接着剤により接合され、前記第２の半導体キャリア基板の上面の電極と前記第１の半導体キャリア基板の上面の電極とが金属細線で電気的に接続され、前記第１の半導体キャリア基板の上面領域の前記第２の半導体装置を含む領域を封止樹脂で封止した積層型半導体装置である。
【００１２】
さらに具体的には、第１の半導体素子と第１の半導体キャリア基板との間隙、および第２の半導体素子と第２の半導体キャリア基板との間隙には、それぞれ樹脂が充填封止されている積層型半導体装置である。
【００１３】
本発明の積層型半導体装置の製造方法においては、第１の半導体素子の主面の電極パッドにバンプを形成し、そのバンプの先端部に導電性接着剤を形成し、第２の半導体素子の電極パッドにバンプを形成し、その先端部に導電性接着剤を形成する工程と、前記第１の半導体チップをその主面側を下にして第１の半導体キャリア基板の上面の電極に対応させ、バンプ上の導電性接着剤を介して接合し、第２の半導体チップをその主面側を下にして第２の半導体キャリア基板の上面の電極に対応させ、バンプ上の導電性接着剤を介して接合する工程と、前記第１の半導体素子と第１の半導体キャリア基板との間隙に封止樹脂を注入して充填封止し、前記第２の半導体素子と第２の半導体キャリア基板との間隙に封止樹脂を注入して充填封止する工程と、前記第２の半導体素子側の第２の半導体キャリアの裏面の略中央部に対して、放熱性接着剤を用いて、放熱用の金属製プレート板を接合する工程と、前記第１の半導体キャリアに接合された第１の半導体素子の裏面と、第２の半導体キャリア基板が接合された第２の半導体素子の裏面とを放熱性接着剤により接合して積層構造を構成する工程と、前記第２の半導体素子が接合された第２の半導体キャリアの電極端子と前記第１の半導体キャリアの上面のボンディングパッド部とを金属細線により電気的に接続する工程と、前記金属製プレート板が被らないように、前記第１の半導体キャリア基板の上面領域をポッティング封止樹脂で封止し、前記第１の半導体素子、第２の半導体素子および金属細線による接続領域を封止する工程とよりなる積層型半導体装置の製造方法である。
【００１４】
前記構成の通り、放熱用の金属製プレート板、放熱性接着剤を用いているので、発熱体である２種の半導体素子からの熱エネルギ−を、電子機器内の筐体を通じて効率良く熱放散することにより、積層化した半導体装置の高放熱化が図れるものである。これにより、急激な半導体装置の温度上昇による半導体装置の破壊を防止し、半導体装置の大容量化・高速化及び更なる高密度実装化等が実現できるものである。
【００１５】
【発明の実施の形態】
本発明の積層型半導体装置は、放熱性接着剤により２つの半導体装置を接合し、上側の半導体装置に放熱用の部材、例えば金属製プレート板を設けたものであり、少なくとも第１の半導体装置と第２の半導体装置とよりなり、互いの半導体装置どうしを放熱性接着剤を介して積層化して接合した積層型半導体装置であって、第１の半導体装置上に第２の半導体装置が積層され、その第１の半導体装置と第２の半導体装置とが電気的に接続され、また第２の半導体装置上に放熱用の金属製プレート板が設けられ、その金属製プレート板が露出するように、第１の半導体装置と第２の半導体装置との外囲を封止樹脂で封止した構成を有するものである。
【００１６】
以下、本発明の積層型半導体装置およびその製造方法の一実施形態について図面を参照しながら説明する。
【００１７】
まず第１の実施形態にかかる積層型半導体装置について説明する。図１は本実施形態の積層型半導体装置を示す断面図である。なお図１において、図１（ａ）は断面図であって、図１（ｂ）は図１（ａ）の破線円の部分を拡大した図である。
【００１８】
図１に示すように本実施形態の積層型半導体装置は、その主面の電極パッド７にバンプ２の形成された第１の半導体素子１がその主面側を下にして、支持体であるセラミックを絶縁基体とした多層回路基板より成る半導体キャリア基板８ａに接合されている。ここで第１の半導体素子１上に形成されたバンプ２と半導体キャリア基板８ａ上の複数の電極９ａとが半田あるいは導電性接着剤１４等により接合されている。そして接合された第１の半導体素子１と半導体キャリア基板８ａとの隙間には、エポキシ系の封止樹脂６が充填封止されている。なお、半導体キャリア基板８ａはその裏面に外部端子１０を有し、電極９ａと外部端子１０とは、半導体キャリア基板８ａ内に形成されたビア（図示せず）により内部接続されているものである。そして第１の半導体素子１の裏面側に放熱性接着剤１５を介して第２の半導体素子５がその裏面側で接合されており、この第２の半導体素子５もまた第１の半導体素子の実装構造と同様に、その主面の電極パッド７にバンプ２の形成された第２の半導体素子５がその主面側を下にして、支持体であるセラミックを絶縁基体とした多層回路基板より成る半導体キャリア基板８ｂに接合されている。そして同様に、第２の半導体素子５上に形成されたバンプ２と半導体キャリア基板８ｂ上の複数の電極９ｂとが半田あるいは導電性接着剤等１４により接合されている。そして接合された第２の半導体素子５と半導体キャリア基板８ｂとの隙間には、エポキシ系の封止樹脂６が充填封止されている。なお、半導体キャリア基板８ｂはその裏面に外部端子１０を有し、電極９ｂと外部端子１０とは、半導体キャリア基板８ｂ内に形成されたビア（図示せず）により内部接続されているものである。
【００１９】
また、積層化した２種の半導体素子のうち、第２の半導体素子５からの電気的信号を電気的にユーザ基板へ導くため、第２の半導体素子５の半導体キャリア基板８ｂ裏面の外周部にある電極端子１６から、積層化した下側にある第１の半導体素子１の半導体キャリア基板８ａの表層面外周部に設けたボンディングパッド部１７へ金線等の金属細線１３でボンディングしているものである。そして第２の半導体素子５側の半導体キャリア基板８ｂの裏面の略中央部には、放熱用の金属メッキ層または金属製プレート板１８が設けられているものである。
【００２０】
そして金属製プレート板1８が被さらないように、半導体キャリア基板８ａの上面領域をポッティング封止樹脂１９で封止しているものである。
【００２１】
なお、半導体キャリア８ｂの略中央部に設けた放熱用の金属製プレート板１８の上面には、マークインク２０で積層化した半導体装置の製品品番や密番等をマーキング捺印しているものである。また、半導体キャリア基板８ａはポッティング封止樹脂１９がはみ出さないように、基板の周囲には上方に突出した枠部が形成されているものである。
【００２２】
以上のように、フリップチップ実装構造の２つの半導体装置をその互いの半導体素子１，５の裏面どうしを合わせて、放熱性接着剤１５を介して積層化し、接合されているものである。この構造により、実装面積を低減し、かつ放熱特性を向上させた積層型半導体装置が得られるものである。
【００２３】
次に本実施形態の積層型半導体装置の製造方法について、同図をもとに説明する。
【００２４】
まず、個々に、第１の半導体素子１の主面の電極パッド７にバンプ２を形成し、そのバンプ２の先端部に導電性接着剤１４を転写法により形成する。同様に第２の半導体素子５の電極パッド７にもバンプ２を形成し、その先端部に導電性接着剤１４を転写法により形成する。
【００２５】
次に、個々に第１の半導体チップ１をその主面側を下にして半導体キャリア基板８ａの電極９ａに対応させ、バンプ２上の導電性接着剤１４を介して接合する。同様に第２の半導体チップ５をその主面側を下にして半導体キャリア基板８ｂの電極９ｂに対応させ、バンプ２上の導電性接着剤１４を介して接合する。なお、半導体素子と半導体キャリアとの接合においては、導電性接着剤１４の硬化のために所定条件で加熱処理を行う。
【００２６】
次に、個々に第１の半導体素子１と半導体キャリア基板８ａとの間隙に封止樹脂６を注入して充填封止する。同様に第２の半導体素子５と半導体キャリア基板８ｂとの間隙に封止樹脂６を注入して充填封止する。通常、封止樹脂６に用いる樹脂は熱硬化型であるため、樹脂注入して加熱し、樹脂を熱硬化させて封止する。
【００２７】
次に、第２の半導体素子５側の半導体キャリア８ｂの裏面の略中央部に対して、放熱性接着剤を用いて、放熱用の金属製プレート板１８を接合する。または金属製プレート板１８の代わりに、金属メッキ層を形成してもよい。なお、ここで、放熱用の金属製プレート板１８を半導体キャリア基板８ｂ裏面の中央部付近に接合するのは、放熱特性を向上させるために熱伝導を均一にするためである。
【００２８】
次に、半導体キャリア８ａに接合された第１の半導体素子１の裏面と、半導体キャリア基板８ｂが接合された第２の半導体素子５の裏面とを放熱性接着剤１５により接合して積層構造を構成する。なお、この工程の後に前記工程で形成した放熱用の金属製プレート板１８を半導体キャリア８ｂの裏面に接合してもよい。
【００２９】
そして、第２の半導体素子５が接合された半導体キャリア８ｂの電極端子１６と半導体キャリア８ａのボンディングパッド部１７とを金属細線１３により電気的に接続する。
【００３０】
最後に金属製プレート板1８が被さらないように、半導体キャリア基板８ａの上面領域をポッティング封止樹脂１９で封止し、第１の半導体素子１、第２の半導体素子５および金属細線１３による接続領域を封止し、積層型半導体装置を得る。
【００３１】
また通常の製品製造工程では、積層型半導体装置の半導体キャリア８ｂの略中央部に設けた放熱用の金属製プレート板１８の上面に、マークインク２０で積層化した半導体装置の製品品番や密番等をマーキング捺印する。
【００３２】
次に本実施形態の積層型半導体装置を応用した実施形態について説明する。図２は本実施形態の積層型半導体装置を示す断面図である。
【００３３】
図２に示す積層型半導体装置は、図１に示した積層型半導体装置を基板に対して２つ並列に配置し、ＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）化した構成である。図２に示した構造は、図１に示した積層型半導体装置として、第１の積層型半導体装置２１と第２の積層型半導体装置２２とを１つの基板２３上に形成し、それら２つの積層型半導体装置を一体でポッティング封止樹脂１９で封止したものである。そして各積層型半導体装置から発生する熱を電子機器内の筐体２４を通じて放熱することが可能となり、更なる高密度実装化が図れるものである。これにより、例えば４種の半導体素子を積層化し、１つの基板に実装でき、高密度実装化を実現できる。なお、他の構成は図１に示した構成と同じである。
【００３４】
次に本実施形態の積層型半導体装置を応用した別の実施形態について説明する。図３は本実施形態の積層型半導体装置を示す断面図である。
【００３５】
図３に示す積層型半導体装置は、図１に示した積層型半導体装置における上側の半導体装置として、図１のようにフリップチップ実装した半導体装置ではなく、パッケージ底面に外部電極２５が配列したモールド封止型の半導体装置２６を第１の半導体素子１の裏面に対して、放熱性接着剤１５により接合した構成である。なお、他の構成は図１に示した構成と同じである。図３の構成のように、フリップチップ実装した半導体装置どうしでなくとも積層型を構成し、半導体装置２６の裏面中央部に放熱用の金属製プレート板１８を設けることにより、電子機器の筐体へ放熱させることができるものであり、高密度実装を実現するとともに、放熱性を向上させることができる。
【００３６】
次に本実施形態の積層型半導体装置を応用した別の実施形態について説明する。図４は本実施形態の積層型半導体装置を示す断面図である。
【００３７】
図４に示す積層型半導体装置は、図１に示した積層型半導体装置における上側の半導体装置として、図１のように半導体素子の裏面どうしを放熱性接着剤により接合した半導体装置ではなく、上側の半導体装置において、半導体キャリア基板８ｂの裏面と第１の半導体素子１の裏面とを放熱性接着剤１５により接合したものであり、図１に示した構造において、上側の半導体装置が１８０度反転して接合した構造である。そして第１の半導体素子１の裏面の略中央部には、薄型の金属製プレート板２７を接合し、半導体キャリア基板８ｂの底面のその金属製プレート板２７と対応する部分には凹部２８が形成されて、金属製プレート板２７が入る構成であり、第１の半導体素子１の裏面、金属製プレート板２７と半導体キャリア基板８ｂの凹部２８とは放熱性接着剤１５により接合されている。なお、他の構成は図１に示した構成と同じである。この構成においても、高密度実装を実現するとともに、放熱性を向上させることができる。
【００３８】
なお、各実施形態において、同一の半導体キャリア８ａ上に種々の半導体装置を複数個積層させることもできるものである。
【００３９】
以上、本実施形態のような構成により、発熱体である２種の半導体素子からの熱エネルギ−を、電子機器内の筐体を通じて効率良く熱放散することにより、積層化した半導体装置の高放熱化が図れるものである。これにより、急激な半導体装置の温度上昇による半導体装置の破壊を防止し、半導体装置の大容量化・高速化及び更なる高密度実装化等が実現できるものである。
【００４０】
【発明の効果】
以上説明したように、本発明の積層型半導体装置は、フリップチップ実装工法で実装した半導体装置どうし、あるいはフリップチップ実装構造でなくても半導体装置裏面の外周部に電気的接続が取れる端子を設けている半導体装置（但し積層化する際、必ず上側に搭載される）と、フリップチップ実装構造の半導体装置（下側に搭載）とを積層化し、互いの半導体素子の裏面どうしを合わせて放熱性接着剤等を介して積層・接着するものである。
【００４１】
また、積層化した半導体装置における上側の半導体装置の半導体キャリア基板あるいは半導体装置の裏面中央部に設けた金属メッキ層または薄型の金属製プレート板が完全に露出されていることにより、発熱した半導体素子からの熱を電子機器システム内の筐体を通じて効率良く熱放散させることができるものである。
【００４２】
これにより、高密度実装化を実現する上で困難であった積層型半導体装置の大容量化・高機能化・高信頼性化等を実現することができるものである。また、個々の半導体装置をユーザ基板に実装するよりも、更に実装面積の縮小化が図れるだけでなく、電気信号の高速化も図ることができるものである。
【図面の簡単な説明】
【図１】本発明の一実施形態における積層型半導体装置を示す断面図
【図２】本発明の一実施形態における積層型半導体装置を示す断面図
【図３】本発明の一実施形態における積層型半導体装置を示す断面図
【図４】本発明の一実施形態における積層型半導体装置を示す断面図
【図５】従来の積層型半導体装置を示す断面図
【図６】従来の積層型半導体装置を示す断面図
【符号の説明】
１ 第１の半導体素子
２ バンプ
３ リード
４ リードフレーム
５ 第２の半導体素子
６ 封止樹脂
７ 電極パッド
８ 半導体キャリア基板
９ 電極
１０ 外部端子
１１ 導電性接着剤
１２ ボンディングパッド
１３ 金属細線
１４ 導電性接着剤
１５ 放熱性接着剤
１６ 電極端子
１７ ボンディングパッド部
１８ 金属製プレート板
１９ 封止樹脂
２０ マークインク
２１ 第１の半導体装置
２２ 第２の半導体装置
２３ 半導体キャリア基板
２４ 筺体
２５ 外部電極
２６ 半導体装置
２７ 金属製プレート板
２８ 凹部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices mounted by a flip chip mounting method or semiconductor devices of a flip chip mounting method and another semiconductor device (a semiconductor having an electrode terminal portion that can be electrically connected to the outer peripheral portion). Devices) are related to stacked semiconductor devices that are bonded via heat-dissipating adhesives. In particular, the heat dissipation of stacked semiconductor devices is improved, and the capacity and functionality of semiconductor devices are increased. The present invention relates to a stacked semiconductor device intended to realize high reliability. The present invention also relates to a stacked semiconductor device and a method for manufacturing the same, which can realize higher-density mounting than mounting individual semiconductor devices having a conventional flip chip mounting structure.
[0002]
[Prior art]
Generally, in a stacked semiconductor device, a plurality of semiconductor devices are stacked, and thus, heat dissipation characteristics are an important issue technically. A conventional stacked semiconductor device has a structure in which two types of semiconductor elements are mounted on the top and bottom of a lead frame, electrically connected by wire bonding, and the entire semiconductor element is molded and sealed. The structure for dissipating heat to the system body of the electronic device is not sufficient.
[0003]
Hereinafter, a structural example of a conventional stacked semiconductor device will be described with reference to the drawings. 5 and 6 are cross-sectional views showing a conventional stacked semiconductor device.
[0004]
First, in the stacked semiconductor device as shown in FIG. 5, a bump 2 such as gold is formed on an electrode (not shown) of the first semiconductor element 1, and a lead 3 made of a copper material is bonded to the bump 2 by inner bonding. Subsequently, the lead 3 is connected to the lead frame 4 by performing outer bonding. Further, the lead frame 4 is turned over and the second semiconductor element 5 is subjected to the above-described process again, so that a lead of copper material is provided between the bump 2 of the second semiconductor element 5 and the lead frame 4. Connect with 3. Thereafter, a resin mold is applied with the sealing resin 6, and the lead frame 4 is formed into a required shape to constitute a resin-sealed stacked semiconductor device.
[0005]
Next, another example of a conventional stacked semiconductor device is shown in FIG. FIG. 6 is a cross-sectional view showing a conventional stacked semiconductor device.
[0006]
As shown in FIG. 6, in the conventional flip-chip mounting type stacked semiconductor device, the first semiconductor element 1 in which the bump 2 is formed on the electrode pad 7 on the main surface has the main surface facing down ( Flip chip) and a plurality of electrodes 9 on a semiconductor carrier substrate 8 made of a multilayer circuit board using ceramic as a support as an insulating base are joined together by solder or conductive adhesive. The gap between the bonded first semiconductor element 1 and the semiconductor carrier substrate 8 is filled and sealed with an epoxy-based sealing resin 6. The semiconductor carrier substrate 8 has an external terminal 10 on its back surface, and the electrode 9 and the external terminal 10 are internally connected by a via (not shown) formed in the semiconductor carrier substrate 8. Another second semiconductor element 5 is bonded to the back surface of the first semiconductor element 1 via solder or a conductive adhesive 11 or the like. The electrode pads 7 are bonded to the bonding pads 12 on the outer peripheral portion of the surface of the semiconductor carrier substrate 8 with the fine metal wires 13. The upper surface side of the semiconductor carrier substrate 8 including the first semiconductor element 1, the second semiconductor element 5, and the fine metal wires 13 is resin-molded with a sealing resin 6 to constitute a stacked semiconductor device.
[0007]
[Problems to be solved by the invention]
However, the structure of the conventional stacked semiconductor device incorporates a high heat dissipation system function for efficiently and sufficiently dissipating heat generated from the semiconductor element as a heating element through the housing in the electronic device system. In the case where a semiconductor element having a high power consumption specification is incorporated in a stacked semiconductor device, there is a problem that the semiconductor element is destroyed due to a rapid rise in the temperature of the semiconductor element, and the stacked semiconductor device does not operate. Therefore, it is important to realize a stacked semiconductor device with high heat dissipation specifications, and it is indispensable to realize a stacked semiconductor device with high capacity and high functionality.
[0008]
The present invention solves the above-described conventional problems, and improves the heat dissipation characteristics of heat generated from a plurality of semiconductor elements to improve the reliability of the stacked semiconductor device, as well as the conventional two semiconductors. It is an object of the present invention to provide a semiconductor device in which a signal delay is small as compared with a case where elements are individually mounted and a mounting area can be reduced.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a stacked semiconductor device of the present invention has the following configuration. That is, conceptually, it is a stacked semiconductor device comprising at least a first semiconductor device and a second semiconductor device, wherein the semiconductor devices are stacked and bonded together via a heat-dissipating adhesive, A second semiconductor device is stacked on the first semiconductor device, the first semiconductor device and the second semiconductor device are electrically connected, and a metal plate for heat dissipation is provided on the second semiconductor device. A stacked semiconductor device in which a plate is provided and an outer periphery of the first semiconductor device and the second semiconductor device is sealed with a sealing resin so that the metal plate plate is exposed.
[0010]
Also, the stacked semiconductor device of the present invention includes a first semiconductor carrier substrate comprising an insulating circuit substrate having an external terminal on the bottom surface and an electrode connected to the external terminal and the substrate on the top surface, and the electrode Correspondingly, a first semiconductor device comprising a first semiconductor element in which electrode pads on its main surface are bonded via bumps, an external terminal on the bottom surface, and the external terminal on the top surface are connected within the substrate. A second semiconductor carrier substrate comprising a second semiconductor carrier substrate comprising an insulating circuit substrate having electrodes, and a second semiconductor element having electrode pads on its main surface bonded to the electrodes via bumps. A laminated semiconductor device in which a device is laminated and bonded via a heat-dissipating adhesive, wherein a back surface of the first semiconductor element and a back surface of a second semiconductor element are bonded, and the second semiconductor carrier Front terminal on the bottom of the board and front An electrode on the upper surface of the first semiconductor carrier substrate is electrically connected with a thin metal wire, a metal plate for heat dissipation is provided on the bottom surface of the second semiconductor carrier substrate, and the metal plate is exposed. Thus, a stacked semiconductor device in which a region including the second semiconductor device in the upper surface region of the first semiconductor carrier substrate is sealed with a sealing resin.
[0011]
A first semiconductor carrier substrate comprising an insulating circuit substrate having an external terminal on the bottom surface and an electrode connected to the external terminal on the substrate on the top surface; and an electrode pad on the main surface corresponding to the electrode From an insulating circuit board having a first semiconductor device comprising a first semiconductor element bonded via a bump, an external terminal on the bottom surface, and an electrode connected to the external terminal on the top surface on the top surface A second semiconductor carrier substrate, and a second semiconductor device comprising a second semiconductor element corresponding to the electrode, the electrode pad of the main surface of which is bonded via a bump, via a heat-dissipating adhesive. In the stacked semiconductor device, the back surface of the first semiconductor element and the bottom surface of the second semiconductor carrier substrate are bonded by the heat-dissipating adhesive via a metal plate plate, Second semiconductor carrier An electrode on the upper surface of the substrate and an electrode on the upper surface of the first semiconductor carrier substrate are electrically connected by a thin metal wire, and a region including the second semiconductor device in the upper surface region of the first semiconductor carrier substrate is sealed. This is a stacked semiconductor device sealed with a stop resin.
[0012]
More specifically, the gap between the first semiconductor element and the first semiconductor carrier substrate and the gap between the second semiconductor element and the second semiconductor carrier substrate are filled and sealed with resin, respectively. This is a stacked semiconductor device.
[0013]
In the method for manufacturing a stacked semiconductor device according to the present invention, a bump is formed on the electrode pad on the main surface of the first semiconductor element, a conductive adhesive is formed on the tip of the bump, and the second semiconductor element Forming a bump on the electrode pad and forming a conductive adhesive at the tip thereof; and causing the first semiconductor chip to correspond to the electrode on the upper surface of the first semiconductor carrier substrate with the main surface side down. Bonding via a conductive adhesive on the bump, the second semiconductor chip is made to correspond to the electrode on the upper surface of the second semiconductor carrier substrate with the main surface side down, and the conductive adhesive on the bump is A step of bonding via a sealing resin, filling and sealing the gap between the first semiconductor element and the first semiconductor carrier substrate, filling the second semiconductor element and the second semiconductor carrier substrate, For filling and sealing by injecting sealing resin into the gap And a step of bonding a metal plate for heat dissipation to the substantially central portion of the back surface of the second semiconductor carrier on the second semiconductor element side using a heat dissipating adhesive, and the first Forming a laminated structure by bonding the back surface of the first semiconductor element bonded to the semiconductor carrier and the back surface of the second semiconductor element bonded to the second semiconductor carrier substrate with a heat-dissipating adhesive; Electrically connecting the electrode terminal of the second semiconductor carrier to which the second semiconductor element is bonded and the bonding pad portion on the upper surface of the first semiconductor carrier with a fine metal wire; and the metal plate plate Sealing an upper surface region of the first semiconductor carrier substrate with a potting sealing resin so as not to cover, and sealing a connection region of the first semiconductor element, the second semiconductor element, and the metal fine wire; Yo A method of manufacturing a stacked semiconductor device comprising.
[0014]
As described above, a metal plate for heat dissipation and a heat-dissipating adhesive are used, so that heat energy from two types of semiconductor elements, which are heating elements, can be efficiently dissipated through the housing in the electronic device. By doing so, the heat radiation of the stacked semiconductor devices can be increased. As a result, the semiconductor device can be prevented from being destroyed due to a rapid temperature rise of the semiconductor device, and the semiconductor device can be increased in capacity, speeded up, and mounted at a higher density.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The stacked semiconductor device of the present invention is obtained by joining two semiconductor devices with a heat-dissipating adhesive and providing a heat-dissipating member, for example, a metal plate plate, on the upper semiconductor device, and at least the first semiconductor device. And a second semiconductor device, in which the semiconductor devices are stacked and bonded together with a heat-dissipating adhesive, and the second semiconductor device is stacked on the first semiconductor device. The first semiconductor device and the second semiconductor device are electrically connected, and a metal plate plate for heat dissipation is provided on the second semiconductor device so that the metal plate plate is exposed. In addition, the outer periphery of the first semiconductor device and the second semiconductor device is sealed with a sealing resin.
[0016]
Hereinafter, an embodiment of a stacked semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
[0017]
First, the stacked semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view showing the stacked semiconductor device of this embodiment. In FIG. 1, FIG. 1A is a cross-sectional view, and FIG. 1B is an enlarged view of a broken-line circle portion of FIG.
[0018]
As shown in FIG. 1, in the stacked semiconductor device of this embodiment, the first semiconductor element 1 in which the bump 2 is formed on the electrode pad 7 on the main surface is the support with the main surface side down. It is bonded to a semiconductor carrier substrate 8a made of a multilayer circuit board using ceramic as an insulating base. Here, the bumps 2 formed on the first semiconductor element 1 and the plurality of electrodes 9a on the semiconductor carrier substrate 8a are joined together by solder or conductive adhesive 14 or the like. The gap between the bonded first semiconductor element 1 and the semiconductor carrier substrate 8a is filled and sealed with an epoxy-based sealing resin 6. The semiconductor carrier substrate 8a has an external terminal 10 on its back surface, and the electrode 9a and the external terminal 10 are internally connected by a via (not shown) formed in the semiconductor carrier substrate 8a. . And the 2nd semiconductor element 5 is joined to the back surface side of the 1st semiconductor element 1 via the heat dissipation adhesive 15 by the back surface side, This 2nd semiconductor element 5 is also 1st semiconductor element's. Similar to the mounting structure, the second semiconductor element 5 in which the bumps 2 are formed on the electrode pads 7 on the main surface thereof is from a multilayer circuit board using the ceramic as a support as an insulating base with the main surface side down. The semiconductor carrier substrate 8b is joined. Similarly, the bumps 2 formed on the second semiconductor element 5 and the plurality of electrodes 9b on the semiconductor carrier substrate 8b are joined by solder or conductive adhesive 14 or the like. The gap between the bonded second semiconductor element 5 and the semiconductor carrier substrate 8b is filled and sealed with an epoxy-based sealing resin 6. The semiconductor carrier substrate 8b has an external terminal 10 on its back surface, and the electrode 9b and the external terminal 10 are internally connected by a via (not shown) formed in the semiconductor carrier substrate 8b. .
[0019]
Moreover, in order to electrically guide the electrical signal from the second semiconductor element 5 to the user substrate among the two types of stacked semiconductor elements, the outer periphery of the back surface of the semiconductor carrier substrate 8b of the second semiconductor element 5 is provided. Bonded with a thin metal wire 13 such as a gold wire from a certain electrode terminal 16 to a bonding pad portion 17 provided on the outer peripheral portion of the surface of the semiconductor carrier substrate 8a of the first semiconductor element 1 on the lower layer. It is. A heat dissipating metal plating layer or metal plate 18 is provided at a substantially central portion of the back surface of the semiconductor carrier substrate 8b on the second semiconductor element 5 side.
[0020]
The upper surface region of the semiconductor carrier substrate 8a is sealed with a potting sealing resin 19 so that the metal plate plate 18 is not covered.
[0021]
Note that, on the upper surface of the heat dissipating metal plate 18 provided substantially at the center of the semiconductor carrier 8b, the product number or the serial number of the semiconductor device laminated with the mark ink 20 is marked and marked. . Further, the semiconductor carrier substrate 8a is formed with a frame portion protruding upward around the substrate so that the potting sealing resin 19 does not protrude.
[0022]
As described above, two semiconductor devices having a flip-chip mounting structure are laminated and bonded via the heat-dissipating adhesive 15 with the back surfaces of the semiconductor elements 1 and 5 being aligned with each other. With this structure, a stacked semiconductor device having a reduced mounting area and improved heat dissipation characteristics can be obtained.
[0023]
Next, a method for manufacturing the stacked semiconductor device of this embodiment will be described with reference to FIG.
[0024]
First, bumps 2 are individually formed on the electrode pads 7 on the main surface of the first semiconductor element 1, and a conductive adhesive 14 is formed on the tip of the bumps 2 by a transfer method. Similarly, bumps 2 are also formed on the electrode pads 7 of the second semiconductor element 5, and a conductive adhesive 14 is formed on the tip of the bumps 2 by a transfer method.
[0025]
Next, the first semiconductor chip 1 is individually bonded to the electrode 9a of the semiconductor carrier substrate 8a with the main surface side down, and is bonded via the conductive adhesive 14 on the bumps 2. Similarly, the second semiconductor chip 5 is bonded to the electrode 9b of the semiconductor carrier substrate 8b with the main surface side down through the conductive adhesive 14 on the bump 2. In joining the semiconductor element and the semiconductor carrier, heat treatment is performed under a predetermined condition in order to cure the conductive adhesive 14.
[0026]
Next, the sealing resin 6 is individually injected into the gap between the first semiconductor element 1 and the semiconductor carrier substrate 8a for filling and sealing. Similarly, a sealing resin 6 is injected into the gap between the second semiconductor element 5 and the semiconductor carrier substrate 8b to fill and seal. Usually, since the resin used for the sealing resin 6 is a thermosetting type, the resin is injected and heated, and the resin is thermoset and sealed.
[0027]
Next, a heat-dissipating metal plate 18 is joined to the substantially central portion of the back surface of the semiconductor carrier 8b on the second semiconductor element 5 side using a heat dissipating adhesive. Alternatively, a metal plating layer may be formed instead of the metal plate plate 18. Here, the metal plate 18 for heat dissipation is joined to the vicinity of the center of the back surface of the semiconductor carrier substrate 8b in order to make heat conduction uniform in order to improve heat dissipation characteristics.
[0028]
Next, the back surface of the first semiconductor element 1 bonded to the semiconductor carrier 8a and the back surface of the second semiconductor element 5 bonded to the semiconductor carrier substrate 8b are bonded by a heat dissipating adhesive 15 to form a laminated structure. Constitute. In addition, after this process, you may join the metal plate board 18 for heat dissipation formed at the said process to the back surface of the semiconductor carrier 8b.
[0029]
Then, the electrode terminal 16 of the semiconductor carrier 8b to which the second semiconductor element 5 is bonded and the bonding pad portion 17 of the semiconductor carrier 8a are electrically connected by the thin metal wire 13.
[0030]
Finally, the upper surface region of the semiconductor carrier substrate 8 a is sealed with a potting sealing resin 19 so as not to cover the metal plate plate 18, and the first semiconductor element 1, the second semiconductor element 5, and the fine metal wires 13 are used. The connection region is sealed to obtain a stacked semiconductor device.
[0031]
Further, in a normal product manufacturing process, the product number and the secret number of the semiconductor device laminated with the mark ink 20 on the upper surface of the heat-dissipating metal plate 18 provided substantially at the center of the semiconductor carrier 8b of the stacked semiconductor device. Mark with markings.
[0032]
Next, an embodiment in which the stacked semiconductor device of this embodiment is applied will be described. FIG. 2 is a cross-sectional view showing the stacked semiconductor device of this embodiment.
[0033]
The stacked semiconductor device shown in FIG. 2 has a configuration in which two stacked semiconductor devices shown in FIG. 1 are arranged in parallel with respect to a substrate to form an MCM (Multi Chip Module). In the structure shown in FIG. 2, the first stacked semiconductor device 21 and the second stacked semiconductor device 22 are formed on one substrate 23 as the stacked semiconductor device shown in FIG. The stacked semiconductor device is integrally sealed with a potting sealing resin 19. The heat generated from each stacked semiconductor device can be dissipated through the casing 24 in the electronic device, and further high-density mounting can be achieved. Thereby, for example, four types of semiconductor elements can be stacked and mounted on one substrate, and high-density mounting can be realized. Other configurations are the same as those shown in FIG.
[0034]
Next, another embodiment in which the stacked semiconductor device of this embodiment is applied will be described. FIG. 3 is a cross-sectional view showing the stacked semiconductor device of this embodiment.
[0035]
The stacked semiconductor device shown in FIG. 3 is not a flip chip mounted semiconductor device as shown in FIG. 1 as the upper semiconductor device in the stacked semiconductor device shown in FIG. 1, but a mold in which external electrodes 25 are arranged on the bottom of the package. The sealing type semiconductor device 26 is bonded to the back surface of the first semiconductor element 1 by the heat dissipating adhesive 15. Other configurations are the same as those shown in FIG. As in the configuration of FIG. 3, the semiconductor device 26 is configured as a stacked type even if not flip-chip mounted semiconductor devices, and a metal plate 18 for heat dissipation is provided at the center of the back surface of the semiconductor device 26, thereby It is possible to dissipate heat and realize high density mounting and improve heat dissipation.
[0036]
Next, another embodiment in which the stacked semiconductor device of this embodiment is applied will be described. FIG. 4 is a cross-sectional view showing the stacked semiconductor device of this embodiment.
[0037]
The stacked semiconductor device shown in FIG. 4 is not an upper semiconductor device in the stacked semiconductor device shown in FIG. 1, but a semiconductor device in which the back surfaces of the semiconductor elements are joined with a heat-dissipating adhesive as shown in FIG. In this semiconductor device, the back surface of the semiconductor carrier substrate 8b and the back surface of the first semiconductor element 1 are joined by the heat dissipating adhesive 15, and in the structure shown in FIG. It is the structure joined together. A thin metal plate plate 27 is joined to the substantially central portion of the back surface of the first semiconductor element 1, and a recess 28 is formed in a portion corresponding to the metal plate plate 27 on the bottom surface of the semiconductor carrier substrate 8b. Thus, the metal plate plate 27 is inserted, and the back surface of the first semiconductor element 1, the metal plate plate 27 and the concave portion 28 of the semiconductor carrier substrate 8 b are joined by the heat dissipating adhesive 15. Other configurations are the same as those shown in FIG. Even in this configuration, high-density mounting can be realized and heat dissipation can be improved.
[0038]
In each embodiment, a plurality of various semiconductor devices can be stacked on the same semiconductor carrier 8a.
[0039]
As described above, according to the configuration of the present embodiment, the heat energy from the two types of semiconductor elements as the heating elements is efficiently dissipated through the housing in the electronic device, so that high heat dissipation of the stacked semiconductor devices is achieved. Can be achieved. As a result, the semiconductor device can be prevented from being destroyed due to a rapid temperature rise of the semiconductor device, and the semiconductor device can be increased in capacity, speeded up, and mounted at a higher density.
[0040]
【The invention's effect】
As described above, the stacked semiconductor device according to the present invention is provided with terminals that can be electrically connected to each other between the semiconductor devices mounted by the flip-chip mounting method or at the outer peripheral portion of the back surface of the semiconductor device even if the flip-chip mounting structure is not used. Semiconductor device (which must be mounted on the upper side when stacking) and flip chip mounting structure (mounted on the lower side) are stacked, and the back surfaces of each semiconductor element are aligned to provide heat dissipation. It is laminated and bonded via an adhesive or the like.
[0041]
Also, the semiconductor element that generates heat by completely exposing the metal carrier layer of the upper semiconductor device in the stacked semiconductor device or the metal plating layer or the thin metal plate plate provided in the center of the back surface of the semiconductor device. Heat can be efficiently dissipated through the housing in the electronic device system.
[0042]
As a result, it is possible to realize a large capacity, high functionality, high reliability, etc. of the stacked semiconductor device, which has been difficult to realize high density mounting. In addition to mounting individual semiconductor devices on a user board, not only can the mounting area be further reduced, but also the speed of electrical signals can be increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a stacked semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a stacked semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a stacked semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing a conventional stacked semiconductor device. Sectional view showing [signs]
DESCRIPTION OF SYMBOLS 1 1st semiconductor element 2 Bump 3 Lead 4 Lead frame 5 2nd semiconductor element 6 Sealing resin 7 Electrode pad 8 Semiconductor carrier substrate 9 Electrode 10 External terminal 11 Conductive adhesive 12 Bonding pad 13 Metal wire 14 Conductive adhesion Agent 15 Heat Dissipating Adhesive 16 Electrode Terminal 17 Bonding Pad 18 Metal Plate Plate 19 Sealing Resin 20 Mark Ink 21 First Semiconductor Device 22 Second Semiconductor Device 23 Semiconductor Carrier Substrate 24 Housing 25 External Electrode 26 Semiconductor Device 27 Metal plate plate 28 recess

Claims (8)

表面に第１の電極と裏面に前記第１の電極と電気的に接続された第１の外部端子とを有する第１のキャリア基板と、前記第１のキャリア基板の表面に配置され、主面を下向きに前記第１の電極とフリップチップ接続した第１の半導体素子と、前記第１の半導体素子の裏面を露出するよう前記第１のキャリア基板と前記第１の半導体素子との間隙を封止する第１の封止樹脂とからなる第１の半導体装置と、
表面に第２の電極と裏面に前記第２の電極と電気的に接続された第２の外部端子とを有する第２のキャリア基板と、前記第２のキャリア基板の表面に配置され前記第２の電極と電気的に接続した第２の半導体素子と、前記第２のキャリア基板と前記第２の半導体素子とを封止する第２の封止樹脂とからなる第２の半導体装置とを備え、
前記第１の半導体装置上に前記第２の半導体装置が積層され、
前記第２の半導体装置の上面から露出する放熱部材を備え、
前記第１の半導体装置と前記第２の半導体装置とが電気的に接続されていることを特徴とする積層型半導体装置。A first carrier substrate having a first electrode on the front surface and a first external terminal electrically connected to the first electrode on the back surface; and a main surface disposed on the surface of the first carrier substrate. A first semiconductor element flip-chip connected to the first electrode and a gap between the first carrier substrate and the first semiconductor element so as to expose a back surface of the first semiconductor element. A first semiconductor device comprising a first sealing resin to be stopped;
A second carrier substrate having a second electrode on the front surface and a second external terminal electrically connected to the second electrode on the back surface; and the second carrier substrate disposed on the surface of the second carrier substrate. And a second semiconductor device comprising: a second semiconductor element electrically connected to the electrode; and a second sealing resin that seals the second carrier substrate and the second semiconductor element. ,
The second semiconductor device is stacked on the first semiconductor device;
A heat dissipation member exposed from the upper surface of the second semiconductor device;
A stacked semiconductor device, wherein the first semiconductor device and the second semiconductor device are electrically connected. 表面に第１の電極と裏面に前記第１の電極と電気的に接続された第１の外部端子とを有する第１のキャリア基板と、前記第１のキャリア基板の表面に配置され、主面を下向きに前記第１の電極とフリップチップ接続した第１の半導体素子と、前記第１の半導体素子の裏面を露出するよう前記第１のキャリア基板と前記第１の半導体素子との間隙を封止する第１の封止樹脂とからなる第１の半導体装置と、
表面に第２の電極と裏面に前記第２の電極と電気的に接続された第２の外部端子とを有する第２のキャリア基板と、前記第２のキャリア基板の表面に配置され前記第２の電極と電気的に接続した第２の半導体素子と、前記第２のキャリア基板と前記第２の半導体素子とを封止する第２の封止樹脂とからなる第２の半導体装置とを備え、
前記第１の半導体装置の前記第１の半導体素子の裏面上に放熱部材を介して前記第２の半導体装置が積層され、
前記第１の半導体装置と前記第２の半導体装置とが電気的に接続されていることを特徴とする積層型半導体装置。A first carrier substrate having a first electrode on the front surface and a first external terminal electrically connected to the first electrode on the back surface; and a main surface disposed on the surface of the first carrier substrate. A first semiconductor element flip-chip connected to the first electrode and a gap between the first carrier substrate and the first semiconductor element so as to expose a back surface of the first semiconductor element. A first semiconductor device comprising a first sealing resin to be stopped;
A second carrier substrate having a second electrode on the front surface and a second external terminal electrically connected to the second electrode on the back surface; and the second carrier substrate disposed on the surface of the second carrier substrate. And a second semiconductor device comprising: a second semiconductor element electrically connected to the electrode; and a second sealing resin that seals the second carrier substrate and the second semiconductor element. ,
The second semiconductor device is stacked on a back surface of the first semiconductor element of the first semiconductor device via a heat dissipation member ,
A stacked semiconductor device, wherein the first semiconductor device and the second semiconductor device are electrically connected. 前記第２の半導体装置は、前記第２の半導体素子が主面を下向きに前記第２のキャリア基板にフリップチップ接続し、前記第２の半導体素子の裏面を露出するように前記第２の封止樹脂が前記第２の半導体素子と前記第２のキャリア基板との間隙を樹脂封止していることを特徴とする請求項１または２に記載の積層型半導体装置。In the second semiconductor device, the second semiconductor element is flip-chip connected to the second carrier substrate with the main surface facing downward, and the second seal is exposed so that the back surface of the second semiconductor element is exposed. 3. The stacked semiconductor device according to claim 1, wherein a stop resin seals a gap between the second semiconductor element and the second carrier substrate . 4. 前記第２の半導体装置は、前記第２の半導体素子と前記第２のキャリア基板とが金属細線により電気的に接続されていることを特徴とする請求項１または２に記載の積層型半導体装置。  3. The stacked semiconductor device according to claim 1, wherein in the second semiconductor device, the second semiconductor element and the second carrier substrate are electrically connected by a thin metal wire. . 前記第１の半導体装置および前記第２の半導体装置は、前記第１の半導体素子の裏面と前記第２の半導体素子の裏面とが向かい合うように積層されていることを特徴とする請求項３に記載の積層型半導体装置。 Before SL first semiconductor device and the second semiconductor device, according to claim 3, characterized in that the rear surface of the first semiconductor element and the back surface of the second semiconductor element is laminated so as to face A stacked semiconductor device according to 1. 前記第１の半導体装置と前記第２の半導体装置とを第３の封止樹脂で封止したことを特徴とする請求項１または２に記載の積層型半導体装置。The stacked semiconductor device according to claim 1 or 2, characterized in that the said first semiconductor device and the second semiconductor device sealed with the third sealing resin. 前記第１の半導体装置と前記第２の半導体装置とを封止する第３の封止樹脂を備え、
前記放熱部材は前記第３の封止樹脂から露出していることを特徴とする請求項１に記載の積層型半導体装置。A third sealing resin for sealing the first semiconductor device and the second semiconductor device;
The stacked semiconductor device according to claim 1 , wherein the heat dissipation member is exposed from the third sealing resin. 前記第２のキャリア基板の前記第２の外部端子と前記第１のキャリア基板の前記第１の電極とを接続する金属細線を備え、
前記第１の半導体装置、前記第２の半導体装置および前記第２の外部端子と前記第１の電極とを接続する前記金属細線は、第３の封止樹脂によって封止されていることを特徴とする請求項３または４に記載の積層型半導体装置。A thin metal wire connecting the second external terminal of the second carrier substrate and the first electrode of the first carrier substrate;
Said first semiconductor device, the thin metal wire for connecting the said second semiconductor device and the second external terminal first electrode, characterized in that it is sealed by the third sealing resin The stacked semiconductor device according to claim 3 or 4 .
JP10227999A 1999-04-09 1999-04-09 Multilayer semiconductor device Expired - Fee Related JP4075204B2 (en)

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