KR101961377B1 - Land Grid Array semiconductor package - Google Patents

Land Grid Array semiconductor package Download PDF

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Publication number
KR101961377B1
KR101961377B1 KR1020150108804A KR20150108804A KR101961377B1 KR 101961377 B1 KR101961377 B1 KR 101961377B1 KR 1020150108804 A KR1020150108804 A KR 1020150108804A KR 20150108804 A KR20150108804 A KR 20150108804A KR 101961377 B1 KR101961377 B1 KR 101961377B1
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South Korea
Prior art keywords
chip stack
substrate
chip
pad
integrated
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KR1020150108804A
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Korean (ko)
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KR20170014845A (en
Inventor
송영희
이혁
송기홍
정준희
윤성식
Original Assignee
송영희
이혁
송기홍
정준희
윤성식
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Application filed by 송영희, 이혁, 송기홍, 정준희, 윤성식 filed Critical 송영희
Priority to KR1020150108804A priority Critical patent/KR101961377B1/en
Priority to PCT/KR2016/008434 priority patent/WO2017023060A1/en
Priority to CN201680042425.6A priority patent/CN108140636B/en
Priority to US15/746,100 priority patent/US10522522B2/en
Publication of KR20170014845A publication Critical patent/KR20170014845A/en
Application granted granted Critical
Publication of KR101961377B1 publication Critical patent/KR101961377B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

An LGA semiconductor package of the present invention comprises an integrated substrate, a bottom chip stack mounted on the integrated substrate, wherein a plurality of memory semiconductor dies are stacked on a chip-on-chip type to account for a portion of the total memory capacity, At least one or more top chip stacks stacked with a plurality of memory semiconductor dies stacked together to account for the remainder of the total memory capacity, an integrated wire for electrically connecting the bottom chip stack and the top chip stack, And an integrated protective member.

Description

A land grid array semiconductor package including a side pad on an edge thereof,

The present invention relates to an LGA package substrate, an LGA chip stack, and an LGA semiconductor package and an SSD including a side pad at an edge, more particularly, to a standardized trend of a solid state drive (SSD) Therefore, it is necessary to provide a high-speed and high-speed service despite the miniaturization of the package, and realize the LGA type NAND flash memory semiconductor package which is most suitable for the package. Even if the memory capacity required in the future is doubled, And a plurality of multi-chip memory chip stacks are integrally packaged by wire-bonding each substrate using a side pad on the side of the LGA package substrate, thereby realizing a NAND flash memory LGA semiconductor Package.

Recently, as the functions of electronic products are increased and the size is reduced, more semiconductor mounting is required in the same area. Therefore, the miniaturization of the electronic portable device and the various functions of the mobile product can not be satisfactorily accomplished with a simple chip stacking technique or package stacking technology.

FIG. 1 is a side view of a conventional 16-stage multichip package.

Referring to FIG. 1, one or more dies 14 are stacked in a conventional semiconductor NAND flash memory package 10. However, if mass production is considered, the number of stackable dies 14 is greatly limited. This causes capacity limitations in implementing a high-capacity semiconductor NAND flash memory.

Nevertheless, if the 16-stage stack is formed in view of the high-capacity memory trend, the electrical characteristics of the upper die 14, which are relatively far from the substrate 12, 16 have a longer length.

On the other hand, a package on package technology is introduced to improve the yield reduction.

FIG. 2 is a side view of a conventional BGA package on package.

Referring to FIG. 2, since the PoP package 20 connects the packages with each other by the ball grid array (BGA), the demand for the slimmer and miniaturization of the SSD by the solder ball 22 can not be realized.

(Patent Document 1) KR publication number 10-2010-0115268

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a NAND flash memory LGA semiconductor package capable of realizing high capacity and ultra- will be.

It is another object of the present invention to provide a NAND flash memory LGA semiconductor package in which a memory semiconductor die is arranged vertically and the electrical characteristics can be maintained while the package height is minimized even if the memory capacity is increased.

According to an aspect of the present invention, there is provided an LGA semiconductor package including an integrated substrate, a plurality of memory semiconductor dies stacked on a chip-on-chip type, At least one top chip stack mounted on the bottom package and stacked with a plurality of memory semiconductor dies for the remainder of the total memory capacity, at least one top chip stack, An integrated wire for electrically connecting the stack, and an integrated protection member for sealing the integrated wire.

According to another aspect of the present invention, an LGA chip stack of the present invention includes a substrate on which a substrate pad and a side pad are printed on an upper surface, a plurality of memory semiconductor dies of a multi-chip package type, a connecting member electrically connecting the memory semiconductor dies, And a bottom protecting member covering all of the semiconductor die and the connecting member and a part of the substrate.

According to another aspect of the present invention, there is provided an LGA package substrate comprising: an insulating PCB body; an upper wiring pattern on which a substrate pad is printed on an inner side of an upper surface of the PCB body and a side pad is printed on an upper edge of the PCB body; And a rewiring pattern for electrically connecting the substrate pad and the side pad to each other.

As described above, according to the configuration of the present invention, the following effects can be expected.

First, since the memory semiconductor dies are not forcibly arranged vertically but divided into a plurality of chip stacks and packaged, it is possible to originally prevent a reduction in the yield caused by the vertical stacking of the semiconductor dies.

Secondly, because each substrate is interposed between the plural memory semiconductor dies and is wire-bonded to electrically connect the divided packages at the side of each substrate, the length of the conductive wires is originally shortened and the wire bonding process is easy Is expected to be effective.

Third, since each substrate is interposed between the plurality of memory semiconductor dies, an effect of effectively dispersing the high heat generated in the high-capacity memory semiconductor die and preventing the degradation of the thermal characteristics is expected.

Finally, the memory package of the present invention is highly likely to be utilized in a SSD product requiring a high capacity and a flexible memory package applicable to a wearable device.

1 is a side view showing a prior art 16-stage multichip package (MCP) configuration;
2 is a side view showing a prior art BGA package on package (PoP) configuration;
3 is a perspective view showing a configuration of an LGA semiconductor package according to the present invention.
Figures 4 and 5 are side views of Figure 3 in accordance with various multichip package embodiments.
6 is a perspective view showing a chip stack structure according to the present invention.
FIGS. 7A and 7B are side views respectively showing a configuration of an LGA semiconductor package according to an embodiment including four four-chip stacks according to the present invention as a hard package and a soft package, respectively.
FIGS. 8A and 8B are side views showing the configuration of an LGA semiconductor package according to another embodiment including four four-chip stacks according to the present invention, as a hard package and a soft package, respectively.
9 is a side view showing a configuration of an LGA semiconductor package according to another embodiment including four four-chip stacks according to the present invention.
10 is a block diagram showing a configuration of an SSD system to which an LGA semiconductor package according to the present invention is applied.

Brief Description of the Drawings The advantages and features of the present invention, and how to achieve them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are produced according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, preferred embodiments of the LGA semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

In the LGA semiconductor package of the present invention, for example, a 16-stage chip stack NAND flash memory semiconductor die is divided into four packages of a four-stage chip stack and then packaged and then packaged on an integrated board.

When the high-capacity stacked memory semiconductor die is divided and packaged in the final packaging, the problem of the yield reduction due to the high-capacity stacking is solved, and the electrical characteristics can be maintained.

1 to 6, an LGA semiconductor package 100 of the present invention is mounted on an integrated substrate 110 and an integrated substrate 110, and a plurality of memory semiconductor dies 220 are mounted on a chip on chip a plurality of memory semiconductor dies 220 are stacked on a bottom chip stack 200 and a plurality of memory semiconductor dies 220 stacked on a bottom chip stack 200, A split top chip stack 300 which is stacked and is responsible for the remainder of the total memory capacity, an integrated wire 130 for electrically connecting the upper and lower chip stacks 200 and 300, (140).

The bottom chip stack 200 and the top chip stack 300 in the embodiment of the present invention are divided into the bottom chip stack 200 and the top chip stack 300. However, if the plurality of packages can be bonded, It is preferable to divide into four packages as shown in FIG. For example, the chip stack may be divided into a first chip stack to a fourth chip stack 200, 300a, 300b, and 300c.

At least one package provided on the integrated substrate 110 side is a bottom chip stack 200 and at least one package bonded on the bottom chip stack 200 is a top chip stack 300 .

6, the bottom chip stack 200 includes a bottom substrate 210, a plurality of memory semiconductor dies 220 stacked in a chip-on-chip form on the bottom substrate 210, a plurality of memory semiconductor dies A connection member 230 of a bonding wire or a penetrating electrode or a bonding wire electrically connecting the bottom substrate 210 and the semiconductor die 220 to each other.

The bottom substrate 210 includes an insulating PCB body (not shown), an upper wiring pattern (not shown) including a substrate pad 212 and a side pad 214 on the top surface of the PCB body, (Not shown) including a connection terminal and a connection pad for connecting the substrate pad 212 and the external connection terminal inside the PCB body or for electrically connecting the substrate pad 212 and the side pad 214, And / or a rewiring pattern (not shown).

The insulating PCB body of the present invention may include a flexible FPCB substrate. For example, a flexible semiconductor substrate and a semiconductor die which are bent freely in recent years have been developed, and a freely bendable flexible semiconductor package including the above-described substrate and die has been developed, so that the insulating PCB body can be constructed using FPCB . That is, the flexible LGA semiconductor package can be implemented through a flexible substrate, a flexible die, a flexible wire, and a flexible molding (see FIGS. 7B and 8B).

For example, the bottom chip stack 200 may be composed of a soft semiconductor package. To this end, the bottom substrate 210 may be bent or bent. For this purpose, the bottom substrate 210 may be formed of a polymer material. For example, the flexible substrate may be typically formed of polyimide (PI), polyester, polyethylene naphthalate (PEN), Teflon, polyethylene terephthalate (PET), or other polymeric.

The substrate pad 212 is formed on the bottom substrate 210. The substrate pad 212 may be formed of a flexible material such as copper (Cu), titanium (Ti), aluminum (Al), or a metal alloy to form a curved conductive film. The substrate pad 212 may include a conductive metal line formed through deposition and etching by lithography, but may include a conductive metal line formed by printing a conductive ink by a printing method for more flexibility have.

The elements of the memory semiconductor die 220 are integrated on a silicon substrate, but the thickness of the silicon substrate is not more than several tens of micrometers so as to be bent.

The bonding material (not shown) for bonding the memory semiconductor die 220 includes a polymer material having a high adhesive force to bond the memory semiconductor die 220 to the semiconductor die 220, even if the bottom substrate 210 is bent or bent. A material having high adhesion strength is required to prevent peeling or separation phenomenon.

The bottom protecting member 240 may be formed of a material bent or bent. For example, the protective member 240 includes a material capable of providing stress, and may include a polymer material or a rubber material. In particular polyimide.

Therefore, even if the semiconductor package 200 is bent or bent arbitrarily, it is flexible and stretchable. Even if stress is generated due to elongation and shrinkage, damage due to stress is prevented. Particularly, when the bottom substrate 210 is bent or stretched, The substrate pad 212 formed on the substrate 210 is not cut off or peeled off from the substrate 210, so that it is possible to prevent a function failure due to a contact fail.

Meanwhile, in the present invention, the external connection terminal can be omitted by connecting the substrate pad 212 directly to the side pad 214 using the rewiring pattern according to the embodiment.

The bottom chip stack 200 may be composed of a conventional semiconductor package in which various types of memory semiconductor dies are stacked on the bottom substrate 210 in various forms. Here, the multi-layer memory semiconductor die may take the form of a multi chip package (MCP) as follows.

As shown in FIG. 4, the memory semiconductor dies 220 are stacked in a step-like fashion or stacked vertically (see reference numeral 200) or zigzag 300), and the memory semiconductor die stacked in order to prevent deterioration of electrical characteristics due to high-speed operation does not exceed the eight-stage stack. However, it is not excluded that some planar arrays are combined, and various array formats can be determined in consideration of the size of the SSD and the memory capacity. Nor does it prevent alignment with logic semiconductor die.

Referring to FIG. 5, when electrical connection between the memory semiconductor dies 220 stacked on the chip stack 300 is performed using a penetrating electrode (not shown) without wire bonding, the semiconductor die stacked vertically and vertically is vertical When the semiconductor die 220 is to be aligned, the semiconductor die 220 can be designed so as to be vertically stacked.

As described above, the bottom substrate 210 of the present invention further includes a side pad 214 for electrically connecting to the top chip stack 300 at an edge where the memory semiconductor die 220 is not bonded The side pad 214 is an area for electrically connecting the top chip stack 300 and the bottom chip stack 200 by the integrated wire 130 and is also connected to each semiconductor die 220 through the redistribution line RDL It is the area to be connected.

Since the top chip stack 300 and the bottom chip stack 200 are connected in one side by the integrated wire 130 in the LGA type, the plurality of packages are not connected by the BGA, And the package can be slimmed down.

In addition, since the plurality of packages are separated and configured by the divided tip stack, the length of the conductive wire is shortened and the electrical characteristics are maintained despite the high-speed operation. For example, each substrate 210 is placed between each of the plurality of memory semiconductor dies 220, and each substrate 210 serves as a terminal through which the conductive wires pass. As a result, the length of the conductive wires can be prevented have.

The side pads 214 are also electrically connected to the plurality of memory semiconductor dies 220 which are connected to the redistribution lines RDL of the bottom substrate 210 and stacked on the bottom substrate 210. The chip stack 200 may be connected to the chip stack 200 through the integrated wire 130 and the existing external connection terminal may be used as it is connected between the bottom chip stack 200 and the integrated substrate 110.

Rather, in the embodiment of the present invention, an external contact terminal for electrically connecting the bottom chip stack 200 to the outside can be omitted without providing an external contact terminal. For example, when the side pad 214 and the plurality of memory semiconductor dies 220 are connected by the redistribution line (RDL), the height of the semiconductor package can be remarkably reduced by not placing the external contact terminal at the bottom.

As a result, by inserting each substrate 210 between the plurality of memory semiconductor dies 220, heat generated in the memory semiconductor die 220 can be effectively discharged through each of the substrates 210 having excellent thermal conductivity, Can be improved.

By dividing the bottom chip stack 200 and the top chip stack 300 as described above, the function of the package can be independently designed, and any type of semiconductor die packaged in the package can be used Semiconductor die can be stacked, which makes it more accessible to package generalization.

Since the memory semiconductor die of the present invention can be divided into a plurality of chip stacks and LGA packages and the LGA chip stacks can be electrically connected to each other without wire bonding by using the side pads provided in the side space of the LGA package substrate, And it is possible to assemble a variety of variously divided chip stacks, which can be generalized as shown in FIG. 9, on the LGA package substrate by various methods.

Referring to FIG. 10, the LGA semiconductor package 100 according to the present invention may be used in a data storage device such as the SSD 500 system. For example, the SSD 500 may include an interface 510, a controller 520, a buffer memory 530, and a NAND flash memory 540. The SSD 500 is a device for storing information by using semiconductor devices and has advantages such as a high speed, a failure rate, heat generation, noise reduction, miniaturization, and weight reduction compared to a hard disk drive (HDD).

The SSD 500 can be used as a general purpose data storage device replacing a hard disk, and the LGA semiconductor package 100 of the present invention can be most suitably applied to such a standardized SSD.

In view of the tendency of the SSD 500 product to be softened, the memory semiconductor die 220 can be divided and packaged under the condition that the memory semiconductor die 220 can not be excessively stacked.

As described above, conventionally, a high-capacity memory is realized through POP (package on package) package in which semiconductor dies are individually packaged and tested semiconductor dies stacked vertically. However, as the number of stacked dies increases, Therefore, the LGA semiconductor package of the present invention is divided and packaged into a 4-stage or 8-stage chip stack, and each chip stack is wire-bonded by using a side pad on the side of the substrate, Is realized as a technical idea. Many other modifications will be possible to those skilled in the art, within the scope of the basic technical idea of the present invention.

100: LGA semiconductor package 110: Integrated substrate
120: joining member 130: integrated wire
140: integrated protection member 200: bottom chip stack
210: bottom substrate 212: substrate pad
214: side pad 220: memory semiconductor die
230: bottom protecting member 300: top chip stack

Claims (10)

Integrated substrate;
A first chip stack mounted on the integrated substrate and stacking a plurality of memory semiconductor dies on a chip-on-chip type, the first chip stack being responsible for a portion of the total memory capacity;
A second chip stack to a fourth chip stack which are mounted on the first chip stack and in which a plurality of memory semiconductor dies are stacked to take up the remainder of the total memory capacity;
An integrated wire electrically connecting the first chip stack to the fourth chip stack; And
And an integrated protective member sealing the integrated wire,
Each chip stack includes:
Each substrate including a substrate pad and a side pad;
The memory semiconductor die of a multi-chip package type;
A connecting member electrically connecting the memory semiconductor die; And
And a bottom protecting member covering the semiconductor die, the connecting member, and the substrate pad,
The side pads of the fourth chip stack are electrically connected to the side pads of the third chip stack through the conductive wires,
The side pads of the third chip stack are electrically connected to the side pads of the second chip stack through the conductive wires,
The side pads of the second chip stack are electrically connected to the side pads of the first chip stack through the conductive wires,
The side pads of the first chip stack are electrically connected to the side pads of the integrated substrate through the conductive wires,
Wherein each chip stack uses the side pads neighboring to the upper and lower sides and combines them by wire bonding to realize a high capacity memory of four or more stages. delete The method according to claim 1,
Each of the above-
Isolated PCB body;
An upper wiring pattern including the substrate pad and the side pad on an upper surface of the PCB body;
A lower wiring pattern including an external connection terminal on a bottom surface of the PCB body; And
And a through electrode or a wiring pattern for connecting the substrate pad and the external connection terminal or electrically connecting the substrate pad and the side pad in the PCB body. The method of claim 3,
Wherein the substrate pad is covered by the bottom protection member,
And the side pad is covered by the integrated protection member. delete delete delete delete delete delete
KR1020150108804A 2015-07-31 2015-07-31 Land Grid Array semiconductor package KR101961377B1 (en)

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KR1020150108804A KR101961377B1 (en) 2015-07-31 2015-07-31 Land Grid Array semiconductor package
PCT/KR2016/008434 WO2017023060A1 (en) 2015-07-31 2016-08-01 Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same
CN201680042425.6A CN108140636B (en) 2015-07-31 2016-08-01 Semiconductor package, semiconductor stack package, and memory module
US15/746,100 US10522522B2 (en) 2015-07-31 2016-08-01 Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same

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AU2003272405A1 (en) * 2002-09-17 2004-04-08 Chippac, Inc. Semiconductor multi-package module having wire bond interconnection between stacked packages
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