KR101563910B1 - EMI shielding device for semiconductor package and method for manufacturing the same - Google Patents

EMI shielding device for semiconductor package and method for manufacturing the same Download PDF

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KR101563910B1
KR101563910B1 KR1020130126884A KR20130126884A KR101563910B1 KR 101563910 B1 KR101563910 B1 KR 101563910B1 KR 1020130126884 A KR1020130126884 A KR 1020130126884A KR 20130126884 A KR20130126884 A KR 20130126884A KR 101563910 B1 KR101563910 B1 KR 101563910B1
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strip substrate
semiconductor chip
shielding material
semiconductor package
conductive
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KR20150047167A (en
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홍성준
박철우
심기동
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앰코 테크놀로지 코리아 주식회사
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

본 발명은 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 다수의 반도체 패키징 영역을 갖는 스트립 기판에 반도체 칩을 부착한 후, 그 위에 전자파 차폐층을 몰딩 공전 전에 미리 형성시킨 새로운 구조의 반도체 패키지 및 이의 제조 방법에 관한 것이다.
즉, 본 발명은 스트립 단위(다수의 동일한 반도체 패키징 영역이 가로 및 세로 방향을 따라 배열된 것)의 기판에 반도체 칩을 도전 가능하게 부착한 후, 반도체 칩과 기판의 표면에 걸쳐 전자파 차폐물질을 미리 도포한 다음, 전자파 차폐물질을 몰딩 컴파운드 수지로 몰딩하는 공정을 진행함으로써, 전자파 차폐물질의 코팅 작업에 대한 생산성 및 작업성을 향상시킬 수 있고, 전자파 차폐물질이 몰딩 컴파운드 수지에 의하여 보호되어 벗겨지는 현상을 방지할 수 있도록 한 반도체 패키지 및 이의 제조 방법을 제공하고자 한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor package having a semiconductor chip mounted on a strip substrate having a plurality of semiconductor packaging areas, and an electromagnetic wave shielding layer formed thereon, Package and a method of manufacturing the same.
That is, the present invention is characterized in that after a semiconductor chip is conductively attached to a substrate in a strip unit (a plurality of the same semiconductor packaging regions are arranged along the lateral and longitudinal directions), the semiconductor chip and the electromagnetic wave shielding material It is possible to improve the productivity and workability of the coating operation of the electromagnetic shielding material by performing the step of molding the electromagnetic shielding material with the molding compound resin in advance and then the electromagnetic shielding material is protected by the molding compound resin, And a method of manufacturing the semiconductor package.

Description

반도체 패키지 및 이의 제조 방법{EMI shielding device for semiconductor package and method for manufacturing the same}Technical Field [0001] The present invention relates to a semiconductor package and a method of manufacturing the same.

본 발명은 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 다수의 반도체 패키징 영역을 갖는 스트립 기판에 반도체 칩을 부착한 후, 그 위에 전자파 차폐층을 몰딩 공전 전에 미리 형성시킨 새로운 구조의 반도체 패키지 및 이의 제조 방법에 관한 것이다.
The present invention relates to a semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor package having a semiconductor chip mounted on a strip substrate having a plurality of semiconductor packaging areas, and an electromagnetic wave shielding layer formed thereon, Package and a method of manufacturing the same.

각종 전자기기에는 다양한 구조로 제조된 다수개의 반도체 패키지 뿐만아니라, 각종 신호 교환용 전자소자들이 한꺼번에 설치되는 바, 이러한 반도체 패키지와 전자소자들은 전기적인 작동중에 전자파를 발산시키는 것으로 알려져 있다.Various electronic devices are provided with a plurality of semiconductor packages manufactured in various structures, as well as electronic devices for various signal exchange. Such semiconductor packages and electronic devices are known to radiate electromagnetic waves during electrical operation.

상기 전자파 장해(EMI, electro magnetic interferenc)를 일으키는 전자파는 전계(電界)와 자계(磁界)의 합성파로 정의되는데, 도체를 통하여 전류가 흐르게 되면, 이 전류에 의하여 형성되는 전계와 자계를 합쳐서 전자파라고 부른다.The electromagnetic wave causing the electromagnetic interference (EMI) is defined as a composite wave of an electric field and a magnetic field. When a current flows through a conductor, the electric field formed by the current and the magnetic field are combined to form an electromagnetic wave I call it.

현재, 전자파들은 인체에 유해한 것으로 밝혀지고 있고, 특히 다양한 구조로 제조된 다수개의 반도체 패키지 뿐만아니라 각종 신호 교환용 전자소자들이 한꺼번에 설치된 전자기기의 마더보드에서, 좁은 간격으로 실장된 반도체 패키지와 기기들로부터 전자파가 발산되면, 그 주변에 실장된 반도체 패키지에까지 직간접으로 영향이 미치게 되어, 칩 회로에 손상을 입히는 것으로 밝혀지고 있다.2. Description of the Related Art [0002] Currently, electromagnetic waves are known to be harmful to the human body. In particular, in a motherboard of an electronic device in which various signal exchange electronic devices are installed at a time as well as a plurality of semiconductor packages manufactured in various structures, It has been found that the electromagnetic wave directly or indirectly affects the semiconductor package mounted on the periphery thereof and damages the chip circuit.

즉, 마더보드와 같은 기판상의 각 반도체 패키지 및 회로기기들은 전자파를 발생하게 되고, 이러한 전자파의 간섭으로 인하여 전자장치 자체에 회로기능 약화 및 동작 불량 등의 기능 장애 및 고장을 유발하게 된다.That is, each semiconductor package and circuit devices on a substrate, such as a mother board, generates electromagnetic waves, and the interference of such electromagnetic waves causes a malfunction and failure of the electronic device itself, such as weakening of circuit function and malfunction.

따라서, 반도체 패키지에도 여러가지 형태의 전자파 차폐 구조가 적용되고 있다.Therefore, various types of electromagnetic wave shielding structures are also applied to semiconductor packages.

여기서, 종래의 반도체 패키지에 적용된 전자파 차폐 구조를 첨부한 도 1을 참조로 살펴보면 다음과 같다.Hereinafter, an electromagnetic wave shielding structure applied to a conventional semiconductor package will be described with reference to FIG.

도 1은 통상의 볼 그리드 어레이 반도체 패키지를 도시하고 있으며, 도 1에서 도면부호 10은 볼 그리그 어레이 타입의 패키지를 제조하기 위한 기판(PCB, Printed Circuit Board)를 지시한다.FIG. 1 shows a conventional ball grid array semiconductor package. In FIG. 1, reference numeral 10 designates a printed circuit board (PCB) for manufacturing a package of a ball grid array type.

통상, 상기 기판(10)은 수지층(11)과, 수지층(11)의 상하면에 임의의 회로 배열을 이루며 형성된 도전성 패턴층(12) 등을 포함하는 구조로 구비되고, 기판(10)의 상면에는 와이어 본딩을 위한 본딩용 패턴(13)이 형성되고, 저면에는 솔더볼과 같은 입출력단자를 부착하기 위한 볼랜드(14)가 형성되어 있다.In general, the substrate 10 has a structure including a resin layer 11 and a conductive pattern layer 12 formed on the upper and lower surfaces of the resin layer 11 in an arbitrary circuit arrangement, A bonding pattern 13 for wire bonding is formed on the upper surface, and a borland 14 for attaching an input / output terminal such as a solder ball is formed on the bottom surface.

상기 볼 그리드 어레이 반도체 패키지의 유닛 구성을 보면, 기판(10)의 상면 중앙부에 부착되는 반도체 칩(20)과, 반도체 칩(20)의 본딩패드와 기판(10)의 본딩용 패턴(13) 간에 연결되는 도전성 와이어(22)와, 반도체 칩(20)과 도전성 와이어(22)를 봉지하면서 기판(10)의 상면에 오버 몰딩되는 몰딩 컴파운드 수지(24)와, 기판(10)의 볼랜드(14)에 부착되는 입출력단자(26) 등을 포함하여 구성된다.The unit structure of the ball grid array semiconductor package includes a semiconductor chip 20 attached to the center of the upper surface of the substrate 10 and a bonding pattern 13 of the substrate 10 bonded to the bonding pad of the semiconductor chip 20, A molding compound resin 24 which is overmolded on the upper surface of the substrate 10 while sealing the semiconductor chip 20 and the conductive wire 22 and a conductive material 22 which is connected to the boron 14 of the substrate 10, And an input / output terminal 26 attached to the input /

이때, 위와 같은 구성을 포함하는 볼 그리드 어레이 반도체 패키지의 전자파 차폐를 위하여, 기판(10)의 측면을 비롯하여 몰딩 컴파운드 수지(24)의 전체 표면에 걸쳐 전자파 차폐물질(28)이 스프레이 방식으로 코팅된다.At this time, in order to shield electromagnetic waves of the ball grid array semiconductor package including the above structure, the electromagnetic wave shielding material 28 is coated in a spray manner on the entire surface of the molding compound resin 24 including the side surface of the substrate 10 .

즉, 상기 반도체 패키지가 하나의 유닛으로 제작된 후, 기판(10)의 측면을 비롯하여 몰딩 컴파운드 수지(24)의 전체 표면에 걸쳐 전자파 차폐물질(28)이 스프레이 방식으로 코팅되어, 전자파 및 각종 노이즈를 차폐하는 역할을 한다.That is, after the semiconductor package is fabricated as a single unit, the electromagnetic wave shielding material 28 is coated on the entire surface of the molding compound resin 24 as well as the side surface of the substrate 10 by a spraying method so that electromagnetic waves and various noises .

그러나, 상기와 같은 종래의 전자파 차폐물질 코팅을 하나의 반도체 패키지 단위마다 진행됨에 따라, 생산성 및 작업성이 저하되는 요인이 되고 있고, 제조 공정수의 증가로 인한 제조 비용 상승의 원인이 되는 문제점이 있다.However, as the above-described conventional electromagnetic shielding material coating is progressed for each semiconductor package unit, the productivity and workability are lowered, and there is a problem that the manufacturing cost is increased due to an increase in the number of manufacturing processes have.

또한, 기판의 측면을 비롯하여 몰딩 컴파운드 수지의 전체 표면에 걸쳐 코팅된 전자파 차폐물질(28)이 외부력에 의하여 쉽게 벗겨지는 현상이 발생되어, 전자파 차폐 기능을 상실하는 문제점이 있다.
Further, there is a problem that the electromagnetic wave shielding material 28 coated on the entire surface of the molding compound resin as well as the side surface of the substrate is easily peeled off by the external force, and the electromagnetic wave shielding function is lost.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출한 것으로서, 스트립 단위(다수의 동일한 반도체 패키징 영역이 가로 및 세로 방향을 따라 배열된 것)의 기판에 반도체 칩을 도전 가능하게 부착한 후, 반도체 칩과 기판의 표면에 걸쳐 전자파 차폐물질을 미리 도포한 다음, 전자파 차폐물질을 몰딩 컴파운드 수지로 몰딩하는 공정을 진행함으로써, 전자파 차폐물질의 코팅 작업에 대한 생산성 및 작업성을 향상시킬 수 있고, 전자파 차폐물질이 몰딩 컴파운드 수지에 의하여 보호되어 벗겨지는 현상을 방지할 수 있도록 한 반도체 패키지 및 이의 제조 방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a method of electrically connecting a semiconductor chip to a substrate in strip units (a plurality of the same semiconductor packaging regions are arranged along the lateral and longitudinal directions) It is possible to improve the productivity and workability of the coating operation of the electromagnetic wave shielding material by applying the electromagnetic wave shielding material in advance on the surface of the semiconductor chip and the substrate and then molding the electromagnetic wave shielding material with the molding compound resin, And an object of the present invention is to provide a semiconductor package and a method of manufacturing the same that can prevent a phenomenon that an electromagnetic wave shielding material is protected by a molding compound resin and peeled off.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는: 다수의 반도체 패키지 영역을 갖는 스트립 기판과; 상기 스트립 기판의 각 반도체 패키지 영역의 상면에 부착되는 반도체 칩과; 상기 반도체 칩의 본딩패드와 스트립 기판의 본딩용 패턴 간에 연결되는 도전성 연결수단과; 상기 반도체 칩의 표면 및 스트립 기판의 표면에 걸쳐 코팅되는 전자파 차폐물질과; 상기 반도체 칩과 도전성 연결수단을 봉지하면서 전자파 차폐물질의 표면에 걸쳐 오버 몰딩되는 몰딩 컴파운드 수지와; 상기 스트립 기판의 저면에 형성된 볼랜드에 융착되는 입출력단자; 를 포함하여 구성된 것을 특징으로 하는 반도체 패키지를 제공한다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a strip substrate having a plurality of semiconductor package regions; A semiconductor chip attached to an upper surface of each semiconductor package region of the strip substrate; Conductive connection means connected between a bonding pad of the semiconductor chip and a pattern for bonding the strip substrate; An electromagnetic wave shielding material coated over the surface of the semiconductor chip and the surface of the strip substrate; A molding compound resin that overmolds the surface of the electromagnetic wave shielding material while sealing the semiconductor chip and the conductive connecting means; An input / output terminal which is fused to a borland formed on a bottom surface of the strip substrate; And a semiconductor package.

바람직하게는, 상기 도전성 연결수단이 반도체 칩의 상면에 형성된 본딩패드와 스트립 기판의 본딩용 패턴 간에 연결되는 도전성 와이어로 채택되면, 전자파 차폐물질의 코팅 전에 도전성 와이어에 절연물질이 도포되어 도전성 와이어가 봉지되는 것을 특징으로 한다.Preferably, when the conductive connecting means is used as a conductive wire connected between a bonding pad formed on the upper surface of the semiconductor chip and a pattern for bonding the strip substrate, an insulating material is applied to the conductive wire before coating the electromagnetic shielding material, And is sealed.

또한, 상기 도전성 연결수단이 반도체 칩의 저면에 형성된 본딩패드와 스트립 기판의 본딩용 패턴 간에 연결되는 도전성 범프로 채택되면, 전자파 차폐물질의 코팅 전에 반도체 칩의 저면과 스트립 기판의 상면 사이에 언더필 재료가 충진되어 도전성 범프들이 절연 가능하게 봉지되는 것을 특징으로 한다.When the conductive connecting means is used as a conductive bump connected between a bonding pad formed on the bottom surface of the semiconductor chip and a pattern for bonding the strip substrate, an underfill material is formed between the bottom surface of the semiconductor chip and the top surface of the strip substrate, So that the conductive bumps are insulatedly sealed.

특히, 상기 스트립 기판의 각 반도체 패키지 영역의 상면 테두리 부분에는 전자파 차폐물질과 도전 가능하게 연결되는 그라운드 패드가 형성된 것을 특징으로 한다.In particular, a ground pad is formed on an upper surface of each semiconductor package region of the strip substrate to electrically connect the electromagnetic shielding material.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는: 다수의 반도체 패키지 영역을 갖는 스트립 기판의 제공 단계와; 상기 스트립 기판의 각 반도체 패키지 영역의 상면에 반도체 칩을 부착하는 단계와; 상기 반도체 칩의 본딩패드와 스트립 기판의 본딩용 패턴 간을 도전성 연결수단으로 연결하는 단계와; 상기 반도체 칩의 표면 및 스트립 기판의 표면에 걸쳐 전자파 차폐물질을 코팅하는 단계와; 상기 전자파 차폐물질의 표면에 걸쳐 반도체 칩과 도전성 연결수단을 봉지하도록 몰딩 컴파운드 수지를 오버 몰딩하는 단계와; 상기 기판의 저면에 형성된 볼랜드에 입출력단자를 융착하는 단계와; 상기 스트립 기판을 하나의 반도체 패키지 단위로 소잉하는 단계; 를 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법을 제공한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a strip substrate having a plurality of semiconductor package regions; Attaching a semiconductor chip to an upper surface of each semiconductor package area of the strip substrate; Connecting a bonding pad of the semiconductor chip and a pattern for bonding of the strip substrate by conductive connection means; Coating an electromagnetic wave shielding material on the surface of the semiconductor chip and the surface of the strip substrate; Overmolding the molding compound resin to seal the semiconductor chip and the conductive connecting means over the surface of the electromagnetic shielding material; Fusing an input / output terminal to a borland formed on a bottom surface of the substrate; Sowing the strip substrate in one semiconductor package unit; The method of manufacturing a semiconductor package according to the present invention includes the steps of:

바람직하게는, 상기 도전성 연결수단이 도전성 와이어로 채택되는 경우, 전자파 차폐물질 코팅 전에 도전성 와이어를 절연물질로 봉지시키는 단계를 더 포함하는 것을 특징으로 한다.Preferably, when the conductive connecting means is adopted as a conductive wire, the method further comprises sealing the conductive wire with an insulating material before coating the electromagnetic wave shielding material.

또한, 상기 도전성 연결수단이 도전성 범프로 채택되는 경우, 전자파 차폐물질 코팅 전에 반도체 칩의 저면과 스트립 기판의 상면 사이에 언더필 재료를 충진하는 단계를 더 포함하는 것을 특징으로 한다.Further, when the conductive connecting means is adopted as the conductive bump, the method further includes filling the underfill material between the bottom surface of the semiconductor chip and the upper surface of the strip substrate before the electromagnetic shielding material is coated.

또한, 상기 전자파 차폐물질을 코팅하는 단계는 스프레이 분사 방식 또는 스퍼터링 방식에 의하여 진행되는 것을 특징으로 한다.Further, the step of coating the electromagnetic wave shielding material is performed by a spraying method or a sputtering method.

특히, 상기 전자파 차폐물질 코팅시, 스트립 기판의 각 반도체 패키지 영역의 상면 테두리 부분에 형성된 그라운드 패드에 전자파 차폐물질이 도전 가능하게 연결되는 것을 특징으로 한다.
Particularly, when the electromagnetic wave shielding material is coated, the electromagnetic wave shielding material is conductively connected to the ground pad formed on the upper edge of each semiconductor package area of the strip substrate.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 스트립 단위의 기판에 반도체 칩을 도전 가능하게 부착한 후, 반도체 칩과 기판의 표면에 걸쳐 전자파 차폐물질을 미리 도포한 다음, 전자파 차폐물질 위에 몰딩 컴파운드 수지를 몰딩하는 공정을 진행함으로써, 전자파 차폐 기능을 갖는 볼 그리드 어레이 타입의 반도체 패키지를 제공할 수 있다.According to the present invention, after a semiconductor chip is electroconductively attached to a substrate of a strip unit, an electromagnetic wave shielding material is applied in advance on the surface of the semiconductor chip and the substrate, and then a molding compound resin is molded on the electromagnetic wave shielding material A ball grid array type semiconductor package having an electromagnetic wave shielding function can be provided.

특히, 스트립 기판의 각 반도체 패키지 영역에 전자파 차폐물질의 코팅이 한꺼번에 이루어짐으로써, 전자파 차폐물질의 코팅 작업에 대한 생산성 및 작업성을 향상시킬 수 있다.Particularly, since the electromagnetic shielding material is coated all over the semiconductor package area of the strip substrate, the productivity and workability of the coating operation of the electromagnetic shielding material can be improved.

또한, 전자파 차폐물질이 몰딩 컴파운드 수지에 의하여 보호되는 상태가 되므로, 기존과 같이 전자파 차폐물질이 외부력에 의하여 벗겨지는 현상을 방지할 수 있다.
In addition, since the electromagnetic wave shielding material is protected by the molding compound resin, it is possible to prevent the electromagnetic wave shielding material from being peeled off by external force.

도 1은 종래의 반도체 패키지의 전자파 차폐 구조를 도시한 단면도,
도 2는 본 발명의 제1실시예에 따른 반도체 패키지를 도시한 단면도,
도 3은 본 발명의 제1실시예에 따른 반도체 패키지 제조 방법을 도시한 평면도,
도 4는 본 발명의 제2실시예에 따른 반도체 패키지를 도시한 단면도,
도 5는 본 발명의 제2실시예에 따른 반도체 패키지 제조 방법을 도시한 평면도.BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a structure of a conventional semiconductor package,
2 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention,
3 is a plan view showing a method of manufacturing a semiconductor package according to the first embodiment of the present invention,
4 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention,
5 is a plan view showing a method of manufacturing a semiconductor package according to a second embodiment of the present invention.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 볼 그리드 어레이 타입의 반도체 패키지를 스트립 기판을 이용하여 제조할 때, 스트립 기판의 각 반도체 패키지 영역에 반도체 칩을 부착하는 공정 후, 각 반도체 패키지 영역에 전자파 차폐물질을 한꺼번에 코팅하여, 전자파 차폐물질의 코팅 작업 및 패키징 공정에 대한 생산성 및 작업성을 향상시킬 수 있도록 한 점에 주안점이 있다.The present invention relates to a method of manufacturing a ball grid array type semiconductor package using a strip substrate, a process of attaching a semiconductor chip to each semiconductor package area of a strip substrate, coating electromagnetic wave shielding materials on each semiconductor package area, There is a point in that it is possible to improve the productivity and workability of the coating and packaging processes of the shielding material.

제1실시예First Embodiment

첨부한 도 2 및 도 3은 본 발명의 제1실시예에 따른 반도체 패키지 및 제조 공정을 나타낸 단면도이다.2 and 3 are cross-sectional views illustrating a semiconductor package and a manufacturing process according to a first embodiment of the present invention.

상기 스트립 기판(100)은 다수의 반도체 패키지 영역(102, 반도체 패키지로 제조될 영역)이 가로 및 세로 방향을 따라 등간격으로 배열된 기판(PCB)로서, 볼 그리드 어레이 타입의 패키지를 하나의 유니트가 아닌 한꺼번에 다수개를 제조할 수 있는데 유용하게 사용된다.The strip substrate 100 is a substrate (PCB) having a plurality of semiconductor package regions 102 (regions to be manufactured as a semiconductor package) arranged at regular intervals along the horizontal and vertical directions. The strip substrate 100 includes a ball grid array type package, It is useful for manufacturing multiple pieces at once instead of one.

본 발명의 반도체 패키지를 제조하기 위하여, 먼저 상기 스트립 기판(100)의 각 반도체 패키지 영역(102)의 상면에 반도체 칩(110)을 에폭시 수지와 같은 접착수단에 의하여 부착한다.In order to manufacture the semiconductor package of the present invention, first, the semiconductor chip 110 is attached to the upper surface of each semiconductor package region 102 of the strip substrate 100 by an adhesive means such as an epoxy resin.

또한, 상기 반도체 칩(110)의 상면에 형성된 본딩패드(112)와 상기 스트립 기판(100)의 각 반도체 패키지 영역(102)의 표면에 노출된 본딩용 패턴(104)을 도전성 와이어와 같은 도전성 연결수단(120)으로 상호 연결한다.The bonding pad 112 formed on the upper surface of the semiconductor chip 110 and the bonding pattern 104 exposed on the surface of each semiconductor package region 102 of the strip substrate 100 are electrically connected to each other through a conductive connection (120).

이어서, 상기 도전성 연결수단(120) 즉, 도전성 와이어를 절연물질(132)로 봉지시키는 단계가 진행된다.Then, the step of sealing the conductive connecting means 120, that is, the conductive wire with the insulating material 132, proceeds.

좀 더 상세하게는, 상기 도전성 와이어들을 에폭시 수지와 같은 절연물질(132)로 감싸여지도록 함으로써, 절연물질(132)에 의하여 개개의 도전성 와이어가 견고하게 고정되면서 상호 절연되는 상태가 되고, 특히 도전성 와이어들이 절연물질(132)로 봉지된 상태가 되면서 전자파 차폐물질(130)과의 상호 절연이 이루어질 수 있다.More specifically, the conductive wires are wrapped with an insulating material 132 such as an epoxy resin, so that the individual conductive wires are firmly fixed by the insulating material 132 and are mutually insulated, As the wires are sealed with the insulating material 132, mutual insulation with the electromagnetic shielding material 130 can be achieved.

다음으로, 상기 반도체 칩(110)의 표면 및 스트립 기판(100)의 표면에 걸쳐 전자파 차폐물질(130)을 코팅하는 단계가 진행되며, 바람직하게는 상기 전자파 차폐물질(130)은 스프레이 분사 방식 또는 스퍼터링 방식에 의하여 고른 두께로 코팅된다.Next, the step of coating the electromagnetic wave shielding material 130 on the surface of the semiconductor chip 110 and the surface of the strip substrate 100 is performed. Preferably, the electromagnetic wave shielding material 130 is spray- It is coated with a uniform thickness by a sputtering method.

이때, 상기 스트립 기판(100)의 각 반도체 패키지 영역(102)의 상면 테두리 부분에는 전자파 차폐물질(130)과 도전 가능하게 연결되는 그라운드용 도전성 패턴 즉, 그라운드 패드(108)가 형성되는 바, 상기와 같이 전자파 차폐물질(130)이 반도체 칩(110) 및 스트립 기판(100)의 표면에 코팅되면서 그라운드 패드(108)에 접지 가능하게 접촉되는 상태가 된다.At this time, a conductive pattern for ground, that is, a ground pad 108, which is conductively connected to the electromagnetic wave shielding material 130 is formed on the upper edge of each semiconductor package area 102 of the strip substrate 100, The electromagnetic wave shielding material 130 is coated on the surface of the semiconductor chip 110 and the strip substrate 100 so as to be in contact with the ground pad 108 so as to be grounded.

이어서, 상기 반도체 칩(110)과 도전성 연결수단(120)이 봉지되도록 전자파 차폐물질(130)의 표면에 걸쳐 몰딩 컴파운드 수지(140)가 몰딩된다.The molding compound resin 140 is molded on the surface of the electromagnetic shielding material 130 so that the semiconductor chip 110 and the conductive connecting means 120 are sealed.

이렇게 전자파 차폐물질(130)이 몰딩 컴파운드 수지(140)에 의하여 감싸여지며 보호되는 상태가 되므로, 기존에 전자파 차폐물질(130)이 외부력에 의하여 벗겨지는 등의 단점을 완전하게 해소할 수 있다.Since the electromagnetic shielding material 130 is wrapped and protected by the molding compound resin 140, the disadvantage that the electromagnetic shielding material 130 is peeled off by the external force can be completely solved .

또한, 전자파 차폐물질(130)이 몰딩 컴파운드 수지(140)에 의하여 감싸여진 상태라 하더라도, 반도체 칩(110)의 동작 중 발생하는 노이즈 등이 전자파 차폐물질(130)에 의하여 차폐되는 동시에 그라운드 패드(108)를 통해 접지되어 용이하게 제거될 수 있다.Even when the electromagnetic wave shielding material 130 is wrapped by the molding compound resin 140, noise generated during operation of the semiconductor chip 110 is shielded by the electromagnetic wave shielding material 130, Lt; RTI ID = 0.0 > 108 < / RTI >

최종적으로, 상기 스트립 기판(100)의 저면에 형성된 볼랜드(106)에 솔더볼과 같은 입출력단자(150)를 융착시킨 다음, 스트립 기판(100)의 소잉라인을 따라 소잉 공정을 진행함으로써, 낱개 단위의 볼 그리드 어레이 반도체 패키지가 완성된다.Output terminal 150 such as a solder ball is fused to the borland 106 formed on the bottom surface of the strip substrate 100 and the sowing process is performed along the sawing line of the strip substrate 100, The ball grid array semiconductor package is completed.

제2실시예Second Embodiment

첨부한 도 4 및 도 5는 본 발명의 제2실시예에 따른 반도체 패키지 및 제조 공정을 나타낸 단면도이다.4 and 5 are cross-sectional views illustrating a semiconductor package and a manufacturing process according to a second embodiment of the present invention.

본 발명의 제2실시예에 따른 반도체 패키지는 상기한 제1실시예와 동일한 구성을 이루되, 반도체 칩(110)이 스트립 기판(100)의 각 반도체 패키지 영역에 도전성 범프를 매개로 연결된 점에 차이가 있을 뿐이다.The semiconductor package according to the second embodiment of the present invention has the same structure as that of the first embodiment described above. The semiconductor chip 110 is connected to each semiconductor package region of the strip substrate 100 via conductive bumps There is only difference.

이렇게, 도전성 연결수단(120)이 반도체 칩(110)의 저면에 형성된 본딩패드(112)와 스트립 기판(100)의 본딩용 패턴(104) 간에 연결되는 도전성 범프로 채택되면, 전자파 차폐물질(130)의 코팅 전에 반도체 칩(110)의 저면과 스트립 기판(100)의 상면 사이에 언더필 재료(134)가 충진되어 도전성 범프들이 절연 가능하게 봉지된다.When the conductive connecting means 120 is used as the conductive bump connected between the bonding pad 112 formed on the bottom surface of the semiconductor chip 110 and the bonding pattern 104 of the strip substrate 100, The underfill material 134 is filled between the bottom surface of the semiconductor chip 110 and the upper surface of the strip substrate 100 so that the conductive bumps are insulatedly sealed.

이어서, 상기와 같이 반도체 칩(110)의 표면 및 스트립 기판(100)의 표면에 걸쳐 전자파 차폐물질(130)을 코팅하는 단계와, 전자파 차폐물질(130)의 표면에 걸쳐 반도체 칩(110)과 도전성 연결수단(120)을 봉지하도록 몰딩 컴파운드 수지(140)를 오버 몰딩하는 단계와, 스트립 기판(100)의 저면에 형성된 볼랜드(106)에 입출력단자(150)를 융착하는 단계와, 스트립 기판(100)의 소잉라인을 따라 소잉하는 단계를 차례로 진행함으로써, 낱개 단위의 볼 그리드 어레이 반도체 패키지가 완성된다.Coating the electromagnetic wave shielding material 130 on the surface of the semiconductor chip 110 and the surface of the strip substrate 100 as described above; A step of overmolding the molding compound resin 140 so as to seal the conductive connecting means 120; a step of fusing the input / output terminal 150 to the borland 106 formed on the bottom surface of the strip substrate 100; 100) are sequentially performed, thereby completing a single-unit ball grid array semiconductor package.

이러한 제2실시예에 따른 패키지도 마찬가지로, 전자파 차폐물질(130)이 몰딩 컴파운드 수지(140)에 의하여 감싸여지며 보호되는 상태가 되므로, 기존에 전자파 차폐물질(130)이 외부력에 의하여 벗겨지는 등의 단점을 완전하게 해소할 수 있고, 반도체 칩(110)의 동작 중 발생하는 노이즈 등이 전자파 차폐물질(130)에 의하여 차폐되는 동시에 그라운드 패드(108)를 통해 접지되어 용이하게 제거될 수 있다.
In the package according to the second embodiment, since the electromagnetic shielding material 130 is wrapped and protected by the molding compound resin 140, the electromagnetic shielding material 130 is peeled off by the external force The noise generated during operation of the semiconductor chip 110 is shielded by the electromagnetic wave shielding material 130 and grounded through the ground pad 108 and can be easily removed .

100 : 스트립 기판
102 : 반도체 패키지 영역
104 : 본딩용 패턴
106 : 볼랜드
108 : 그라운드 패드
110 : 반도체 칩
112 : 본딩패드
120 : 도전성 연결수단
130 : 전자파 차폐물질
132 : 절연물질
134 : 언더필 재료
140 : 몰딩 컴파운드 수지
150 : 입출력단자100: strip substrate
102: semiconductor package area
104: pattern for bonding
106: Borland
108: Ground pad
110: semiconductor chip
112: bonding pad
120: conductive connecting means
130: Electromagnetic wave shielding material
132: Insulation material
134: underfill material
140: Molding compound resin
150: I / O terminal

Claims (9)

다수의 반도체 패키지 영역(102)을 갖는 스트립 기판(100)과;
상기 스트립 기판(100)의 각 반도체 패키지 영역(102)의 상면에 부착되는 반도체 칩(110)과;
상기 반도체 칩(110)의 본딩패드(112)와 스트립 기판(100)의 본딩용 패턴(104) 간에 연결되는 도전성 연결수단(120)과;
상기 반도체 칩(110)의 표면 및 스트립 기판(100)의 표면에 걸쳐 코팅되는 전자파 차폐물질(130)과;
상기 스트립 기판(100)의 각 반도체 패키지 영역(102)의 상면 테두리 부분에형성되어 전자파 차폐물질(130)과 도전 가능하게 연결되는 그라운드 패드(108)와;
상기 전자파 차폐물질(130)의 표면에 걸쳐 오버 몰딩되는 몰딩 컴파운드 수지(140)와;
상기 스트립 기판(100)의 저면에 형성된 볼랜드(106)에 융착되는 입출력단자(150);
를 포함하여 구성된 것을 특징으로 하는 반도체 패키지.
A strip substrate (100) having a plurality of semiconductor package regions (102);
A semiconductor chip 110 attached to an upper surface of each semiconductor package region 102 of the strip substrate 100;
Conductive connection means 120 connected between the bonding pad 112 of the semiconductor chip 110 and the bonding pattern 104 of the strip substrate 100;
An electromagnetic wave shielding material 130 coated over the surface of the semiconductor chip 110 and the surface of the strip substrate 100;
A ground pad 108 formed on an upper surface of each semiconductor package region 102 of the strip substrate 100 and electrically connected to the electromagnetic shielding material 130;
A molding compound resin (140) overmolding the surface of the electromagnetic wave shielding material (130);
An input / output terminal 150 fused to a borland 106 formed on a bottom surface of the strip substrate 100;
The semiconductor package comprising:
청구항 1에 있어서,
상기 도전성 연결수단(120)이 반도체 칩(110)의 상면에 형성된 본딩패드(112)와 스트립 기판(100)의 본딩용 패턴(104) 간에 연결되는 도전성 와이어로 채택되면, 전자파 차폐물질(130)의 코팅 전에 도전성 와이어에 절연물질(132)이 도포되어 도전성 와이어가 봉지되는 것을 특징으로 하는 반도체 패키지.
The method according to claim 1,
When the conductive connection unit 120 is used as a conductive wire connected between the bonding pad 112 formed on the upper surface of the semiconductor chip 110 and the bonding pattern 104 of the strip substrate 100, Wherein an insulating material (132) is applied to the conductive wire prior to the coating of the conductive wire to seal the conductive wire.
청구항 1에 있어서,
상기 도전성 연결수단(120)이 반도체 칩(110)의 저면에 형성된 본딩패드(112)와 스트립 기판(100)의 본딩용 패턴(104) 간에 연결되는 도전성 범프로 채택되면, 전자파 차폐물질(130)의 코팅 전에 반도체 칩(110)의 저면과 스트립 기판(100)의 상면 사이에 언더필 재료(134)가 충진되어 도전성 범프들이 절연 가능하게 봉지되는 것을 특징으로 하는 반도체 패키지.
The method according to claim 1,
When the conductive connecting means 120 is used as a conductive bump connected between the bonding pad 112 formed on the bottom surface of the semiconductor chip 110 and the bonding pattern 104 of the strip substrate 100, Wherein an underfill material (134) is filled between the bottom surface of the semiconductor chip (110) and the upper surface of the strip substrate (100) before coating the conductive bumps.
삭제delete 다수의 반도체 패키지 영역(102)을 갖는 스트립 기판(100)의 제공 단계와;
상기 스트립 기판(100)의 각 반도체 패키지 영역(102)의 상면에 반도체 칩(110)을 부착하는 단계와;
상기 반도체 칩(110)의 본딩패드(112)와 스트립 기판(100)의 본딩용 패턴(104) 간을 도전성 연결수단(120)으로 연결하는 단계와;
상기 반도체 칩(110)의 표면 및 스트립 기판(100)의 표면에 걸쳐 전자파 차폐물질(130)을 코팅하는 동시에 스트립 기판(100)의 각 반도체 패키지 영역(102)의 상면 테두리 부분에 형성된 그라운드 패드(108)에 전자파 차폐물질(130)이 도전 가능하게 연결되도록 한 단계와;
상기 전자파 차폐물질(130)의 표면에 걸쳐 반도체 칩(110)과 도전성 연결수단(120)을 봉지하도록 몰딩 컴파운드 수지(140)를 오버 몰딩하는 단계와;
상기 스트립 기판(100)의 저면에 형성된 볼랜드(106)에 입출력단자(150)를 융착하는 단계와;
상기 스트립 기판(100)을 하나의 반도체 패키지 단위로 소잉하는 단계;
를 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
Providing a strip substrate (100) having a plurality of semiconductor package regions (102);
Attaching a semiconductor chip (110) to an upper surface of each semiconductor package area (102) of the strip substrate (100);
Connecting the bonding pad 112 of the semiconductor chip 110 and the bonding pattern 104 of the strip substrate 100 with the conductive connecting means 120;
Shielding material 130 is coated on the surface of the semiconductor chip 110 and the surface of the strip substrate 100 and at the same time a ground pad (not shown) formed on the upper surface of each semiconductor package region 102 of the strip substrate 100 108) so that the electromagnetic shielding material (130) is conductively connected;
Overmolding the molding compound resin (140) to seal the semiconductor chip (110) and the conductive connecting means (120) over the surface of the electromagnetic shielding material (130);
Fusing input / output terminals (150) to a borland (106) formed on a bottom surface of the strip substrate (100);
Sawing the strip substrate (100) in units of one semiconductor package;
≪ / RTI >
청구항 5에 있어서,
상기 도전성 연결수단(120)이 도전성 와이어로 채택되는 경우, 전자파 차폐물질(130)의 코팅 전에 도전성 와이어를 절연물질(132)로 봉지시키는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
Further comprising sealing the conductive wire with an insulating material (132) before coating the electromagnetic shielding material (130) when the conductive connecting means (120) is employed as the conductive wire.
청구항 5에 있어서,
상기 도전성 연결수단(120)이 도전성 범프로 채택되는 경우, 전자파 차폐물질(130)의 코팅 전에 반도체 칩(110)의 저면과 스트립 기판(100)의 상면 사이에 언더필 재료(134)를 충진하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
Filling the underfill material 134 between the bottom surface of the semiconductor chip 110 and the top surface of the strip substrate 100 before coating the electromagnetic shielding material 130 when the conductive connection means 120 is adopted as a conductive bump, ≪ / RTI >
청구항 5에 있어서,
상기 전자파 차폐물질(130)을 코팅하는 단계는 스프레이 분사 방식 또는 스퍼터링 방식에 의하여 진행되는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
Wherein the step of coating the electromagnetic wave shielding material (130) is performed by a spraying method or a sputtering method.
삭제delete
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190003331A (en) * 2017-06-30 2019-01-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device with shielding structure for cross-talk reduction
US10896879B2 (en) 2018-03-14 2021-01-19 Samsung Electronics Co., Ltd. Semiconductor package having reflective layer with selective transmittance

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9918414B2 (en) * 2015-12-18 2018-03-13 Intel Corporation Electromagnetic interference shields for electronic packages and related methods
CN105870104A (en) * 2016-03-30 2016-08-17 江苏长电科技股份有限公司 Packaging structure with electromagnetic shielding function
KR101837511B1 (en) * 2016-04-04 2018-03-14 주식회사 네패스 Semiconductor package and method of manufacturing the same
DE102018109028B4 (en) 2017-06-30 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a shield structure for reducing crosstalk and method of manufacturing the same
CN113555493A (en) * 2021-07-20 2021-10-26 甬矽电子(宁波)股份有限公司 Semiconductor packaging structure and semiconductor packaging method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005539403A (en) * 2002-09-17 2005-12-22 チップパック，インク． Semiconductor multi-package module having wire bond interconnections between stacked packages
JP2012119688A (en) * 2010-12-02 2012-06-21 Samsung Electronics Co Ltd Stacked package structure, package-on-package element, and method of manufacturing package-on-package element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005539403A (en) * 2002-09-17 2005-12-22 チップパック，インク． Semiconductor multi-package module having wire bond interconnections between stacked packages
JP2012119688A (en) * 2010-12-02 2012-06-21 Samsung Electronics Co Ltd Stacked package structure, package-on-package element, and method of manufacturing package-on-package element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190003331A (en) * 2017-06-30 2019-01-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device with shielding structure for cross-talk reduction
KR102145467B1 (en) 2017-06-30 2020-08-19 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device with shielding structure for cross-talk reduction
US10896879B2 (en) 2018-03-14 2021-01-19 Samsung Electronics Co., Ltd. Semiconductor package having reflective layer with selective transmittance

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