JP4284744B2 - High frequency integrated circuit device - Google Patents

High frequency integrated circuit device Download PDF

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Publication number
JP4284744B2
JP4284744B2 JP10546199A JP10546199A JP4284744B2 JP 4284744 B2 JP4284744 B2 JP 4284744B2 JP 10546199 A JP10546199 A JP 10546199A JP 10546199 A JP10546199 A JP 10546199A JP 4284744 B2 JP4284744 B2 JP 4284744B2
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semiconductor chip
multilayer substrate
integrated circuit
layer
frequency integrated
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JP2000299427A (en
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章 栖原
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Sony Corp
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Sony Corp
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Abstract

PROBLEM TO BE SOLVED: To reduce the size of a high-frequency integrated circuit and increase the degree of integration of the circuit, by effectively utilizing the area of a multilayered substrate by mounting semiconductor chips and chip parts on both surfaces of the substrate. SOLUTION: Semiconductor chips 11 and 21 are flip-chip mounted on both surfaces of the multilayered substrate 2 of a high-frequency integrated circuit 1 and chips parts, a heat radiation cover 3, and a heat sink 5 are provided on one surface of the substrate 2. In addition, bumps BP are respectively formed on the rear surfaces of the chips 11 and 21 and the chips 11 and 21 are joined to the substrate 2 by positioning the chips 11 and 21 on the substrate 2, in a state where the surface electrodes of the dies of the chips 11 and 21 are directly faced oppositely to the electrodes formed on the surface of the substrate 2 through the bumps BP and applying heat and pressures to the chips 11 and 21. The chip parts are composed of passive elements, such as inductance elements, capacitance elements, resistance elements, etc., and constitute a prescribed circuit together with a circuit wiring layer formed on the surface or inside of the substrate 2. Therefore, the size of the high-frequency integrated circuit 1 can be reduced and the degree of integration of the circuit 1 can be increased.

Description

【０００１】
【発明の属する技術分野】
本発明は、たとえば、移動体通信等の各種通信機器の高周波帯域の信号の処理に用いられる高周波集積回路装置に関する。
【０００２】
【従来の技術】
近年、携帯電話、自動車電話に代表される移動体通信システムの進展には目覚ましいものがある。
たとえば、日本国内では、８００ＭＨｚ帯および１．５ＧＨｚ帯のディジタルセルラー（ＰＤＣ）や、１．９ＧＨｚ帯の信号伝送を行うパーソナルハンディーホンシステム（ＰＨＳ）がサービスを行っている。日本国外においても、ＧＳＭ(Global System Mobile) を代表とする複数のシステムが既にサービスを展開している。
また、異なる通信システムをひとつの端末で利用可能な、例えば、デュアルバンド（ＣＤＭＡ(Code Division Multiple Access) 方式で１９００ＭＨｚ帯の信号伝送＋ＡＭＰＳ(Advanced Mobile Phone System)方式で８００ＭＨｚ帯の信号伝送）やデュアルモード（ＣＤＭＡ方式およびＡＭＰＳ方式で８００ＭＨｚ帯の信号伝送）などのサービスが活発になっている。
こうした発展の要因には、インフラの整備、サービスの充実とともに、携帯端末の小型、軽量化が挙げられる。当然のことながら、ｌＣチップ自体にも小型、軽量化が要求され、小型モールドパッケージやチップ外形と同程度の寸法の基板にチップを実装するＣＳＰ（Chip Size/Scale Package)が注目を浴びている。
【０００３】
高周波ＩＣでは、ＩＣ外部の外付け部品でインピーダンス整合回路やバイアス回路を実現する場合、実装する基板や周辺部品の実装状況により、ＩＣ特性が変動する場合がある。
カスタマーごとに異なるセット基板上でＩＣの特性を十分に引き出すには、周辺部品の素子値の最適化や、基板の再設計が必要になり、多大な工数がかかっている。
そのため、異なるセット基板上でもＩＣ性能が保証されるように、整合回路やバイアス回路などの回路要素を内蔵した状態で小型化を実現した実装形態が望まれている。
さらに、ＩＣの高機能化や多機能化も期待されており、半導体チップ上でさらなる集積化が進められている。
【０００４】
しかしながら、多機能化を実現する際に、たとえば、半導体材料がＧａＡｓからなる半導体チップとＳｉからなる半導体チップのように、同一プロセスでは製造できない場合や、それぞれの機能で最適なプロセス条件が異なり（最適なしきい値が異なり）プロセスが複雑になるような場合には、一つの半導体チップでの集積化は難しく、複数の半導体チップで実現するマルチチップ化が不可欠となる。
高周波ＩＣのマルチチップ化の例としては、スイッチ機能をＧａＡｓチップで実現し、ロジック機能をＳｉチップで実現した多機能スイッチや、パワーアンプおよびスイッチ機能とを有するチップと低雑音アンプおよびミキサ一機能を有するチップの二つのチップを用いた集積化ＩＣなどがある。
【０００５】
【発明が解決しようとする課題】
たとえば、図１３に示す高周波ＩＣ１０１は、ダイパッド１０２上に複数の半導体チップ１０３および１０４を搭載し、各リード１０６と各半導体チップ１０３および１０４の電極とを金属細線１０５で接続し、これらを封止樹脂１０７で封止固定したモールドパッケージ型の半導体装置である。
また、図１４に示す高周波ＩＣ２０１は、ダイパッド２０２上に複数の半導体チップ２０３および２０４を搭載し、ダイパッド２０２と半導体チップ２０３および２０４の各電極とを金属細線２０５で接続し、これらを封止樹脂２０７で封止固定し、ダイパッド２０２の裏面にバンプ２０６が形成されたＢＧＡ(Ball Grid Alley) 型の半導体装置である。
しかしながら、図１３および図１４に示す高周波ＩＣ１０１、２０１では、各半導体チップを２次元的に配置せざるを得ないため、小型化には限界があり、バイアス回路や整合回路の内蔵が難しい。また、２つの半導体チップを近接して配置しなければならないため、お互いの電気的な干渉を考慮する必要がある。
【０００６】
一方、メモリーにおいては、メモリー同士（例えばフラッシュメモリーとスタティックメモリー）の集積化や機能の異なるＩＣ（メモリーとロジック）の集積化が非常に活発である。
たとえば、図１５に示すように、２種類の半導体チップ３０３および３０４をリードフレーム上のダイパッド３０２の上下面に搭載し、金属細線３０５および３０６でワイヤボンディングし、これらとリード部３０７とを封止樹脂３０８で封止固定した半導体装置３０１では、ある程度の小型化は可能だが、整合回路やバイアス回路の内蔵は困難である。
また、たとえば、図１６に示すように、２種類の半導体チップ４０３および４０４をダイパッド４０２上に積層し、それぞれ金属細線４０５、４０６で接続し、封止樹脂４０７で封止固定したチップ積層型の半導体装置４０１方式では、２つの半導体チップ４０３および４０４をワイヤボンディングする際のスペース確保と金属細線４０５、４０６のワイヤ長の制約から実装可能なチップサイズに制限が加わり、また、整合回路やバイアス回路の内蔵も困難である。
また、たとえば、図１７に示すように、２枚のインターポーザ５０２および５０３にインナーバンプ５０７および５０９によって２つの半導体チップ５０６および５０８をそれぞれ実装し、２枚のインターポーザ５０２および５０３をスタックバンプ５０４によって接続したフリップチップ実装型ＣＳＰのスタック方式の半導体装置５０１においても、小型化の実現は可能だが、整合回路やバイアス回路の内蔵は考慮されていない。
また、たとえば、図１８に示すように、２つの半導体装置６０２および６０３のパッケージ自体を積層したパッケージ積層方式の半導体装置６０１においても、整合回路やバイアス回路の内蔵は困難であり、最終的なパッケージ厚や実装外形は大きくなってしまう。
【０００７】
本発明は、上述の従来の問題に鑑みてなされたものであって、小型化、高集積化され、回路間の電気的干渉が抑制され、放熱特性の良い高周波集積回路装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明は、複数の誘電体層が積層された多層基板と、前記多層基板の両面に実装された、能動素子を有する半導体チップと、前記多層基板の層間および表面に形成された回路配線層と、前記多層基板の表面の少なくとも一方に実装された受動素子からなるチップ部品とを有する。
【０００９】
前記多層基板の電子機器への装着面側の表層には、隣接する内層に通じる開口部が形成されており、前記半導体チップは、前記開口部内に収容され、かつ前記隣接する層上に実装されている。
【００１０】
前記開口部が形成された表層の表面には、電子機器への装着のための電極が形成されている。
【００１１】
前記開口部が形成された表層の厚さは、前記半導体チップまたは前記チップ部品の高さに応じて調整されている。
【００１２】
前記多層基板の層間に接地層が形成されている。
【００１３】
前記回路配線層は、インピーダンス整合回路およびバイアス回路の少なくとも一部を構成する。
【００１４】
前記チップ部品は、前記回路配線層とともに、前記インピーダンス整合回路およびバイアス回路を構成する。
【００１５】
前記バイアス回路が前記多層基板の層間に形成されている。
【００１６】
前記多層基板の周囲を囲む被覆部と、一方に半導体チップの表面に直接接触する接触部とを具備する放熱板を有する。
【００１７】
前記放熱板は、電磁シールドとして機能する。
【００１８】
前記放熱板は、前記多層基板の電子機器への非装着面側に実装された半導体チップの表面に接触している。
【００１９】
前記多層基板の電子機器への装着面側に実装された半導体チップの表面に直接接触し、かつ、前記開口部内に収容されている放熱板を有する。
【００２０】
前記半導体チップは、フリップチップボンディングによって前記多層基板に電気的に接合されている。
【００２１】
前記半導体チップは、ワイヤボンディングによって前記多層基板に電気的に接続されている。
【００２２】
前記各半導体チップのうち、一方面に実装された半導体チップは、フリップチップボンディングによって前記多層基板に電気的に接合され、
他方面に実装された半導体チップは、ワイヤボンディングによって前記多層基板に電気的に接続されている。
【００２３】
前記多層基板内には、前記半導体チップの実装位置に空洞が形成されている。
【００２４】
また、本発明は、積層された第１〜第４の誘電体層と、前記第４の誘電体層に積層され当該第４の誘電体層の表面に通ずる開口部が形成された第５の誘電体層と、前記第１および第２の誘電体層間と前記第３および第４の誘電体層間とに形成された導電材料からなる接地層と、前記第２および第３の誘電体層間に形成された導電性材料からなる回路配線層と、前記第１および第４の誘電体層の表面に形成された導電性材料からなる回路配線層とを有する多層基板と、前記第１および第４の表面に実装された能動素子を有する半導体チップと、前記第１および第４の少なくとも一方に実装された受動素子が形成されたチップ部品とを有する。
【００２５】
前記第２および第３の誘電体層間に形成された回路配線層は、バイアス回路を構成しており、前記第１および第４の誘電体層の表面に形成された導電性材料からなる回路配線層と前記第１および第４の少なくとも一方に実装された受動素子とは、インピーダンス整合回路を構成している。
【００２６】
前記第５の誘電体層の表面には、電子機器への装着のための電極が形成されている。
【００２７】
前記多層基板の側面および前記第１の誘電体層側を覆い、かつ第１の誘電体層表面に実装された半導体チップの表面に直接接触する放熱板を有する。
【００２８】
前記多層基板の第５の誘電体層の開口部内に収容され、当該開口部内の半導体チップの表面に直接接合された放熱板を有する。
【００２９】
本発明では、半導体チップが多層基板の両面に半導体チップが実装され、多層基板の少なくとも一方面にチップ部品が実装され、かつ、多層基板の内層および表面に回路配線層が形成されているため、複数の半導体チップおよび高周波集積回路に必要な各種の回路の集積化を多層基板の表面および内層で構成でき、小型化、高集積化が可能となる。
【００３０】
【発明の実施の形態】
以下に、本発明の実施の形態について図面を参照して説明する。
第１実施形態
図１は、本発明の第１実施形態に係る高周波集積回路装置の構造を示す断面図である。本実施形態に係る高周波集積回路装置は、たとえば、携帯端末の高周波アンプ（ＣＤＭＡ方式で１９００ＭＨｚ帯の信号送信およびＡＭＰＳ方式で８００ＭＨｚ帯の信号送信を行うデュアルバンド送信用増幅器）集積回路に適用したものである。
【００３１】
図１において、高周波集積回路装置１は、多層基板２と、多層基板２の両面にそれぞれ実装された半導体チップ１１、２１と、多層基板２の一方面に実装されたチップ部品４１と、多層基板２に対して設けられた放熱カバー３と、放熱板５とを有している。
【００３２】
半導体チップ１１、２１は、たとえば、送信信号の高周波電力増幅を行うための能動素子がそれぞれ形成されており、能動素子とともに、たとえばキャパシタ、抵抗等の受動素子が形成されており、これらの素子によって高周波回路を構成している。
能動素子は、たとえば、シリコン（Ｓｉ）を用いたバイポーラトランジスタや、ガリウム砒素（ＧａＡｓ）を用いた電界効果トランジスタや、ＭＯＳＦＥＴ等である。
半導体チップ１１、２１を形成する材料としては、たとえば、ＧａＡｓ等の化合物半導体や、Ｓｉ等の半導体が用いられる。
また、半導体チップ１１、２１は、高周波電力増幅を行うため、熱的に放熱が不可欠である。
【００３３】
半導体チップ１１、２１の裏面には、それぞれバンプＢＰが形成されており、半導体チップ１１、２１は、多層基板２にフリップチップ方式で実装されている。
すなわち、半導体チップ１１、１２のダイの表面電極と多層基板２の表面に形成された電極とをバンプＢＰを介して直接対向させて位置決めし、熱および圧力を加えて半導体チップ１１、１２を多層基板２に接合してある。
【００３４】
チップ部品４１は、たとえば、インダクター素子、容量素子、抵抗素子等の受動素子がそれぞれ形成されており、多層基板２の表面または内層に形成された回路配線層とともに、所定の機能の回路を構成している。
具体的には、チップ部品４１は、たとえば、多層基板２の表面に形成された回路配線層とともに、半導体チップ１１、２１が行う送信信号の高周波増幅におけるインピーダンス整合回路を構成している。
なお、図１では、チップ部品４１は多層基板２の一方面にのみ実装されているが、本実施形態では多層基板２の両面に実装されているものとする。
【００３５】
多層基板２は、５層の第１〜第５誘電体層２ａ〜２ｅの積層構造となっていおる。
多層基板２の各誘電体層２ａ〜２ｅの形成材料は、たとえば、窒化アルミニウム、アルミナ、窒化シリコン、ガラスセラミック、ガラスエポキシ等の誘電体を用いることができる。また、これらの誘電体材料から、誘電率やコストを考慮して決定される。なお、必要に応じて、これらの材料を組み合わせて使用してもよい。
【００３６】
図２および図３は、多層基板２の構成を示す断面図である。
なお、図２の（ａ）は、多層基板２の第１誘電体層２ａを表面側から見た図であり、（ｂ）は第１誘電体層２ａを第２誘電体層２ｂとの層間側から見た図であり、（ｃ）は第２誘電体層２ａを第３誘電体層２ｃとの層間側から見た図である。図３の（ａ）は第３誘電体層２ｃを第４誘電体層２ｄとの層間側から見た図であり、（ｂ）は第４誘電体層２ｄを第５誘電体層２ｅとの層間側から見た図であり、（ｃ）は第５誘電体層２ｅを表面側から見た図である。
【００３７】
第１誘電体層２ａは最上層であり、図２（ａ）に示すように、第１誘電体層２ａの上面には、たとえば、図示しないストリップライン（導体線路）で構成される回路配線層５１が形成されているとともに、半導体チップ１１およびチップ部品４１が実装されている。
回路配線層５１は、具体的には、たとえば、チップ部品４１とともに半導体チップ１１に対するインピーダンス整合回路を構成している。
【００３８】
図２（ｂ）に示すように、第１誘電体層２ａの下面、すなわち、第１誘電体層２ａと第２誘電体層２ｂとの層間には、たとえば、銅、アルミニウム等の導電性材料からなる接地層Ｇ１が形成されている。接地層Ｇ１は接地レベルである。
【００３９】
図２（ｃ）に示すように、第２誘電体層２ｂの下面には、すなわち、第２誘電体層２ｂと第３誘電体層２ｃとの層間には、たとえば、図示しないストリップライン（導体線路）で構成される回路配線層５２が導電性材料によって形成されている。
回路配線層５２は、具体的には、たとえば、半導体チップ１１、２１に各種電源を供給するバイアス回路を構成している。
バイアス回路は、基本波から発生した高調波を減衰させるために、伝送信号の基準波長λのλ／４の長さのストリップラインなどで構成する。なお、λ／４ののストリップラインの長さは、たとえば、８００ＭＨｚの場合には、約３０ｍｍとなる。
【００４０】
図３（ａ）に示すように、第３誘電体層２ｃの下面、すなわち、第３誘電体層２ｃと第４誘電体層２ｄとの層間には、接地層Ｇ２が形成されている。接地層Ｇ２は接地レベルである。
【００４１】
図３（ｂ）に示すように、第４誘電体層２ｄの下面、すなわち、第４誘電体層２ｄと第５誘電体層２ｅとの層間には、たとえば、図示しないストリップラインによって構成される回路配線層５３が形成されるとともに、半導体チップ２１とチップ部品４１とが実装されている。
【００４２】
第５誘電体層２ｅは最下層であり、図示しない電子機器の親基板に装着される層である。
第５誘電体層２ｅは、図３（ｃ）に示すように、第４誘電体層２ｄに実装された半導体チップ２１やチップ部品４１が挿通しかつ収容する開口部５５が設けられている。
また、第５誘電体層２ｅには、電子機器の親基板との接合のための、たとえば、ランド型の電極５４が複数形成されている。
第５誘電体層２ｅの厚さは、半導体チップ２１の高さ、または、チップ部品４１の高さ、あるいはチップ部品４１の有無によって、開口部５５内に半導体チップ２１およびチップ部品４１が確実に収容されるように調整されている。
【００４３】
上記の第１〜第５誘電体層２ａ〜２ｅの層間に形成された回路配線層５２および接地層Ｇ１、Ｇ２と、多層基板２の両面に形成された回路配線層５１，５３、半導体チップ１１，２１、各チップ部品４１は、図１に示すように、各誘電体層２ａ〜２ｅに形成されたスルーホール内の配線５６および多層基板の周囲に形成された配線５７によって互いに電気的に接続されている。配線５７は、第５誘電体層２ｅに形成された電極５４に電気的に接続されている。
【００４４】
放熱カバー３は、多層基板２の第１誘電体層２ａ側に対して、多層基板２の外周および第１誘電体層２ａ側を覆うように設けられた被覆部３ｂと、被覆部３ｂに一体に形成された半導体チップ１１の表面と直接接触する接触部３ａとを有している。
放熱カバー３の接触部３ａは、多層基板２に実装された半導体チップ１１の表面と、たとえば、接着剤によって接合されており、多層基板２は放熱カバー３に保持されている。
放熱カバー３の材質としては、熱伝導性の良好なもの、例えばアルミニウム等の金属材料が用いられる。
放熱カバー３の被覆部３ｂの端部には、放熱カバー３を電子機器の親基板に取り付けるための取り付け部３ｃが形成されている。
【００４５】
多層基板２の下面に実装された半導体チップ２２の下面には、放熱板５が取り付けられ、半導体チップ２２とともに封止樹脂Ｒによって樹脂固定されている。放熱板５は、多層基板２の第５誘電体層５ｅの開口部５５内に収容されており、第５誘電体層５ｅの表面から突出していない。
放熱板５は、熱伝導性の良好な上記の放熱カバー３と同様の材料で形成される。
【００４６】
上記高周波集積回路装置１は、電子機器の親基板に対して、放熱カバー３の取り付け部３ｃおよび第５誘電体層５ｅが接合される。
電子機器から高周波集積回路装置１に装着されると、たとえば、多層基板２の第２誘電体層２ｂと第３誘電体層２ｃとの層間に形成された回路配線層５２のバイアス回路を通じて半導体チップ１１、２１に電源が供給され、半導体チップ１１、２１は高周波電力増幅を行う。
【００４７】
多層基板２の両面に実装された半導体チップ１１および２１とも高周波電力増幅を行うので、半導体チップ１１および２１の発熱量は大きく、放熱を行う必要がある。
多層基板２の上面に実装された半導体チップ１１から発生した熱は、接触部３ａを通じて放熱カバー３に伝えられる。
放熱カバー３の被覆部３ｂは、広い表面積で空気に触れているため、放熱カバー３に伝えられた熱は空気中に放熱される。さらに、放熱カバー３の取り付け部３ｃにより親基板に取り付けていると、放熱カバー３の熱は、親基板により放熱される。なお、この放熱カバー３は、半導体チップ１１の放熱を行うとともに、多層基板２の表面への塵の侵入防止や、外部との電磁シールドとしても機能する。
【００４８】
多層基板２の下面に実装された半導体チップ２１から発生した熱は、その下面に取り付けられている放熱板５を介して多層基板２が装着される図示しない電子機器の親基板に伝えられ、親基板より放熱される。
【００４９】
本実施形態に係る高周波集積回路装置１では、多層基板２の両面を使って半導体チップ１１、２１やチップ部品４１の実装を行っており、基板面積を有効に利用でき、３次元的な小型化が可能となる。
また、複数の誘電体層２ａ〜２ｅが積層された多層基板２を用いることにより、誘電体層２ａ〜２ｅの層間に、たとえば、バイアス回路においてλ／４の長さのストリップライン等の比較的線路長の長い回路を形成することができ、立体的に、整合回路やバイアス回路を組み込むことが可能となる。
また、多層基板２の両面には、インダクター素子や容量素子などのチップ部品４１も実装され、多層基板２の両面を使って部品実装を行うことで基板面積が有効に利用でき、小型化が可能となる。
【００５０】
さらに、本実施形態に係る高周波集積回路装置１によれば、誘電体層２ａ〜２ｅの層間に接地層Ｇ１およびＧ２を形成して、各回路配線層５１、５２、５３の間に位置させているため、各回路配線層５１、５２、５３間の電気的な干渉を防止することができる。
また、放熱カバー３は、放熱のみならず、高周波集積回路装置１内への塵の侵入防止や電磁シールドのためにも必要であるから、元々カバーは必要なものであり、放熱カバー３を取り付けることにより、大型化したり、コストアップになることはない。
なお、上述の説明では、チップ部品４１は多層基板２の両面上に実装されているものとしたが、一方面のみの実装でも構わない。また、チップ部品４１を実装せずに、半導体チップ１１、２１のみの実装でもよい。
【００５１】
第２の実施形態
図４〜図７は、本発明の第２の実装形態に係る高周波集積回路装置の構造を示す断面図である。なお、第１の実施形態に係る高周波集積回路装置の構成要素と同一の構成要素については同一の符号をもって示している。
図４および図５に示す高周波集積回路装置は、基本的には、上述した第１の実施形態に係る高周波集積回路装置と同一の構成であるが、多層基板２の両面に実装される半導体チップ１１および２１のうち、一方が発熱量が比較的大きく、他方が発熱量が比較的小さい場合に本発明を適用した場合の構成を示している。
【００５２】
図４に示す高周波集積回路装置６１は、多層基板２の第１誘電体層２ａの表面に実装された半導体チップ１１の発熱が大きく、多層基板２の第５誘電体層２ｅに実装された半導体チップ２１の発熱が小さい場合である。
半導体チップ１１は、たとえば、送信信号増幅回路を有し、半導体チップ２１は、たとえば、多機能スイッチ回路を有している。
図４に示すように、発熱が大きい半導体チップ１１に対しては、放熱カバー３を設け、発熱量の小さい半導体チップ２１には上記の放熱板５は設けず、半導体チップ２１は、フリップチップ方式で多層基板２の第４誘電体層２ｄに実装され、封止樹脂Ｒによって覆われている。
【００５３】
図５に示す高周波集積回路装置６２は、図４に示した高周波集積回路装置６１と同様に、半導体チップ１１の発熱が大きく、半導体チップ２１の発熱が小さい場合である。
図５に示すように、発熱が大きい半導体チップ１１に対しては、放熱カバー３を設け、発熱量の小さい半導体チップ２１には上記の放熱板５は設けない。
また、半導体チップ２１は、表面電極が形成された面を第４誘電体層２ｄに対して反対向きにして第４誘電体層２ｄに接合し、半導体チップ２１の表面電極と第４誘電体層２ｄ上の電極とを金属細線５９でワイヤリングするとともに、第５誘電体層２ｅの開口部５５内を樹脂Ｒで充填して半導体チップ２１および金属細線５９を固定する。
【００５４】
以上のように、半導体チップ１１の発熱が大きく、半導体チップ２１の発熱が小さい場合には、図４および図５に示した構成のように、ワイヤ長のばらつきやインダクタンスの影響を避けるべき半導体チップや放熱を必要とする半導体チップはフリップチップ方式で実装し、これらの必要のない半導体チップはワイヤボンディングを用いて実装することで対応可能となる。
【００５５】
図６に示す高周波集積回路装置６３は、半導体チップ１１の発熱が小さく、半導体チップ２１の発熱が大きい場合である。
この場合には、図６に示すように、半導体チップ１１に対して上記の放熱カバー３は設けず、半導体チップ２１に対しては放熱板５を設ける。
また、半導体チップ１１および半導体チップ２１は、バンプＢＰを介して多層基板２の両面にそれぞれフリップチップ方式で実装されている。
半導体チップ２１およびは放熱板５は、第５誘電体層２ｅの開口部５５内に樹脂Ｒによって固定されている。
【００５６】
図７に示す高周波集積回路装置６４は、図６に示した高周波集積回路装置６３と同様に、半導体チップ１１の発熱が小さく、半導体チップ２１の発熱が大きい場合である。
図７に示すように、半導体チップ１１は、半導体チップ１１の表面電極形成側を第１誘電体層２ａに対して反対向きに配置し、この表面電極と第１誘電体層２ａ上の電極とを金属細線７０でワイヤリングするとともに、半導体チップ１１および金属細線７０を樹脂Ｒで固定している。
半導体チップ２１の実装構造は、図６に示した高周波集積回路装置６３と同様にしている。
【００５７】
以上のように、半導体チップ１１の発熱が小さく、半導体チップ２１の発熱が大きい場合には、図６および図７に示した構成で対応可能である。
【００５８】
第３の実施形態
図８〜図１１は、本発明の第３の実装形態に係る高周波集積回路装置の構造を示す断面図である。なお、第１の実施形態に係る高周波集積回路装置の構成要素と同一の構成要素については同一の符号をもって示している。
図８〜図１１に示す高周波集積回路装置は、基本的には、上述した第１の実施形態に係る高周波集積回路装置と同一の構成であるが、多層基板２の両面に実装される半導体チップ１１および２１の発熱量が小さく、特に放熱手段を設けなくてもよい場合である。
【００５９】
図８に示す高周波集積回路装置６５は、半導体チップ１１および２１をフリップチップ方式で多層基板２に実装し、樹脂Ｒで固定している。
図９に示す高周波集積回路装置６６は、半導体チップ１１が特に発熱量が少ない場合であり、半導体チップ１１の表面電極形成側を第１誘電体層２ａに対して反対向きに配置し、この表面電極と第１誘電体層２ａ上の電極とを金属細線７２でワイヤリングするとともに、半導体チップ１１および金属細線７０を樹脂Ｒで固定している。
【００６０】
図１０に示す高周波集積回路装置６７は、多層基板２の下面に実装される半導体チップ２１が特に発熱量が少ない場合であり、半導体チップ２１の表面電極形成側を第４誘電体層２ｄに対して反対向きに配置し、この表面電極と第５誘電体層２ｄ上の電極とを金属細線７３でワイヤリングするとともに、半導体チップ２１および金属細線７３を樹脂Ｒで固定している。
図１１に示す高周波集積回路装置６８は、多層基板２の両面に実装される半導体チップ１１、１２が共に特に発熱量が少ない場合であり、半導体チップ１１、１２が図９および図１０に示した方法で実装されている。
【００６１】
以上のように、半導体チップ１１、１２の発熱量が小さい場合には、図８〜図１１に示した構成で対応可能となる。
【００６２】
第４の実施形態
図１２は、本発明の第４の実装形態に係る高周波集積回路装置の構造を示す断面図である。なお、第１の実施形態に係る高周波集積回路装置の構成要素と同一の構成要素については同一の符号をもって示している。
図１２に示す高周波集積回路装置６９は、多層基板２の下面に実装される半導体チップ２１の処理する周波数がより高い場合である。
半導体チップ２１が、さらに高い周波数の処理を行う場合には、たとえば、図１２に示すように、多層基板２の第４誘電体層２ｄの表面に実装した半導体チップ２１の実装位置に対応する多層基板２の第４誘電体層２ｄおよび第３誘電体層２ｃに空洞であるキャビティーＨを形成する。
このような構成とすることにより、キャビティーＨの空間は、誘電体よりも誘電率が低く、低インダクタンスとなり、半導体チップ２１の高周波特性への影響を抑制することができる。
なお、本実施形態では、多層基板２の下面に実装される半導体チップ２１に対してキャビティーＨを形成しているが、同様に、多層基板２の上面に実装される半導体チップ１１に対してもキャビティーＨを形成することが可能である。
【００６３】
本発明は、上述した実施形態では、多層基板２の各表面に実装された半導体チップはそれぞれ単数であったが、本発明はこれに限定されるわけではなく、多層基板２の両面に実装される半導体チップが複数であってもよい。
【００６４】
【発明の効果】
本発明によれば、多層基板の両面を使って半導体チップおよびチップ部品の実装を行っているため、基板面積を有効に利用でき、高周波集積回路装置の小型化、高集積化が可能である。
また、本発明によれば、ワイヤ長のばらつきやインダクタンスの影響を避けるべき半導体チップや放熱を必要とする半導体チップの実装については、フリップ実装を用い、それらを考慮しなくてよい場合には、ワイヤリング方式を採用するため、実装方式の自由度を拡大させることができる。
また、本発明によれば、半導体チップおよびチップ部品を実装する基板として多層基板を用いることにより、高密度実装が行えるとともに、多層基板中には接地層を含める回路配線層間の電気的な干渉が防止され、かつ熱抵抗を低下させることが可能となる。
また、本発明によれば、半導体チップおよびチップ部品を実装する基板として多層基板を用いることにより、バイアス回路を多層基板の誘電体層間に実現可能であり、層間を有効に活用することで小型化、高実装化が可能となる。
また、本発明によれば、放熱が必要な半導体チップを実装した場合であっても、容易に対応可能である。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る高周波集積回路装置の構造を示す断面図である。
【図２】図１の高周波集積回路装置の多層基板の構成を示す図である。
【図３】図１の高周波集積回路装置の多層基板の構成を示す図である。
【図４】本発明の第２の実施形態に係る高周波集積回路装置の構造の一例を示す断面図である。
【図５】本発明の第２の実施形態に係る高周波集積回路装置の構造の他の例を示す断面図である。
【図６】本発明の第２の実施形態に係る高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図７】本発明の第２の実施形態に係る高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図８】本発明の第３の実施形態に係る高周波集積回路装置の構造の一例を示す断面図である。
【図９】本発明の第３の実施形態に係る高周波集積回路装置の構造の他の例を示す断面図である。
【図１０】本発明の第３の実施形態に係る高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図１１】本発明の第３の実施形態に係る高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図１２】本発明の第４の実施形態に係る高周波集積回路装置の構造を示す断面図である。
【図１３】従来の高周波集積回路装置の構造の一例を示す断面図である。
【図１４】従来の高周波集積回路装置の構造の他の例を示す断面図である。
【図１５】従来の高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図１６】従来の高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図１７】従来の高周波集積回路装置の構造のさらに他の例を示す断面図である。
【図１８】従来の高周波集積回路装置の構造のさらに他の例を示す断面図である。
【符号の説明】
１…高周波集積回路装置、２…多層基板、２ａ〜２ｅ…第１〜第５誘電体層、３…放熱カバー、５…放熱板、１１，２１…半導体チップ、４１…チップ部品、５１，５２，５３…回路配線層、Ｇ１，Ｇ２…接地層。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high frequency integrated circuit device used for processing a signal in a high frequency band of various communication devices such as mobile communication.
[0002]
[Prior art]
In recent years, there has been a remarkable progress in mobile communication systems represented by mobile phones and automobile phones.
For example, in Japan, 800 MHz band and 1.5 GHz band digital cellular (PDC) and personal handy phone systems (PHS) that perform signal transmission of 1.9 GHz band provide services. Outside Japan, a number of systems represented by GSM (Global System Mobile) have already developed services.
Further, different communication systems can be used in one terminal, for example, dual band (1900 MHz band signal transmission by CDMA (Code Division Multiple Access) system + 800 MHz band signal transmission by AMPS (Advanced Mobile Phone System) system) or dual band. Services such as modes (800 MHz band signal transmission in CDMA and AMPS systems) are active.
These development factors include the development of infrastructure and enhancement of services, as well as the reduction in size and weight of mobile terminals. Naturally, the IC chip itself is also required to be small and light, and CSP (Chip Size / Scale Package) that mounts the chip on a substrate of the same size as the small mold package or chip outline is attracting attention. .
[0003]
In a high-frequency IC, when an impedance matching circuit and a bias circuit are realized by external components external to the IC, the IC characteristics may vary depending on the mounting state of the substrate to be mounted and peripheral components.
In order to fully extract the characteristics of the IC on different set substrates for each customer, it is necessary to optimize the element values of peripheral components and to redesign the substrate, which takes a lot of man-hours.
Therefore, there is a demand for a mounting form that achieves miniaturization in a state in which circuit elements such as a matching circuit and a bias circuit are incorporated so that IC performance is guaranteed even on different set substrates.
Furthermore, higher functionality and multi-function of ICs are also expected, and further integration is being promoted on semiconductor chips.
[0004]
However, when realizing multi-functionality, for example, when the semiconductor material cannot be manufactured in the same process, such as a semiconductor chip made of GaAs and a semiconductor chip made of Si, the optimum process conditions differ for each function ( When the process is complicated (differing in the optimum threshold value), it is difficult to integrate with one semiconductor chip, and it is indispensable to make a multi-chip realized with a plurality of semiconductor chips.
Examples of multi-chip high frequency ICs include a multi-function switch in which the switch function is realized with a GaAs chip and a logic function with an Si chip, a chip having a power amplifier and a switch function, a low-noise amplifier, and a single mixer function There is an integrated IC using two chips of a chip having
[0005]
[Problems to be solved by the invention]
For example, a high-frequency IC 101 shown in FIG. 13 has a plurality of semiconductor chips 103 and 104 mounted on a die pad 102, and leads 106 and electrodes of the semiconductor chips 103 and 104 are connected by metal thin wires 105 and sealed. This is a mold package type semiconductor device sealed and fixed with a resin 107.
14 has a plurality of semiconductor chips 203 and 204 mounted on a die pad 202, and the die pad 202 and each electrode of the semiconductor chips 203 and 204 are connected by a thin metal wire 205, and these are sealed with a sealing resin. This is a BGA (Ball Grid Alley) type semiconductor device that is sealed and fixed at 207 and has bumps 206 formed on the back surface of the die pad 202.
However, in the high frequency ICs 101 and 201 shown in FIG. 13 and FIG. 14, each semiconductor chip must be two-dimensionally arranged, so there is a limit to downsizing and it is difficult to incorporate a bias circuit and a matching circuit. Moreover, since two semiconductor chips must be arranged close to each other, it is necessary to consider electrical interference between them.
[0006]
  On the other hand, in memories, integration of memories (for example, flash memory and static memory) and integration of ICs (memory and logic) having different functions are very active.
  For example, as shown in FIG.3In the semiconductor device 301 in which 03 and 304 are mounted on the upper and lower surfaces of the die pad 302 on the lead frame, wire-bonded with the fine metal wires 305 and 306, and the lead portion 307 are sealed and fixed with the sealing resin 308, Although downsizing is possible, it is difficult to incorporate a matching circuit and a bias circuit.
  Further, for example, as shown in FIG. 16, two types of semiconductor chips 403 and 404 are stacked on a die pad 402, respectively connected by thin metal wires 405 and 406, and sealed and fixed by a sealing resin 407. In the semiconductor device 401 system, the chip size that can be mounted is limited due to the space secured when wire bonding the two semiconductor chips 403 and 404 and the wire length of the thin metal wires 405 and 406, and the matching circuit and bias circuit are also limited. It is also difficult to incorporate.
  Further, for example, as shown in FIG. 17, two semiconductor chips 506 and 508 are mounted on two interposers 502 and 503 by inner bumps 507 and 509, respectively, and the two interposers 502 and 503 are connected by stack bumps 504. The flip-chip mounting type CSP stack type semiconductor device 501 can also be reduced in size, but does not take into account the incorporation of a matching circuit or a bias circuit.
  Also, for example, as shown in FIG. 18, in a package stacking type semiconductor device 601 in which the packages of two semiconductor devices 602 and 603 themselves are stacked, it is difficult to incorporate a matching circuit and a bias circuit. Thickness and mounting outline become large.
[0007]
The present invention has been made in view of the above-described conventional problems, and is to provide a high-frequency integrated circuit device that is miniaturized and highly integrated, suppresses electrical interference between circuits, and has good heat dissipation characteristics. Objective.
[0008]
[Means for Solving the Problems]
The present invention includes a multilayer substrate in which a plurality of dielectric layers are laminated, a semiconductor chip having active elements mounted on both surfaces of the multilayer substrate, and a circuit wiring layer formed between layers and on the surface of the multilayer substrate. And a chip component made of a passive element mounted on at least one of the surfaces of the multilayer substrate.
[0009]
In the surface layer on the mounting surface side of the multilayer substrate on the electronic device, an opening leading to an adjacent inner layer is formed, and the semiconductor chip is accommodated in the opening and mounted on the adjacent layer. ing.
[0010]
An electrode for mounting on an electronic device is formed on the surface of the surface layer where the opening is formed.
[0011]
The thickness of the surface layer in which the opening is formed is adjusted according to the height of the semiconductor chip or the chip component.
[0012]
A ground layer is formed between the layers of the multilayer substrate.
[0013]
The circuit wiring layer constitutes at least a part of an impedance matching circuit and a bias circuit.
[0014]
The chip component forms the impedance matching circuit and the bias circuit together with the circuit wiring layer.
[0015]
The bias circuit is formed between layers of the multilayer substrate.
[0016]
The heat sink includes a covering portion that surrounds the periphery of the multilayer substrate and a contact portion that directly contacts the surface of the semiconductor chip on one side.
[0017]
The heat sink functions as an electromagnetic shield.
[0018]
The heat sink is in contact with the surface of the semiconductor chip mounted on the non-mounting surface side of the multilayer substrate to the electronic device.
[0019]
A heat dissipation plate that is in direct contact with the surface of the semiconductor chip mounted on the electronic device mounting surface side of the multilayer substrate and is housed in the opening;
[0020]
The semiconductor chip is electrically bonded to the multilayer substrate by flip chip bonding.
[0021]
The semiconductor chip is electrically connected to the multilayer substrate by wire bonding.
[0022]
Of each of the semiconductor chips, a semiconductor chip mounted on one surface is electrically bonded to the multilayer substrate by flip chip bonding,
The semiconductor chip mounted on the other surface is electrically connected to the multilayer substrate by wire bonding.
[0023]
A cavity is formed in the multilayer substrate at the mounting position of the semiconductor chip.
[0024]
Further, according to the present invention, there is provided a fifth dielectric layer in which first to fourth dielectric layers are laminated, and an opening is formed that is laminated on the fourth dielectric layer and communicates with a surface of the fourth dielectric layer. A dielectric layer, a ground layer made of a conductive material formed between the first and second dielectric layers and the third and fourth dielectric layers, and between the second and third dielectric layers A multilayer substrate having a circuit wiring layer made of a conductive material and a circuit wiring layer made of a conductive material formed on the surfaces of the first and fourth dielectric layers; and the first and fourth A semiconductor chip having an active element mounted on the surface thereof, and a chip component on which a passive element mounted on at least one of the first and fourth is formed.
[0025]
The circuit wiring layer formed between the second and third dielectric layers constitutes a bias circuit, and the circuit wiring made of a conductive material formed on the surfaces of the first and fourth dielectric layers. The layer and the passive element mounted on at least one of the first and fourth constitute an impedance matching circuit.
[0026]
An electrode for mounting on an electronic device is formed on the surface of the fifth dielectric layer.
[0027]
A heat dissipation plate that covers a side surface of the multilayer substrate and the first dielectric layer side, and that directly contacts the surface of the semiconductor chip mounted on the surface of the first dielectric layer;
[0028]
A heat sink is housed in the opening of the fifth dielectric layer of the multilayer substrate and is directly bonded to the surface of the semiconductor chip in the opening.
[0029]
In the present invention, the semiconductor chip is mounted on both surfaces of the multilayer substrate, the chip component is mounted on at least one surface of the multilayer substrate, and the circuit wiring layer is formed on the inner layer and the surface of the multilayer substrate. Integration of various circuits necessary for a plurality of semiconductor chips and a high-frequency integrated circuit can be configured on the surface and inner layer of a multilayer substrate, and miniaturization and high integration are possible.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First embodiment
FIG. 1 is a cross-sectional view showing the structure of the high-frequency integrated circuit device according to the first embodiment of the present invention. The high-frequency integrated circuit device according to the present embodiment is applied to, for example, a high-frequency amplifier (dual-band transmission amplifier that performs signal transmission in the 1900 MHz band by the CDMA method and signal transmission in the 800 MHz band by the AMPS method) of a portable terminal. It is.
[0031]
In FIG. 1, a high-frequency integrated circuit device 1 includes a multilayer substrate 2, semiconductor chips 11 and 21 mounted on both surfaces of the multilayer substrate 2, a chip component 41 mounted on one surface of the multilayer substrate 2, and a multilayer substrate. 2 has a heat dissipating cover 3 and a heat dissipating plate 5.
[0032]
  The semiconductor chips 11 and 21 are, for example, active elements for performing high-frequency power amplification of transmission signals.ChildAre formed, and passive elements such as capacitors and resistors are formed together with the active elements, and these elements constitute a high-frequency circuit.
  The active element is, for example, a bipolar transistor using silicon (Si), a field effect transistor using gallium arsenide (GaAs), a MOSFET, or the like.
  As a material for forming the semiconductor chips 11 and 21, for example, a compound semiconductor such as GaAs or a semiconductor such as Si is used.
  Further, since the semiconductor chips 11 and 21 perform high-frequency power amplification, heat dissipation is indispensable.
[0033]
Bumps BP are respectively formed on the back surfaces of the semiconductor chips 11 and 21, and the semiconductor chips 11 and 21 are mounted on the multilayer substrate 2 by a flip chip method.
That is, the surface electrodes of the dies of the semiconductor chips 11 and 12 and the electrodes formed on the surface of the multilayer substrate 2 are directly opposed via the bumps BP, and the semiconductor chips 11 and 12 are multilayered by applying heat and pressure. Bonded to the substrate 2.
[0034]
The chip component 41 is formed with passive elements such as an inductor element, a capacitive element, and a resistive element, for example, and constitutes a circuit having a predetermined function together with a circuit wiring layer formed on the surface or inner layer of the multilayer substrate 2. ing.
Specifically, the chip component 41 constitutes, for example, an impedance matching circuit for high-frequency amplification of transmission signals performed by the semiconductor chips 11 and 21 together with a circuit wiring layer formed on the surface of the multilayer substrate 2.
In FIG. 1, the chip component 41 is mounted only on one surface of the multilayer substrate 2, but in this embodiment, it is mounted on both surfaces of the multilayer substrate 2.
[0035]
The multilayer substrate 2 has a laminated structure of five first to fifth dielectric layers 2a to 2e.
As a material for forming the dielectric layers 2a to 2e of the multilayer substrate 2, for example, a dielectric such as aluminum nitride, alumina, silicon nitride, glass ceramic, glass epoxy, or the like can be used. Further, it is determined from these dielectric materials in consideration of dielectric constant and cost. In addition, you may use it combining these materials as needed.
[0036]
2 and 3 are cross-sectional views showing the configuration of the multilayer substrate 2.
2A is a diagram of the first dielectric layer 2a of the multilayer substrate 2 as viewed from the surface side, and FIG. 2B is a diagram illustrating the first dielectric layer 2a and the second dielectric layer 2b. It is the figure seen from the side, (c) is the figure which looked at the 2nd dielectric material layer 2a from the interlayer side with the 3rd dielectric material layer 2c. FIG. 3A is a view of the third dielectric layer 2c as viewed from the interlayer side with respect to the fourth dielectric layer 2d, and FIG. 3B is a diagram illustrating the fourth dielectric layer 2d with the fifth dielectric layer 2e. It is the figure seen from the interlayer side, (c) is the figure which looked at the 5th dielectric layer 2e from the surface side.
[0037]
The first dielectric layer 2a is the uppermost layer. As shown in FIG. 2A, on the upper surface of the first dielectric layer 2a, for example, a circuit wiring layer constituted by strip lines (conductor lines) not shown. 51 is formed, and the semiconductor chip 11 and the chip component 41 are mounted.
Specifically, the circuit wiring layer 51 constitutes, for example, an impedance matching circuit for the semiconductor chip 11 together with the chip component 41.
[0038]
As shown in FIG. 2B, a conductive material such as copper or aluminum is formed on the lower surface of the first dielectric layer 2a, that is, between the first dielectric layer 2a and the second dielectric layer 2b. A ground layer G1 is formed. The ground layer G1 is at the ground level.
[0039]
As shown in FIG. 2C, on the lower surface of the second dielectric layer 2b, that is, between the second dielectric layer 2b and the third dielectric layer 2c, for example, a strip line (not shown) A circuit wiring layer 52 composed of a line is formed of a conductive material.
Specifically, the circuit wiring layer 52 constitutes, for example, a bias circuit that supplies various power supplies to the semiconductor chips 11 and 21.
The bias circuit is composed of a strip line having a length of λ / 4 of the reference wavelength λ of the transmission signal in order to attenuate harmonics generated from the fundamental wave. The length of the λ / 4 strip line is about 30 mm in the case of 800 MHz, for example.
[0040]
As shown in FIG. 3A, a ground layer G2 is formed on the lower surface of the third dielectric layer 2c, that is, between the third dielectric layer 2c and the fourth dielectric layer 2d. The ground layer G2 is at the ground level.
[0041]
As shown in FIG. 3B, the lower surface of the fourth dielectric layer 2d, that is, the interlayer between the fourth dielectric layer 2d and the fifth dielectric layer 2e is constituted by, for example, a strip line (not shown). The circuit wiring layer 53 is formed, and the semiconductor chip 21 and the chip component 41 are mounted.
[0042]
The fifth dielectric layer 2e is the lowermost layer and is a layer attached to a parent substrate of an electronic device (not shown).
As shown in FIG. 3C, the fifth dielectric layer 2e is provided with an opening 55 through which the semiconductor chip 21 and the chip component 41 mounted on the fourth dielectric layer 2d are inserted and accommodated.
The fifth dielectric layer 2e is formed with a plurality of, for example, land-type electrodes 54 for bonding to the parent substrate of the electronic device.
The thickness of the fifth dielectric layer 2e depends on the height of the semiconductor chip 21, the height of the chip component 41, or the presence or absence of the chip component 41. It is adjusted to be accommodated.
[0043]
Circuit wiring layer 52 and ground layers G1 and G2 formed between the first to fifth dielectric layers 2a to 2e, circuit wiring layers 51 and 53 formed on both surfaces of the multilayer substrate 2, and the semiconductor chip 11 , 21 and each chip component 41 are electrically connected to each other by a wiring 56 in a through hole formed in each dielectric layer 2a to 2e and a wiring 57 formed around the multilayer substrate as shown in FIG. Has been. The wiring 57 is electrically connected to the electrode 54 formed on the fifth dielectric layer 2e.
[0044]
The heat radiating cover 3 is integrated with the covering portion 3b and the covering portion 3b provided to cover the outer periphery of the multilayer substrate 2 and the first dielectric layer 2a side with respect to the first dielectric layer 2a side of the multilayer substrate 2. And a contact portion 3a that is in direct contact with the surface of the semiconductor chip 11 formed on the substrate.
The contact portion 3 a of the heat dissipation cover 3 is bonded to the surface of the semiconductor chip 11 mounted on the multilayer substrate 2 by, for example, an adhesive, and the multilayer substrate 2 is held by the heat dissipation cover 3.
As the material of the heat radiating cover 3, a material having good thermal conductivity, for example, a metal material such as aluminum is used.
An attachment portion 3c for attaching the heat dissipation cover 3 to the parent substrate of the electronic device is formed at the end of the covering portion 3b of the heat dissipation cover 3.
[0045]
The heat sink 5 is attached to the lower surface of the semiconductor chip 22 mounted on the lower surface of the multilayer substrate 2, and is fixed to the semiconductor chip 22 together with the sealing resin R. The heat sink 5 is accommodated in the opening 55 of the fifth dielectric layer 5e of the multilayer substrate 2, and does not protrude from the surface of the fifth dielectric layer 5e.
The heat radiating plate 5 is formed of the same material as that of the heat radiating cover 3 having good thermal conductivity.
[0046]
In the high-frequency integrated circuit device 1, the attachment portion 3c of the heat dissipation cover 3 and the fifth dielectric layer 5e are joined to the parent substrate of the electronic device.
When mounted on the high frequency integrated circuit device 1 from an electronic device, for example, the semiconductor chip through a bias circuit of a circuit wiring layer 52 formed between the second dielectric layer 2b and the third dielectric layer 2c of the multilayer substrate 2 11 and 21 are supplied with power, and the semiconductor chips 11 and 21 perform high-frequency power amplification.
[0047]
  Since the semiconductor chips 11 and 21 mounted on both surfaces of the multilayer substrate 2 also perform high-frequency power amplification, the semiconductor chips 11 and 21 generate a large amount of heat and need to dissipate heat.
  Heat generated from the semiconductor chip 11 mounted on the upper surface of the multilayer substrate 2 is transmitted to the heat dissipation cover 3 through the contact portion 3a.
  Cover of heat dissipation cover 33bSince the air touches the air with a large surface area, the heat transferred to the heat dissipation cover 3 is dissipated into the air. Further, when the heat radiation cover 3 is attached to the parent substrate by the attachment portion 3c of the heat radiation cover 3, the heat of the heat radiation cover 3 is radiated by the parent substrate. The heat radiating cover 3 radiates heat from the semiconductor chip 11, and also functions as a dust intrusion prevention to the surface of the multilayer substrate 2 and as an electromagnetic shield with the outside.
[0048]
The heat generated from the semiconductor chip 21 mounted on the lower surface of the multilayer substrate 2 is transmitted to the parent substrate of an electronic device (not shown) on which the multilayer substrate 2 is mounted via the heat sink 5 attached to the lower surface. Heat is radiated from the substrate.
[0049]
In the high-frequency integrated circuit device 1 according to the present embodiment, the semiconductor chips 11 and 21 and the chip component 41 are mounted using both surfaces of the multilayer substrate 2, and the board area can be used effectively, and the three-dimensional downsizing is achieved. Is possible.
In addition, by using the multilayer substrate 2 in which a plurality of dielectric layers 2a to 2e are stacked, a relative distance between the dielectric layers 2a to 2e, such as a strip line having a length of λ / 4 in the bias circuit, is relatively small. A circuit having a long line length can be formed, and a matching circuit and a bias circuit can be incorporated three-dimensionally.
In addition, chip parts 41 such as inductor elements and capacitive elements are also mounted on both surfaces of the multilayer substrate 2. By mounting the components using both surfaces of the multilayer substrate 2, the board area can be used effectively and the size can be reduced. It becomes.
[0050]
Furthermore, according to the high-frequency integrated circuit device 1 according to the present embodiment, the ground layers G1 and G2 are formed between the dielectric layers 2a to 2e and are positioned between the circuit wiring layers 51, 52, and 53. Therefore, electrical interference between the circuit wiring layers 51, 52, and 53 can be prevented.
Further, since the heat radiation cover 3 is necessary not only for heat radiation but also for preventing dust from entering the high frequency integrated circuit device 1 and for electromagnetic shielding, the cover is originally necessary and the heat radiation cover 3 is attached. As a result, there is no increase in size or cost.
In the above description, the chip component 41 is mounted on both surfaces of the multilayer substrate 2, but it may be mounted on only one surface. Alternatively, only the semiconductor chips 11 and 21 may be mounted without mounting the chip component 41.
[0051]
Second embodiment
4 to 7 are sectional views showing the structure of the high-frequency integrated circuit device according to the second mounting form of the present invention. Note that the same components as those of the high-frequency integrated circuit device according to the first embodiment are denoted by the same reference numerals.
The high-frequency integrated circuit device shown in FIGS. 4 and 5 has basically the same configuration as the high-frequency integrated circuit device according to the first embodiment described above, but a semiconductor chip mounted on both surfaces of the multilayer substrate 2. 11 shows a configuration in which the present invention is applied when one of the heat generation amounts is relatively large and the other is a relatively small heat generation amount.
[0052]
  In the high-frequency integrated circuit device 61 shown in FIG. 4, the semiconductor chip 11 mounted on the surface of the first dielectric layer 2 a of the multilayer substrate 2 generates a large amount of heat, and the semiconductor mounted on the fifth dielectric layer 2 e of the multilayer substrate 2. This is a case where the heat generation of the chip 21 is small.
  The semiconductor chip 11 has a transmission signal amplifier circuit, for example, and the semiconductor chip 21 has a multifunction switch circuit, for example.
  As shown in FIG. 4, the heat dissipation cover 3 is applied to the semiconductor chip 11 that generates a large amount of heat.TheThe semiconductor chip 21 provided with a small amount of heat is not provided with the heat dissipation plate 5. The semiconductor chip 21 is mounted on the fourth dielectric layer 2 d of the multilayer substrate 2 by the flip chip method and covered with the sealing resin R. ing.
[0053]
  The high-frequency integrated circuit device 62 shown in FIG. 5 is a case where the heat generation of the semiconductor chip 11 is large and the heat generation of the semiconductor chip 21 is small, similarly to the high-frequency integrated circuit device 61 shown in FIG.
  As shown in FIG. 5, the heat radiation cover 3 is applied to the semiconductor chip 11 that generates a large amount of heat.TheThe above-described heat sink 5 is not provided in the semiconductor chip 21 provided with a small amount of heat generation.
  The semiconductor chip 21 is joined to the fourth dielectric layer 2d with the surface on which the surface electrode is formed facing away from the fourth dielectric layer 2d, and the surface electrode and the fourth dielectric layer of the semiconductor chip 21 are joined. The electrode on 2d is wired with a fine metal wire 59, and the opening 55 of the fifth dielectric layer 2e is filled with resin R to fix the semiconductor chip 21 and the fine metal wire 59.
[0054]
As described above, when the heat generation of the semiconductor chip 11 is large and the heat generation of the semiconductor chip 21 is small, as shown in FIGS. 4 and 5, the semiconductor chip that should avoid the influence of wire length variation and inductance. Semiconductor chips that require heat dissipation are mounted by a flip chip method, and semiconductor chips that do not need to be mounted can be accommodated by mounting using wire bonding.
[0055]
The high frequency integrated circuit device 63 shown in FIG. 6 is a case where the heat generation of the semiconductor chip 11 is small and the heat generation of the semiconductor chip 21 is large.
In this case, as shown in FIG. 6, the heat dissipation cover 3 is not provided for the semiconductor chip 11, and the heat dissipation plate 5 is provided for the semiconductor chip 21.
Further, the semiconductor chip 11 and the semiconductor chip 21 are mounted on the both surfaces of the multilayer substrate 2 via the bumps BP by the flip chip method.
The semiconductor chip 21 and the heat sink 5 are fixed by the resin R in the opening 55 of the fifth dielectric layer 2e.
[0056]
The high-frequency integrated circuit device 64 shown in FIG. 7 is a case where the heat generation of the semiconductor chip 11 is small and the heat generation of the semiconductor chip 21 is large, similarly to the high-frequency integrated circuit device 63 shown in FIG.
As shown in FIG. 7, in the semiconductor chip 11, the surface electrode forming side of the semiconductor chip 11 is arranged in the opposite direction to the first dielectric layer 2a, and the surface electrode and the electrode on the first dielectric layer 2a Are wired with a fine metal wire 70, and the semiconductor chip 11 and the fine metal wire 70 are fixed with a resin R.
The mounting structure of the semiconductor chip 21 is the same as that of the high-frequency integrated circuit device 63 shown in FIG.
[0057]
As described above, when the semiconductor chip 11 generates a small amount of heat and the semiconductor chip 21 generates a large amount of heat, the configuration shown in FIGS. 6 and 7 can be used.
[0058]
Third embodiment
8 to 11 are sectional views showing the structure of the high-frequency integrated circuit device according to the third mounting form of the present invention. Note that the same components as those of the high-frequency integrated circuit device according to the first embodiment are denoted by the same reference numerals.
The high-frequency integrated circuit device shown in FIGS. 8 to 11 has basically the same configuration as the high-frequency integrated circuit device according to the first embodiment described above, but a semiconductor chip mounted on both surfaces of the multilayer substrate 2. This is a case where the heat generation amount of 11 and 21 is small and it is not particularly necessary to provide a heat dissipating means.
[0059]
In the high-frequency integrated circuit device 65 shown in FIG. 8, the semiconductor chips 11 and 21 are mounted on the multilayer substrate 2 by a flip chip method and fixed with a resin R.
The high-frequency integrated circuit device 66 shown in FIG. 9 is a case where the semiconductor chip 11 generates a particularly small amount of heat, and the surface electrode forming side of the semiconductor chip 11 is disposed opposite to the first dielectric layer 2a. The electrode and the electrode on the first dielectric layer 2a are wired with a fine metal wire 72, and the semiconductor chip 11 and the fine metal wire 70 are fixed with a resin R.
[0060]
The high-frequency integrated circuit device 67 shown in FIG. 10 is a case where the semiconductor chip 21 mounted on the lower surface of the multilayer substrate 2 has a particularly small amount of heat generation. The surface electrode and the electrode on the fifth dielectric layer 2d are wired with a fine metal wire 73, and the semiconductor chip 21 and the fine metal wire 73 are fixed with a resin R.
The high-frequency integrated circuit device 68 shown in FIG. 11 is a case where both the semiconductor chips 11 and 12 mounted on both surfaces of the multilayer substrate 2 have a particularly small amount of heat generation, and the semiconductor chips 11 and 12 are shown in FIG. 9 and FIG. Implemented in a way.
[0061]
As described above, when the heat generation amount of the semiconductor chips 11 and 12 is small, the configuration shown in FIGS.
[0062]
Fourth embodiment
FIG. 12 is a cross-sectional view showing the structure of the high-frequency integrated circuit device according to the fourth mounting form of the present invention. Note that the same components as those of the high-frequency integrated circuit device according to the first embodiment are denoted by the same reference numerals.
The high frequency integrated circuit device 69 shown in FIG. 12 is a case where the frequency processed by the semiconductor chip 21 mounted on the lower surface of the multilayer substrate 2 is higher.
When the semiconductor chip 21 performs processing at a higher frequency, for example, as shown in FIG. 12, the multilayer corresponding to the mounting position of the semiconductor chip 21 mounted on the surface of the fourth dielectric layer 2 d of the multilayer substrate 2. A cavity H that is a cavity is formed in the fourth dielectric layer 2 d and the third dielectric layer 2 c of the substrate 2.
By adopting such a configuration, the space of the cavity H has a lower dielectric constant and lower inductance than that of the dielectric, and the influence on the high frequency characteristics of the semiconductor chip 21 can be suppressed.
In the present embodiment, the cavity H is formed in the semiconductor chip 21 mounted on the lower surface of the multilayer substrate 2. Similarly, the cavity H is formed in the semiconductor chip 11 mounted on the upper surface of the multilayer substrate 2. It is also possible to form the cavity H.
[0063]
In the embodiment described above, the number of semiconductor chips mounted on each surface of the multilayer substrate 2 is one in the above-described embodiment. However, the present invention is not limited to this and is mounted on both surfaces of the multilayer substrate 2. There may be a plurality of semiconductor chips.
[0064]
【The invention's effect】
According to the present invention, since the semiconductor chip and the chip component are mounted using both sides of the multilayer substrate, the substrate area can be used effectively, and the high-frequency integrated circuit device can be downsized and highly integrated.
In addition, according to the present invention, for the mounting of a semiconductor chip that should avoid the influence of wire length variation and inductance or a semiconductor chip that requires heat dissipation, when flip mounting is used and it is not necessary to consider them, Since the wiring method is adopted, the degree of freedom of the mounting method can be expanded.
In addition, according to the present invention, by using a multilayer substrate as a substrate for mounting semiconductor chips and chip components, high-density mounting can be achieved, and electrical interference between circuit wiring layers including a ground layer is present in the multilayer substrate. It is possible to prevent heat resistance.
Further, according to the present invention, a bias circuit can be realized between the dielectric layers of the multilayer substrate by using the multilayer substrate as a substrate for mounting the semiconductor chip and the chip component, and the size can be reduced by effectively utilizing the interlayer. High mounting is possible.
Further, according to the present invention, even when a semiconductor chip that requires heat dissipation is mounted, it can be easily handled.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of a high-frequency integrated circuit device according to a first embodiment of the present invention.
2 is a diagram showing a configuration of a multilayer substrate of the high-frequency integrated circuit device of FIG. 1;
3 is a diagram showing a configuration of a multilayer substrate of the high-frequency integrated circuit device of FIG. 1;
FIG. 4 is a cross-sectional view showing an example of the structure of a high-frequency integrated circuit device according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view showing another example of the structure of the high-frequency integrated circuit device according to the second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing still another example of the structure of the high-frequency integrated circuit device according to the second embodiment of the present invention.
FIG. 7 is a cross-sectional view showing still another example of the structure of the high-frequency integrated circuit device according to the second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing an example of the structure of a high-frequency integrated circuit device according to a third embodiment of the present invention.
FIG. 9 is a cross-sectional view showing another example of the structure of the high-frequency integrated circuit device according to the third embodiment of the present invention.
FIG. 10 is a cross-sectional view showing still another example of the structure of the high-frequency integrated circuit device according to the third embodiment of the present invention.
FIG. 11 is a cross-sectional view showing still another example of the structure of the high-frequency integrated circuit device according to the third embodiment of the present invention.
FIG. 12 is a cross-sectional view showing the structure of a high-frequency integrated circuit device according to a fourth embodiment of the present invention.
FIG. 13 is a cross-sectional view showing an example of the structure of a conventional high-frequency integrated circuit device.
FIG. 14 is a cross-sectional view showing another example of the structure of a conventional high-frequency integrated circuit device.
FIG. 15 is a cross-sectional view showing still another example of the structure of a conventional high-frequency integrated circuit device.
FIG. 16 is a cross-sectional view showing still another example of the structure of a conventional high-frequency integrated circuit device.
FIG. 17 is a cross-sectional view showing still another example of the structure of a conventional high-frequency integrated circuit device.
FIG. 18 is a cross-sectional view showing still another example of the structure of a conventional high-frequency integrated circuit device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... High frequency integrated circuit device, 2 ... Multilayer substrate, 2a-2e ... 1st-5th dielectric layer, 3 ... Radiation cover, 5 ... Radiation plate, 11, 21 ... Semiconductor chip, 41 ... Chip components, 51, 52 53, circuit wiring layers, G1, G2, ground layers.

Claims (12)

複数の誘電体層が積層された多層基板と、
前記多層基板の電子機器への非装着面側である一方面の表層に、フリップチップボンディングによる電気的な接続により実装された、能動素子を有する第１半導体チップと、
前記多層基板の電子機器への装着面側である他方面の表層に、フリップチップボンディングによる電気的な接続により実装された、能動素子を有する第２半導体チップと、
前記多層基板の層間および表面に形成された回路配線層と、
前記多層基板の表面の前記一方面もしくは両面に実装された受動素子からなるチップ部品と、
前記多層基板の周囲を囲む被覆部と、前記第１半導体チップ及び前記チップ部品が実装された前記一方面において、前記第１半導体チップの表面に直接接触する接触部とを具備する第１放熱板とを有し、
前記第２半導体チップは、前記他方面の表層に、隣接する内層に通じるように形成された開口部内に収容され、かつ前記隣接する内層上に実装されており、
前記開口部が形成された表層の厚さは、前記半導体チップまたはチップ部品の高さに応じて調整されおり、
前記第２半導体チップの表面に直接接触し、かつ、前記開口部内に収容されている第２放熱板をさらに有する
高周波集積回路装置。A multilayer substrate in which a plurality of dielectric layers are laminated;
A first semiconductor chip having an active element mounted on a surface layer on one side which is a non-mounting surface side of the multilayer substrate to an electronic device by electrical connection by flip chip bonding;
A second semiconductor chip having an active element mounted on the surface layer of the other surface, which is the mounting surface side of the multilayer substrate, to the electronic device by electrical connection by flip chip bonding ;
A circuit wiring layer formed between the layers and the surface of the multilayer substrate;
A chip component composed of passive elements mounted on the one or both surfaces of the surface of the multilayer substrate;
A first heat radiating plate comprising: a covering portion surrounding the multilayer substrate; and a contact portion that directly contacts the surface of the first semiconductor chip on the one surface on which the first semiconductor chip and the chip component are mounted. And
The second semiconductor chip is accommodated in an opening formed in the surface layer on the other surface so as to communicate with an adjacent inner layer, and is mounted on the adjacent inner layer,
The thickness of the surface layer in which the opening is formed is adjusted according to the height of the semiconductor chip or chip component,
The high-frequency integrated circuit device further comprising a second heat radiating plate in direct contact with the surface of the second semiconductor chip and housed in the opening. 前記開口部が形成された表層の表面には、電子機器への装着のための電極が形成されている
請求項１に記載の高周波集積回路装置。The high frequency integrated circuit device according to claim 1, wherein an electrode for mounting to an electronic device is formed on a surface of the surface layer where the opening is formed. 前記多層基板の層間に接地層が形成されている
請求項１または２のいずれかに記載の高周波集積回路装置。The high-frequency integrated circuit device according to claim 1, wherein a ground layer is formed between layers of the multilayer substrate. 前記回路配線層は、インピーダンス整合回路およびバイアス回路の少なくとも一部を構成する
請求項１〜３のいずれかに記載の高周波集積回路装置。The high-frequency integrated circuit device according to claim 1, wherein the circuit wiring layer constitutes at least a part of an impedance matching circuit and a bias circuit. 前記チップ部品は、前記回路配線層とともに、前記インピーダンス整合回路およびバイアス回路を構成する
請求項４に記載の高周波集積回路装置。The high-frequency integrated circuit device according to claim 4, wherein the chip component constitutes the impedance matching circuit and the bias circuit together with the circuit wiring layer. 前記バイアス回路が前記多層基板の層間に形成されている
請求項４に記載の高周波集積回路装置。The high-frequency integrated circuit device according to claim 4, wherein the bias circuit is formed between layers of the multilayer substrate. 前記第１放熱板は、電磁シールドとして機能する
請求項１〜６のいずれかに記載の高周波集積回路装置。The high-frequency integrated circuit device according to claim 1, wherein the first heat radiation plate functions as an electromagnetic shield. 前記多層基板の他方面に実装された前記第２半導体チップは、フリップチップボンディングによって前記多層基板に電気的に接合されている
請求項１〜７のいずれかに記載の高周波集積回路装置。The high-frequency integrated circuit device according to claim 1, wherein the second semiconductor chip mounted on the other surface of the multilayer substrate is electrically bonded to the multilayer substrate by flip chip bonding. 前記多層基板内には、前記第２半導体チップの実装位置に空洞が形成されている
請求項１〜８のいずれかに記載の高周波集積回路装置。Wherein the multilayer substrate, the high-frequency integrated circuit device according to any one of claims 1 to 8, cavity mounting position of the second semiconductor chip are formed. 積層された第１〜第４の誘電体層と、前記第４の誘電体層に積層され当該第４の誘電体層の表面に通ずる開口部が形成された第５の誘電体層と、
前記第１および第２の誘電体層間と前記第３および第４の誘電体層間とに形成された導電材料からなる接地層と、
前記第２および第３の誘電体層間に形成された導電性材料からなる回路配線層と、
前記第１および第４の誘電体層の表面に形成された導電性材料からなる回路配線層と
を有する多層基板と、
前記第１誘電体層の表面に、フリップチップボンディングによる電気的な接続により実装された、能動素子を有する第１半導体チップと、
前記第４の誘電体層の表面に、フリップチップボンディングによる電気的な接続により実装された、能動素子を有する第２半導体チップと、
前記第１の誘電体層に、または、前記第１および第４の誘電体層双方に実装された、受動素子が形成されたチップ部品と、
前記多層基板の側面および前記第１半導体チップ及び前記チップ部品が実装された、前記第１の誘電体層側を覆い、かつ第１の誘電体層表面に実装された前記第１半導体チップの表面に直接接触する第１放熱板とを有し、
前記第２半導体チップは、前記他方面の表層に、隣接する内層に通じるように形成された開口部内に収容され、かつ前記隣接する内層上に実装されており、
前記開口部が形成された表層の厚さは、前記半導体チップまたはチップ部品の高さに応じて調整されおり、
前記第２半導体チップの表面に直接接触し、かつ、前記開口部内に収容されている第２放熱板をさらに有する
高周波集積回路装置。A first dielectric layer to a fourth dielectric layer laminated, and a fifth dielectric layer laminated on the fourth dielectric layer and having an opening leading to the surface of the fourth dielectric layer;
A ground layer made of a conductive material formed between the first and second dielectric layers and the third and fourth dielectric layers;
A circuit wiring layer made of a conductive material formed between the second and third dielectric layers;
A multilayer substrate having a circuit wiring layer made of a conductive material formed on the surfaces of the first and fourth dielectric layers;
A first semiconductor chip having active elements mounted on the surface of the first dielectric layer by electrical connection by flip chip bonding;
A second semiconductor chip having active elements mounted on the surface of the fourth dielectric layer by electrical connection by flip chip bonding ;
A chip component on which the passive element is formed, which is mounted on the first dielectric layer or on both the first and fourth dielectric layers;
The side surface of the multilayer substrate and the surface of the first semiconductor chip that covers the first dielectric layer side on which the first semiconductor chip and the chip component are mounted and is mounted on the surface of the first dielectric layer A first heat radiating plate in direct contact with
The second semiconductor chip is accommodated in an opening formed in the surface layer on the other surface so as to communicate with an adjacent inner layer, and is mounted on the adjacent inner layer,
The thickness of the surface layer in which the opening is formed is adjusted according to the height of the semiconductor chip or chip component,
The high-frequency integrated circuit device further comprising a second heat radiating plate in direct contact with the surface of the second semiconductor chip and housed in the opening. 前記第２および第３の誘電体層間に形成された回路配線層は、バイアス回路を構成しており、
前記第１および第４の誘電体層の表面に形成された導電性材料からなる回路配線層と前記第１の誘電体層に、または、前記第１および第４の誘電体層双方に実装された受動素子とは、インピーダンス整合回路を構成している
請求項１０に記載の高周波集積回路装置。The circuit wiring layer formed between the second and third dielectric layers constitutes a bias circuit,
Mounted on the circuit wiring layer and the first dielectric layer made of a conductive material formed on the surfaces of the first and fourth dielectric layers, or on both the first and fourth dielectric layers. The high-frequency integrated circuit device according to claim 10 , wherein the passive element constitutes an impedance matching circuit. 前記第５の誘電体層の表面には、電子機器への装着のための電極が形成されている
請求項１０または１１に記載の高周波集積回路装置。Wherein the fifth surface of the dielectric layer, a high-frequency integrated circuit device according to claim 10 or 11 electrodes for attachment to the electronic device is formed.
JP10546199A 1999-04-13 1999-04-13 High frequency integrated circuit device Expired - Fee Related JP4284744B2 (en)

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