TWI354522B - - Google Patents

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Publication number
TWI354522B
TWI354522B TW095147038A TW95147038A TWI354522B TW I354522 B TWI354522 B TW I354522B TW 095147038 A TW095147038 A TW 095147038A TW 95147038 A TW95147038 A TW 95147038A TW I354522 B TWI354522 B TW I354522B
Authority
TW
Taiwan
Prior art keywords
layer
wiring board
resin
printed wiring
metal layer
Prior art date
Application number
TW095147038A
Other languages
Chinese (zh)
Other versions
TW200733842A (en
Inventor
Sotaro Ito
Michimasa Takahashi
Yukinobu Mikado
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of TW200733842A publication Critical patent/TW200733842A/en
Application granted granted Critical
Publication of TWI354522B publication Critical patent/TWI354522B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Description

1354522 九、發明說明： 【發明所屬之技術領域】 * ·本發明係關於内藏有IC等電子零件（半導體元件）之多 、層印刷佈線板，更詳細而言，係關於確保半導體元件之概 f與多層印刷佈線板之導體電路的電性連接性及連接可 •靠性之多層印刷佈線板及其製造方法。 【先前技術】 籲作為内藏半導體元件之多層印刷佈線板而言，具有例如 日本專利特開2001 — 339165號公報或者日本專利2〇〇2_ 050874號公報中所揭示者。於該等文獻中揭示之多層印 刷佈線板由下述部分而構成，即，形成有半導體元件埋入 用凹部之基板，·於該基板之凹部内埋入之半導體元件；形 ^於基板上以覆蓋該半導體元件之絕緣層；形成於絕緣層 體電路;以及設置於絕緣層上以使上述導體電路 與+導體7G件之襯墊電性連接之通孔。 譬於上述習知之多層印刷佈線板中，於其最外層表面設置 有外部連接端子（例如PGA、BGA等），内藏於基板上之半 導體兀件經由過該料部連接端子而與外部電性連接。 對於如上所述之習知技術，於埋人有半導體元件 t板中，亦存在電氣特性不穩定之現象。尤其於埋入之 ί導體70件附近载設之㈣電財，存在f氣特性不穩 疋之現象’其結果會產生信號延遲等不良情況。即，本於 樹脂基板上設置用以内藏半導體元件之凹部時，半導二元 件自身或者内藏有半導體元件之周邊導體電路中受到電 312XP/發明說明書(補件)/96-03/95147038 c 信號佈線中之信號傳輸變得不穩定，由此 引起以延遲或誤作動等，未能夠確保基板之功能。 2此：不良情況之一例亦具有如下所述於截斷(。f。 •儿士 於來自外部之雜訊而將其誤認為接通（on)信 唬，由此而受到引起誤作動等之影響。又，亦具有下述情 況.導體元件中，由於雜訊之影響，於截斷信號時’ 將，、誤》心為接通仏破，由此而受到引起誤作動等之影塑。 因此’本發明之目的在於解決習知技術所具有之上述曰問 題點’提出確保内藏有半導體元件之基板的電性連接性及 連接可靠性之多層印刷佈線板及其製造方法。 【發明内容】 本發明者等為了實現上述目的而反覆進行銳意研究，最 終完成以如下内容為主旨結構之本發明。 即’本發明係提供-種多層印刷佈線板，其係於收納有 半導體it件之樹脂絕緣層上，形成其他樹脂絕緣層及導體 電路，經由通孔而電性連接所形成之多層印刷佈線板， 上述半導體元件内藏於上述樹脂絕緣層上所設之凹部 内，於包圍該凹部之樹脂絕緣層上形成有電磁屏蔽層。 上述電磁屏蔽層較佳為，包圍半導體元件，由側面金屬 層及下部金屬層所形成。 又，上述屏蔽層亦可由側面金屬層或下部金屬層之任一 方而形成。 於本發明中較佳為，於上述凹部之底面形成下部金屬 層，半導體元件載置於下部金屬層上。 312XP/發明說明書(補件)/96-03/95147038 6 U54522 於本發明中’上述電磁屏蔽層亦可為位於凹部外側之樹 脂絕緣層上所形成之側面金屬層。 又’上述電磁屏蔽層可設為下述結構：其由位於凹部外 • 之树脂絕緣層上所形成之複數個柱狀（圓柱、橢圓柱、 多角柱等）侧面金屬層所形成，各侧面金屬層相互連結。 又，上述電磁屏蔽層可由位於凹部之底面或者凹部底面 之下方之樹脂絕緣層上所形成之下部金屬層而形成。 .又，上述電磁屏蔽層可由形成於位於凹部外側之樹脂絕 緣層且相互連結之複數個柱狀侧面金屬層、及形成於位於 立凹部之底面或者位於凹部底面之下方之樹脂絕緣層之下 P金屬層而構成，而上述柱狀側面金屬層與上述下部金 層形成連結之結構。 又’上述下部金屬層可以τ述方式而構成：與上述多個 柱狀侧面金屬層連接，作為電磁屏蔽層發揮作用。 •個二部金屬層可以下述方式而構成··與上述複數 =二二壁由金屬覆蓋而形成之側面金屬層、或者於 屏充金屬而形成之側面金屬層連結，作為電磁 屏蔽層發揮作用。 又，上述電磁屏蔽層可由 而形成。 形成於上述凹部内 壁之金屬層 於本發明中，上述凹部 自底面朝向上方而逐漸成為具推拔形，其侧面隨著 半於本發明中，可於收納、固定於上述凹部之 +導體70件之㈣㈣介層，經由該柱^ ^2XP/mmmmm/96.03/95147038 7 1354522 電極或中介層而將上述襯墊與通孔電性連接。 又’本案發明係一種多層印刷佈線板， • ·其係於收納有半導體元件之樹脂絕緣層上，形成其他樹 !.脂絕緣層及導體電路，經由通孔而電性連接所形成之多層 印刷佈線板， . 上述半導體元件内藏於樹脂絕緣層上所設之凹部内，於 +包圍該凹部之樹脂絕緣層上形成有電磁屏蔽層，該電磁屏 籲蔽層由具有下述形態之側面金屬層而形成··複數個非貫通 孔之内壁表面由金屬覆蓋而成之形態、或複數個非貫通孔 内由金屬填充而成之形態、或者由金屬所構成之複數個柱 狀體之形態。 上述側面金屬層較佳為於複數個非貫通孔内填充有導 電性金屬者。導電性金屬可使用電鍍、漿料等。 上述柱狀體較佳為選自圓柱、橢圓柱及多角柱之至少一 種形狀。 • 上述電磁屏蔽層較佳為包含下部金屬層，該下部金屬層 係於位於上述凹部之底面或者位於上二 之樹脂絕緣層上所形成。 之下方 上述側面金屬層較佳為具有下述形態：複數個非貫通孔 之内壁表面由金屬覆蓋而成之形態、或複數個非貫通孔内 由金屬填充而成之形態、或者由金屬所構成之複數個柱狀 體之形態，而該等之至少一部分係相互連結。 ，上述電磁屏蔽層較佳為由上述侧面金屬層與上述下部 r 金屬層連結而形成。 312XP/發明說明書(補件)/96-03/95147038 8 1354522 上述凹部較佳為形成為推拔形，其侧面隨著自底面朝向 上方而逐漸擴展。 •又，本案發明係一種多層印刷佈線板， 1 ·其係於收納有半導體元件之樹脂絕緣層上，形成其他樹 脂絕緣層及導體電路，經由通孔而電性連接所形成之多層 印刷佈線板， s 上述半導體元件内藏於樹脂絕緣層上所設之凹部内；與 鲁半導體元件連接之通孔形成為填充導電性材料後所成之 填孔（via filling)形態；於包圍上述凹部之樹脂絕緣層 形成有電磁屏蔽層。 又’本案發明係一種多層印刷佈線板， 其係於收納有半導體元件之樹脂絕緣層上，形成其他樹 脂絕緣層及導體電路，經由通孔而電性連接所形成之多層 印刷佈線板， 上述半導體元件内藏於樹脂絕緣層上所設之凹部内；上 籲述其他樹脂絕緣層含有纖維基材，且於該樹脂絕緣層上形 成有與半導體元件連接之通孔；於包圍上述凹部之樹脂絕 緣層上形成有電磁屏蔽層。 上述電磁屏蔽層較佳為，由侧面金屬層與下部金屬層所 構成。 上述電磁屏蔽層較佳為，由側面金屬層所構成，而該側 面金屬層係複數個非貫通孔之内壁由金屬覆蓋之形態、或 •f 複數個非貫通孔内填充有金屬之形態、或者複數個柱狀體 -Γ 之形態。 312XP/發明說明書(補件)/96-03/95147038 9 1354522 上述側面金屬層較佳為非貫通孔之内壁由導電性金屬 覆盖之形態，或者於非貫通孔内填充有導電性金屬之 •.態。 / ? ·上述側面金屬層較佳為形成下述形態：複數個非貫通孔 之内壁由金屬覆蓋而成之形態、或複數個非貫通孔内填充 .有金屬而成之形態、或者複數個金屬柱狀體之形態，至少 一部分係相互連結。 上述柱狀體較佳為選自圓柱、橢圓柱、多角柱之至少一 種形狀。 上述電磁屏蔽層較佳為包含下部金屬層，其係於位於上 述凹。卩之底面或者位於上述凹部底面之下方之樹脂絕緣 層上而形成。 上述電磁屏蔽層較佳為由上述側面金屬層與上述下部 金屬層連結而形成。 又’本案發明係一種多層印刷佈線板， ^ 其係於收納有半導體元件之樹脂絕緣層上，形成其他樹 月曰絕緣層及導體電路，經由通孔而電性連接所形成之多層 印刷佈線板， 上述半導體元件内藏於樹脂絕緣層上所設之凹部内，於 包圍該凹部之樹脂絕緣層上形成有電磁屏蔽層，該電磁屏 蔽層由配置於半導體元件之下部之下部金屬層所構成，該 下部金屬層之面積大於上述凹部底面之面積。 上述下部金屬層較佳為由輥軋銅箔所形成。 上述電磁屏蔽層較佳為由侧面金屬層與下部金屬層所 312XP/發明說明書(補件)/96-03/95147038 10 構成。 上述電磁屏蔽層較佳為 .屬層形成為下述形能屬層所構成，該側面金 •内壁由金屬覆蓋而成 數個非貝通孔之 金屬而成之形雄、態、或複數個非貫通孔内填充有 μ m 〜、或者複數個金屬柱狀體之形態。 之内壁由金屬覆宴而^/、有下杨態·硬數個非貫通孔 充有導電性厶凰疏成之形態，或者複數個非貫通孔内填 兄有V電性金屬而成之形態。 具 上述導電性金屬可使用電鍍、_等。 之mi::較佳為形成下述形態:複數個非貫通孔 屬填充而成=二成;=或複數個非貫通孔内由金 〜次者複數個金屬柱狀體之形態，至少 一部分係相互連結。 〃 =柱狀體較佳為選自圓柱、橢圓柱、多角柱之至少一 種形狀。 鲁上述電磁屏蔽層較佳為 金屬層連結而形成。 由上述侧面金屬層與上述下部 又’本發明提供一種多層印刷佈線板之製造方法，盆於 製造多層印刷佈線板（其係於收納有半導體元件所叙樹 脂絕緣層上，形成有其他樹脂絕緣層及導體電路，並且經 由通孔而電性連接所形成者)時，至少包括下述步驟：、 於樹脂絕緣層之-面至少形成導體電路與金屬層，並且 於另-面至少職導體電路及與上述金屬㈣向之位置 之導體電路非形成區域，更進一步利用電鍍而形成下述通 312XP/發明說明書(補件)/96·03/95147038 1354522 =，即，將上述另一面之導體電路與上述一面之導體電路 电性連接之通孔、以及於上述另一面之導體電路非形成區 :·域之外側貫穿樹脂絕緣層而到達上述一面之金屬層之通 孔，藉此形成第一絕緣性樹脂基材之步驟； 將於樹脂絕緣層之一面貼附有銅箔而形成之第二絕緣 .性樹脂基材之樹脂面，壓合於上述第一絕緣性樹脂基材上 而一體化之步驟； φ 於上述第二絕緣性樹脂基材上形成導體電路，並且形成 與該導體電路電性連接之通孔之步驟； 於上述第一絕緣性樹脂基材之導體電路非形成區域，自 樹脂絕緣層表面形成凹部之步驟； 將半導體元件收納於上述凹部内，利用黏著劑將其黏著 之步驟；以及 覆蓋上述半導體元件而形成其他樹脂絕緣層，形成通孔 之步驟。 • 更進一步，本發明提供一種多層印刷佈線板之製造方 法，其於製造多層印刷佈線板（其係於收納有半導體元件 所成之樹脂絕緣層上，形成有其他樹脂絕緣層及導體電 路，經由通孔而電性連接所形成者）時，至少包括下述步 驟： 於樹脂絕緣層之一面至少形成導體電路與金屬層，並且 於另一面至少形成導體電路及與上述金屬層對向之位置 之導體電路非形成區域，利用電鍍形成與導體電路電性連 接之通孔，藉此形成第一絕緣性樹脂基材之步驟； 312XP/發明說明書(補件)/96-03/95147038 10 1354522 將於樹脂絕緣層之-面貼附有㈣而 性樹脂基材之樹脂面，壓合於上 一、、緣 而-體化之步驟； 第、絕緣性樹脂基材上 於上述第二絕緣性樹脂基材之一面形成導體 利用電鍍而形成通孔之步冑，其係 於上述第—絕緣性樹脂基材上之通孔電電路與形成 成Si:驟絕緣性樹脂基材之導體電路非形成區域形 利用電鍍形成覆蓋上述凹部之金屬層之步驟； 將半導體元件收納於上述凹部内 於上述凹部之金屬層上之步锁抑黏者劑將其固定 =上述半導體元件而形成其他樹腊絕緣層 而形成電性連接之通孔之步驟。 電鍍 根據本發明，將半導體元件收納於樹脂基板之樹脂 層上所設的凹部，於贫凹邱用囹 、’ *蔽内藏於凹部：磁屏蔽層’藉此可 動等不良情況之2 件&可减少信號延遲或誤作 又，根據本發明’於凹部之底面形成金屬層，由此易使 =之深度均勾化。尤其當凹部剖面為矩形時， 度亦易於均勾化。因此，當將半導體元件收 納於凹部時，半導體元件之傾斜現象減少 脂絕緣層上形成有與所收納之半導體元件之襯^接^ 通：時，可形成所需之通孔形狀。更進一步，由於 形成於樹脂絕緣層内，故因熱應力或外部應力等影響而產 312XP/發明說明書(補件)/96—03/95147〇38 ]3 1354522 生翹曲之現象減少，其結果，不易產生例如半導體元件之 連接襯墊與通孔等導體電路之連接不良情況，從而電性連 、接性及連接可靠性不易降低。 ? 【實施方式】 曾本發明之多層印刷佈線板之—實施形態係於收納有半 .導體疋件之樹脂絕緣層1，形成其他樹脂絕緣層及導體f 路,&由通孔而電性連接所形成之多層印刷饰線板中，其 籲特徵在於.將上述半導體元件收納於樹脂絕緣層上所設之 凹部内’於該凹部之周圍形成有電磁屏蔽層。 於本發明之實施形態中，所謂收納半導體元件之「凹部 之周圍」係私位於凹部侧面之外側之樹脂絕緣層、與凹 卩底面相連或者位於凹部底面之正下方之樹脂絕緣層、位 於凹部之開口周緣之樹脂絕緣層或者凹部之内壁（底面+ 側面）。 _ 又所明「電磁屏蔽層」，係指與基板内傳輸電信號之 •導體電路(包含通孔)無電性連接之電性孤立之金屬層，抑 制半導體元件由於其他半導體元件啟動而引起之誤作動 T ’具有保護半導體元件之屏蔽效果。又，視情況，只要 ，夠確保收納於凹部内之半導體元件之屏蔽性，則電磁屏 敝層亦可具有電性連接性。本申請案中之屏蔽層較佳為， 於半導體元件之周圍，由侧面金屬層或下部金屬層而構 成’或者由側面金屬層與下部金屬層而構成。 於本發明之實施形態中，電磁屏蔽層之一種形態係位於 内藏有半導體元件之凹部之外侧的樹脂絕緣層内之侧面 312XP/發明說明書(補件)/96獅5147〇38 14 1354522 金屬層。 作為上述側面金屬層，可藉由於複數個非貫通孔之内壁 、表面覆蓋金屬而形成，或者於複數個非貫通孔内填充金屬 ?.而形成。 又，可形成由金屬構成之複數個柱狀體作為上述側面金 .屬層，該複數個柱狀體係於位於凹部外側之樹脂絕緣層上 所形成。 φ 作為上述非貫通孔形成方法之一例，可於位於凹部外側 之 '，邑緣層上，利用雷射、光蝕刻等設置開口，以電鍍層等 金屬覆蓋該開口内部，或者利用電鍍、漿料等導電性材料 填充該開口内。上述金屬可使用一種或者複數種金屬。 作為上述柱狀體形成方法之一例，可將金屬等事先形成 為所需形狀（圓柱、多邊形柱體）後之金屬體打入位於凹部 外側之絕緣層中，或者使該金屬體預先排列後，形成位於 凹部外側之絕緣層等。 • 上述電磁屏蔽層可為形成為下述形態之各側面金屬層 之部分相互連結之結構，即，複數個非貫通孔由金屬覆 蓋之形態、或複數個非貫通孔内填充有金屬之形態、或者 柱狀體之形態，該結構可連結，亦可部分不連結。 又，形成為下述形態之各侧面金屬層亦可各自分離而存 在，即，複數個非貫通孔由金屬覆蓋之形態、或複數個非 貝通孔内填充有金屬之形態、或者柱狀體之形態。又，視 需要，亦可將上述各形態之側面金屬層混合而成者作為電 磁屏蔽層而構成。 15 3 ΠΧΡ/發明說明書(補件)/9孚〇3/95147038 上，/面金屬層形成於半導體元件之凹部外侧之絕緣層 藉此可獲得屏蔽效果。上述各側面金屬層可具有電性 逮接，亦可不具有電性連接。 離、甲〜形成為複數個非貫通孔之内壁由金屬覆蓋之形 ^能’複數個非貫通孔内填充有金屬之形態、或者柱狀體 雷I之侧面金屬層’可為未與基板内構成電子電路之導體 雷^生連接者，或者未與電性連接該等導體電路之通孔 2連接者，亦可為與其等電性連接者。 為方便說明’將·L述形態之側面金屬層稱為「屏 藏t'shleld〜via)」。利用該屏蔽通道，可形成包圍内 電磁干涉之影響，件側面之電磁屏蔽區域’故可抑制 上述屏蔽通道例如自基板 VL ^ 口邊緣部平行之方6 3 ^方觀察時’>σ者與凹部之開 緣部平行之方向μσ線排列。或者在與凹部之開口邊 •而形成電磁屏蔽層。 α(千鳥排列)，以此 又，上述屏蔽通道較佳為柱狀。此時，「柱 柱形狀（亦包括橫剖面為#圓形之 」形狀曰= 包括橫剖面為三角形、正方形亦 二角形等之形狀)’以及其他具有不規則橫剖面之、:：、 a狀。當橫剖面為圓形（包含糖圓），且於基板之;^之 向上形成為細長筒狀之形態時特佳。其理由為=方 形且呈細長筒狀之導體層可形成甚 ：面為圓 區域亦能夠屏蔽之區域，故不僅可確保半導體二^ 3】2XP/發明說明書(補件)/96·〇3/95ΐ 47038 16 1354522 :二亦可確保其於寬度方向之㈣電磁屏蔽區域。即， 易取基板之厚度方向’亦可於其寬度方向上容 二效果。又’即使對屏蔽通道施加熱等應力，由 之點容易消失，故於該通道附近亦不易產生龜 农寻不良情況。 =，上述屏蔽通道於非貫通孔由金屬覆蓋之形態、或者 非二通孔内填充有金屬之形態下，亦可取得與柱狀 相同之效果。 更進一步，上述複數個屏蔽通道以相互連結之形態且包 圍内藏有半導體元件之凹部之側面而配置，藉此可進一步 提高於基板寬度方向上之屏蔽效果。 上述屏蔽通道之連結亦可如圖Ua)所示，以沿著與凹 部之開口周緣平行之方向呈直線排狀狀態而連結。又， 亦可如圖1(b)所示’以在與凹部開口周緣平行之方向上 錯開排列之狀態(千鳥排列)而連結。 、Ρ為了利用沿著凹部之開口周緣所配置之複數個屏蔽 通道來形成電磁屏蔽層’亦可將屏蔽通道連續地接合，以 形成如塊金屬才反之形態。或者，亦可使屏蔽通道一邊交 互錯位if排列(千鳥排列），以形成如一片金屬板之形 態。當為該等任一形態時’均可以環繞半導體元件周圍之 弋而开y成無電性連接之金屬層，藉此形成電磁屏蔽層， 可取得内藏於凹部之半導體元件的側面方向之電磁 蔽效果。 ％ 上 ν 蔽通道之連接，可為使所有屏蔽通道連結之連續 312ΧΡ/發明說明書(補件)/96_〇3/95147〇38 17 ⑸4522 性連結構造’亦可為部分性連結之部分連結構造。其理由 ,2，無論為何種形態，與埋入有半導體元件之凹部周圍未 .設置電磁屏蔽層之安裝基板相比，均可取得半導體元件之 :.側面方向之電磁屏蔽效果。 於本發明之實施形態中’電磁屏蔽層之其他形態較佳 -為，於位於内藏有半導體元件之凹部底面之樹脂絕緣層内 ，成的下部金屬層、或者於位於凹部底面之正下方之樹脂 魯絕緣層内形成的下部金屬層之形態❶該等金屬層為片狀^ 佳。 上述片狀電磁屏蔽層較佳為，與内藏半導體元件之凹部 底面具有相同尺寸，或者形成為比底面面積稍大之尺寸或 面積。藉此可取得半導體元件之底面方向之電磁屏蔽效 果。 5亥片狀屏蔽層較佳為，與形成於凹部側面之外側之電磁 屏蔽層、即屏蔽通道連接（參照圖1(a)—圖1(b))。 i藉此，可取得半導體元件之側面方向及底面方向的電磁 屏蔽效果。其結果，可更有效地抑制電磁干涉之影響，且 可抑制誤作動等不良情況之產生。 、再者，除於如上所述之非貫通孔内填充導電性材料而形 成之屏蔽通道形態之電磁屏蔽層、或片狀電磁屏蔽層以 外，亦可形成為在設置於基板之貫通孔内填充有導電性材 料而成之形態、或者***金屬板而成之形態等。 又，於本發明之實施形態中，電磁屏蔽層之再其他形態 可如圖1(c)所示，於内藏有半導體元件之凹部之至少= 312XP/發明說明書(補件)/96〇3/95147〇38 18 1354522 壁所形成的金屬層之形態。即，覆蓋凹部底面及侧面之金 屬層或者除覆蓋凹部底面及側面之金屬層之外並形成自 .凹部側面之上端沿著開口周緣而延設之金屬層形態之電 磁屏蔽層，係環繞内藏於凹部内之半導體元件之封裝樹脂 層的整個外側表面（除設置有連接襯墊之上表面之外），故 可同時取得半導體元件之侧面方向及底面方向之電磁屏 蔽效果。 φ 作為形成上述電磁屏蔽層時所使用之金屬而言，較佳為 使用鎳、銅、鉻之任i種金屬’或者將2種以上混合而成 之金屬。 該等金屬之一例可列舉銅、銅_鉻合金、銅_鎳合金、鎳、 鎳—鉻合金、鉻等，亦可使用該等以外之金屬。 上述金屬層之厚度較佳為5 #m〜2〇 其理由為， 當厚度未滿5 //Hi時，會使屏蔽層之效果抵消。另一方面， 當厚度超過20 時，無法使屏蔽層之效果提高。 瞻該等金屬層之形成方法較佳為無電解電鍍、電解電鍍、 濺鍍、蒸鍍等。其理由為，可易於形成膜厚均勻之金屬膜， 故更易於取得電磁波屏蔽效果。 利用該等方法所形成之屏蔽層亦可形成為單層或2層 以上之複數層。當形成為複數層時，可使用相同方法而形 成，亦可使用不同方法而形成。可根據形成為屏蔽層之金 屬層之種類、厚度等而適宜形成。因此，該屏蔽層並非係 使電磁波屏蔽效果急遽降低者。 於本發明之實施形態中較佳為，於内藏有半導體元件之 312XP/發明說明書(補件)/96-〇3/95147038 19 1354522 凹部之底面形成金屬層，半導體元件介隔該金屬層而内 藏。其理由為，可使凹部之深度均勻，由此而消除半導體 元件於傾斜狀態下收納、内藏於凹部内之情況。因此，即 使收納半導體元件之基板為樹脂製，當於樹脂絕緣層上形 成與半導體元件之連接襯墊連接之通孔時，亦可製成所需 之通孔形狀，並且金屬層形成於樹脂絕緣層内，故因熱應 力或外部應力等之影響而產生翹曲之現象減少。因此，易 於確保半導體元件之連接襯墊與導體電路之電性連接性 及連接可靠性，該導體電路包含與半導體元件之連接襯墊 連接之通孔。 又，下部金屬層亦可為具有平坦表面者。藉此，可易於 確保凹部形狀之保持性及與黏著劑之黏著性。視需要，亦 可於下部金屬層上形成粗化面。利用該等粗化面可使下部 金屬層與黏著劑密接，故易於確保黏著性。 又二下部金屬層較佳為由銅所形成。因蝕刻等之加工性 良好等。其中尤佳為使用輥軋銅箔而形成。其理由為，易 於確保下部金屬層之平坦性，且胃於_保與載置於下部金 屬層上之半導體元件t收納性及與半導體元件 平坦性。 4 α < t進一步作詳細說明，形成有收納半導體元件之凹部之樹 = 睛料所形成，該樹脂材料係於破璃環氧 树月曰丰中含有玻璃布等屬纖維基材之補強材。因此，每利 用魚眼（spot facing)加工等形成凹部時，於該: 面依位置而形成不規則之凹凸。 一 312XP/發明說明書(補件)/96〇3/95147〇38 20 1354522 其結果，凹部之深度易不均勻。尤盆 尤其於剖面形成為大致 矩形之凹部之四角附近，相比與其他部分，其凹部之产产 .易變淺。因此，如本發明於凹部底面形成金屬層，由 •凹部之深度易於均句化。尤其當凹部之剖面為二形時，於 四角附近之凹部之深度亦易於均勻化。 、 .因此’當將半導體元件收納於凹部時，半導體元件之傾 斜現象減少。故而，即使於樹脂絕緣層上形成與所收納之 鲁半導體元件之襯塾連接之通孔時，亦可形成所需之通孔形 狀。更進一步，金屬層以收納於樹脂絕緣層内之方式而妒 成，故由於熱應力或外部應力等之影響而產生之/曲現^ 減少。其結果，冑以引起例如半導體元件之連接概塾斑通 孔等之導體電路之連接不良情況，從而電性連接性及連接 可罪性不易降低。 又，於半導體元件與金屬層之間所形成之黏著劑層之厚 度^於均勻，故即便使半導體元件之密接性均勻地進行熱 循環等可靠性試驗，亦可易於經長時間而確保密接性。 再者，上述下部金屬層之面積可設為大於凹部底面之面 積，並且形成於凹部側面之外側。因此，如此所形成之下 部金屬層可發揮内藏於基板之半導體元件的底面方向之 屏蔽效果。又，其與作為側面金屬層之屏蔽通道形態之電 磁屏蔽層併設時較佳^視需要，亦可使側面金屬層與下部 金屬層連接。藉此而易於確保電磁屏蔽層之效果。 上述下部金屬層亦可經雷射處理而露出。藉此可易於使 凹部之厚度均勻。 312ΧΡ/發明說明書(補件)/96-03/95147038 21 13545221354522 IX. Description of the Invention: [Technical Fields of the Invention] The present invention relates to a multilayer printed wiring board in which electronic components (semiconductor elements) such as ICs are incorporated, and more specifically, to secure semiconductor elements. The electrical connection between the f and the conductor circuit of the multilayer printed wiring board and the multilayer printed wiring board capable of connecting the reliability and the method of manufacturing the same. [Prior Art] A multilayer printed wiring board as a built-in semiconductor element is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2001-339165, or Japanese Patent No. Hei. The multilayer printed wiring board disclosed in the above-mentioned documents is composed of a substrate in which a recess for semiconductor element embedding is formed, a semiconductor element embedded in a recess of the substrate, and a shape on the substrate. An insulating layer covering the semiconductor element; a circuit formed on the insulating layer; and a via hole disposed on the insulating layer to electrically connect the conductor circuit to the pad of the +conductor 7G. In the above-mentioned conventional multilayer printed wiring board, external connection terminals (for example, PGA, BGA, etc.) are provided on the outermost surface of the multilayer printed wiring board, and the semiconductor element embedded in the substrate is electrically connected to the external via the connection terminal of the material portion. connection. In the conventional technique as described above, there is also a phenomenon in which electrical characteristics are unstable in a semiconductor device. In particular, in the case of embedded (4) electricity, there is a phenomenon in which the f-characteristics are unstable, and the result is a signal delay or the like. That is, when the recessed portion for accommodating the semiconductor element is provided on the resin substrate, the semiconductor material of the semiconductor device or the peripheral conductor circuit in which the semiconductor element is housed is received by the 312XP/invention specification (supplement)/96-03/95147038c The signal transmission in the signal wiring becomes unstable, thereby causing delay or erroneous operation, etc., and the function of the substrate cannot be ensured. 2: One example of a bad situation is also cut off as follows (.f. • The child is mistaken for the signal on the outside due to the noise from the outside, which is affected by the misoperation, etc. In addition, in the case of a conductor element, due to the influence of noise, when the signal is cut off, the heart is turned "on" and "broken", thereby causing a malfunction such as a malfunction. An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a multilayer printed wiring board and a method for manufacturing the same, which are capable of ensuring electrical connectivity and connection reliability of a substrate in which a semiconductor element is housed. In order to achieve the above object, the inventors have repeatedly conducted intensive studies, and finally completed the present invention having the following structure. That is, the present invention provides a multilayer printed wiring board which is attached to a resin insulating layer in which a semiconductor element is housed. Forming another resin insulating layer and a conductor circuit, electrically connecting the formed multilayer printed wiring board via the via hole, and the semiconductor element is built in the resin insulating layer In the recessed portion, an electromagnetic shielding layer is formed on the resin insulating layer surrounding the recessed portion. Preferably, the electromagnetic shielding layer surrounds the semiconductor element and is formed of a side metal layer and a lower metal layer. In the present invention, it is preferable that a lower metal layer is formed on a bottom surface of the concave portion, and a semiconductor element is placed on the lower metal layer. 312XP/Invention Manual (Supplement)/96 -03/95147038 6 U54522 In the present invention, the electromagnetic shielding layer may be a side metal layer formed on the resin insulating layer outside the concave portion. Further, the electromagnetic shielding layer may be configured as follows: it is located in the concave portion The outer resin layer is formed by a plurality of columnar (cylindrical, elliptical, polygonal, etc.) side metal layers formed on the resin insulating layer, and the side metal layers are connected to each other. Further, the electromagnetic shielding layer may be located on the bottom surface or the concave portion of the concave portion. Forming a lower metal layer formed on the resin insulating layer below the bottom surface. Further, the electromagnetic shielding layer may be formed in the concave portion a plurality of columnar side metal layers connected to each other on the side of the resin insulating layer, and a P metal layer formed under the resin insulating layer located on the bottom surface of the vertical recess or below the bottom surface of the recess, and the columnar side metal layer The lower metal layer is configured to be connected to the lower gold layer. The lower metal layer may be configured to be connected to the plurality of columnar side metal layers to function as an electromagnetic shielding layer. According to the configuration, the side metal layer formed by covering the plurality of walls or the metal layer or the side metal layer formed by filling the metal layer functions as an electromagnetic shielding layer. In the present invention, the recessed portion is gradually pushed upward from the bottom surface, and the side surface of the recessed portion can be accommodated and fixed to the +conductor of the recessed portion as compared with the present invention. 70 (4) (four) layers, through the column ^ ^ 2XP / mmmmmm / 96.03 / 95147038 7 1354522 electrode or interposer to the above pad and through hole Connection. Further, the invention of the present invention is a multilayer printed wiring board, which is formed on a resin insulating layer in which a semiconductor element is housed to form another tree. The grease insulating layer and the conductor circuit are electrically connected by a via hole and formed by multilayer printing. The wiring board, the semiconductor element is housed in a recess provided in the resin insulating layer, and an electromagnetic shielding layer is formed on the resin insulating layer surrounding the recess, the electromagnetic shielding layer is made of a side metal having the following form The layer is formed by a plurality of non-through holes whose inner wall surface is covered with a metal, or a plurality of non-through holes filled with a metal, or a plurality of columnar bodies made of a metal. Preferably, the side metal layer is filled with a conductive metal in a plurality of non-through holes. Electroplating, slurry, or the like can be used as the conductive metal. The columnar body is preferably at least one selected from the group consisting of a cylinder, an elliptical cylinder, and a polygonal column. The electromagnetic shielding layer preferably comprises a lower metal layer formed on the bottom surface of the recess or on the resin insulating layer of the upper two. Preferably, the side metal layer is formed in a form in which the inner wall surface of the plurality of non-through holes is covered with metal, or a plurality of non-through holes are filled with metal, or is made of metal. The plurality of columns are in the form of at least a portion of which are interconnected. Preferably, the electromagnetic shielding layer is formed by connecting the side metal layer to the lower r metal layer. 312XP/Invention Manual (Supplement)/96-03/95147038 8 1354522 The recessed portion is preferably formed in a push-pull shape, and its side surface gradually expands as it goes upward from the bottom surface. Further, the present invention is a multilayer printed wiring board, which is formed on a resin insulating layer in which a semiconductor element is housed to form another resin insulating layer and a conductor circuit, and is electrically connected to each other via a via hole. The semiconductor element is embedded in a recess provided in the resin insulating layer; the through hole connected to the Lu semiconductor element is formed in a form of a via filling filled with the conductive material; and the resin surrounding the recess The insulating layer is formed with an electromagnetic shielding layer. Further, the invention of the present invention is a multilayer printed wiring board which is formed on a resin insulating layer in which a semiconductor element is housed, forms another resin insulating layer and a conductor circuit, and electrically connects the formed multilayer printed wiring board via a via hole, and the semiconductor The component is housed in a recess provided in the resin insulating layer; the other resin insulating layer is provided with a fibrous base material, and a through hole connected to the semiconductor element is formed on the resin insulating layer; and resin insulation surrounding the recessed portion is formed An electromagnetic shielding layer is formed on the layer. Preferably, the electromagnetic shielding layer is composed of a side metal layer and a lower metal layer. Preferably, the electromagnetic shielding layer is formed of a side metal layer, wherein the inner wall of the plurality of non-through holes is covered with a metal, or a plurality of non-through holes are filled with a metal, or The shape of a plurality of columnar bodies - Γ. 312XP/Invention Manual (Replenishment)/96-03/95147038 9 1354522 The above-mentioned side metal layer is preferably a form in which the inner wall of the non-through hole is covered with a conductive metal, or a non-through hole is filled with a conductive metal. state. Preferably, the side metal layer is formed in a form in which a plurality of non-through holes are covered with a metal, or a plurality of non-through holes are filled, a metal is formed, or a plurality of metals are formed. At least a part of the shape of the columnar body is connected to each other. The columnar body is preferably at least one selected from the group consisting of a cylinder, an elliptical cylinder, and a polygonal column. Preferably, the electromagnetic shielding layer comprises a lower metal layer which is attached to the recess. The bottom surface of the crucible or the resin insulating layer located below the bottom surface of the recess is formed. Preferably, the electromagnetic shielding layer is formed by connecting the side metal layer to the lower metal layer. Further, the invention of the present invention is a multilayer printed wiring board, which is formed on a resin insulating layer in which a semiconductor element is housed to form another resin layer and a conductor circuit, and is electrically connected via a via hole to form a multilayer printed wiring board. The semiconductor element is housed in a recess provided in the resin insulating layer, and an electromagnetic shielding layer is formed on the resin insulating layer surrounding the recess, and the electromagnetic shielding layer is formed of a metal layer disposed under the lower portion of the semiconductor element. The area of the lower metal layer is larger than the area of the bottom surface of the recess. The lower metal layer is preferably formed of a rolled copper foil. Preferably, the electromagnetic shielding layer is composed of a side metal layer and a lower metal layer 312XP/invention specification (supplement)/96-03/95147038. Preferably, the electromagnetic shielding layer is formed by forming a genus layer, wherein the side gold/inner wall is made of metal and is formed of a plurality of non-becomy-hole metal shapes, states, or plurals. The through hole is filled with a form of μ m 〜 or a plurality of metal columns. The inner wall is made of a metal banquet, ^/, has a lower Yang state, a hard number of non-through holes are filled with a conductive phoenix, or a plurality of non-through holes are filled with a V-electric metal. . Electroplating, _, etc. can be used for the above conductive metal. The mi:: is preferably formed in a form in which a plurality of non-through holes are filled to form = 20%; or a plurality of non-through holes are in the form of a plurality of metal columns from the gold to the second, at least a part of which is Connected to each other. 〃 = The columnar body is preferably at least one shape selected from the group consisting of a cylinder, an elliptical cylinder, and a polygonal column. Preferably, the electromagnetic shielding layer is formed by joining metal layers. The present invention provides a method of manufacturing a multilayer printed wiring board in which a multilayer printed wiring board is formed on a resin insulating layer in which a semiconductor element is housed, and another resin insulating layer is formed. And the conductor circuit, and electrically connected by the via hole), comprising at least the steps of: forming at least a conductor circuit and a metal layer on the surface of the resin insulating layer, and at least the conductor circuit on the other side The non-formation region of the conductor circuit at the position of the metal (4) is further formed by electroplating to form the following 312XP/invention specification (supplement)/96·03/95147038 1354522=, that is, the conductor circuit of the other side is a via hole electrically connected to the conductor circuit on the one surface, and a via hole extending through the resin insulating layer on the outer side of the conductor circuit in the other surface to reach the metal layer of the one surface, thereby forming the first insulating property a resin substrate; a resin surface of a second insulating resin substrate formed by attaching a copper foil to one surface of the resin insulating layer, and being pressed onto a step of integrating the first insulating resin substrate; φ forming a conductor circuit on the second insulating resin substrate, and forming a through hole electrically connected to the conductor circuit; and the first insulating property a step of forming a concave portion from the surface of the resin insulating layer in a conductor circuit non-formation region of the resin substrate; a step of accommodating the semiconductor element in the concave portion and adhering it with an adhesive; and covering the semiconductor element to form another resin insulating layer, The step of forming a through hole. Further, the present invention provides a method of manufacturing a multilayer printed wiring board in which a multilayer printed wiring board (which is formed on a resin insulating layer in which a semiconductor element is housed) is formed with another resin insulating layer and a conductor circuit. The method further comprises the steps of: forming at least a conductor circuit and a metal layer on one side of the resin insulating layer, and forming at least a conductor circuit and a position opposite to the metal layer on the other surface; a non-formation region of the conductor circuit, forming a first insulating resin substrate by forming a through hole electrically connected to the conductor circuit by electroplating; 312XP/invention specification (supplement)/96-03/95147038 10 1354522 The resin insulating layer is bonded to the surface of the resin substrate of the (4) resin substrate, and is pressed against the upper layer and the edge of the resin layer. The insulating resin substrate is coated on the second insulating resin substrate. a step of forming a via hole by electroplating on one side of the material, which is a through-hole electrical circuit on the first insulating resin substrate and formed into a Si: a step insulating resin a step of forming a metal layer covering the concave portion by electroplating in a non-formation region of a substrate; and a step-locking inhibitor fixing the semiconductor element in the concave portion on the metal layer of the concave portion to fix the semiconductor element The step of forming other insulating layers of the wax to form electrically connected through holes. According to the present invention, the semiconductor element is housed in a concave portion provided on the resin layer of the resin substrate, and the two parts are inconvenient in the recessed portion and the magnetic shield layer. Further, the signal delay or misoperation can be reduced. According to the present invention, a metal layer is formed on the bottom surface of the concave portion, whereby the depth of the = is easily made uniform. Especially when the concave portion has a rectangular cross section, the degree is also easy to be homogenized. Therefore, when the semiconductor element is accommodated in the concave portion, the tilting phenomenon of the semiconductor element is reduced. When the insulating layer of the semiconductor element is formed on the grease insulating layer, a desired via shape can be formed. Further, since it is formed in the resin insulating layer, the phenomenon of occurrence of warpage is reduced by the influence of thermal stress or external stress, etc. 312XP/Invention Manual (supplement)/96-03/95147〇38]3 1354522 For example, it is difficult to cause a connection failure between a connection pad of a semiconductor element and a conductor circuit such as a via hole, and electrical connection, connection reliability, and connection reliability are not easily lowered. [Embodiment] The embodiment of the multilayer printed wiring board according to the present invention is a resin insulating layer 1 in which a semi-conductor element is housed, and another resin insulating layer and a conductor f path are formed, and the via hole is electrically connected. In the multilayer printed wiring board formed by the connection, the semiconductor element is housed in a recess provided in the resin insulating layer, and an electromagnetic shielding layer is formed around the recess. In the embodiment of the present invention, the "surrounding portion of the concave portion" of the semiconductor element is a resin insulating layer which is privately located on the outer side of the side surface of the concave portion, a resin insulating layer which is connected to the bottom surface of the concave portion or directly under the bottom surface of the concave portion, and is located at the concave portion. The resin insulating layer on the periphery of the opening or the inner wall of the recess (bottom surface + side surface). _ "Electromagnetic shielding layer" refers to an electrically isolated metal layer that is electrically connected to a conductor circuit (including a via hole) that transmits electrical signals in a substrate, and suppresses the semiconductor component from being activated by other semiconductor components. Acting T' has the shielding effect of protecting the semiconductor components. Further, as long as the shielding property of the semiconductor element housed in the concave portion is ensured, the electromagnetic screen layer may have electrical connectivity. The shield layer in the present application is preferably formed of a side metal layer or a lower metal layer around the semiconductor element or consists of a side metal layer and a lower metal layer. In an embodiment of the present invention, one form of the electromagnetic shielding layer is located on the side of the resin insulating layer on the outer side of the recess in which the semiconductor element is housed. 312XP/Invention Manual (Supplement)/96 Lion 5147〇38 14 1354522 Metal layer . The side metal layer may be formed by a plurality of non-through holes, an inner wall, a surface covering metal, or a plurality of non-through holes filled with a metal. Further, a plurality of columnar bodies made of a metal may be formed as the side gold layer, and the plurality of columnar systems are formed on the resin insulating layer located outside the concave portion. φ As an example of the non-through hole forming method, an opening may be provided on the outer edge of the concave portion by laser or photolithography, and the inside of the opening may be covered with a metal such as a plating layer, or plating or slurry may be used. An electrically conductive material fills the opening. One or a plurality of metals may be used for the above metals. As an example of the method for forming the columnar body, a metal body or the like which has been previously formed into a desired shape (cylindrical or polygonal column) may be inserted into an insulating layer located outside the concave portion, or the metal body may be pre-arranged. An insulating layer or the like located outside the concave portion is formed. The electromagnetic shielding layer may have a structure in which portions of the side metal layers formed in the following manner are connected to each other, that is, a plurality of non-through holes are covered with a metal, or a plurality of non-through holes are filled with a metal, Or the shape of the columnar body, the structure may be connected or partially unconnected. Further, each of the side metal layers formed in the following form may be separated, that is, a plurality of non-through holes covered with a metal, or a plurality of non-becomy holes filled with a metal, or a columnar body The form. Further, if necessary, the side metal layers of the above-described respective forms may be mixed as an electromagnetic shielding layer. 15 3 ΠΧΡ / invention manual (supplement) / 9 Fu 〇 3 / 95147038 upper, / surface metal layer formed on the outer side of the recess of the semiconductor element of the insulating layer, thereby obtaining a shielding effect. Each of the side metal layers may have electrical or no electrical connection. The shape of the inner wall of the plurality of non-through holes is covered by metal, and the plurality of non-through holes are filled with a metal, or the side metal layer of the columnar body I can be The conductors constituting the electronic circuit may be connected to the through hole 2 of the conductor circuit, or may be electrically connected to the conductor. For the sake of convenience, the side metal layer in the form of "L" is referred to as "screen t'shleld~via". By using the shielding channel, the electromagnetic shielding region on the side of the member can be formed to surround the electromagnetic interference region on the side of the member, so that the shielding channel can be prevented from being viewed from the side of the edge of the VL ^ port of the substrate, for example, when the square is observed. The open edges of the recesses are arranged in a line parallel to the direction μσ. Or an electromagnetic shielding layer is formed on the side of the opening with the recess. α (thousand bird arrangement), whereby the shield channel is preferably columnar. At this time, "the shape of the column (including the shape of the cross section is #圆) 曰 = including the shape of a triangle, a square, and a square) and other irregular cross sections::, a . It is particularly preferable when the cross section is circular (including a sugar circle) and is formed in the form of an elongated tube in the upward direction of the substrate. The reason is that the square layer and the elongated tubular conductor layer can form a region in which the surface is a circular region and can be shielded, so that it is possible to ensure not only the semiconductor 2^2]2XP/invention specification (supplement)/96·〇3/ 95ΐ 47038 16 1354522 : 2 can also ensure its (4) electromagnetic shielding area in the width direction. That is, the thickness direction of the easily-receivable substrate can also accommodate the effect in the width direction. Further, even if a stress such as heat is applied to the shield passage, the point is likely to disappear, so that it is less likely to cause a problem in the vicinity of the passage. =, the shielding channel can achieve the same effect as the column shape in the form where the non-through hole is covered with metal or the non-two-hole hole is filled with metal. Further, the plurality of shield channels are disposed to be connected to each other and surround the side surface of the concave portion in which the semiconductor element is housed, whereby the shielding effect in the substrate width direction can be further improved. The connection of the shield passages may be connected in a straight line shape in a direction parallel to the peripheral edge of the opening of the recess as shown in Fig. Ua). Further, as shown in Fig. 1(b), the state may be connected in a state of being staggered in a direction parallel to the periphery of the opening of the concave portion (a thousand bird arrangement). In order to form the electromagnetic shielding layer by using a plurality of shielding channels disposed along the periphery of the opening of the recess, the shielding channels may be continuously joined to form a block metal such as a block metal. Alternatively, the shield channels may be arranged in a misaligned if arrangement (thousands of birds) to form a sheet metal shape. When it is in any of the above forms, the metal layer which is electrically connected to the periphery of the semiconductor element can be opened, thereby forming an electromagnetic shielding layer, and electromagnetic shielding can be obtained in the side direction of the semiconductor element embedded in the concave portion. effect. The connection of the upper ν shielding channel can be a continuous connection of all the shielding channels 312 ΧΡ / invention manual (supplement) / 96_ 〇 3 / 95147 〇 38 17 (5) 4522 sexual connection structure ' can also be part of the connection of the partial connection structure . The reason for this is that, in any form, the semiconductor element can be obtained as compared with the mounting substrate in which the electromagnetic shielding layer is provided around the recess in which the semiconductor element is embedded. In another embodiment of the present invention, the other aspect of the electromagnetic shielding layer is preferably such that the lower metal layer is located in the resin insulating layer on the bottom surface of the concave portion in which the semiconductor element is housed, or is located directly under the bottom surface of the concave portion. The form of the lower metal layer formed in the resin Lu insulating layer is preferably in the form of a sheet. Preferably, the sheet-like electromagnetic shielding layer has the same size as the bottom surface of the recessed portion of the built-in semiconductor element, or is formed to have a size or an area slightly larger than the area of the bottom surface. Thereby, the electromagnetic shielding effect of the bottom surface direction of the semiconductor element can be obtained. Preferably, the 5 chip-shaped shield layer is connected to the electromagnetic shielding layer formed on the outer side of the side surface of the concave portion, that is, the shield channel (see Fig. 1 (a) - Fig. 1 (b)). By this, the electromagnetic shielding effect of the side direction and the bottom direction of the semiconductor element can be obtained. As a result, the influence of electromagnetic interference can be more effectively suppressed, and the occurrence of malfunctions such as malfunction can be suppressed. Further, in addition to the electromagnetic shielding layer or the sheet-shaped electromagnetic shielding layer in the form of a shield channel formed by filling a conductive material in the non-through hole as described above, the through hole may be filled in the through hole provided in the substrate. It is made of a conductive material or a form in which a metal plate is inserted. Further, in another embodiment of the present invention, as shown in FIG. 1(c), at least the recessed portion of the semiconductor element is included in the recessed portion of the semiconductor element = 312XP / invention specification (supplement) / 96 〇 3 /95147〇38 18 1354522 The form of the metal layer formed by the wall. That is, the metal layer covering the bottom surface and the side surface of the concave portion or the metal layer in the form of a metal layer extending from the upper end of the side surface of the concave portion along the periphery of the opening is formed in addition to the metal layer covering the bottom surface and the side surface of the concave portion. The entire outer surface of the encapsulating resin layer of the semiconductor element in the recess (except for the upper surface of the connection pad) is provided, so that the electromagnetic shielding effect of the side direction and the bottom surface direction of the semiconductor element can be simultaneously obtained. φ As the metal used for forming the electromagnetic shielding layer, it is preferable to use any one of nickel, copper, and chromium, or a metal obtained by mixing two or more kinds. Examples of such a metal include copper, a copper-chromium alloy, a copper-nickel alloy, nickel, a nickel-chromium alloy, chromium, and the like, and metals other than these may be used. The thickness of the metal layer is preferably 5 #m~2〇. The reason is that when the thickness is less than 5 //Hi, the effect of the shielding layer is offset. On the other hand, when the thickness exceeds 20, the effect of the shield layer cannot be improved. The method of forming the metal layers is preferably electroless plating, electrolytic plating, sputtering, vapor deposition, or the like. The reason for this is that it is easy to form a metal film having a uniform film thickness, and it is easier to obtain an electromagnetic wave shielding effect. The shielding layer formed by these methods may also be formed as a single layer or a plurality of layers of two or more layers. When formed into a plurality of layers, the same method can be used, or a different method can be used. It can be suitably formed according to the kind, thickness, etc. of the metal layer formed as a shield layer. Therefore, the shield layer is not intended to reduce the electromagnetic wave shielding effect. Preferably, in the embodiment of the present invention, a metal layer is formed on the bottom surface of the recessed portion of the 312XP/invention specification (supplement)/96-〇3/95147038 19 1354522 in which the semiconductor element is housed, and the semiconductor element is interposed between the metal layer. Built inside. The reason for this is that the depth of the concave portion can be made uniform, thereby eliminating the case where the semiconductor element is housed in the inclined state and is housed in the concave portion. Therefore, even if the substrate in which the semiconductor element is housed is made of a resin, when a through hole to which the connection pad of the semiconductor element is connected is formed on the resin insulating layer, a desired through hole shape can be formed, and the metal layer is formed in resin insulation. In the layer, the phenomenon of warpage due to the influence of thermal stress or external stress is reduced. Therefore, it is easy to ensure electrical connection and connection reliability of the connection pads of the semiconductor element and the conductor circuit, and the conductor circuit includes a via hole connected to the connection pad of the semiconductor element. Also, the lower metal layer may be a flat surface. Thereby, the shape retaining property of the recess and the adhesion to the adhesive can be easily ensured. A roughened surface may also be formed on the lower metal layer as needed. By using these roughened faces, the lower metal layer can be adhered to the adhesive, so that it is easy to ensure adhesion. The second lower metal layer is preferably formed of copper. The workability due to etching or the like is good. More preferably, it is formed by using a rolled copper foil. The reason for this is that it is easy to ensure the flatness of the lower metal layer, and the semiconductor element t and the flatness of the semiconductor element placed on the lower metal layer. 4 α < t is further described in detail, and is formed by a tree having a concave portion for accommodating a semiconductor element, which is a reinforcing material containing a fiber substrate such as a glass cloth in a broken glass epoxy tree. . Therefore, when a concave portion is formed by a fish-faced process or the like, irregularities are formed depending on the position of the surface. A 312XP / invention manual (supplement) / 96 〇 3 / 95147 〇 38 20 1354522 As a result, the depth of the recess is easy to be uneven. In particular, the sump is formed in the vicinity of the four corners of the concave portion having a substantially rectangular cross section, and is more likely to be lighter than the other portions. Therefore, as the present invention forms a metal layer on the bottom surface of the concave portion, the depth of the concave portion is easily uniformized. In particular, when the cross section of the concave portion is in a bishape, the depth of the concave portion near the four corners is also easily uniformized. Therefore, when the semiconductor element is housed in the concave portion, the tilting phenomenon of the semiconductor element is reduced. Therefore, even when a through hole is formed on the resin insulating layer to be connected to the lining of the semiconductor element to be housed, the desired through hole shape can be formed. Further, since the metal layer is formed so as to be housed in the resin insulating layer, the occurrence of the curve due to the influence of thermal stress or external stress is reduced. As a result, for example, a connection failure of a conductor circuit such as a connection of a semiconductor element to a spot hole or the like is caused, and electrical connectivity and connection sinusability are not easily lowered. Further, since the thickness of the adhesive layer formed between the semiconductor element and the metal layer is uniform, even if the adhesion of the semiconductor element is uniformly tested for reliability such as thermal cycling, it is easy to ensure adhesion over a long period of time. . Further, the area of the lower metal layer may be larger than the area of the bottom surface of the recess and formed on the outer side of the side surface of the recess. Therefore, the underlying metal layer thus formed can exhibit a shielding effect in the direction of the bottom surface of the semiconductor element embedded in the substrate. Further, it is preferably provided in combination with an electromagnetic shielding layer in the form of a shield channel as a side metal layer, and the side metal layer may be connected to the lower metal layer. Thereby, it is easy to ensure the effect of the electromagnetic shielding layer. The lower metal layer may also be exposed by laser treatment. Thereby, the thickness of the concave portion can be easily made uniform. 312ΧΡ/Invention Manual (supplement)/96-03/95147038 21 1354522

為上之下部金屬層之表層較佳為光澤面。其理由 -田為光澤面時，易於確保下部金屬層盥半I 之通孔之連接性=體:件=於其他樹-絕緣層 與半導趙元件之間的：著二之c下部金屬層 導體元件之密接均勻等保半 :’較佳為，黏著劑層與半導體元件之底面及侧 接Ί理由為’利用黏著劑層與半導體元件之底 性。貝|面底部周緣之接觸’而易於4保半導體元件之密接 一又，用以收納半導體元件之凹部之側面亦可如 不:形成為推拔形形狀。其理由為，收納於凹部内 ^件即使受到側面方向之應力（例如熱應力或外部應力 ^)，该應力亦可由推拔形上部之樹脂材料而緩和。又， 易於向凹部内***半導體元件。 =部之推拔形形狀較佳為，侧面與底面所成之 小角度約為60度以上，以未滿⑽度。其理 ::㈣拔形上部之樹脂材料來緩和應力。又，藉此：; 於向凹部内***半導體元件。 又’較佳為’於以凹部之壁面與半導體元件之側面所構 成之間隙内填充有樹脂層。藉由填充樹脂，可使半導體元 件穩定’因而易於確料導體元件之連接性及可靠性。 接ί進一步’亦可於以凹部之壁面與半導體元件之側面所 構成之間隙内填充樹脂層’且與樹脂絕緣層一體化。 312XP/發明說明書(補件)/96-03/95147038 22 1354522 之緣層與填充於一部 層為,所構成之間隙内之樹脂絕緣 二ί=ΤΓ抑制材料間之熱膨服係數差等引起之 以確仵财η/ 制半導體端部之龜裂等不良情況， 性。保ί久性。因此易於確保半導體元件之連接性及可靠 本發明之實施形態中較佳為，如圖3或圖4所示， 於+¥體元件之襯塾上形成柱狀電極或中介層。藉 於進行半導體元件之襯墊與通孔之電性連接。曰 =體元件之襯墊通常由氫氧化銘等而製造，特別於襯 β上未形成任何金屬層等之結襯墊之狀態下，引起如下問 題。當利用光蝕刻(經過曝光、顯像之步驟)而於層間絕緣 層上形成通孔時，於曝光、顯像後，易於襯墊之表層殘留 ，脂。又’除此之外’亦出現下述情況’即，由於顯像液 等之附著或後續步驟之藥液（例如電鍍液、酸、鹼等之溶 液）而引起襯墊變色。因此，出現難以確保該半導體元件 之襯墊與通孔之電性連接性及連接可靠性之情況。 另一方面，利用雷射而形成通孔時，具有燒損鋁製襯墊 之危險。又，於不燒損之條件下進行雷射照射時，會於襯 墊上產生樹脂殘留之情況。又，若經過後續步驟（例如指 於酸或氧化劑或者蝕刻液中之浸潰步驟、各種退火步驟 等），則亦會出現半導體元件之襯墊產生變色或溶解之情 況。因此，難以確保半導體元件之襯墊周邊之電性連接4 及連接可靠性。 312ΧΡ/發明說明書(補件)/96-03/95147038 23 1354522 更進一步，將半導體元件之襯墊製作為直徑40 am左 右，通孔可製作為直徑大於襯墊，故易引起位置偏移等， 從而易產生襯墊與通孔未連接等不良情況。因此，有時難 ! 以確保該半導體元件之襯墊與通孔之電性連接性及連接 可靠性。 對此，於半導體元件之襯墊上設置由銅等構成之中介 層’藉此可消除通孔形成之不良情況’且可使用溶劑，故 籲可防止襯墊上之樹脂殘留，並且即使經過後續步驟，亦不 會引起襯墊變色或溶解。藉此’襯墊與通孔之電性連接性 及連接可靠性難以降低。更進一步，***直徑大於半導體 元件之晶片襯墊之中介層可使襯墊與通孔可靠地連接。 更進一步，藉由設置中介層，而可於將半導體元件埋入 至印刷佈線板而進行收納、收納前、或者收納後，均易於 進行半導體元件之動作確認及電性檢查。其理由為，形成 有大於半導體元件之襯墊之中介層，使檢查用探針易於接 鲁觸。藉此，可預先判定製品之可否，並且可使生產性或成 本方面得到提高。又，亦難以產生探針造成之襯墊損失或 者傷痕等。因此，於半導體元件之襯墊上形成過渡態 (transition)，藉此可將半導體元件較佳地埋入、收納於 印刷佈線板。 作為本發明中所使用之收納半導體元件之樹脂絕緣 層，可使用選自下述基材等之硬質積層基材等：玻璃布環 氧樹脂基材、苯酚樹脂基材、玻璃布雙順丁烯二醯亞胺三 啡樹脂基材、玻璃布聚苯醚樹脂基材、芳香族聚醯胺不織 312Xp/發明說明書(補件)/96-03/95147038 24 1354522 :。二氧樹I基材、芳香族聚酿胺不織布-聚醯亞胺樹脂基 矛、此之外’亦可使用通常印刷佈線板所使用者。例如， ·=用雙面或單面覆銅積層板、無金屬膜之樹脂板、樹脂 /專膜、或者該專之複合材料。 述树月曰基材之厚度較佳為2〇 〜ρ之範圍。 ^由為田厚度為此範圍内時，易於確保層間絕緣層之 絕緣性，並且易於獲得層間連接性。 ，田厚度未滿20以m時’易於難以確保層間絕緣層之絕 緣f另方面，备厚度超過350 // m b夺，無法獲得層間 之連接性。 於本發明中，收納導體電路、半導體元件之金屬層以及 形成電磁波屏蔽之金屬層較佳為使用銅洛。其原因主要在 於外形加工優異，且電氣特性優異。 用以形成上述導體電路之銅箔之厚度較佳為“卜別 ”之範圍。其理由為，當銅箔之厚度為此範圍内時，使 用下述之雷射加工而於，絕緣性_基材上形成通孔形成 用開口時’開口周緣之銅箱之變形會減少，從而易於形成 導體電路。又，藉此而易於利用餘刻來形成細微線寬之導 體電路圖案。當銅簿之厚度未滿5⑽時，使用下述之雷 射加工而於絕緣性樹脂基材形成通孔形成用開口時，存在 開口周緣之銅落變形之虞。或者，會難以形成導體電路。 另方面，當銅箔之厚度超過20以m時，難以利用蝕刻 而形成細微線寬之導體電路圖案。 本發明中所使用之銅箔亦可係經半蝕刻處理而使其厚 312XP/發明說明書(補件)/96-03/9514703 8 25 丄乃4522 度得到補敕1 °疋者。於該情況時，較佳為’貼附於樹脂絕緣層 之銅4使用厚度大於上述數值者，蝕刻後之銅箔厚度調整 為5以m〜20以m。 更進一步’當為雙面覆銅積層板時，銅箔厚度為上述範 圍内，亦可為雙面且厚度不相同。藉此可確保強度而不妨 礙後續步驟。The surface layer of the upper and lower metal layers is preferably a glossy surface. The reason - when the field is a glossy surface, it is easy to ensure the connectivity of the through hole of the lower metal layer = half I = body: piece = between the other tree-insulating layer and the semi-conductive element: the second metal layer of the second It is preferable that the adhesion of the conductor elements is uniform and the like: 'It is preferable that the adhesive layer and the bottom surface and the side surface of the semiconductor element are connected to each other for the purpose of using the adhesive layer and the bottom of the semiconductor element. The contact of the peripheral edge of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of The reason for this is that even if the inside of the concave portion is subjected to stress in the lateral direction (for example, thermal stress or external stress ^), the stress can be alleviated by pushing down the resin material at the upper portion. Moreover, it is easy to insert a semiconductor element into the concave portion. The push shape of the portion is preferably such that the small angle formed by the side surface and the bottom surface is about 60 degrees or more, which is less than (10) degrees. The reason: (4) pull the upper resin material to ease the stress. Further, the semiconductor element is inserted into the recess. Further, it is preferable that a resin layer is filled in a gap formed between the wall surface of the concave portion and the side surface of the semiconductor element. By filling the resin, the semiconductor element can be stabilized', and thus the connectivity and reliability of the conductor element can be easily determined. Further, the resin layer may be filled in the gap formed between the wall surface of the concave portion and the side surface of the semiconductor element and integrated with the resin insulating layer. 312XP / invention manual (supplement) / 96-03/95147038 22 1354522 The edge layer and the filling of a layer, the resin insulation in the gap formed by the ί = ΤΓ suppression material between the thermal expansion coefficient difference caused by In order to ensure that the η / / the end of the semiconductor cracks and other undesirable conditions, sex. Guaranteed forever. Therefore, it is easy to ensure the connectivity and reliability of the semiconductor element. In the embodiment of the present invention, as shown in Fig. 3 or Fig. 4, a columnar electrode or an interposer is formed on the liner of the +¥ body element. The electrical connection between the pad of the semiconductor component and the via hole is performed.曰 = The spacer of the body member is usually manufactured by a hydroxide or the like, and in particular, in a state where a liner pad of any metal layer or the like is not formed on the liner β, the following problems are caused. When a through hole is formed in the interlayer insulating layer by photolithography (step of exposure and development), it is easy to remain on the surface layer of the liner after exposure and development. Further, in addition to the above, the gasket may be discolored due to the adhesion of the developing liquid or the like (for example, a solution of a plating solution, an acid, an alkali or the like). Therefore, it has been difficult to ensure electrical connection and reliability of connection between the spacer of the semiconductor element and the via. On the other hand, when a through hole is formed by laser, there is a risk of burning a pad made of aluminum. Further, when laser irradiation is performed under the condition of no burning, resin residue may occur on the liner. Further, if a subsequent step (for example, an acid or oxidizing agent or an immersion step in an etching solution, various annealing steps, etc.) is passed, the spacer of the semiconductor element may be discolored or dissolved. Therefore, it is difficult to ensure the electrical connection 4 and the connection reliability around the pad of the semiconductor element. 312 ΧΡ / invention manual (supplement) / 96-03/95147038 23 1354522 Further, the spacer of the semiconductor element is made to have a diameter of about 40 am, and the through hole can be made larger than the spacer, so that it is easy to cause positional deviation, etc. Therefore, it is easy to cause a problem that the gasket and the through hole are not connected. Therefore, it is sometimes difficult to ensure electrical connection and connection reliability of the spacer of the semiconductor element and the via. In this case, an interposer made of copper or the like is provided on the spacer of the semiconductor element, thereby eliminating the problem of via formation, and a solvent can be used, so that the resin residue on the liner can be prevented, and even after the subsequent The steps also do not cause the liner to discolor or dissolve. Therefore, it is difficult to reduce the electrical connectivity and connection reliability of the spacer and the via. Further, the interposer having a diameter larger than the wafer pad of the semiconductor element allows the pad to be reliably connected to the via. Further, by providing the interposer, it is possible to easily confirm the operation and electrical inspection of the semiconductor element by burying the semiconductor element in the printed wiring board, storing it, or storing it. The reason for this is that an interposer having a spacer larger than that of the semiconductor element is formed, and the inspection probe is easily touched. Thereby, the possibility of the product can be determined in advance, and the productivity or cost can be improved. Moreover, it is also difficult to generate pad loss or scratches caused by the probe. Therefore, a transition state is formed on the spacer of the semiconductor element, whereby the semiconductor element can be preferably buried and housed in the printed wiring board. As the resin insulating layer for accommodating the semiconductor element used in the present invention, a hard laminate substrate selected from the group consisting of a glass cloth epoxy resin substrate, a phenol resin substrate, and a glass cloth bi-butene can be used. Diimine imine triphenyl resin substrate, glass cloth polyphenylene ether resin substrate, aromatic polyamine non-woven 312Xp / invention manual (supplement) / 96-03/95147038 24 1354522 :. A dioxosite I substrate, an aromatic polyamine-based nonwoven fabric-polyimine resin-based spear, and the like can be used as a user of a conventional printed wiring board. For example, • use a double-sided or single-sided copper-clad laminate, a metal-free resin sheet, a resin/special film, or a specialized composite material. The thickness of the substrate of the tree sap is preferably in the range of 2 〇 to ρ. When the thickness of the field is within this range, it is easy to ensure insulation of the interlayer insulating layer, and interlayer connectivity is easily obtained. When the thickness of the field is less than 20 m, it is difficult to ensure the insulation of the interlayer insulating layer. In addition, the thickness is more than 350 // m b, and the connectivity between the layers cannot be obtained. In the present invention, it is preferable to use a copper wire for accommodating the conductor circuit, the metal layer of the semiconductor element, and the metal layer forming the electromagnetic wave shield. The reason is mainly due to excellent shape processing and excellent electrical characteristics. The thickness of the copper foil used to form the above conductor circuit is preferably in the range of "b". The reason is that when the thickness of the copper foil is within this range, the following laser processing is used, and when the opening for forming the through hole is formed on the insulating substrate, the deformation of the copper box at the periphery of the opening is reduced. It is easy to form a conductor circuit. Further, by this, it is easy to form a conductor circuit pattern having a fine line width by using the residual. When the thickness of the copper sheet is less than 5 (10), when the opening for forming a through hole is formed in the insulating resin substrate by the laser processing described below, there is a possibility that the copper is deformed by the peripheral edge of the opening. Or, it may be difficult to form a conductor circuit. On the other hand, when the thickness of the copper foil exceeds 20 m, it is difficult to form a conductor circuit pattern of a fine line width by etching. The copper foil used in the present invention may also be subjected to a half etching process to have a thickness of 312XP/invention specification (supplement)/96-03/9514703 8 25 452 is 4522 degrees. In this case, it is preferable that the thickness of the copper 4 attached to the resin insulating layer is larger than the above value, and the thickness of the copper foil after etching is adjusted to 5 m to 20 m. Further, when it is a double-sided copper-clad laminate, the thickness of the copper foil is within the above range, and it may be double-sided and different in thickness. This ensures strength without hindering the next steps.

又作為形成於上述凹部底面之金屬層的銅箔之厚度較 佳^ 5 〜20 //m。其理由為，當銅箔之厚度為此範圍 =時，於進行空腔之外形加工時，貫通該銅箔之虞會減 夕，故於凹部底面金屬層之形成受到妨礙之情況減少。 又，利用蝕刻易於加工形成金屬層。 作為形成於上述凹部底面之金屬層，除銅以外，亦可使 用鎳、鐵、鈷等金屬。 ^又’作為形成電磁屏蔽層之片狀金屬層的銅箔之厚度， 較佳為5 〜20 "。其理由為，當銅箔之厚度為此範 圍内時，易於確保屏蔽效果。 *再者作為上述絕緣性樹脂基材及銅箱，特佳為使用預 次體與覆銅積層後加熱壓製而獲得之單面或雙面覆銅積 層板，上述預浸體係將環氧樹脂含浸入玻璃布中而形成之 Β-階段之預浸體。其理由為，於銅箔蝕刻後之處理中，佈 線圖案及通孔之位置不會偏移，從而位置精度優異。 於本發明中’用以收納半導體元件而設置於樹脂絕緣層 之凹部，可利用魚眼加工、穿孔、雷射加工等而形成。^ 佳為利用雷射加工而形成。藉此，與其他加卫相比，易】 312ΧΡ/發明說明書(補件)/96_〇3/95147()38 26 形成均勻深度之凹部。 進行力T雷射加工而形成上述凹部時’亦可利用雷射昭射 密接性I'於金屬層(銅箱)之表面形成氧化膜，從而使 i t :雷射加工易於將凹部加工成推拔形㈣ 金屬声=工而形成凹部時，形成於凹部底面之 。屬揮緩衝作用，故可使凹部之深度均勻。 亡述凹部之深度，可根據所收 度及形成於該半導體元件 ；°件自身之尽 中介層之厚度、黏著劑層之厚戶接:二之柱/電極或者 加 > — 日々度寻而決定。並且，因於 絕缘成金屬層’故易於使設置於半導體元件與樹脂 崎劑層之厚度均句。其結果，於收納半導 _ 夺可減少半導體元件之傾斜等現象。 纟於可均句保持半導體元件與樹脂絕緣層之密接 難以tr 吏進行熱循環等可靠性試驗，經長時間密接性亦 狀又二r納半導體S件之凹部較佳為形成為推拔形形 狀ΛΓ、側面自底面向上方而逐漸擴展。由於設為此形 1’：1於凹部内之半導體元件受到側面方向之應力 (例如熱應力或外部應力等），該應力亦可緩和。更進一 ^為了使t導體元件固著而設置於半導體元件底面之黏 者劑因毛細管現象而沿著凹部側面流動之現象減少，故與 半導體元件之凹部底部之密接性難以降低。 於本發明中，推拔形之角度如圖2所示，定義為側面與 氐面所成之外角，該推拔形之角度較佳為60度以上且未 312XP/發明說明書(補件)/96-03/95147038 27 大'!、與半導體元件尺寸基本相當之開口而成） 二個開口之形態的半導體元件收納用凹 ㊁者： 之另-表面進行雷射照射，形成:=屬一: 露出，因此，金屬層會自該非貫通孔之底面 ，、後於非貝通孔内填充金屬電鍍，藉此於 之外側形成作為電磁屏蔽層之屏蔽通道。 】面 更進纟，作為其他實施形態，彳以下述方式而形成 導體收納用基板：將於其中之—表面形成有尺寸大於半導 體凡件收納用凹部之底面尺寸之金屬層的第—絕緣 材、與第二絕緣性樹脂基材，積層於上述第一絕緣性 樹月曰基材之金屬層形成侧之表面，並對第一絕緣性樹脂基 材之另一表面進行雷射照射，形成到達金屬層之半導體元 件收納用凹部’因此’金屬層會自該凹部之底面露出，其 後对於該凹部之整個内壁面進行電鍍、或者濺鍍，以形成 金屬覆蓋層，藉此而形成電磁屏蔽層。 • 於上述實施形態中，第一絕緣性樹脂基材及第二絕緣性 樹脂基材之厚度較佳為2〇 〜350 /zm。其理由為，當 厚度為此範圍内時，易確保層間絕緣層之絕緣性以及形成 進行層間連接之通孔，從而使導致電性連接性降低之現象 減少。 又，作為各絕緣性樹脂基材而言，可使用由單層所構成 之樹脂基材’亦可使用多層化為複數層之樹脂基材。 將半導體元件埋入至上述半導體收納用基板之凹部内 而收納之後，於半導體收納用基板之單面或雙面形成層間 312XP/發明說明書(補件)/96-03/95147038 29 1354522 樹脂絕緣層，繼而於該層間樹脂絕緣層上，形 .之導體電路，該通孔係與半導體元件電性連接而成= .更進一步將其他層間樹脂絕緣層與導體電路交互積岸，、 、此可製造本發明之多層印刷佈線板。 θ ^ 作為埋入至上述半導體收納用基板之凹部内之半導體 〇件而5，可使用於連接襯墊上預先形成有柱狀電極之半 • ^體元件，或者形成有覆蓋連接襯墊之中介層之半導體元 _件„亥等半導體元件經由柱狀電極或中介層而與設置於層 間樹脂絕緣層之通孔電性連接。 θ 以下，就（1)具有柱狀電極之半導體元件以及（2)具有中 介層之半導體元件之製造方法加以說明。 U)具有柱狀電極之半導體元件之製造方法 本發明中使用之所謂具有柱狀電極之半導體元件，係指 具有柱狀電極或者再佈線之半導體元件。 如圖3所示，進行下述準備：於晶圓狀態之半導體元件 Φ κ矽基板）上形成由氫氧化鋁等所構成之連接襯墊2，再 於其上表面去除連接襯墊2之中央部之部分，形成保護膜 3(鈍化膜）。於該狀態，連接襯墊2之表面於未由保護膜 3覆蓋之中央部露出。 繼而’於半導體元件1之整個上表面形成基礎金屬層 4。基礎金屬層可使用鉻、銅、鎳等。 其次’於基礎金屬層4之上表面形成由液狀抗蝕劑構成 ' 之電鍍抗蝕層’於電鍍抗蝕層之半導體元件連接襯墊所對 — 應之部分形成開口部。 312ΧΡ/發明說明書(補件)/96-03/95^038 30 1354522 —繼之，將基礎金屬層4作為電鍍電流路徑而進行電鍍， 猎此於電鍍抗蝕層開口部内之基礎金屬層之上表面形成 .,狀電極5其後，剝離電鍍抗#層，更進一步，將柱狀 電極5作為料而㈣基礎金屬層之多餘部分以將其去 除，則僅會於柱狀電極下殘存有基礎金屬層4。 .、更進—步，於半導體元件1之上表面側形成由環氧樹脂 •或聚醯亞胺等構成之密封膜6。於該狀態下，當柱狀電極 籲5之上表面由密封膜6覆i時，矛μ對表面進行之適當研 使柱狀電極5之上表面露出。繼而，經切割步驟，獲 得各個半導體晶片（具有柱狀電極之半導體元件）。 (2)具有中介層之半導體元件之製造方法 本毛月中使用之所謂中介層，係指用以與設置於半導體 元件之襯墊上之通孔電性連接之***層。 如圖4所示’對内藏之半導體元件1()之全表面進行蒸 鍍、韻等處理，使於全表面形成導電性金屬層12(第…工 籲薄膜層）。該金屬較佳為錫、鉻、欽、鎳、鋅、錄、金、 銅等。厚度較佳為形成於〇.〇〇1 ^〜以㈣之間。直 理由為，若金屬層之厚度於此範圍内，則易於全表面„ 膜厚均勻之金屬層，從而膜厚之不均現象減少。 連接襯塾14由上述第1薄膜層12覆蓋，可提高中介芦 20與半導體元件之連接襯塾14之界面的密接性。又，: 於=等金屬覆蓋半導體元件1〇之連接概塾14，故可防止 X刀進入界面’防止襯塾溶解、腐名虫，從而難以使可靠性 312XP/發明說明書(補件)/96-〇3/95147〇38 31 1354522 第1薄膜層12之金屬較佳為使用鉻、鎮、 趙 ^ 斌之任一.^ 屬。其理由為，連接襯墊14與金屬層12之密 ^ 易於防止水分進入界面。 佳，且 利用濺鍍、蒸鍍或無電解電鍍，使第2薄臈芦 於第1薄膜層12上。該金屬具有鎳、鋼、金、化成 據電性特性、經濟性、或者後續步驟中形成之加厚屌。根 =銅所形成之觀點’較佳為第2薄膜層17 “用Further, the thickness of the copper foil as the metal layer formed on the bottom surface of the concave portion is preferably from 5 to 20 //m. The reason for this is that when the thickness of the copper foil is in the range of =, when the cavity is formed outside the cavity, the entanglement of the copper foil is reduced, so that the formation of the metal layer on the bottom surface of the concave portion is hindered. Further, the metal layer is easily formed by etching. As the metal layer formed on the bottom surface of the concave portion, a metal such as nickel, iron or cobalt may be used in addition to copper. Further, the thickness of the copper foil as the sheet metal layer forming the electromagnetic shielding layer is preferably 5 to 20 ". The reason is that when the thickness of the copper foil is within this range, it is easy to ensure the shielding effect. * In addition, as the insulating resin substrate and the copper case, a single-sided or double-sided copper-clad laminate obtained by heating and pressing a pre-substrate and a copper-clad laminate is used, and the prepreg system impregnates the epoxy resin. A Β-stage prepreg formed into a glass cloth. The reason for this is that the position of the wiring pattern and the through hole is not shifted during the post-etching of the copper foil, and the positional accuracy is excellent. In the present invention, the concave portion provided in the resin insulating layer for accommodating the semiconductor element can be formed by fisheye processing, perforation, laser processing or the like. ^ Jia is formed by laser processing. Thereby, compared with other reinforcements, it is easy to form a concave portion of uniform depth by 312 ΧΡ / invention specification (supplement) / 96_ 〇 3 / 95147 () 38 26 . When the force T laser processing is performed to form the concave portion, an oxide film can be formed on the surface of the metal layer (copper box) by using the laser radiation adhesion property I', so that the laser processing is easy to process the concave portion into a push-out process. Shape (4) Metal sound = when forming a recess, it is formed on the bottom surface of the recess. It is a buffering effect, so the depth of the concave portion can be made uniform. The depth of the recess can be determined according to the degree of convergence and formation of the semiconductor component; the thickness of the interposer itself and the thickness of the adhesive layer: the column/electrode or the addition Decide. Further, since the metal layer is insulated, it is easy to make the thickness of the semiconductor element and the resin sacrificial layer uniform. As a result, the phenomenon of tilting the semiconductor element can be reduced by accommodating the semiconductor.可 可 可 可 可 保持 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体ΛΓ, the side gradually expands from the bottom to the top. Since the semiconductor element in the recessed portion is subjected to the stress in the side direction (e.g., thermal stress or external stress, etc.), the stress can be alleviated. Further, in order to fix the t-conductor element, the adhesion of the adhesive provided on the bottom surface of the semiconductor element to the side surface of the concave portion due to the capillary phenomenon is reduced, so that the adhesion to the bottom portion of the concave portion of the semiconductor element is hardly lowered. In the present invention, the angle of the push-out shape is as shown in FIG. 2, and is defined as an outer angle formed by the side surface and the top surface. The angle of the push-out shape is preferably 60 degrees or more and is not 312XP/invention specification (supplement)/ 96-03/95147038 27 Large '!, which is basically equivalent to the size of the semiconductor element.) Both of the semiconductor elements in the form of two openings are recessed: the other surface is irradiated with laser light to form: = one: Exposed, the metal layer is filled with metal plating from the bottom surface of the non-through hole and then in the non-beacon hole, thereby forming a shielded channel as an electromagnetic shielding layer on the outer side. In other embodiments, the conductor housing substrate is formed by forming a first insulating material having a metal layer having a size larger than a bottom surface of the semiconductor housing recessed portion. And the second insulating resin substrate is laminated on the surface of the first insulating tree base material on the metal layer forming side, and the other surface of the first insulating resin substrate is irradiated with laser light to form the reaching metal The semiconductor element housing recessed portion of the layer is such that the metal layer is exposed from the bottom surface of the recessed portion, and then the entire inner wall surface of the recessed portion is plated or sputtered to form a metal coating layer, thereby forming an electromagnetic shielding layer. . In the above embodiment, the thickness of the first insulating resin substrate and the second insulating resin substrate is preferably 2 〜 to 350 / zm. The reason for this is that when the thickness is within this range, it is easy to ensure the insulating property of the interlayer insulating layer and to form via holes for interlayer connection, thereby reducing the phenomenon of lowering electrical connectivity. Further, as the insulating resin substrate, a resin substrate composed of a single layer can be used. A resin substrate in which a plurality of layers are formed into a plurality of layers can also be used. After the semiconductor element is embedded in the recessed portion of the semiconductor housing substrate and stored, the interlayer 312XP/invention specification (supplement)/96-03/95147038 29 1354522 resin insulating layer is formed on one surface or both surfaces of the semiconductor housing substrate. Then, on the interlayer resin insulating layer, the conductor circuit of the shape is electrically connected to the semiconductor element. Further, the other interlayer resin insulating layer and the conductor circuit are alternately stacked, and the same can be manufactured. The multilayer printed wiring board of the present invention. θ ^ is a semiconductor element embedded in the concave portion of the semiconductor housing substrate, and can be used to connect a half-body element in which a columnar electrode is formed in advance on the connection pad, or to form an intermediate layer covering the connection pad. The semiconductor element of the layer is electrically connected to the via hole provided in the interlayer resin insulating layer via the columnar electrode or the interposer. θ Hereinafter, (1) the semiconductor element having the columnar electrode and (2) A method of manufacturing a semiconductor element having an interposer. U) A method of manufacturing a semiconductor element having a columnar electrode. A semiconductor element having a columnar electrode as used in the present invention means a semiconductor having a columnar electrode or a rewiring. As shown in FIG. 3, a connection pad 2 made of aluminum hydroxide or the like is formed on a semiconductor element Φ κ 矽 substrate in a wafer state, and a connection pad 2 is removed on the upper surface thereof. In the central portion, a protective film 3 (passivation film) is formed. In this state, the surface of the connection pad 2 is exposed at a central portion not covered by the protective film 3. The entire upper surface of the body member 1 is formed with a base metal layer 4. The base metal layer may be made of chromium, copper, nickel, etc. Next, 'the plating resist formed of a liquid resist is formed on the upper surface of the base metal layer 4' The portion of the semiconductor device connection pad on which the plating resist is applied is formed as an opening portion. 312 ΧΡ / invention specification (supplement) / 96-03/95^038 30 1354522 - Next, the base metal layer 4 is used as a plating The current path is electroplated, and the surface of the base metal layer in the opening portion of the plating resist layer is formed. The electrode 5 is thereafter stripped of the plating resist layer, and further, the columnar electrode 5 is used as a material (4) If the excess portion of the metal layer is removed, the base metal layer 4 remains only under the columnar electrode. Further, the epoxy resin layer or the polyimide layer is formed on the upper surface side of the semiconductor element 1. A sealing film 6 made of an amine or the like. In this state, when the upper surface of the columnar electrode 5 is covered with the sealing film 6, the surface of the column electrode 5 is appropriately exposed to the surface of the columnar electrode 5, and then, Through the cutting step, each semiconductor wafer is obtained (Semiconductor element having a columnar electrode) (2) Method of manufacturing a semiconductor element having an interposer The so-called interposer used in this month refers to the via hole electrical property for use on a pad provided on a semiconductor element. As shown in Fig. 4, the entire surface of the semiconductor element 1 () is subjected to vapor deposition, rhyme, and the like to form a conductive metal layer 12 on the entire surface. The metal is preferably tin, chrome, chin, nickel, zinc, lanthanum, gold, copper, etc. The thickness is preferably formed between 〇.〇〇1^~(4). The reason is that if the thickness of the metal layer is Within this range, it is easy to have a full-surface metal layer with a uniform film thickness, and the unevenness of the film thickness is reduced. The connection liner 14 is covered by the first film layer 12, and the adhesion between the intermediate reed 20 and the interface of the semiconductor element to the lining 14 can be improved. Moreover, the connection of the semiconductor element 1 is covered by the metal such as =, so that the X-knife can be prevented from entering the interface, which prevents the lining from being dissolved and rots, making it difficult to make the reliability 312XP/invention specification (supplement)/96 - 〇3/95147〇38 31 1354522 The metal of the first film layer 12 is preferably any one of chromium, town, and Zhao. The reason for this is that the connection pad 14 is dense from the metal layer 12, and it is easy to prevent moisture from entering the interface. Preferably, the second thin cucurbit is placed on the first film layer 12 by sputtering, vapor deposition or electroless plating. The metal has nickel, steel, gold, chemical properties, economy, or thickened enthalpy formed in subsequent steps. Root = the viewpoint of copper formation' is preferably the second film layer 17

此處，設置第2薄膜層17之理由為，僅第i薄膜 難以獲得下述用以形成加厚層之電鑛用導 L 17作為加厚之導線而使用。 相層 第2薄膜層17之厚度較佳為〇.〇1㈣〜㈠㈣之範 圍。八理由為，當厚度為此範圍内時，可發揮導線之作用， 並且於蝕刻時’下層之第i薄膜層被更多削除而出現: 之：況減少’故水分難以進入，從而不會導致可靠性降低： 藉由無電解或者電解電鍍，而使上述第2薄膜層17上 加厚。所形成之金屬之種類具有錄、銅、金、銀、辞 等。根據電性特性、經濟性、中介層之強度或結構上之耐 性'或者後續步驟中形成之電錢佈線層之導體層主要由鋼 所形成之觀點，較佳為藉由電解鍍銅而形成。 加厚電解鍍銅層18之厚度較佳為2 ^〜別"之範 圍其理由為，當厚度為此範圍内時，與上層通孔之連接 :靠性降低之情況減少。又，蝕刻時產生底邊之現象減 少且所形成之t介層與通孔之界面產生間隙之情況減 312XP/發明說明書(補件)/96-03/95147038 32 1J54522 少。 其後，形絲刻抗_，利料光、顯像而使中介声以 :卜=之金屬露出’以進行餘刻，使由第！薄膜層；2、 ^興賴層、17、加厚層18所構成之中介層2G形成於半 導體元件之概塾•上。 除上述中介層之製造方法以外，可在將半導體元件内藏 於基板之凹部内之後形成中介層，亦可在形成於半導體元 件及核心基板上之金屬膜上形成乾膜抗㈣後，去除相當 於中介層之部分，利用電鑛而加厚，其後剝離抗钱層，利 用敍刻液使中介層同樣形成於半導體元件之晶片概塾上。 繼而，具體說明本發明之多層印刷佈線板之製造方法之 一例0 A.半導體元件收納用基板之製作 當製造本發明之多層印刷佈線板時，構成其之半導體元 件收納用基板使用具有下述形態者：於絕緣性樹脂基材之 籲單面或雙面貼附有鋼箔而形成之第一絕緣性樹脂基材與 第二絕緣性樹脂基材積層。 ^ (1)上述第一絕緣性樹脂基材例如可由雙面覆銅積層板而 形成，對上述雙面覆銅積層板之一表面進行雷射照射，形 成貫通其中之一銅箔及樹脂絕緣層而到達銅箱之另—背 面的通孔形成用開口及屏蔽通道形成用開口。 此時，屏蔽通道形成用開口形成於如下所述半導體元件 收納用凹部之形成區域之外側，並且形成為鄰接之開口彼 此連結之形態。 312XJV發明說明書(補件)/96.03/95147038 33 10^22 、上述雷射照射使用脈衝振動型二氧化碳雷射加工裝置 進仃，其加工條件較佳為，脈衝能〇· 5 mJ〜1〇〇 mj、脈 衝寬度1以s〜100以s、脈衝間隔〇. 5 ms以上、頻率2000 Hz〜30〇〇 Hz、發數1〜5之範圍内。 以上述加工條件為基礎所形成之開口直徑較佳為2〇 江广250 #m。其理由為，當口徑為此範圍内時，通孔之 3於技術方面變得容易，且導致電性連接性降低之情況 Γ v。又，利用電鍍進行之填充變得容易，故導致電性連 $ !·生降低之情况減少，從而易實現佈線之高密度化。當口 4未滿20 βιη時，通孔形成於技術方面困難，且難以確 保電性連接性。另-方面，當口徑超過250 ^ m時，電鍍 =填充性存在因難，未能確保電性連接性，亦妨礙佈線之 向密度化。 再者’為了利用雷射照射使通孔形成用開口及屏蔽通道 形成用㈤口形成於覆銅積層板上，具有下述方法：直接雷 射法’其係以使銅镇及絕緣性樹脂基材上同時形成開口之 方法而進行之雷射照射；以及保角（c〇nf〇rmai)法，其係 利用蝕刻而預先去除相當於通孔形成用開口之銅箔部分 之後對絕緣性樹脂基材以光束照射，可使用上一方 法。 (2)為了去除上述步驟中形成之開口内所殘留之樹脂殘 渣，較佳為進行除膠渣（desmear)處理。 =除膠渣處理可藉由酸或氧化劑（例如鉻酸、過錳酸） 之藥液處理等漏式處理而進行，或者藉由氧氣電衆放電處 3丨2XP/發明說明書(補件)/96-03/95147038 理、電暈放電處理、紫外線雷 乾式處理而進行。 射處理或準分子雷射處理 等 之方法可根據絕緣性樹脂基材之 雷射條件等，依照預測之殘留膠 選擇該等除膠渣處理 種類、厚度、開口直徑、 渣量而選擇。 (3i對Μ上述除料處理後之基板之通孔形成㈣口以及側 面金屬層上之屏蔽通道形成用開口，實施以銅猪為電鑛導 線之電解鍍域理，將電解鍍銅完全填充至通孔形成用開 =及屏蔽通道形成用開口内，形成通孔（填孔）及屏蔽通 道0 再者，亦可根據情況，於電解鑛銅處理後，將於基板之 開口上部凸起之電解錄銅，藉由砂帶研磨、抛光研磨、姓 刻等去除而使其平坦化。 ⑷於上述第—絕緣性樹脂基材之兩面上形成錢層，經 過曝光、顯像步驟，對抗银層非形成部分以含有氯化銅等 _之姓刻液進行姓刻處理。其後，剝離抗㈣，藉此於第-絕緣性樹脂基材之其中一表面，形成有包含通孔焊點之導 體電路、位置對準用定位標記等，並且於另―表面，形成 有具有與半導體元件相關之尺寸之金屬詹、包含通孔焊點 之導體電路、位置對準用定位標記等。 再者複數個屏蔽通道形成相互連結之形態，其等之一 端於第絕緣性樹脂基材之一表面露出，另一端與金屬層 表面連接，形成電磁屏蔽層。 (5)於上述第一絕緣性樹脂基材之金屬層形成侧之表面， 312ΧΡ/發明說明書(補件)/96·〇3/95147038 35 完全填充至開口内，以形成填孔。 二=上:二:電:鍍銅處理後，將於叫 光研磨、钱刻等去除而使=銅，藉由砂帶研磨、抛 又’亦可經過無電解雷# 無電解電鍍膜亦可使用=7成電鑛膜。於該情況時， J J便用銅、鎳、銀等金屬。 或者貼形成抗钱層°抗#層可利用塗佈 有貼附預先形成薄膜灿本+〜 載置預先描繪有電路之遮法。對該抗_層上 蝕劑層，並對蝕刻浐蝕_订’光、顯像，形成姓刻抗 成包含通孔：:=形之金屬層進行㈣，形 貼附之保護薄膜剥離電路’其後’使上述步驟⑻中所 ^虫，液較佳為，選自硫酸一過氧化氫 化銅、氣化鐵之水溶液中之至少！種水溶液。文-乳 :了易於形成精細圖案’亦可預先對銅落之表面之整個 路之前處理。 &乍為蝕刻上述銅落而形成導體電 i 導體電路之一部分之通孔輝點(一 e land)較佳為’其内徑與通孔口徑大致相同，或者苴外秤 形f為大於通孔直徑，焊點直徑形成為5“ m 之範圍内。其理由為’當谭點直徑為此範圍内時，妨礙通 孔與焊點之連接之情況減少，且妨礙高密度化之情況亦減 少。 ⑽繼而，與第一絕緣性樹腊基材之金屬層設置面相反側 312XP/發明說明書(補件)/96-03/95147038 37 而开體元件收納區域），例如，利用雷射加工 貫通樹腊層並到達金屬層表面之開口，自該開口形 路出金屬層表面之凹部’藉此形成半導體元件收納用基 :=要’亦可經過抗㈣形成步驟、㈣處理步驟而 形成金屬層露出之凹部。 例如於上述第一絕緣性樹脂基材與第二絕緣性樹脂基 ^積層體上，利用脈衝振動型二氧化碳雷射加工裝置進 仃雷射照射’藉此形成自第一絕緣性樹脂基材之表面貫通 樹脂層而到達金屬層表面之開σ，從而形成收納或内藏半 導體元件之凹部。 上述收納半導體元件凹部之加工條件較佳為，脈衝能 脈衝寬度為1 〜1〇〇 #s、脈衝間 隔〇. 5 ms以上、頻率2〇〇〇 Hz〜3〇〇〇 Hz、衝擊數工〜“ 之範圍内。 藉由上述雷射加工而形成内藏有半導體元件之凹部，並 _且於該凹部之底面露出有金屬層（此時指銅箔^ 。 B.半導體元件之收納_、埋入 (11)於由上述A中步驟（1)〜（10)所獲得之半導體元件收 納用基板中’埋入半導體元件。 該埋入之半導體元件如上所述，可使用於連接襯墊上預 先形成有柱狀電極之半導體元件，或者形成有覆蓋連接襯 墊之中介層的半導體元件，此處對使用後者之情況加以說 明。 該中介層係為了使半導體元件之襯墊與包含印刷佈線 312XP/發明說明書(補件)/96-03/95147038 38 1354522 板之通孔的導體電路直接連接而設置之中介層，其藉由於 晶片襯墊上設置薄膜層，更進一步於該薄臈層上設置加厚 '層而形成，較佳為，以至少2層以上之金屬層而形成。 :.又，該中介層較佳為，形成大於半導體元件之晶片觀塾 之尺寸。形成上述尺寸，可使與晶片襯墊之位置對準容 易，其結果為，與晶片襯墊之電性連接性提高，並且可利 用雷射照射或光钱料行通孔加工’而不會對晶片襯塾造 籲成損害。因此，能夠將半導體元件可靠地埋入、收納於印 刷佈線板内，或者與印刷佈線板可靠地電性連接。 又，於中介層上，可直接形成構成印刷佈線板之導體電 路之金屬層。 又，除如上所述之製造方法以外，中介層亦可於形成於 半導體元件之連接襯墊侧之全表面或者形成於埋入半導 體兀件之半導體元件收納用基板上的金屬膜上，形成由乾 膜構成之抗蝕層，去除相當於中介層之部分後，利用電鍍 φ進行加厚處理，其後剝離抗蝕層，利用蝕刻液使中介層同 樣形成於半導體元件之連接襯墊上。 (12)於收納、内藏有半導體元件之基板上設置絕緣樹脂層 之後，進行與上述A中（1)〜（4)相同之處理，藉此可形 成：與形成於内藏之半導體元件之連接襯墊上的中介層電 性連接之通孔；與包含形成於半導體元件收納用基板之通 孔的導體電路電性連接之通孔；以及外側之導體電路。更 進步’使絕緣樹脂層及覆銅積層，並反覆進行與上述a 中（1)〜（4)相同之處理，藉此可更進一步獲得多層化印刷 39 312xp/mmmmmmm/96-〇3/95 moss 1354522 佈線板。 上述方法係將絕緣樹脂層逐次積層以使絕緣樹脂層多 •:化’視需要’絕緣樹脂層亦可Μ單位之電路基板上積 '上’再—併進行加㈣合，藉此而形成將絕緣樹 月曰層夕層化之多層印刷佈線板。 • (13)繼而，於最外側轉基板之表面分卿成㈣劑層。 =該情況下，對電路基板之整個外表面塗佈阻谭劑組成 φ物，當該塗膜乾燥後，對該塗膜上載置描繪有焊錫塾開口 部之先罩薄膜進行曝光、顯像，藉此分別形成位於導體電 路之通孔正上方之導電性襯塾部分露出的焊錫概塾開 此時亦可貼附已乾膜化之阻焊劑層，經曝光、顯像 或者雷射加工而形成開口。 =自上述料層之非形成部露出之料襯塾上，形成錄 -金等耐㈣。此時，錦層之厚度較佳為i 口〜7 _， 金層之厚度較佳為0.01 ym〜0 1 am。 »除此之外，亦可形成鎳_鈀-金、金（單層）、銀（單層） 等。於耐姓層形成後，剝離遮罩層。藉此，成為形成有耐 蝕層之焊錫襯墊及未形成有耐蝕層之焊錫襯墊混合存在 之印刷佈線板。 (14)自上述步驟（13)中所獲得之阻焊劑之開口，將焊錫體 供給至露出於通孔正上方之焊錫墊部分，並利用該焊錫體 之熔融、固化而形成焊錫凸塊，或者使用導電性黏著劑或 焊錫層，將導電性球或導電性銷與襯墊部接合，以形成多 層電路基板。 312XP/發明說明書(補件)/96-03/95147038 40 1354522 (3)電解鍍銅膜之形成 於除膠潰處理結束後，於設置有第一絕緣性基材3〇的 通孔形成用開口 36及屏蔽通道形成用開口 37之銅箔面 上，以如下之電鍍條件，實施將鋼箔作為電鍍導線之電解 錄銅處理。 [電解電鍍液] 2.24 mol/1 〇·26 mol/l H.O ml/1 1〇.0 ml/1 硫酸 硫酸銅 添加劑A (反應促進劑） 添加劑B (反應抑制劑） [電解電鍍條件] 電流欲度 時間 65分鐘 溫度 22±2ΐ 藉由上述電鍍處理，利用 銅膜之形成，相反，利用不Α促進開口内之電解鍍 以抑制電㈣之形成。又=^主要附著於銅箱部分， 當成為與銅箱大致相同之二用：解鍍銅來填充開口内’ B，故與㈣部分同樣地；口内會附著添加劑 口内完全填充有電解鍍鋼:：:：膜之形成。藉此’於開 出之電解鑛銅與銅箱(參 c大：平坦地形成自開口露 又，亦可藉由對包含銅々々 。 刻而調整厚度。視情況，，及電解電鍍膜之導體層進行蝕 物理方法而調整導二禺亦可利用砂帶研磨及拋光研磨之 屬之厚度。 3聰發明說明書(補件)/96_51侧 43 !354522Here, the reason why the second thin film layer 17 is provided is that it is difficult to obtain the electroconductive guide L 17 for forming the thickened layer as the thickened lead wire only for the i-th thin film. The thickness of the second film layer 17 is preferably in the range of 〇.1(4)~(1)(4). The reason is that when the thickness is within this range, the role of the wire can be exerted, and when the etching, the ith film layer of the lower layer is more removed: the condition is reduced, so the moisture is difficult to enter, and thus does not cause Reduced reliability: The second thin film layer 17 is thickened by electroless or electrolytic plating. The types of metals formed are recorded, copper, gold, silver, and the like. From the viewpoint of electrical characteristics, economy, strength of the interposer or structural resistance' or the conductor layer of the electric money wiring layer formed in the subsequent step, which is mainly formed of steel, it is preferably formed by electrolytic copper plating. The thickness of the thick electrolytic copper plating layer 18 is preferably 2^~", and the reason is that when the thickness is within this range, the connection with the upper via hole is reduced. Further, the phenomenon in which the bottom edge is generated during etching is reduced and the gap between the formed t-layer and the via hole is reduced by 312 XP/invention specification (supplement)/96-03/95147038 32 1J54522. After that, the shape of the wire is resisted by _, and the material is lighted and developed to make the intermediate sound: the metal of the cloth = exposed to make the remaining moment, so that the first! The intermediate layer 2G composed of a thin film layer; 2, a grading layer 17, and a thickened layer 18 is formed on the outline of the semiconductor element. In addition to the above-described method of manufacturing the interposer, an interposer may be formed after the semiconductor element is housed in the recess of the substrate, or a dry film may be formed on the metal film formed on the semiconductor element and the core substrate. In the part of the interposer, it is thickened by electric ore, and then the anti-money layer is peeled off, and the interposer is also formed on the wafer outline of the semiconductor element by using the engraving liquid. Then, an example of a method for producing a multilayer printed wiring board according to the present invention will be specifically described. A. Production of a semiconductor element storage substrate When the multilayer printed wiring board of the present invention is produced, the semiconductor element storage substrate constituting the same has the following form. A first insulating resin substrate formed by attaching a steel foil to one or both sides of an insulating resin substrate is laminated with a second insulating resin substrate. (1) The first insulating resin substrate may be formed, for example, by a double-sided copper-clad laminate, and a surface of one of the double-sided copper-clad laminates may be subjected to laser irradiation to form a copper foil and a resin insulating layer. On the other hand, the through hole forming opening and the shielding channel forming opening of the other side of the copper case are reached. At this time, the opening for forming the shield channel is formed on the outer side of the region where the semiconductor element housing recess is formed as described below, and is formed such that the adjacent openings are connected to each other. 312XJV invention manual (supplement) / 96.03/95147038 33 10^22, the above laser irradiation using a pulse vibration type carbon dioxide laser processing device, the processing conditions are preferably, pulse energy 〇 5 mJ~1〇〇mj The pulse width 1 is in the range of s to 100 s, pulse interval 〇 5 ms or more, frequency 2000 Hz to 30 〇〇 Hz, and number of transmissions 1 to 5. The diameter of the opening formed on the basis of the above processing conditions is preferably 2 〇 Jiangguang 250 #m. The reason for this is that when the aperture is in this range, the through hole 3 is technically easy and causes electrical connectivity to deteriorate. Moreover, the filling by electroplating becomes easy, and the electrical connection is reduced, and the density of wiring is easily realized. When the port 4 is less than 20 βιη, the via hole formation is technically difficult, and it is difficult to ensure electrical connectivity. On the other hand, when the diameter exceeds 250 μm, the plating/filling property is difficult, the electrical connectivity is not ensured, and the wiring density is hindered. Further, in order to form a through-hole forming opening and a shielding channel forming opening (5) by laser irradiation, a method of forming a copper-clad laminate is as follows: a direct laser method for making copper and an insulating resin base Laser irradiation by a method of simultaneously forming an opening on a material; and a conformal (c〇nf〇rmai) method in which an insulating resin base is removed by previously removing a copper foil portion corresponding to an opening for forming a via hole by etching The material is irradiated with a light beam, and the previous method can be used. (2) In order to remove the resin residue remaining in the opening formed in the above step, desmear treatment is preferably carried out. = The desmear treatment can be carried out by a leak treatment such as treatment with an acid or an oxidizing agent (such as chromic acid or permanganic acid), or by oxygen discharge at the battery 3丨2XP/invention specification (supplement)/ 96-03/95147038 Chemical, corona discharge treatment, UV-ray dry treatment. The method such as the shot processing or the excimer laser treatment can be selected according to the laser conditions of the insulating resin substrate, and the type, thickness, opening diameter, and slag amount of the desmear treatment are selected in accordance with the predicted residual rubber. (3i for the through-hole forming of the substrate after the above-mentioned material removal treatment, and the opening for forming the shielding channel on the side metal layer, performing electrolytic plating of the copper pig as the electric ore wire, and completely filling the electrolytic copper plating to The through hole is formed in the opening and the opening for forming the shielding channel, and the through hole (filling hole) and the shielding channel are formed. Further, depending on the situation, after the electrolytic copper treatment, the electrolysis will be raised on the upper part of the opening of the substrate. The copper is recorded and flattened by abrasive belt polishing, polishing, and surname cutting. (4) A money layer is formed on both surfaces of the above-mentioned first insulating resin substrate, and subjected to an exposure and development step to resist the silver layer. The forming portion is subjected to a surname treatment with a surname liquid containing copper chloride or the like. Thereafter, the anti-(4) is peeled off, whereby a conductor circuit including a through-hole solder joint is formed on one surface of the first insulating resin substrate. Positioning marks for positioning, etc., and on the other surface, a metal having a size related to the semiconductor element, a conductor circuit including a via solder joint, a positioning alignment mark, etc. are formed. The channels are formed in a mutually connected form, and one of the ends is exposed on one surface of the insulating resin substrate, and the other end is connected to the surface of the metal layer to form an electromagnetic shielding layer. (5) The metal of the first insulating resin substrate The surface of the layer forming side, 312 ΧΡ / invention specification (supplement) / 96 · 〇 3 / 95147038 35 completely filled into the opening to form a hole. Two = upper: two: electricity: after copper plating, will call light Grinding, money engraving, etc. to remove = copper, by abrasive belt grinding, throwing 'can also pass the electroless mine # electroless plating film can also use = 7 into the electric ore film. In this case, JJ uses copper Metal such as nickel or silver. Or paste to form an anti-money layer. The anti-# layer can be coated with a pre-formed film. The mask is pre-drawn with a circuit. The anti-layer layer is applied to the layer. And etching etched _ order 'light, development, forming a last name resistance into a hole containing: through the shape of the metal layer (4), attached to the protective film stripping circuit 'subsequent' to make the above step (8) The insect or liquid is preferably at least one selected from the group consisting of sulfuric acid-copper peroxide hydrogen peroxide and an aqueous solution of iron carbide. !Aqueous solution. Wen-milk: easy to form a fine pattern' can also be pre-processed on the entire surface of the copper drop surface. & 通 is a through hole bright spot that forms part of the conductor electrical i conductor circuit by etching the above copper drop Preferably, the inner diameter is substantially the same as the diameter of the through hole, or the outer scale f is larger than the diameter of the through hole, and the diameter of the solder joint is formed within a range of 5" m. The reason is 'When Tan point When the diameter is within this range, the connection between the through hole and the solder joint is impeded, and the case where the density is hindered is also reduced. (10) Then, the side opposite to the metal layer setting surface of the first insulating wax substrate is 312XP/ Inventive specification (supplement)/96-03/95147038 37 and the opening element storage area), for example, laser processing through the tree wax layer and reaching the opening of the surface of the metal layer, and the concave portion of the surface of the metal layer is formed from the opening 'The semiconductor element storage base is formed by this: = It is also possible to form a concave portion in which the metal layer is exposed by the anti-(four) forming step and the (iv) processing step. For example, on the first insulating resin substrate and the second insulating resin substrate, a laser irradiation type carbon dioxide laser processing device is used to perform laser irradiation, thereby forming a surface from the first insulating resin substrate. The resin layer is penetrated to reach the opening σ of the surface of the metal layer, thereby forming a recess in which the semiconductor element is housed or housed. Preferably, the processing condition for accommodating the concave portion of the semiconductor element is such that the pulse energy pulse width is 1 to 1 〇〇 #s, the pulse interval 〇 5 ms or more, the frequency is 2 〇〇〇 Hz to 3 Hz, and the impact is small. In the range of the laser processing, the recessed portion in which the semiconductor element is housed is formed, and a metal layer is exposed on the bottom surface of the recessed portion (in this case, the copper foil is used. B. Storage of the semiconductor element _, buried (11) The semiconductor element is embedded in the semiconductor element housing substrate obtained in the steps (1) to (10) of the above A. The buried semiconductor element can be used in advance on the connection pad as described above. A semiconductor element in which a columnar electrode is formed, or a semiconductor element in which an interposer covering a pad is formed, and the case where the latter is used will be described. The interposer is for the pad of the semiconductor element and the printed wiring 312XP/ SUMMARY OF THE INVENTION (Reply)/96-03/95147038 38 1354522 The interposer layer of the via hole of the board is directly connected and provided by the film layer on the wafer pad, and further disposed on the thin layer It is formed by thickening a layer, preferably formed of at least two or more metal layers. Further, the interposer is preferably formed to have a size larger than that of the wafer of the semiconductor element. The positional alignment with the wafer pad is easy, and as a result, the electrical connection with the wafer pad is improved, and laser irradiation or light-filled through-hole processing can be utilized without making the wafer lining Therefore, the semiconductor element can be reliably embedded in the printed wiring board or reliably electrically connected to the printed wiring board. Further, on the interposer, the metal constituting the conductor circuit of the printed wiring board can be directly formed. Further, in addition to the above-described manufacturing method, the interposer may be formed on the entire surface of the connection pad side of the semiconductor element or on the metal film formed on the semiconductor element storage substrate in which the semiconductor element is embedded. A resist layer made of a dry film is formed, and a portion corresponding to the interposer is removed, and then thickened by plating φ, and then the resist layer is removed, and the interposer is formed by an etching solution. (12) After the insulating resin layer is provided on the substrate on which the semiconductor element is housed and stored, the same processing as (1) to (4) of the above A is performed, whereby: a through hole electrically connected to the interposer formed on the connection pad of the built-in semiconductor device; a via hole electrically connected to the conductor circuit including the via hole formed in the substrate for accommodating the semiconductor element; and a conductor circuit on the outer side More progress' The insulating resin layer and the copper-clad layer are laminated, and the same processing as (1) to (4) in the above a is repeated, whereby the multilayer printing 39 312xp/mmmmmmm/96-〇3/ can be further obtained. 95 moss 1354522 wiring board. The above method is to laminate the insulating resin layer one by one to make the insulating resin layer more. The 'insulating resin layer can also be 'on' on the circuit board of the unit and then added (four) Thereby, a multilayer printed wiring board in which an insulating tree is layered is formed. • (13) The surface of the outermost substrate is then divided into four layers. In this case, a resist composition is applied to the entire outer surface of the circuit board, and after the coating film is dried, the first cover film on which the opening of the solder crucible is drawn is placed on the coating film to be exposed and developed. Thereby, the solder exposed to the conductive lining portion directly above the through hole of the conductor circuit is formed, and the dried solder resist layer can be attached to the solder layer by exposure, development or laser processing. Opening. = On the material lining exposed from the non-formed portion of the above-mentioned layer, a resistance such as recording gold is formed (4). At this time, the thickness of the gold layer is preferably i port ~7 _, and the thickness of the gold layer is preferably 0.01 ym to 0 1 am. » In addition to this, nickel-palladium-gold, gold (single layer), silver (single layer), and the like can be formed. After the formation of the resistance layer, the mask layer is peeled off. Thereby, a printed wiring board in which a solder pad having a corrosion-resistant layer and a solder pad having no corrosion-resistant layer are formed are mixed. (14) from the opening of the solder resist obtained in the above step (13), supplying the solder body to the solder pad portion exposed directly above the via hole, and forming a solder bump by melting and solidifying the solder body, or A conductive ball or a conductive pin is bonded to the pad portion using a conductive adhesive or a solder layer to form a multilayer circuit substrate. 312XP/Invention Manual (Supplement)/96-03/95147038 40 1354522 (3) The electrolytic copper plating film is formed in the opening for forming a through hole provided with the first insulating substrate 3〇 after the completion of the gelation treatment. 36 and the copper foil surface of the opening for forming the shield channel 37 were subjected to electrolytic copper recording treatment using a steel foil as a plating wire under the following plating conditions. [electrolytic plating solution] 2.24 mol/1 〇·26 mol/l HO ml/1 1〇.0 ml/1 copper sulfate sulfate additive A (reaction accelerator) additive B (reaction inhibitor) [electrolytic plating conditions] The time is 65 minutes and the temperature is 22 ± 2 ΐ. By the above plating treatment, the formation of a copper film is utilized, and conversely, electrolytic plating in the opening is promoted to suppress the formation of electricity (4). Also =^ mainly attached to the copper box part, when it is almost the same as the copper box: de-plating copper to fill the opening 'B, so the same as (4) part; the inside of the mouth will be filled with additives filled with electrolytically plated steel: ::: Formation of the film. By means of the electrolytic copper and copper boxes that are opened out (see c large: flatly formed from the open dew, but also by the inclusion of copper crucible. The thickness is adjusted. As the case may be, and the electrolytic plating film The conductive layer is etched by physical methods and the conductive guide can also be adjusted by the thickness of the abrasive belt grinding and polishing. 3 Cong invention manual (supplement) / 96_51 side 43 !354522

⑷導體電路（包含填孔）、屏蔽通道及金屬層之形成 :經過上述步驟⑻後之第一絕緣性基材3〇之銅箱^ 一5鑛膜上’使用感純乾膜而形成㈣抗㈣層（省略 =二即’於第一絕緣性基材30之雙面之銅笛面上形成 =刻Μ劑層。該抗银層之厚度為15㈣〜2〇 "之範 上形成抗银層非形成部 圍’使ms包含焊點之導體電路以及尺寸與半導體元 件之尺寸相關之金屬層的遮罩，經過曝光、顯像，於銅落(4) The formation of the conductor circuit (including the filling hole), the shielding channel and the metal layer: after the above step (8), the first insulating substrate 3 is formed on the copper film of the metal film, and the film is formed by using a pure dry film. (4) Layer (omit = two is 'formed on the copper flute on both sides of the first insulating substrate 30 = engraved layer. The thickness of the anti-silver layer is 15 (four) ~ 2 〇 " The layer non-formed portion encloses a conductor circuit including a solder joint of ms and a mask of a metal layer having a size related to the size of the semiconductor element, after exposure and development, in copper

，繼而1用由魏水/硫酸所才冓成之蝕刻液對抗蝕層非 」成β進行㈣〗，去除相當於非形成部之銅電鐘膜以及銅 其後，利用鹼液來剝離抗蝕層，藉此形成包含填孔39 之焊點的導體電路4卜金屬層42、以及屏蔽通道47。可 視需要而形成空白圖案、或者對準標記、產品識別標記等。 再者，於該步驟中，複數個屏蔽通道47成為如圖lu) 修所示之串列連結之形態，連接於金屬層42之表面而形成 電磁屏蔽層。 藉此而獲得下述電路基板，即，於第一絕緣性基材3〇 之表面與背面形成有導體電路41，並且形成有與該等導 體電路41電性連接之填孔39，更進一步形成有與半導體 元件接觸之金屬層42,繼而形成與金屬層42之表面連接 而構成電磁屏蔽層之屏蔽通道47。 再者’形成於該電路基板上之金屬層42於第一絕緣性 基材之背面形成，與收納有半導體元件之凹部之形成區域 312XP/發明說明書(補件)/96·〇3/95147〇3s 44 1354522 相當的電路基板表面之銅箔部分藉由蝕刻而去除（參照圖 5(d)) 〇 .(5)第一絕緣性基材與第二絕緣性基材之積層 ' 積層於上述第一絕緣性基材30之第二絕緣性基材40使 用單面覆銅積層板，該單面覆銅積層板係於厚度為6〇 之樹脂絕緣層43之單面上貼附厚度為15 之銅箔44 而形成。 • 上述第二絕緣性基材40以未形成有銅箔之側之表面與 第一絕緣性基材30之形成有金屬層42之表面接觸的狀態 而積層。第一絕緣性基材30與第二絕緣性基材4〇以如下 條件將兩者熱壓合而進行積層（參照圖5(e))。 (壓合條件） 溫度：15〇r 〜180°c 壓製壓力：100 kgf/cm2 〜200 kgf/cm2 壓合時間：5分鐘〜1 〇分鐘 »再者，於該實施财，可使第—絕緣性基材3g及第二 絶緣性基材40形成為單層，亦可形成為2層以上之複數 (6)通孔形成用開口之形成 對上述第二絕緣性基材4G之鋼g形成面進行二氧化 46貝她“4,並且通過樹脂絕緣層43而到達設置 ^上述第-絕緣性基材30的包含填孔39之通 ^ 體電路41之表面（參照圖5(f))。 坪”的導 }更進一步，利用過錳酸 312χΡ/發明說明書(補件)/96-03/95147038 45 丄 丄 之 藥液處理對料開Π内進行 於該實施例t，為了扒笛Then, using an etching solution formed by Weishui/sulfuric acid, the resist layer is not subjected to β (four), the copper electric clock film corresponding to the non-formed portion and copper are removed, and then the resist is removed by using an alkali solution. The layer thereby forms a conductor circuit 4 including a solder joint of the filling hole 39, and a shielded via 47. A blank pattern, or an alignment mark, a product identification mark, or the like can be formed as needed. Further, in this step, a plurality of shield channels 47 are connected in series as shown in Fig. 5), and are connected to the surface of the metal layer 42 to form an electromagnetic shielding layer. Thereby, the following circuit substrate is obtained, that is, the conductor circuit 41 is formed on the front surface and the back surface of the first insulating base material 3, and the filling hole 39 electrically connected to the conductor circuit 41 is formed, and further formed. There is a metal layer 42 in contact with the semiconductor element, which in turn forms a shield via 47 which is connected to the surface of the metal layer 42 to form an electromagnetic shielding layer. Further, the metal layer 42 formed on the circuit board is formed on the back surface of the first insulating substrate, and the formation region 312XP of the recess in which the semiconductor element is housed (invention)/96·〇3/95147〇 3s 44 1354522 The copper foil portion on the surface of the circuit board is removed by etching (see FIG. 5(d)). (5) The first insulating substrate and the second insulating substrate are laminated. The second insulating substrate 40 of an insulating substrate 30 is a single-sided copper-clad laminate which is attached to a single surface of a resin insulating layer 43 having a thickness of 6 Å to have a thickness of 15 The copper foil 44 is formed. The second insulating base material 40 is laminated in a state in which the surface on the side where the copper foil is not formed is in contact with the surface of the first insulating base material 30 on which the metal layer 42 is formed. The first insulating base material 30 and the second insulating base material 4 are laminated by thermocompression bonding under the following conditions (see Fig. 5(e)). (Compression condition) Temperature: 15〇r ~180°c Pressing pressure: 100 kgf/cm2 ~200 kgf/cm2 Pressing time: 5 minutes~1 〇 minutes » Again, in this implementation, the first insulation can be made The base material 3g and the second insulating base material 40 are formed as a single layer, or may be formed in a plurality of two or more layers. (6) Formation of a through hole forming opening to form a steel g forming surface of the second insulating base material 4G The surface of the semiconductor circuit 41 including the filling holes 39 of the first insulating substrate 30 is formed by the resin insulating layer 43 (see FIG. 5(f)). Further, the use of permanganic acid 312 χΡ / invention instructions (supplement) / 96-03/95147038 45 药 药 药 药 药 药 96 96 96 96 96 96 96 该 该 该 该 该 该 该 该 扒

m时 T # 了於第二絕緣性基材40上形成通孔 46 ’而使用HITACHI VIA公司製造之高峰值 衝振動型一氧化碳雷射加工機。對貼附於第二絕緣性 基材I之基材厚度為6G心之玻璃布環氧樹脂基材43 銅4 44以如下照射條件直接照射雷射光束，以1 μ 孔/心之速度而形成直徑75以m之通孔形成用開口 46。When m is used, a through hole 46' is formed in the second insulating substrate 40, and a high peak shock type carbon monoxide laser processing machine manufactured by HITACHI VIA Co., Ltd. is used. The glass cloth epoxy resin substrate 43 to which the substrate of the second insulating substrate I is attached has a thickness of 6 G. The copper 4 44 directly irradiates the laser beam with the following irradiation conditions, and is formed at a speed of 1 μ hole/heart. A through hole forming opening 46 having a diameter of 75 m.

(照射條件） 脈衝能：0.5 mJ〜1〇〇 mj 脈衝寬度：1 〜1〇〇 As 脈衝間隔：0. 7 ms 頻率：2000 Hz (7)電解鍍銅膜之形成 於上述第一絕緣性基材30之表面貼附保護薄膜48而將 其覆蓋之後，使用如下組成之電鍍液溶液，對開口内除膠 鲁〉查處理結束後之第二絕緣性基材4 0之銅箔面實施將銅箱 作為電锻導線之電解鑛銅處理。 [電鍍液] 硫酸 2. 24 mol/1 硫酸銅 0· 26 mol /1 添加劑A(反應促進劑） 11.0 ml/1 添加劑B(反應抑制劑） 10.0 ml/1 [電解電鍍條件] 電流密度 1 A/dm2 312XP/發明說明書(補件)/96·〇3/95147038 46 時間 65分鐘 溫度 22±2°c 於上述電鍍處理中， 銅膜之形成，相反，利^ :劑A促進開口内之電解鍍 以抑制電鍍膜之形成* ^ B主要附著於㈣部分， 為與銅箱大致相同電解鑛銅填充開口内，當成 舆銅荡部分同樣地抑添加劑b，故 王真充有電解鍍銅，並且 内疋 解錢銅與銅領。 致仪地形成自開口露出之電 又亦可藉由對由包含銅落及 ::::r度，況，亦可利用砂帶研 之物理方法而調整導體層之厚度。 疋唧厲 (8)導體電路及填孔之形成(Irradiation condition) Pulse energy: 0.5 mJ to 1 〇〇 mj Pulse width: 1 to 1 〇〇 As Pulse interval: 0. 7 ms Frequency: 2000 Hz (7) Electrolytic copper plating film is formed on the above first insulating base After the protective film 48 is attached to the surface of the material 30 and covered with the plating solution, the copper foil surface of the second insulating substrate 40 after the completion of the treatment in the opening is subjected to copper. The box is treated as electrolytic ore copper of the electric forged wire. [Plating solution] Sulfuric acid 2. 24 mol/1 Copper sulfate 0· 26 mol /1 Additive A (reaction accelerator) 11.0 ml/1 Additive B (reaction inhibitor) 10.0 ml/1 [Electroplating conditions] Current density 1 A /dm2 312XP/Invention Manual (Supplement)/96·〇3/95147038 46 Time 65 minutes Temperature 22±2°c In the above plating treatment, the formation of the copper film, on the contrary, the agent A promotes the electrolysis in the opening Plating to suppress the formation of the plating film * ^ B is mainly attached to the (four) part, which is substantially the same as the copper box filled in the electrolytic copper filling opening, and when the copper is turned into the same portion to suppress the additive b, the king is filled with electrolytic copper plating, and the inner sputum Solve the copper and copper collar. The thickness of the conductor layer can be adjusted by the physical method including the copper drop and the ::::r degree, and the abrasive tape can also be used.疋唧 (8) Conductor circuit and the formation of holes

及=過±34步驟⑺後之第二絕緣性基材4(3之銅箱44 一；’又上’使用感光性乾膜而形成蝕刻抗蝕劑層(省略圖 亥抗I虫層之厚度為15……之範圍，使用描 金匕含填孔之焊點之導體電路的遮罩，經過曝光、顯 於銅沾上形成抗银層非形成部。 遒而’利用由雙氧水/硫酸所構成之钮刻液對抗餘層非 j成部進行蝕刻，去除相當於非形成部之銅電鍍膜以及 箔。 其後，利用鹼液來剝離抗蝕層，更進一步，使於上述步 驟（7)中貼附於第一絕緣性基材3〇之表面之保護薄膜 亲J離，藉此而於第二絕緣性基材之單面形成導體電路 312XP/發明說明書(補件)/96-03/95147038 47 1354522 基本均勻，四角之形狀未成為圓弧狀。 (10)具有柱狀電極之半導體元件之收納 ' 於依照上述步驟（1)〜（9)而製作之半導體元件收納用 Γ基板之凹部54收納、内藏之半導體元件55，使用由下述 步驟（a)〜（d)所製作之具有柱狀電極之半導體元件。 (a)矽基板之準備 進订下述準備：於晶圓狀態之矽基板（半導體基板）上形 鲁成連接襯墊，於其上表面之連接襯墊的中央部去除之部分 形成保護膜（鈍化膜）’並且使連接襯墊之中央部經由形成 於保護膜之開口部而露出。 (b) 基礎金屬層之形成 於矽基板之整個上表面，利用濺鍍而形成由厚度為2 /zm之銅構成之基礎金屬層。 (c) 柱狀電極之形成 繼而，對基礎金屬層之上表面由丙烯酸系樹脂等感光性 籲樹脂所構成之乾膜抗蝕層進行層壓，形成厚度為11〇 之電鍍抗蝕層。將應形成之柱狀電極之高度設定為ι〇〇 β m A 右。 其··人，使用於對應電鑛抗餘層之襯墊之部分描繪有開口 之遮罩，經過曝光、顯像，於抗蝕層上形成開口^。幵 更進一步，將基礎金屬層作為電鍍電流路徑進行電解鍍 銅，藉此而於電鍍抗蝕層之開口部内的基礎銅層之上表面 形成由銅構成之柱狀電極。 最後，剝離電鍍抗蝕層，將柱狀電極作為遮罩而蝕刻上 312ΧΡ/發明說明書(補件)/96-03/95147038 1354522 述土礎金屬層之多餘部分以將其去除，僅於柱狀電極下方 殘存有基礎金屬層。 *. (d)密封膜之形成 - 於上述（c)中所獲得之矽基板之上表面側形成由環氧樹 脂或聚醯亞胺等構成之絕緣樹脂即密封膜。於該狀態，當 •柱狀電極之上表面由密封膜覆蓋時，因表面之適宜研磨而 使柱狀電極之上表面露出。 φ 繼而，利用切割步驟而獲得各個半導體晶片（半導體裝 置）。此時，具有柱狀電極之半導體元件之厚度形成為100 私m。 對由上述步驟（a)〜（d)所製作之半導體元件55之下表 面侧施以熱硬化型黏著劑，該熱硬化型黏著劑之一例為， 由使環氧樹脂之一部分丙烯基化後的熱硬化型樹脂所構 成之黏著钟]，由此形成厚度為3〇 #m〜5〇以爪之黏著劑 層5 6。 • 其後，收納於半導體元件收納用基板之凹部54之後， 於100度〜20G度之間進行熱處理，使黏著劑層56硬化。 藉此，獲得内藏有半導體元件55之基板60(參照圖6(b))。 此時，半導體元件之柱狀電極58之前端與基板之上表 面處於大致同一面上。即，半導體元件55未傾斜。 01)積層步驟 於上述（10)所獲得之基板60上隔著預浸體等之黏著材 * 層62’於其上積層下述早面覆銅積層板，即，於厚度為 60 # m之樹脂絕緣層64之單面上貼附厚度為15 # m之 312XP/發明說明書(補件)/96-03/95147038 50 1354522 銅4 66所形成之單面覆銅積層板（參照圖，以如下 條件於箭頭方向進行加熱壓製而使其多層化（參照圖 6(d))。 (壓製條件）And = 2 after the step (7) of the second insulating substrate 4 (3 of the copper box 44; 'again' using a photosensitive dry film to form an etch resist layer (omitting the thickness of the Tuhai anti-I insect layer For the range of 15..., the mask of the conductor circuit containing the solder joints of the filled holes is exposed, and the copper is adhered to form a non-forming portion of the anti-silver layer. 遒 ' 'Used by hydrogen peroxide / sulfuric acid The button engraving is etched against the non-j portion of the remaining layer, and the copper plating film and the foil corresponding to the non-formed portion are removed. Thereafter, the resist layer is peeled off by the alkali solution, and further, the paste is applied in the above step (7). The protective film attached to the surface of the first insulating substrate 3 is separated, thereby forming a conductor circuit 312XP on one side of the second insulating substrate/invention specification (supplement)/96-03/95147038 47 1354522 is substantially uniform, and the shape of the four corners is not in the shape of an arc. (10) The storage of the semiconductor element having the columnar electrode is accommodated in the recessed portion 54 of the substrate for accommodating the semiconductor element prepared in accordance with the above steps (1) to (9). The built-in semiconductor component 55 is manufactured by the following steps (a) to (d) A semiconductor element having a columnar electrode. (a) Preparation of a germanium substrate The following preparations are made for forming a connection pad on a substrate (semiconductor substrate) in a wafer state, and a pad on the upper surface thereof. The portion removed at the central portion forms a protective film (passivation film)' and the central portion of the connection pad is exposed through the opening formed in the protective film. (b) The base metal layer is formed on the entire upper surface of the substrate, using a splash Plating to form a base metal layer composed of copper having a thickness of 2 /zm. (c) Formation of a columnar electrode, followed by dry film resisting of a surface of the base metal layer made of a photosensitive resin such as an acrylic resin The layer is laminated to form an electroplated resist layer having a thickness of 11 Å. The height of the columnar electrode to be formed is set to ι 〇〇 β m A. The person is used for the lining of the corresponding anti-corrosion layer of the electric mine. A part of the pad is patterned with an opening, and an opening is formed on the resist layer after exposure and development. Further, the base metal layer is electrolytically plated as a plating current path, thereby plating the resist layer. Opening A columnar electrode made of copper is formed on the upper surface of the base copper layer. Finally, the plating resist is peeled off, and the columnar electrode is etched as a mask. 312 ΧΡ / invention specification (supplement) / 96-03/95147038 1354522 The excess portion of the earth metal layer is removed to remove the base metal layer only under the columnar electrode. *. (d) Formation of the sealing film - formed on the upper surface side of the substrate obtained in the above (c) An insulating resin composed of an epoxy resin or a polyimide, that is, a sealing film. In this state, when the upper surface of the columnar electrode is covered by the sealing film, the upper surface of the columnar electrode is exposed due to the appropriate grinding of the surface. φ Then, each semiconductor wafer (semiconductor device) is obtained by a dicing step. At this time, the thickness of the semiconductor element having the columnar electrode is formed to be 100 m. A thermosetting adhesive is applied to the lower surface side of the semiconductor element 55 produced by the above steps (a) to (d), and one example of the thermosetting adhesive is obtained by activating a part of the epoxy resin An adhesive clock composed of a thermosetting resin, thereby forming an adhesive layer 56 having a thickness of 3 Å #m to 5 〇. Then, after being stored in the recessed portion 54 of the semiconductor element housing substrate, heat treatment is performed between 100 degrees and 20 G degrees to cure the adhesive layer 56. Thereby, the substrate 60 in which the semiconductor element 55 is housed is obtained (see FIG. 6(b)). At this time, the front end of the columnar electrode 58 of the semiconductor element is substantially flush with the upper surface of the substrate. That is, the semiconductor element 55 is not inclined. 01) Laminating step The following surface copper-clad laminate is laminated on the substrate 60 obtained in the above (10) via a bonding material* layer 62' of a prepreg or the like, that is, a thickness of 60 #m. A single-sided copper-clad laminate formed by a thickness of 15 # m 312XP/invention specification (supplement)/96-03/95147038 50 1354522 copper 4 66 is attached to one surface of the resin insulating layer 64 (refer to the figure, as follows) The conditions are heated and pressed in the direction of the arrow to make it multilayer (see Fig. 6 (d)).

溫度：8(TC 〜25(TC 壓力：1.0 kgf/cm2 〜5.0 kgf/cm2 壓I時間.10分鐘〜60分鐘 (12 )通孔形成用開口之形成 以與上述步驟⑻相同之方式，形成通孔形成用開口 7〇 及72，該通孔形成用開口 70及72貫通銅笛66,並且通 脂絕緣層64 ’分別到達包含形成半導體S件收納用 土反之第、，€緣性基材上所形成之通孔谭點的導體電路 w :乂及於半導體兀件上之襯墊上所設置之柱狀電極 (參照圖7(a))°此時之雷射照射條件與上述步驟⑻相 同。更進一步對該等開口内利用 膠渣處理。 ㈣用過猛酉夂之樂液處理進行除 (13)電解鍍銅膜之形成 成==_處理結束後之銅箱面上，使用如下組 =電解錢銅溶液，實施將銅落作為電鑛導線之電解錢銅 [電鍍液] 2.24 m〇l/i 0.26 mol/1 10.0 ml/i 硫酸 硫酸銅 添加劑A (反應促進劑） 312XP/發明說明書(補件)/96-03/95147038 添加劑B(反應抑制劑） [電解電鍍條件] 10.0 ml/1Temperature: 8 (TC ～ 25 (TC pressure: 1.0 kgf/cm 2 〜 5.0 kgf/cm 2 pressure I time. 10 minutes to 60 minutes (12 ) formation of a through hole forming opening in the same manner as the above step (8), forming a pass Hole forming openings 7 and 72, the through hole forming openings 70 and 72 are passed through the copper flute 66, and the grease insulating layer 64' respectively reaches the inclusion of the semiconductor S piece to accommodate the soil, and vice versa. The conductor circuit w of the formed via hole is formed by a columnar electrode provided on the spacer on the semiconductor element (see FIG. 7(a)). The laser irradiation condition at this time is the same as the above step (8). Further, the slag is treated in the openings. (4) The process of removing the (13) electrolytic copper plating film by the treatment of the mammoth liquid is made ==_ on the copper box surface after the treatment, the following group is used = Electrolytic copper solution, electrolyzed copper as electroplating wire for electroplating copper [electroplating solution] 2.24 m〇l/i 0.26 mol/1 10.0 ml/i copper sulfate sulfate additive A (reaction accelerator) 312XP/invention manual ( Supplement)/96-03/95147038 Additive B (Reaction Inhibitor) [Electroplating Conditions] 10.0 ml/1

電流密度 時間 溫度Current density time temperature

1 A/dm2 65分鐘 22±2°C 鋼膜之：：鑛中利用添加劑A促進開口内之電解鑛 ' ^ ，目反，利用添加劑B主要附著於銅箔部分，1 A/dm2 65 minutes 22±2°C Steel film:: Use of additive A in the ore to promote the electrolytic ore in the opening ' ^ , the reverse, using additive B mainly attached to the copper foil part,

P制電鍍膜之形成。x，利用電解鍍銅來填充開口内， 田成為與㈣大致相同之高度時，開口内會附著添 B ’故與㈣部分同樣地抑制鍍膜之形成。藉此，於開口 内完全填充有電解鑛銅，並且大致平坦地形成自開口 之電解鍍銅與銅箱。 又亦可藉由對包含銅箔及電解電鍍臈之導體層進行蝕 d而調整厚度。視情況，亦可利用砂帶研磨及拋光研磨之 物理方法而調整導體層之厚度。 猎此，於開口内完全填充有電解鍍銅，形成將連接導體 電路之通孔與半導體元件之主體相連接之通孔。 (14)導體電路之形成 於、左過上述步驟（〗3 )後之銅箱及銅鐘上，使用感光性乾 膜j形成蝕刻抗蝕劑層。該抗蝕層之厚度為i5 #m〜2〇 之圍’❹描繪有包含填孔之焊點之導體電路的遮罩， 經過曝光、顯像，於銅箔上形成抗蝕層非形成部。 繼而’利用由雙氧水/硫酸所構成之蝕刻液 形成部進行蝕刻，去除相當於非形成部之鋼電鍍膜以及銅 312XP/發明說明書(補件)/96__5147〇38 52 1354522 箔。 j置利用驗液來剝離抗姓層，藉此於覆蓋半導體元件 收、内用基板而設置之樹脂絕緣層64上形成導體電路Μ， 形成填孔76及填孔78，該填孔76將該導體電 ^又置於半導體元件内藏基板60之填孔之焊點41 (連接，上述填孔78與設置於半導體元件55之襯墊上 ==58電性連接。再者，視需要，亦可形成空白 圖案或者對準標記、產品識別標記等。 更進-步視需要，亦可藉由重複上述步驟（⑴〜（⑷ 而獲得更多層化之印刷佈線板。 再者’於上述積層化中’可以通孔之朝向為同一方向之 方式而積層，亦可以通孔之朝向為相反方向之方式而積 層。又，亦可藉由該等以外之組合而實現多層化。 (15 )阻烊劑層之形成 於位於由上述步驟⑴〜（⑷所得之多層域板之最上 層及最下層的電路基板之表面，形成阻焊劑層⑽。貼附 薄膜化阻焊劑，或者利用預先有調整黏度之清漆進行塗 佈，藉此於基板上形成厚度為2〇〜3〇㈣之阻焊劑層8〇。 繼而，於7代下進行2G分鐘乾燥處理，再於1〇代下 進行30分鐘乾燥處理’之後，使藉由鉻層而指繪有阻焊 劑開口部之圓形圖案（遮罩圖案）的厚5襲之納轉玻璃基 板之鉻層形成側與阻焊劑層密接，於1〇〇〇 mj/ciQ2之紫= 線下進行曝光、DMTG顯像處理。更進一步，以12〇艺下！ 小時之條件及15(TC下3小時之條件進行加熱處理，形成 312XP/發明說明書(補件)勝03/95147038 52 1354522 具有對應於襯墊部分 焊劑層80(厚度為20 之開口 82(開口直徑為2〇〇 # m) » V m)的阻The formation of a P plating film. x, when the inside of the opening is filled by electrolytic copper plating, when the field is substantially the same height as (4), the addition of B in the opening causes the formation of the plating film to be suppressed in the same manner as the portion (4). Thereby, electrolytic copper ore is completely filled in the opening, and electrolytic copper plating and a copper tank which are self-opening are formed substantially flat. Alternatively, the thickness can be adjusted by etching the conductor layer containing the copper foil and the electrolytically plated crucible. The thickness of the conductor layer may also be adjusted by physical means of abrasive belt polishing and polishing, as the case may be. In this case, electrolytic copper plating is completely filled in the opening to form a through hole for connecting the through hole of the connecting conductor circuit to the main body of the semiconductor element. (14) Formation of Conductor Circuit An etch resist layer is formed on the copper case and the copper bell which has been left by the above step (Fig. 3) using the photosensitive dry film j. The resist layer has a thickness of i5 #m 2 〇 ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Then, etching was performed by using an etching liquid forming portion composed of hydrogen peroxide/sulfuric acid to remove a steel plating film corresponding to the non-formed portion and a copper 312XP/invention specification (supplement)/96__5147〇38 52 1354522 foil. J is used to peel off the anti-surname layer by using the test liquid, thereby forming a conductor circuit 上 on the resin insulating layer 64 provided to cover the semiconductor element receiving and inner substrate, thereby forming a filling hole 76 and a filling hole 78, which will The conductors are further placed in the pads 41 of the semiconductor device built-in substrate 60 (connections, and the holes 78 are electrically connected to the pads provided on the semiconductor device 55 ==58. Further, if necessary, Blank patterns or alignment marks, product identification marks, etc. may be formed. Further steps may be performed by repeating the above steps ((1) to ((4) to obtain more layered printed wiring boards. In the middle of the process, the through holes may be stacked in the same direction, or the through holes may be stacked in the opposite direction. Alternatively, the layers may be multilayered. The enamel layer is formed on the surface of the circuit board located at the uppermost layer and the lowermost layer of the multilayered domain plate obtained in the above steps (1) to ((4), and the solder resist layer (10) is formed. The thin film solder resist is attached, or the viscosity is adjusted in advance. Varnish for varnish Thus, a solder resist layer 8〇 having a thickness of 2 〇 3 〇 (4) is formed on the substrate. Then, 2G minutes of drying treatment is performed in 7th generation, and drying is performed for 30 minutes in 1 〇 generation. The chrome layer is indicated by the circular pattern (mask pattern) of the opening of the solder resist. The chrome layer forming side of the glass substrate is closely adhered to the solder resist layer, and is purple at 1〇〇〇mj/ciQ2. = Under-line exposure, DMTG imaging processing. Further, heat treatment is carried out under the conditions of 12 !! hours and 15 (3 hours under TC to form 312XP/invention manual (supplement) win 03/95147038 52 1354522 has a resistance corresponding to the pad portion of the solder layer 80 (opening 82 of thickness 20 (opening diameter is 2〇〇# m) » V m)

’於位於多層化基板之最上層及最下層的電路基板 :面形成阻烊劑層之前，亦可視需要而設置粗化層。 :該情況下，於阻谭劑層上形成由感光性樹脂所“之 二乾膜狀之遮罩層。貼附薄麻之料層，或者利用預 調整黏度之清漆進行塗佈，藉此於阻焊劑層上形成厚 又1 〇 # m〜2 0 # m之遮罩層。 其:人’於8(TC下進行30分鐘之乾燥處理後，使藉由絡 :而描繪有遮罩層形成圖案（遮罩圖案）的厚5職之_ 玻璃基板之鉻層形成側與阻焊劑層密接，於8〇〇 mj/cm2 之紫外線下進行曝光、DMTG顯像處理。更進一步以UOt 下1小時之條件進行加熱處理，形成阻焊㈣（厚 Am)。 ’ (16)耐餘層之形成 繼而，將形成阻谭劑層80之基板浸潰於包含氯化錄3〇 g/卜次磷酸鈉10 g/ι、檸檬酸鈉1〇 g/1之pH=5之無 電解鍍錄液中2G分鐘，於開σ部形成厚度為5 "之錄 鍛層。 更進-步，將該基板於包含氰化金鉀2g/1、氯化錄Μ g/卜檸檬酸鈉50 g/Ι、次磷酸鈉1〇 g/1之無電解鍍金 液中，於93eC之條件下浸潰23秒鐘，於㈣層上形成厚 度為0. 03 "之金㈣，並且形成由騎層及金鍍層所 構成之覆蓋金屬層（省略圖示）。 312XP/發明說明書(補件)/96-03/95147038 54 (17)谭錫層之形成 繼而’對自最上声 的開口 82所露出^捏级.夕S電路基板之阻焊劑層80 Sn/Pb焊錫或者由ς 襯墊，印刷熔點約為183t：之 谭，形成焊t84祕構成之焊鎮膏，於聰下迴 (實施例1~ 2 ) 將以下步驟(a)〜(c)所製作之 件55埋入至丰崑騁_从 、啕1P "層之+導體兀 n眷 兀牛收納用基板之凹部42，除此之外 進行與實施例1 —丨相π m Α ^除此之外 (a)於連接福執D處製造多層印刷佈線板。 laj於運接襯塾及佈線 ± , ^ 平上办成有保濩膜之半導體元件 =而遍及整個面’使厚度為〇 ι…鉻薄膜及 ；旱度為〇.5em之銅薄膜層& 价古 、 連續地形成。 ㈣膜層此2層，於真空腔室内 =其入後爲使利用乾膜之抗钱層形成於薄膜層上。將描繪 有中，丨層形成部分之遮罩載置於該抗蝕層上，經過曝光、 顯像而形成抗姓層非形成部。實施電解鑛銅’於抗姓 形成部设置厚度為9❹之加厚層（電解鑛銅膜）。 (c)利用驗溶液等去除電鑛抗钮層之後，藉由钮刻液而去 除電鍍抗餘層下之金屬膜，由此而於半導體元件之襯塾上 形成中介層。 藉此，獲得長5 mmx寬5 mm、厚度100 之半導體元 件。 (實施例1 — 3) 將屏蔽通道形成為如圖1(c)所示之錯開排列（千鳥排 312XP/發明說明書(補件)/96-03/95147038 1354522 相同之處理，製造多層 列）’除此之外進行與實施例 印刷佈線板。 (實施例1一4) 將屏蔽通道形成為如圖一 0 ^ S〗（c)所不之錯開排列（千鳥排 列）’且將具有中）丨層之半導體^ 55埋人至半導體元件 收：用基板之凹部42，除此之外進行與實施例二相同牛 之處理，製造多層印刷佈線板。 (實施例2— 1) 於實施例1-1之上述步驟（9)中，藉由如下之雷射照射 條件，於半導體元件收納用凹部之側㈣成Μ度之推拔 形’除此之外進行與實施例卜i相同之處 印刷佈線板。 衣仏夕層 (照射條件）Before the circuit substrate on the uppermost layer and the lowermost layer of the multilayered substrate is formed on the surface of the multilayered substrate, a roughened layer may be provided as needed. In this case, a mask layer of a two-thick film formed of a photosensitive resin is formed on the resist layer, and a layer of thin hemp is attached or coated with a pre-adjusted viscosity varnish. A mask layer having a thickness of 1 〇#m~2 0 #m is formed on the solder resist layer. It is formed by a person's drying process after 8 minutes at TC for 30 minutes. The thickness of the pattern (mask pattern) is 5 _ The chrome layer forming side of the glass substrate is in close contact with the solder resist layer, and exposure is performed under ultraviolet light of 8 〇〇mj/cm 2 , and DMTG development processing is performed. Further, UOt is performed for 1 hour. The conditions are heat-treated to form a solder resist (4) (thickness Am). ' (16) Formation of a residual layer, and then the substrate on which the resist layer 80 is formed is immersed in a chloride containing 3 〇g/picophosphoric acid 10 g / ι, sodium citrate 1 〇 g / 1 pH = 5 in the electroless plating liquid 2G minutes, forming a thickness of 5 " in the opening σ part of the forging layer. Further step, the substrate It is impregnated for 23 seconds at 93eC in an electroless gold plating solution containing potassium cyanide 2g/1, chlorinated ruthenium g/sodium citrate 50 g/Ι, sodium hypophosphite 1〇g/1. A gold (4) having a thickness of 0.03 " is formed on the (four) layer, and a covering metal layer (not shown) composed of a riding layer and a gold plating layer is formed. 312XP/Invention Manual (Repair)/96-03/95147038 54 (17) The formation of the tan tin layer is then 'exposed to the opening 82 of the most sounding. The solder resist layer 80 Sn/Pb solder or the padding of the S circuit board, the printing melting point is about 183t: Tan, the formation of welding t84 secret composition of the welding paste, Yu Cong next back (Examples 1 ~ 2) The following steps (a) ~ (c) made of pieces 55 buried in Fengkun _ _, 啕 1P & quot In addition to the concave portion 42 of the substrate 兀n yak accommodating substrate, the π m Α 丨 与 实施 实施 除 除 除 除 除 除 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造Laj is transported to the lining and wiring ±, ^ flat on the semiconductor component with a protective film = and throughout the entire surface 'to make the thickness of 〇ι... chrome film and; dryness of 〇.5em copper film layer & Price is formed continuously and continuously. (4) Film layer These two layers are placed in the vacuum chamber. After the entry, the anti-money layer using the dry film is formed on the film layer. The mask of the layer forming portion of the ruthenium layer is placed on the resist layer, and is formed into an anti-surname layer non-formed portion after exposure and development. The electrolytic copper is formed in a thick layer of 9 Å in the anti-surname formation portion. (electrolytic copper film) (c) After removing the electro-mine resist layer by using a test solution or the like, the metal film under the plating resist layer is removed by the button engraving, thereby forming an intermediary on the liner of the semiconductor element In this way, a semiconductor component having a length of 5 mm x 5 mm and a thickness of 100 is obtained. (Embodiment 1 - 3) The shielded passages are formed in a staggered arrangement as shown in Fig. 1(c) (the same treatment as that of the thousand bird row 312XP/invention specification (supplement)/96-03/95147038 1354522, manufacturing a multilayer column) Except for this, the printed wiring board was carried out in the same manner as in the example. (Embodiment 1 - 4) The shield channel is formed as shown in Fig. 1 (c) (c), staggered (chicken arrangement) and the semiconductor layer having the middle layer is buried into the semiconductor component: A multilayer printed wiring board was produced by the same treatment as in the second embodiment except for the concave portion 42 of the substrate. (Embodiment 2-1) In the above step (9) of the embodiment 1-1, the side of the semiconductor element housing recessed portion (four) is formed by the following laser irradiation conditions. The wiring board is printed in the same manner as the embodiment.仏 仏 layer (irradiation conditions)

脈衝能：95 mJ 脈衝寬度：90 β s 脈衝間隔：0. 7 ms 頻率：2000 Hz (實施例2 — 2) 於實施例1—1之上述步驟（9)中，藉由如下之雷射昭射 條件，於半導體元件收納用凹部之側面形成85度之^拔 形，將具有中介層之半導體元件55埋入至半導體元件收 納用基板之凹部42，除此之外進行與實施例i — i相同之 處理’製造多層印刷佈線板。 (照射條件） 312XP/發明說明書(補件)/96·03/95147038 56 脈衝能：80 mj 脈衝寬度：100以s 脈衝間隔：〇. 7 ms 頻率：2000 Hz (實施例2 — 3) 圖1(c)所示之錯開排列（千鳥排 施例2- 1相同之處理，製造多層 將屏蔽通道形成為如 列），除此之外進行與實 印刷佈線板。Pulse energy: 95 mJ Pulse width: 90 β s Pulse interval: 0. 7 ms Frequency: 2000 Hz (Embodiment 2 - 2) In the above step (9) of Embodiment 1-1, by the following laser The radiation condition is formed in a shape of 85 degrees on the side surface of the recessed portion for accommodating the semiconductor element, and the semiconductor element 55 having the interposer is embedded in the recess 42 of the substrate for accommodating the semiconductor element, and i - i is performed in the same manner as in the example i - i The same process 'manufacturing a multilayer printed wiring board. (Irradiation conditions) 312XP/Invention manual (supplement)/96·03/95147038 56 Pulse energy: 80 mj Pulse width: 100 s Pulse interval: 〇. 7 ms Frequency: 2000 Hz (Embodiment 2 – 3) Figure 1 (c) The staggered arrangement shown (the same treatment as in the thousand bird row application 2-1, the multilayer is formed to form the shield channel as a column), and the printed wiring board is printed and printed.

(實施例2—4) 將屏蔽通道形成為如圖 列），將且右Φ八爲 （）所不之錯開排列（千烏排 )將具有中，,層之半導體元件55埋入至半導體元件收 納用基板之凹部42，除此之外、隹> 也 牛收 陈此之外進打與實施例2—1相同之 處理，製造多層印刷佈線板。 门之 (實施例3— 1) (〇除未形成屏蔽通道之外’進行與實施例Η之步 相同之處理，製作於第一絕緣性基材30上形成有半 ⑴對上述基板之雙面二Γ 9(a))。 a r, 艾囬以厚度為15 之乾膜抗蝕層進行 塾，形成抗姓層49,並且形成設置於第一絕緣性基材 〇之凹部54以及其開口周緣部露出之抗蝕層非形成部。 ⑴對上述抗㈣非形成部之表面提供纪觸媒’藉此使觸 媒核附著於凹部54之内壁面及其開口周緣部之表面。 ⑷繼而’將於上述步驟中提供觸媒之基板浸潰於如下組 成之無電解鍍銅水溶液中，於凹部54之内壁面及其開口 312XP/發明說明書(補件)/96*03/95147038 1354522 V 10之無電解鍍鋼 周緣部之表面，形成厚度為0.5〜3. 〇 膜 57a。 (無電解鍍銅液） 硫酸銅：〇. 03 mol/1 EDTA ： 〇.200 mol/1 HCHO ： 〇. 18 g/1 NaOH ： 〇. loo m〇i/L a，a，-聯吡啶·· loo mg/i 聚乙二醇：〇. l〇 g/1 (電鍍條件） 於34°C之液溫下進行40分鐘 ⑸繼而’於如下組成之電解鍍銅切液及㈣條 施電解鍍銅，於抗㈣非形成部形成電解鑛銅膜、貫 (電解鍍銅液） 硫酸：2. 24 mol/1 硫酸銅：0. 26 mol/1 添加劑：19. 5 m 1 /1 KAPARASID GL) (ATOTECH JAPAN公司製造，商品名 (電鍍條件） 電流密度：1 A/dm2 時間：35±5分鐘(Embodiment 2-4) The shield channel is formed as shown in the figure, and the right Φ is () is not staggered (Wanwu row) will have the middle, the layer of the semiconductor device 55 buried into the semiconductor device In addition to the above-described recessed portion 42 of the substrate for storage, the same processing as in Example 2-1 was carried out to produce a multilayer printed wiring board. The door (Embodiment 3-1) (excluding the case where the shielded passage is not formed) is processed in the same manner as in the embodiment, and the first insulating substrate 30 is formed with a half (1) on both sides of the substrate II. 9(a)). Ar, Ai Hui is rubbed with a dry film resist layer having a thickness of 15 to form an anti-surname layer 49, and a concave portion 54 provided on the first insulating substrate and a non-formed portion of the resist layer exposed at the peripheral portion of the opening are formed. . (1) A catalyst is provided on the surface of the anti-(four) non-formed portion, whereby the catalyst core is attached to the inner wall surface of the concave portion 54 and the surface of the peripheral portion of the opening. (4) Then, the substrate in which the catalyst is supplied in the above step is immersed in an electroless copper plating aqueous solution having the following composition, on the inner wall surface of the concave portion 54 and its opening 312XP/invention specification (supplement)/96*03/95147038 1354522 The surface of the peripheral portion of the electroless plated steel of V 10 is formed to have a thickness of 0.5 to 3. The film 57a. (electroless copper plating solution) Copper sulfate: 〇. 03 mol/1 EDTA : 〇.200 mol/1 HCHO : 〇. 18 g/1 NaOH : 〇. loo m〇i/L a,a,-bipyridine· · loo mg/i polyethylene glycol: 〇. l〇g/1 (plating conditions) 40 minutes at 34 ° C liquid temperature (5) and then 'electrolytic copper plating solution and (4) electrolytic plating Copper, in the anti-(four) non-formed part of the formation of electrolytic copper film, through (electrolytic copper plating) sulfuric acid: 2. 24 mol / 1 copper sulfate: 0. 26 mol / 1 additive: 19. 5 m 1 / 1 KAPARASID GL) (Manufactured by ATOTECH JAPAN, trade name (plating conditions) Current density: 1 A/dm2 Time: 35 ± 5 minutes

溫度：22±2°C (6)其後，利用鹼來剝離去除電鍍枋 餘層49’藉此於凹邱 之内壁面（底面及側面）及凹部 4 ^周緣部形成由無電 312XP/發明說明書(補件)/96.03/95147038 58 1354522 用金屬層 解鍍銅膜57a與電解鍍銅膜57b所構成之屏蔽 57(參照圖9(b))。 再者，於凹部之底面露出之具有平坦表面之金屬層42 之表面，由無電解鍍銅膜57a而覆蓋，於該無電解鍍銅膜 57a上形成電解鍍銅膜57b，以此形成屏蔽用金屬層57。 (7)更進一步，進行與實施例i—丨中步驟（1〇)〜（17)相同 之處理，製造多層印刷佈線板（參照圖9(c)〜圖i〇(d))。 (實施例3 — 2) 將具有中介層之半導體元件55埋入至半導體元件收納 用基板之凹部42,除此之外進行與實施例3—丨相同之處 理’製造多層印刷佈線板。 (實施例3—3) 藉由鎳而形成屏蔽用金屬層，並且將具有中介層之半導 體兀件55埋入至半導體元件收納用基板之凹部42，除此 之外進行與實施例3H才目同之處理，製造多層印刷佈線 (實施例3 — 4) 藉由銀而形成屏蔽用金屬層，並且將具有中介層之半導 體兀件55埋人至半導體元件收納用基板之凹部42，除此 =外進行與實施例Η相同之處理，製造多層印刷佈線 (實施例4 — 1) 於上述步驟（9)中’利用如下 — 卜w射照射條件，於半導體 冗件收納用凹部之侧面形成许+也以/ x 度之推拔形，除此之外進 312XP/發明說明書(補件)/96-03/95147038 59 ⑶ 4：)22 二與實施例3-1相同之處理，製造多層印刷佈線板。 (貫施例4一 2) .於上述步驟⑻中，利用如下雷射照射條件，於半導體 騎收納用凹部42之側面形成85度之 :介層之半導體元件55埋入至凹部《，除此之外進= •、施例3—1相同之處理，製造多層印刷佈線板。 (實施例4— 3) _力錄而形成屏蔽用金屬層，且將具有中介層之半導體元 件55埋入至凹部42，除此之外進行與實施例4—"目同 之處理，製造多層印刷佈線板。 (實施例4 — 4) 由銀而形成屏蔽用金屬層，且將具有中介層之半導體元 5埋入至凹部42，除此之外進行與實施例4 相同 之處理，製造多層印刷佈線板。 (比較例1 — 1) •立藉'魚眼加工而形成設於第一絕緣性樹脂基材上之凹 /使孩凹部之底面成為未到達第二絕緣性樹脂基材之形 態，於凹部底部之表面未形成平坦之金屬層，而且未形成 屏蔽通道，除此之外以與實施例U相同之方式進行， 製造多層印刷佈線板。 (比較例1 — 2 ) 藉由魚眼加工而形成設於第一絕緣性樹脂基材上之凹 部，使該凹部之底面成為未到達第二絕緣性樹脂基材之形 ,4 ’於凹部底部之表面未形成平坦之金屬層，而且未形成 312XP/發明說明書(補件)/96-03/95147038 60 1354522 屏蔽通道’除此之外以與實施例1 — 2相同之方式進行， 製造多層印刷佈線板。 • 對依照上述各實施例1 — 1〜4 — 4及比較例1 ~ 1〜1 — $ - 而製造之多層印刷佈線板，進行關於以下項目A〜c之評 價試驗。各評價試驗之結果於表1所示。 A. 驅動試驗 使半導體元件驅動，來測定於1 GHz下之信號線之波 鲁形。在使之驅動後，確認最初20分鐘之波形有無紊亂。 該信號線之波形紊亂係指於半導體元件中產生誤作動，本 發明可稱為半導體元件之誤作動之確認試驗。 該試驗結果依有無波形之紊亂而評價如下。 2〇分鐘内無波形紊亂：〇 1 5分鐘後確認波形紊亂：△Temperature: 22±2°C (6) Thereafter, the electroplating remaining layer 49' is peeled off by alkali to form an inner wall surface (bottom surface and side surface) and a concave portion 4^ peripheral portion of the concave portion by the electroless 312XP/invention specification (Repair)/96.03/95147038 58 1354522 A shield 57 composed of a copper layer 57a and an electrolytic copper plating film 57b is deplated with a metal layer (see Fig. 9(b)). Further, the surface of the metal layer 42 having a flat surface exposed on the bottom surface of the concave portion is covered with an electroless copper plating film 57a, and an electrolytic copper plating film 57b is formed on the electroless copper plating film 57a to form a shield. Metal layer 57. (7) Further, a process similar to the steps (1) to (17) in the example i-丨 is performed to produce a multilayer printed wiring board (see Fig. 9(c) to Fig. (d)). (Embodiment 3 - 2) A multilayer printed wiring board was produced in the same manner as in Example 3 except that the semiconductor element 55 having the interposer was embedded in the recess 42 of the substrate for accommodating the semiconductor element. (Embodiment 3-4) The metal layer for shielding is formed of nickel, and the semiconductor element 55 having the interposer is embedded in the recess 42 of the substrate for accommodating the semiconductor element, and the result is the same as that of the embodiment 3H. In the same process, a multilayer printed wiring is produced (Examples 3 to 4), a metal layer for shielding is formed by silver, and a semiconductor element 55 having an interposer is buried in the recess 42 of the substrate for semiconductor element storage, except In the same manner as in Example ,, a multilayer printed wiring was produced (Example 4-1). In the above step (9), the following conditions were used to form the surface of the concave portion of the semiconductor redundant member. It is also in the shape of / x degrees, in addition to the 312XP / invention manual (supplement) / 96-03 / 95147038 59 (3) 4:) 22 Second, the same treatment as in Example 3-1, the manufacture of multilayer printed wiring board. (Example 4-2) In the above step (8), 85 degrees is formed on the side surface of the semiconductor riding recess 42 by the following laser irradiation conditions: the semiconductor element 55 of the via is buried in the recess " In addition, the same processing as in Example 3-1 is used to manufacture a multilayer printed wiring board. (Embodiment 4 - 3) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Multilayer printed wiring board. (Example 4 - 4) A multilayer printed wiring board was produced by performing the same treatment as in Example 4 except that the metal layer for shielding was formed of silver and the semiconductor element 5 having the interposer was buried in the recess 42. (Comparative Example 1 - 1) • The concave portion provided on the first insulating resin substrate was formed by the fisheye processing, and the bottom surface of the child recessed portion was not in the form of the second insulating resin substrate, and was formed at the bottom of the concave portion. A multilayer printed wiring board was produced in the same manner as in Example U except that a flat metal layer was not formed on the surface and a shielded via was not formed. (Comparative Example 1 - 2) The concave portion provided on the first insulating resin substrate was formed by fisheye processing so that the bottom surface of the concave portion was in a shape that did not reach the second insulating resin substrate, and 4' was at the bottom of the concave portion. The surface was not formed with a flat metal layer, and the 312XP/invention specification (supplement)/96-03/95147038 60 1354522 shielding channel was not formed except in the same manner as in Example 1-2, and multilayer printing was produced. Wiring board. • The evaluation test for the following items A to c was carried out on the multilayer printed wiring board manufactured in accordance with each of the above Examples 1 - 1 to 4 - 4 and Comparative Examples 1 - 1 to 1 - $ -. The results of each evaluation test are shown in Table 1. A. Driving test The semiconductor element is driven to measure the wave shape of the signal line at 1 GHz. After driving it, confirm that the waveform of the first 20 minutes is disordered. The waveform disorder of the signal line refers to a malfunction in the semiconductor element, and the present invention can be referred to as a confirmation test of the malfunction of the semiconductor element. The test results were evaluated as follows according to the disorder of the waveform. No waveform disorder within 2 minutes: 〇 1 5 minutes after confirming waveform disorder: △

於15分前確認波形紊亂：XConfirm waveform disorder before 15 minutes: X

B. 可靠性試驗I • 進行於如下試驗條件下之高溫高濕偏壓試驗，並於試驗 結束後，使其放置2小時，之後進行導通試驗，評價半導 體元件有無誤作動。 (試驗條件） 溫度：185°C 濕度：85%B. Reliability Test I • Perform a high-temperature and high-humidity bias test under the following test conditions, and leave it at the end of the test for 2 hours, then conduct a conduction test to evaluate the presence or absence of misoperation of the semiconductor components. (Test conditions) Temperature: 185 ° C Humidity: 85%

引火電壓：5. 5 V • · 試驗時間：5 0 0小時、1 〇 〇 〇小時、15 0 0小時Ignition voltage: 5. 5 V • · Test time: 500 hours, 1 〇 〇 〇 hour, 1500 hours

-- c.可靠性試驗E 312XP/發明說明書(補件)/96-03/95147038 61 1354522 進行將130°C/3分鐘〇-55°C/3分鐘作為1週期之週期 試驗直至2000週期為止，於1000週期以後之每200週 -. 期，當試驗結束後，使其放置2小時，之後進行導通試驗， ， 測定有無電阻變化率（將進行可靠性試驗前所測定之電阻 值作為初始值，以百分率計算其變化。）超過20%之電路， 並且比較超過20%之週期數。-- c. Reliability test E 312XP / invention manual (supplement) / 96-03/95147038 61 1354522 Perform 130 ° C / 3 minutes 〇 -55 ° C / 3 minutes as a cycle test of 1 cycle until 2000 cycles Every 200 weeks after the 1000th cycle, during the end of the test, it is allowed to stand for 2 hours, and then the conduction test is performed to determine the resistance change rate (the resistance value measured before the reliability test is taken as the initial value). The change is calculated as a percentage.) More than 20% of the circuit, and more than 20% of the cycle number.

312XP/發明說明書(補件)/96-03/95147〇38 62 1354522 (表1) 驅動試驗 可靠性試驗I 可靠性試驗π 500小時 1000小時 2000小時 週期數 實施例1_ 1 〇 〇 〇 〇 1600 實施例1 —2 〇 〇 〇 〇 1800 實施例1 — 3 〇 〇 〇 Δ 1800 實施例1 一4 〇 〇 〇 Δ 1800 實施例2 — 1 〇 〇 〇 〇 1800 實施例2 —2 〇 〇 〇 〇 2000 實施例2 —3 〇 〇 〇 Δ 1800 實施例2—4 〇 〇 〇 Δ 2000 實施例3 — 1 〇 〇 〇 〇 1800 實施例3 — 2 〇 〇 〇 〇 1800 實施例3 — 3 〇 〇 〇 〇 1800 實施例3—4 〇 〇 〇 〇 1800 實施例4 — 1 〇 〇 〇 〇 1800 實施例4一2 〇 〇 〇 〇 2000 實施例4—3 〇 〇 〇 Δ 1800 實施例4一4 〇 〇 〇 Δ 1800 比較例1一 1 X X X X 1000 比較例1 一2 Δ Δ X X 1000 63 312XP/發明說明書(補件)/96-03/95147038 例=述=驗之結果可確認上述各實施例，與比較 二T確保電性連接性及連接可靠性。 L產業上之可利用性） 納==件=之=刷佈線板係於基板上形成收 成電磁屏蔽芦去甘° 於匕圍該凹部之樹脂絕緣層上形 屏蔽電磁法、、可將内藏於凹部之半導體元件有效地 f mi’故能_用於可減少信號延遲或誤作動等不 良It，兄產生之半導體元件封裝基板。 【圖式簡單說明】 磁L:)至一圖1 (c)係表示本發明的多層印刷佈線板之電 屏蔽層之貫施形態之概略圖。 圖2係用以說明本發明的多層印刷佈線板中，收納、埋 入有半導體元件之凹部之推拔形形狀之概略剖面圖。 -圖3係表示本發明的多層印刷佈線板之形成於半導體 元件之襯墊上的柱狀電極之概略剖面圖。 圖4係表示本發明的多層印刷佈線板之形成於半導體 元件之襯墊上的中介層之概略剖面圖。 圖5(a)至圖5(g)係表示本發明的實施例} — i之多層印 刷佈線板之製造步驟的一部分之概略剖面圖。 圖6(a)至圖6(d)係表示本發明的實施例！ 一 j之多層印 刷佈線板之製造步驟的一部分之概略剖面圖。 曰 圖7(a)至圖7(d)係表示本發明的實施例1一1之多層印 刷佈線板之製造步驟的一部分之概略剖面圖。 圖8(a)至圖8(g)係表示本發明的實施例3一 1之多層印 312XP/發明說明書(補件)/96-03/95147038 刷佈線板之製造步驟的一部分之概略剖面圖。 圖9⑷至圖9(e)係表示製造本發明的實施例3 層印刷佈線板之製造步料1分之概略剖面圖 圖10(a)至圖1()⑷係表示本發明的實施例 :刷佈線板之製造步驟的一部分之概略剖面圖。 【主要元件符號說明】 一 1之多 〇 [之多層312XP/Invention Manual (Supplement)/96-03/95147〇38 62 1354522 (Table 1) Drive Test Reliability Test I Reliability Test π 500 hours 1000 hours 2000 hours Cycle number Example 1_ 1 〇〇〇〇1600 Implementation Example 1 - 2 〇〇〇〇 1800 Example 1 - 3 〇〇〇 Δ 1800 Example 1 - 4 〇〇〇 Δ 1800 Example 2 - 1 〇〇〇〇 1800 Example 2 - 2 〇〇〇〇 2000 Implementation Example 2 - 3 〇〇〇 Δ 1800 Example 2-4 〇〇〇 Δ 2000 Example 3 - 1 〇〇〇〇 1800 Example 3 - 2 〇〇〇〇 1800 Example 3 - 3 〇〇〇〇 1800 Implementation Example 3-4 〇〇〇〇 1800 Example 4 - 1 〇〇〇〇 1800 Example 4 - 2 〇〇〇〇 2000 Example 4 - 3 〇〇〇 Δ 1800 Example 4 - 4 〇〇〇 Δ 1800 Comparison Example 1 - 1 XXXX 1000 Comparative Example 1 - 2 Δ Δ XX 1000 63 312XP / invention specification (supplement) / 96-03 / 95147038 Example = description = test results can confirm the above embodiments, and compare the two T to ensure electricity Sexual connectivity and connection reliability. L industry availability] nano == piece = the = brush wiring board is formed on the substrate to form a magnetic shielded reed to go to the edge of the resin insulation layer of the concave portion of the electromagnetic shielding method, can be built The semiconductor element in the recess is effectively used to reduce the signal delay or misoperation, etc., and the semiconductor device package substrate. BRIEF DESCRIPTION OF THE DRAWINGS The magnetic L:) to Fig. 1 (c) is a schematic view showing a form of the electrical shielding layer of the multilayer printed wiring board of the present invention. Fig. 2 is a schematic cross-sectional view showing a push-out shape of a concave portion in which a semiconductor element is housed and embedded in the multilayer printed wiring board of the present invention. - Fig. 3 is a schematic cross-sectional view showing a columnar electrode formed on a spacer of a semiconductor element of the multilayer printed wiring board of the present invention. Fig. 4 is a schematic cross-sectional view showing an interposer formed on a spacer of a semiconductor element of the multilayer printed wiring board of the present invention. Fig. 5 (a) to Fig. 5 (g) are schematic cross-sectional views showing a part of the manufacturing steps of the multilayer printed wiring board of the embodiment of the present invention. 6(a) to 6(d) show an embodiment of the present invention! A schematic cross-sectional view of a portion of the manufacturing steps of a multi-layer printed wiring board. 7(a) to 7(d) are schematic cross-sectional views showing a part of the manufacturing steps of the multilayer printed wiring board according to the first to first embodiment of the present invention. 8(a) to 8(g) are schematic cross-sectional views showing a part of a manufacturing process of a multilayer printed circuit 312XP/invention specification (supplement)/96-03/95147038 of a brush wiring board according to a third embodiment of the present invention. . 9(4) to 9(e) are schematic cross-sectional views showing a manufacturing step of manufacturing a three-layer printed wiring board of an embodiment of the present invention. Figs. 10(a) to 1()(4) show an embodiment of the present invention: A schematic cross-sectional view of a portion of the manufacturing steps of the brush wiring board. [Main component symbol description] One more than one 〇 [Multilayer

1 半導體元件 2 連接襯墊 3 保護膜 4 基礎金屬層 5 柱狀電極 6 密封膜 10 半導體元件 12 第1薄膜層 14 連接襯墊 17 第2薄膜層 18 加厚層 20 中介層 30 第一絕緣性基材 32 樹脂絕緣層 34 銅羯 36 通孔形成用開口 37 屏蔽通道形成用開口 39 填孔 312XP/發明說明書(補件)/96-03/95147038 65 1354522 40 第二絕緣性基材 41 導體電路 42 金屬層 43 樹脂絕緣層 44 銅洛 46 通孔形成用開口 47 屏蔽通道 48 保護薄膜 49 電鍵抗^虫層 50 導體電路 52 填孔 54 半導體元件收納用凹部 55 半導體元件 56 黏著劑層 57 屏蔽用金屬層 57a 無電解鍍銅膜 57b 電解鍍銅膜 58 柱狀電極 60 基板 62 黏著材層 64 樹脂絕緣層 66 銅箱 70 通孔形成用開口 72 通孔形成用開口 3 ΠΧΡ/發明說明書(補件)/96-03/95147038 66 1354522 74 導體電路 76 填孔 78 填孔 80 阻焊劑層 82 阻焊劑層之開口 84 焊錫層1 semiconductor element 2 connection pad 3 protective film 4 base metal layer 5 columnar electrode 6 sealing film 10 semiconductor element 12 first film layer 14 connection pad 17 second film layer 18 thick layer 20 interposer 30 first insulation Substrate 32 Resin insulating layer 34 Causeway 36 Through hole forming opening 37 Shielding channel forming opening 39 Filling hole 312XP / Invention specification (supplement) /96-03/95147038 65 1354522 40 Second insulating substrate 41 Conductor circuit 42 Metal layer 43 Resin insulating layer 44 Tongluo 46 Through hole forming opening 47 Shielding channel 48 Protective film 49 Keying resistant layer 50 Conductor circuit 52 Filling hole 54 Semiconductor element housing recess 55 Semiconductor element 56 Adhesive layer 57 Shielding Metal layer 57a Electroless copper plating film 57b Electrolytic copper plating film 58 Column electrode 60 Substrate 62 Adhesive layer 64 Resin insulating layer 66 Copper case 70 Through hole forming opening 72 Through hole forming opening 3 ΠΧΡ/Invention manual (Repair ) /96-03/95147038 66 1354522 74 Conductor circuit 76 Filling hole 78 Filling hole 80 Solder resist layer 82 Solder resist layer opening 84 Solder layer

312XP/發明說明書(補件)/96-03/95147038 67312XP/Invention Manual (supplement)/96-03/95147038 67

Claims (1)

NOV 1 7 2010 替換本 十、一申T專利範S ·· 管換; 脂絕緣層印刷佈線板，其係於收納有半導體元件之樹 "5上，形成其他樹脂絕緣層及導體電路 體元件係經由通孔而電性連接路’上述半導 者’其特徵在於： 接至上^體電路所形成 上述半導體元件係内藏於上述 絕緣層的-面貫通至另―面而設之凹㈣，日上《該树脂 :上述凹部之底面形成有下部金 係載置於該下部金屬層上， 件 於包圍上述凹部之樹脂絕緣層上，包含上 全 而形成有電磁屏蔽層。 至屬層 、、.如巾請專利範圍第丨項之多層印刷佈線板，其中，上 述下部金屬層具有大於上述凹部之底面的面積。 3. 如申請專利範圍第1 $ 2項之多層印刷佈線板，其 上辻·下。卩金屬層為形成於上述樹脂絕緣層的單面之 鲁體層的一部分。 4. 如申請專利範圍第1或2項之多層印刷佈線板，其 中’上述下部金屬層為形成於雙面覆銅積層板的單面之銅 箔。 、5.如申請專利範圍第丨項之多層印刷佈線板，其中，上 述電磁屏蔽層包含形成為選自下述形態之至少一種形態 之側面金屬層：複數個非貫通孔之内壁表面由金屬覆蓋之 形怨、複數個非貫通孔内填充有金屬之形態、複數個柱狀 體之形態。 95147038 68 丄354522 2如申請專利範圍第1項之多層印刷佈線板，其中，上 述電磁屏蔽層包含形成於上述凹部之内壁之金屬層。 •复=如申請專利範圍第卜5或6項之多層印刷佈曰線板， .-，上述電磁屏蔽層係將上述側面金屬層與上述下部金 屬層連結而形成。 • 8.如申請專利範圍第i項之多層印刷佈線板，其中，上 .$凹部形成為具推拔形，其側面隨著自底面朝 漸擴展。 φ ^-種多層印刷佈線板，其係於㈣有半導體元件之樹 Λ彖層上，形成其他樹脂絕緣層及導體電路，上述半導 $元件係經由通孔而電性連接至上述 者，其特徵在於： 風 上述半導體元件係内藏於樹脂絕緣層上所設之凹部 作為:If/自下述形態之至少一種形態之側面金屬層係 ;，、、電磁屏敝層而形成於包圍上述凹部之樹脂絕緣層NOV 1 7 2010 Replace this ten, one application T patent S · · tube change; grease insulating layer printed wiring board, which is attached to the tree containing semiconductor elements, 5, forming other resin insulation layer and conductor circuit body components Electrically connecting the 'semiconductor' via a via hole, wherein the semiconductor element formed in the upper body circuit is recessed (four) formed in the surface of the insulating layer and penetrates to the other surface. In the above-mentioned resin, the lower surface of the concave portion is formed with a lower metal layer placed on the lower metal layer, and the member is formed on the resin insulating layer surrounding the concave portion, and an electromagnetic shielding layer is formed thereon. The multilayer printed wiring board of the invention, wherein the lower metal layer has an area larger than a bottom surface of the concave portion. 3. For example, apply for the multilayer printed wiring board of the 1st and 2nd patents. The base metal layer is a part of a single-layered luer layer formed on the above-mentioned resin insulating layer. 4. The multilayer printed wiring board according to claim 1 or 2, wherein the lower metal layer is a copper foil formed on one side of the double-sided copper clad laminate. 5. The multilayer printed wiring board according to claim 2, wherein the electromagnetic shielding layer comprises a side metal layer formed in at least one of the following forms: an inner wall surface of the plurality of non-through holes is covered with metal The form of complaints, a plurality of non-through holes filled with a metal form, and a plurality of columnar bodies. A multilayer printed wiring board according to the first aspect of the invention, wherein the electromagnetic shielding layer comprises a metal layer formed on an inner wall of the concave portion. • The above-mentioned electromagnetic shielding layer is formed by joining the side metal layer to the lower metal layer, as in the multi-layer printed fabric splicing plate of the patent application No. 5 or 6. 8. The multilayer printed wiring board of claim i, wherein the upper portion is formed in a push-out shape, and the side surface thereof gradually expands from the bottom surface. a φ ^ - type multilayer printed wiring board which is formed on (4) a tree layer having a semiconductor element to form another resin insulating layer and a conductor circuit, wherein the semiconductor material is electrically connected to the above via a via hole. The recessed portion provided in the resin insulating layer in the semiconductor element is a side metal layer of at least one of the following forms; and an electromagnetic screen layer is formed around the recess. Resin insulation 數個非貫通孔之内壁由金屬覆蓋之形態、複數個非 貝^内填充有金屬之形態、複數個金屬柱狀體之形能。 10.如申請專利範圍第9項之多層印刷佈線板，盆 述側面金屬層之至少一部分係相互連結。 如申請專利範圍帛9項之多層印刷佈線板，其中， ΓΓΛ體為選自圓柱、橢圓柱、多角柱之至少—種形狀。 12.如申請專利範圍第9項之多層印刷佈線板，发中， 屏蔽層包含形成於位於上述凹部底面之樹脂免 、、彖層上的下部金屬層，或者形成於位於上述凹部底面之下 95147038 69 方之樹脂絕緣層上的下部金屬層。 13.如申請專利範圍第 ,^ w = ^ 員之夕層印刷佈線板，其中， 上述电磁屏敝層係將上述 連結而形成。 面金屬層與上訂部金屬層 二？咖圍第9至13項中任-項之多層印刷佈 部形成為具推拔形，其側面隨著自底 面朝向上方而逐漸擴展。 _ 15· -種多層印刷佈線板，其係於收納有半導體元 樹脂絕緣層上，形忐苴 牛之 ;力成其他樹脂絕緣層及導體電路，上述半 ¥體凡件係經由通孔而電 者，其特徵在於： 連接至上逑導體電路所形成 上述半導體元件係、内藏於樹脂絕緣層上所設之凹部 内’與半導體元件連接 成之填編“⑴二: 緣β m干 y心，於包圍上述凹部之樹脂絕 、，彖層形成有電磁屏蔽層。 16·如申請專利範圍第 m ± 固弟15項之夕層印刷佈線板，其中， 上述填孔之表面為大致平坦。 上、°月專利耗圍第15項之多層印刷佈線板，其中， ^電磁屏蔽層係由侧面金屬層與下部金屬層所構成。 18.如申請專利範圍第15項之多層印刷佈線板，其中， 处電磁屏蔽層係形成為選自下述形態之至少一種形能 =面金屬層:複數個非貫通孔之内壁表面由金屬繼 ^ μ 金屬之形態、複數個柱狀 腹 < 形惡。 95147038 19. 如申請專利範圍第18項之多層印刷佈線板，其中， 逃側面金屬層之至少一部分係相互連結。 20. 如申請專利範圍第丨8項之多層印刷佈線板，其中， ，&柱狀體為選自圓柱、橢圓柱、多角柱之至少-種形狀。 21. 如申請專利範圍帛17項之多層印刷佈線板，其中， 述电磁屏蔽層包含位於上述凹部之底面上的下部金屬 ^或者形成於位於上述凹部底面之下方之樹脂絕緣層上 的下部金屬層。 佑％2 .如申5月專利知圍第17至21項中任一項之多層印刷 、’板其中，上述電磁屏蔽層係將上述側面金屬層盥上 述下部金屬層連結而形成。 /、 種夕層印刷佈線板，其係於收納有半導體元件之 树月曰絶緣層上，形成其他樹脂絕緣層及導體電路，上述半 土— _件係，.二由通孔而電性連接至上述導體電路 者’其特徵在於： 鲁力上述半‘體兀件係内藏於上述樹脂絕緣層上所設之凹 邛内:上述其他樹脂絕緣層纟有纖維基材，且形成有與半 導體兀件連接之通孔；於包圍上述凹部之樹脂絕緣層上形 成有電磁屏蔽層。 24·如中請專利範圍第23項之多層印刷佈線板，其中， 上述填孔之表面為大致平坦。 25. 如申請專利範圍第23項之多層印刷佈線板，其中， 上述電磁屏蔽層由側面金屬層與下部金屬層所構成。 26. 如申5月專利範圍第23項之多層印刷佈線板，其中， 95147038 71 :述電磁屏蔽層係形成為 之侧面金屬層:複數個非〜之至v種形悲 形態、複數個非貫、甬ti貝通孔之内壁表面由金屬覆蓋之 體之形態。、k填充有金屬之形態、複數個柱狀 上專利範圍第26項之多層印刷佈線板，盆中， 上逑側面金屬層之至少一部分係相互連結。-中 上:^：=第26項之多層印刷佈線板，其中， 29如申 1直才主，圓柱、多角柱之至少一種形狀。 上：:二 範圍第23項之多層印刷佈線板，其中， 包含形成於位於上述凹部底面之樹脂絕 方：二 ，或者形成於位於上述凹部底面之下 树月曰絕緣層上的下部金屬層。 3〇·如申請專利範圍第以至29項中任—項之多 ^反，其中，上述電磁屏蔽層係將上述側 迷下部金屬層連結而形成。 蜀上 31 · —種多層印刷佈線板，其係於收納有半 =月曰絕緣層上，形成其他樹脂絕緣層及導體電路，上述丰 元件係經由通孔而電性連接至上述導體電 = 者，其特徵在於： 化成 上述半導體元件係内藏於樹脂絕緣層上所設之凹邛 包圍該凹部之樹顏緣層上形成有電磁屏蔽層，ς 粗7L件之下部配置有下部金屬層作為電磁屏蔽岸， 下。卩金屬層之面積大於上述凹部底面之面積。 32.如申請專利範圍第31項之多層印刷佈線板，其中， 95147038 72 上述填孔之表面為大致平坦。 上3二如邱申Λ專:j範圍第31項之多層印刷佈線板，其中， 上述下部金屬層由輥軋鋼箱所形成。 34. 如申請專利範圍第 上述電磁屏蔽層由側面全印刷佈線板’其中’ 35. 如申請專利範圍第.3 屬層所構成。 卜# + Μ P # 固乐Μ項之多層印刷佈線板，其中， 之側：々I:層係形成為選自下述形態之至少-種形態 形熊、：童曰，數個非貫通孔之内壁表面由金屬覆蓋之 體：形Ϊ。固非貝通孔内填充有金屬之形態、複數個柱狀 中°月專利範圍第35項之多層印刷佈線板，其中， 上迭側面金屬層之至少一部分係相互連結。 37. 如申凊專利範圍第35項之多層印刷佈線板，其中， 上述柱狀體為選自 Μ丄Λ 橢固柱、多角柱之至少一種形狀。 38. 如申請專利範圍帛31項之多層印刷佈線板，其中， • 2電磁屏敝層包含形成於位於上述凹部底面之樹脂維 、、g上的下部金屬層，或者形成於位於上述凹部底面 方之樹脂絕緣層上的下部金屬戶。 39·如中請專利範圍第34/38項中任__項之多層、 秦板其中，上述電磁屏蔽層係將上述側面金屬層 述下部金屬層連結而形成。 /、上 40.-種多層印刷佈線板之製造方法，其於製造多心 刷佈線板（其係於收納半導體元件而成之樹脂絕緣層丄，p 形成其他樹脂絕緣層及導體電路，上述半導體元件係經由 95147038 73 ^54522 通孔而電性連接至上述導體電路 述步驟： 战）扦，至少包括下 於樹腊絕緣層之一面至少形成導體 於另-面至少形成導體電路及與上述^層，並且 之導體電路非形成區域，更進一步 ：對向之位置 (其係將上述另一面之導體電路與上 鍍而形成通孔 性連接之通孔、以及於上述另一面之導=之導體電路電 之外側貫穿樹脂絕緣層而到達上述一電路非形成區域 孔）’藉此形成第一絕緣性樹月旨基材 之金屬層之通 將於樹脂絕緣層之一面貼附有鋼箱而 ★ 性樹脂基材之樹脂面，壓合於上 ^成之弟二絕緣 而一體化之步驟； ^ —絕緣性樹脂基材上 於上述第二絕緣性樹脂基材上 與該導體電路電性連接之通孔之步驟；體電路’亚且形成 於上述第一絕緣性樹脂基材之 樹脂絕緣層表面形成凹部之步驟. ^形成區域，自 之::導:r收納於上述凹部内，利-著劑使其黏著 之=述半導體元件而形成其他樹脂絕緣層，形成通孔 仏-種多層印刷佈線板之製造方法，1 刷佈線板（其係於收納半導體 /、、衣故夕層P 形成其他樹脂絕緣層及導體電 絕緣層上， 通孔而電性連接至上述導體導體元件係經由 妝罨路所形成）時，至少包括下 95147038 74 述步驟： :樹緣層之—面至少形成導體電路及金 於另-面至少形成導體電路及與上 二亚且 之導體電路非形成區敁m U屬層對向之位置 連接之通?丨，4 °°域’利用電鍍而形成與導體電路電性 ，猎此形成第一絕緣性樹脂基材 將於樹脂絕緣芦夕^ 竹驟， 性槲时㈣而形叙第二絕缘 陡樹知基材之樹脂面，壓人 、巴緣 而一體化之步驟；口於上生樹脂基材上 利第二絕緣性樹脂基材之一面形成導體電路，並且 而形成通孔之步驟，該通孔係將上述導體電路盘 乂成 逑第—絕緣性樹脂基材上之通孔予以電性連接； 於上述第一絕緣性樹脂基材之導體電路形 成凹部之步驟； 〜匕·Λ办 利用電鑛形成覆蓋上述凹部之金屬層之步驟； 將半導體元件收納於上述凹部内’使用黏著劑使其固定 鲁於上述凹部之金屬層上之步驟；以及 覆蓋上述半導體元件而形成其他樹脂絕緣層，利用電鍍 而形成電性連接之通孔之步驟。 电又 95147038 75 1354522 圖 圖 年『丨月(7日修次)正替換頁 半導體元件The inner wall of a plurality of non-through holes is covered by a metal, a plurality of non-shells are filled with a metal, and a plurality of metal columns are shaped. 10. The multilayer printed wiring board of claim 9, wherein at least a portion of the side metal layers are joined to each other. The multi-layer printed wiring board of claim 9 is characterized in that the carcass is at least one shape selected from the group consisting of a cylinder, an elliptical cylinder and a polygonal column. 12. The multilayer printed wiring board of claim 9, wherein the shielding layer comprises a lower metal layer formed on the resin free layer on the bottom surface of the recess, or a bottom layer located under the bottom surface of the recess 951-4038 The lower metal layer on the 69-square resin insulation layer. 13. The printed wiring board of the member of the present invention, wherein the electromagnetic screen layer is formed by joining the above-mentioned electromagnetic screen layers. Surface metal layer and upper part metal layer II? The multilayer printed fabric portion of the items 9 to 13 of the café is formed in a push-pull shape, and the side surface thereof gradually expands from the bottom surface toward the upper side. _ 15· a multilayer printed wiring board which is housed on a semiconductor element resin insulating layer and shaped like a yak; and is formed into another resin insulating layer and a conductor circuit, and the above-mentioned half-body is electrically connected via a through hole It is characterized in that: the semiconductor element formed by the upper conductor circuit is formed in a recess provided in the resin insulating layer, and the semiconductor element is connected to form a "(1) two: edge β m dry y, An electromagnetic shielding layer is formed on the enamel layer in the resin surrounding the concave portion. 16* The printed circuit board of the ninth layer of the application of the invention is in the range of the m-th aspect of the invention, wherein the surface of the filling hole is substantially flat. The multi-layer printed wiring board of the fifteenth item of the patent, wherein the electromagnetic shielding layer is composed of a side metal layer and a lower metal layer. 18. A multilayer printed wiring board according to claim 15 of the patent application, wherein The electromagnetic shielding layer is formed by at least one of the following forms of shape energy = surface metal layer: the inner wall surface of the plurality of non-through holes is formed by a metal followed by a metal shape, a plurality of columnar abdomen shapes 95147038 19. The multilayer printed wiring board of claim 18, wherein at least a portion of the metal layer of the escape side is bonded to each other. 20. The multilayer printed wiring board of claim 8 of the patent application, wherein, & The columnar body is at least one type selected from the group consisting of a cylinder, an elliptical column, and a polygonal column. 21. The multilayer printed wiring board of claim 17, wherein the electromagnetic shielding layer comprises a lower portion on a bottom surface of the concave portion a metal or a lower metal layer formed on the resin insulating layer below the bottom surface of the concave portion. The multi-layer printing of any one of items 17 to 21 of the Japanese Patent Publication No. 17-21, The electromagnetic shielding layer is formed by connecting the side metal layer to the lower metal layer. The seed layer printed wiring board is formed on a tree-shaped insulating layer in which a semiconductor element is housed to form another resin insulating layer and a conductor circuit. The above-mentioned semi-soil---pieces, two are electrically connected to the conductor circuit by a through hole, and are characterized in that: the above-mentioned half-body element of Luli is built in In the recess provided in the resin insulating layer: the other resin insulating layer has a fibrous base material and is formed with a through hole connected to the semiconductor element; and an electromagnetic shielding layer is formed on the resin insulating layer surrounding the concave portion. The multilayer printed wiring board of the invention, wherein the surface of the hole is substantially flat. The multilayer printed wiring board of claim 23, wherein the electromagnetic shielding layer is made of a side metal The layer and the lower metal layer are formed. 26. The multilayer printed wiring board of claim 23, wherein the electromagnetic shielding layer is formed as a side metal layer: a plurality of non-~ to v species The shape of the tragic form, the plurality of non-continuous, and the inner wall of the 甬ti bei hole is covered by metal. And k is filled with a metal form, a plurality of columns, and a multilayer printed wiring board of the 26th item of the patent scope, wherein at least a part of the metal layer on the side of the upper side is connected to each other. - 中上: ^: = The multilayer printed wiring board of item 26, wherein, for example, the shape of the main body, the cylinder, and the polygonal column is at least one shape. The multilayer printed wiring board of item 23, wherein the resin is formed on the bottom surface of the concave portion: or a lower metal layer formed on the insulating layer of the tree under the bottom surface of the concave portion. 3. The above-mentioned electromagnetic shielding layer is formed by joining the lower metal layers of the above-mentioned side, as in the case of the patent application.蜀 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 The invention is characterized in that: the semiconductor element is formed on the resin insulating layer, and the concave layer provided on the resin insulating layer surrounds the concave portion of the tree, and an electromagnetic shielding layer is formed on the edge layer of the tree, and a lower metal layer is disposed under the thick 7L as electromagnetic Shield the shore, down. The area of the base metal layer is larger than the area of the bottom surface of the recess. 32. The multilayer printed wiring board of claim 31, wherein 95147038 72 is substantially flat on the surface of the hole. The above-mentioned lower metal layer is formed by a rolled steel box. The above-mentioned lower metal layer is formed by a rolled steel box. 34. As claimed in the patent application, the electromagnetic shielding layer is composed of a side full printed wiring board 'where' 35. As claimed in the patent application.卜# + Μ P # 固 Μ 之 多层 多层 多层 , , , : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The inner wall surface is covered by metal: shape. The solid non-belt hole is filled with a metal form, a plurality of columns, and a multilayer printed wiring board of the above-mentioned patent range, wherein at least a part of the upper side metal layer is connected to each other. The multilayer printed wiring board of claim 35, wherein the columnar body is at least one shape selected from the group consisting of a 椭 ellipsoidal column and a polygonal column. 38. The multilayer printed wiring board of claim 31, wherein: 2 the electromagnetic screen layer comprises a lower metal layer formed on a resin dimension, g on a bottom surface of the recess, or formed on a bottom surface of the recess The lower metal house on the resin insulation layer. 39. The multi-layer, 秦板 of the __ item of the patent scope of claim 34/38, wherein the electromagnetic shielding layer is formed by joining the side metal layer to the lower metal layer. And a manufacturing method of a multilayer printed wiring board for manufacturing a multi-card wiring board (which is a resin insulating layer formed by accommodating a semiconductor element, p forms another resin insulating layer and a conductor circuit, and the semiconductor The component is electrically connected to the conductor circuit via a 95174703 73^54522 through hole. The step of: at least including forming a conductor on at least one side of the insulating layer of the tree wax to form at least a conductor circuit and the above layer And the conductor circuit non-formation region, further: the position of the opposite direction (the conductor circuit of the other surface is formed by a through hole which is plated with a through hole, and the conductor circuit of the other side of the other surface The outer side of the electricity penetrates through the resin insulating layer and reaches the hole of the non-formation region of the circuit. The first insulating layer is formed by the metal layer of the substrate, and a steel case is attached to one side of the resin insulating layer. The resin surface of the resin substrate is press-bonded to the step of integrating the insulation of the second substrate; ^ - the insulating resin substrate is on the second insulating resin substrate a step of electrically connecting the through-holes of the conductor circuit; the step of forming a concave portion on the surface of the resin insulating layer of the first insulating resin substrate. The forming region is: In the above-mentioned recessed portion, a resin-bonded semiconductor element is formed to form another resin insulating layer, and a via-hole multilayer printed wiring board is formed. 1 A wiring board (which is used for housing a semiconductor/, When the clothing layer P forms another resin insulating layer and the conductor electrical insulating layer, and the through hole is electrically connected to the conductor conductor element formed by the makeup circuit, at least includes the following 95,714,038. The layer-plane forms at least a conductor circuit and the gold is formed on at least the other side of the conductor circuit and is connected to the position of the conductor circuit non-formation region of the upper two sub-layers, and the 4°° domain The electroplating is used to form electrical properties with the conductor circuit, and the first insulating resin substrate is formed by the resin, and the resin is insulated, and the resin surface of the substrate is formed by the second insulating steep tree. People a step of integrating the edge of the barrier; forming a conductor circuit on one side of the second insulating resin substrate on the upper resin substrate, and forming a through hole, the through hole is formed by winding the conductor circuit The through hole on the insulating resin substrate is electrically connected; the step of forming the concave portion in the conductor circuit of the first insulating resin substrate; and the metal layer covering the concave portion is formed by using the electric ore a step of accommodating a semiconductor element in the recessed portion, a step of fixing the metal layer on the recessed portion with an adhesive, and forming a resin insulating layer by covering the semiconductor element to form an electrically connected via hole by electroplating The steps. Electric again 95147038 75 1354522 Figure Figure "Yueyue (7-day repair) is replacing page Semiconductor component 黏著劑層 金屬層 第二^邑緣性樹脂基材 推拔形苒复 第一絕缘性樹月旨基材Adhesive layer, metal layer, second edge, resin substrate, push-pull shape, first insulating tree, substrate 圖Figure 2/8 NOV 1 7 2010 替換頁2/8 NOV 1 7 2010 replacement page
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