JP4103549B2 - Multilayer wiring board manufacturing method and multilayer wiring board - Google Patents

Multilayer wiring board manufacturing method and multilayer wiring board Download PDF

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JP4103549B2
JP4103549B2 JP2002317664A JP2002317664A JP4103549B2 JP 4103549 B2 JP4103549 B2 JP 4103549B2 JP 2002317664 A JP2002317664 A JP 2002317664A JP 2002317664 A JP2002317664 A JP 2002317664A JP 4103549 B2 JP4103549 B2 JP 4103549B2
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bare chip
semiconductor bare
wiring board
multilayer wiring
conductor pattern
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JP2004153084A (en
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健治 成瀬
健 西岡
基春 江▲崎▼
初 岡
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、熱可塑性樹脂からなる多層の絶縁層を有すると共に、層間に形成された導体パターン及びそれら導体パターン間を接続する層間接続部を有する多層配線基板の製造方法及び多層配線基板に関する。
【０００２】
【従来の技術】
例えば各種の小型電子機器に組込まれる実装基板においては、多層配線基板の表面に、例えばＢＧＡ（Ball Grid Array ）タイプや、ＣＳＰ（Chip Size Package ）タイプといった小型、高密度のパッケージ型の半導体部品（電子部品）を実装することが行われている。また、前記多層配線基板は、例えばエポキシ樹脂などの熱硬化性樹脂を主体とした多層の絶縁層を有すると共に、表面や層間に導体パターンを有して構成され、その表面に形成されたランドに、前記半導体部品のはんだバンプが接合（はんだ付け）されるようになっている。
【０００３】
ところが、このような実装基板にあっては、多層配線基板及び電子部品の各部の熱膨張係数の差などに起因して、温度変化を繰返し受けることにより、はんだ接合部（はんだバンプ）部分にストレスが作用し、例えばはんだ接合部のうち多層配線基板表面のランドとの界面などにクラックが発生し、ひいては剥離に至るなど、接続信頼性に劣る問題点があった。そのため、接合の安定性を確保するためには、実装条件出しをシビアにする必要等があり、評価に多大な時間を必要とする不具合があった。
【０００４】
【発明が解決しようとする課題】
ところで、上記のような多層配線基板にあって、電子部品を内部に埋込んだ形態で設けることができれば、電子部品と基板との間の電気的な接合安定性を向上させることができ、また、基板の表面の面積の有効利用を図ることも期待できる。しかしながら、従来の多層配線基板にあっては、内部に電子部品を埋込んだ形態に設けようとすれば、多層配線基板の製造工程がかなり複雑（面倒）となることが予測される。
【０００５】
本発明は上記事情に鑑みてなされたもので、その目的は、電子部品を埋込んだ形態で備える多層配線基板を、容易に製造することができる多層配線基板の製造方法及び多層配線基板を提供するにある。
【０００６】
【課題を解決するための手段】
本出願人は、例えばポリエーテルエーテルケトン（ＰＥＥＫ）樹脂、ポリエーテルイミド（ＰＥＩ）樹脂といった結晶転移型の熱可塑性樹脂製のフィルムを用いた多層配線基板の製造方法を開発してきている。このような熱可塑性樹脂は、例えば２００℃付近では軟質となるが、それより低い温度でも高い温度でも硬質となり（さらに高い温度（約４００℃）では溶解する）、また、高温から温度低下する際には、２００℃付近でも硬質を保つ性状を呈するものとなっている（図４参照）。
【０００７】
このため、このような熱可塑性樹脂製のフィルムに導体パターンや層間接続部となる部分を形成した基材を積層し、一括して約２００℃で熱プレスすることにより、多層配線基板を容易に製造することができる。また、このような製造方法を用いることにより、例えば数十層もの多層のものを一括して製造できて生産性が大幅に向上すると共に、熱硬化性樹脂を用いた場合と比較して寸法精度に優れる、リサイクル性にも優れるなどの多大なメリットを得ることができる。
【０００８】
本発明者は、このような多層配線基板の製造方法の応用により、電子部品を埋込んだ形態で備える多層配線基板を、容易に製造することができることを確認し、本発明を成し遂げたのである。
【０００９】
即ち、本発明の多層配線基板の製造方法は、基材を形成する基材形成工程、基材を積層する積層工程、熱プレス工程を含み、積層工程において、多数枚の基材間の所定位置に半導体ベアチップを配置することにより、導体パターンに電気的に接続された半導体ベアチップを、絶縁層内に埋込まれた形態で設け、基材形成工程において、基材のうち半導体ベアチップが配置される部分に、該半導体ベアチップに対応した穴を形成すると共に、基材のうち半導体ベアチップの放熱面に接触する部分に、放熱用の放熱パターンを導体パターンと一体的に形成し、更に、その放熱パターンの表面に導電ペーストを塗布するようにしたところに特徴を有する（請求項１の発明）。また、本発明の多層配線基板は、導体パターンに電気的に接続された半導体ベアチップを、熱可塑性樹脂からなる多層の絶縁層の穴内に埋込まれた形態で備えると共に、前記半導体ベアチップの放熱面に導電ペーストの硬化層を介して熱的に接触する放熱パターンが、導体パターンと一体的に設けられているところに特徴を有する（請求項４の発明）。
【００１０】
これによれば、熱可塑性樹脂のフィルムを主体とした基材を複数枚積層する際に、基材間の所定位置に半導体ベアチップを配置し、熱プレスを行うことにより、絶縁層内に半導体ベアチップを埋込んだ形態で備える多層配線基板を製造することができる。このとき、埋込まれた半導体ベアチップと導体パターンとの間の電気的な接合安定性は高いものとなり、また、多層配線基板の表面の面積の有効利用を図ることができる。そして、積層工程において、半導体ベアチップを所定位置に配置することによって、半導体ベアチップを埋込んだ形態に設けることができるので、工程を特に複雑化することなく済ませることができ、製造が容易となる。
【００１１】
この場合、絶縁層（多層配線基板自体）によって半導体ベアチップの保護を図ることができてパッケージの形成を不要とすることができると共に、多層配線基板内に埋込む部品を、より小さいもので済ませることができる。
【００１２】
そして、上記した製造方法にあっては、半導体ベアチップが配置される部分に、基材が存在すると、熱プレス工程において、半導体ベアチップがその厚み（体積）分だけ基材の材料（熱可塑性樹脂）を押しのけることになり、基板の変形を招く等の様々な弊害の発生を招く虞もある。ところが、基材形成工程において、基材のうち半導体ベアチップが配置される部分に、該半導体ベアチップに対応した穴が形成されているので、そのような弊害の発生を防止することができる。
【００１４】
ところで、半導体ベアチップを絶縁層内に埋込んだ場合、半導体ベアチップの発熱が内部にこもってしまうようなことがあると、絶縁層の劣化などの弊害を招く虞がある。そこで、基材形成工程において、基材のうち半導体ベアチップの放熱面に接触する部分に、放熱用の放熱パターンを導体パターンと一体的に形成することにより、多層配線基板に、半導体ベアチップの放熱のための放熱パターンを設けることができる。
【００１５】
これにより、半導体ベアチップの放熱を良好に行うことができ、また、放熱パターンを設けるための別途の工程を不要とすることができる。更にこのとき、放熱パターンの表面に、導電ペーストが塗布されるので、その導電ペーストの層が熱プレス工程におけるクッションとなって、半導体ベアチップに過大な力がかかることを防止でき、また、多少の寸法誤差を吸収して半導体ベアチップと放熱パターンとを密着させることができる。
【００１６】
また、積層工程において半導体ベアチップの電極に導電ペーストを塗布しておき、それら電極が層間接続部に接続されるように構成することができる（請求項２の発明）。これによれば、同種の材質同士の接合により、半導体ベアチップの電気的接続が行われるので、接合の安定性を一層高めることができる。
さらには、基材形成工程において、基材のうち半導体ベアチップの上下に位置される部分に、半導体ベアチップの電磁シールド用のシールドパターンを導体パターンと一体的に形成することにより、多層配線基板に、半導体ベアチップの電磁シールド用のシールドパターンを設けることができる（請求項３，５の発明）。これによれば、多層配線基板に埋込まれた半導体ベアチップの放射ノイズの低減を図ることができ、基板外部に対策部品を不要として、機器設計の容易化を図ることができる。
【００１７】
【発明の実施の形態】
以下、本発明の第１の実施例について、図１ないし図４を参照しながら説明する。まず、図２は、本実施例に係る多層配線基板１の構成を概略的（模式的）に示しており、この多層配線基板１は、後述する熱可塑性樹脂材料からなる多数の絶縁層２を積層して構成されており、その表面（上面）及び各絶縁層２間には、例えば銅箔からなる導体パターン３が形成されていると共に、要所には層間の導体パターン３を電気的に接続する層間接続部４が設けられている。
【００１８】
そして、この多層配線基板１内には、ほぼ中央部に位置して、この場合電子部品としての半導体ベアチップ５が、電極面を図で上面側として埋込まれた形態に設けられている。この場合、半導体ベアチップ５の図で上面の各電極は、上から２層目の絶縁層２内の層間接続部４に対して接続され、ひいては導体パターン３に電気的に接続されている。
【００１９】
また、本実施例では、前記半導体ベアチップ５の図で下面側が放熱面とされ、この放熱面にやはり銅箔からなる放熱用の放熱パターン６が密着するように設けられている。図示はしないが、この放熱パターン６は、多層配線基板１の外部へ放熱を行うための所定の放熱経路に接続されている。尚、実際には、絶縁層２の層数は、十数層〜数十層にもなるが、ここでは便宜上６層で図示している。また、これも便宜上、半導体ベアチップ５の厚み寸法は、絶縁層２の３層分の厚みにほぼ等しいものとされている。
【００２０】
さて、上記構成の多層配線基板１を製造するための本実施例に係る製造方法について、図１、図３、図４も参照して述べる。多層配線基板１を製造するにあたっては、まず、図１、図３に示すような基材７を形成する基材形成工程が実行される。この基材７は、絶縁層２を構成する結晶転移型の熱可塑性樹脂からなるフィルム８上に、導体パターン３を形成してなり、また、要所に層間接続部４を構成するためのビアホール８ａが形成されると共にそのビアホール８ａ内に導電ペースト９を充填して構成される。
【００２１】
このとき、前記フィルム８は、例えばポリエーテルエーテルケトン（ＰＥＥＫ）樹脂３５〜６５重量％と、ポリエーテルイミド（ＰＥＩ）樹脂３５〜６５重量％とを含んだ材料からなり（商品名「ＰＡＬ−ＣＬＡＤ」）、厚みが例えば２５〜７５ミクロンの、多層配線基板１の大きさに対応した矩形状をなしている。この樹脂材料は、図４に示すように、例えば２００℃付近では軟質となるが、それより低い温度でも高い温度でも硬質となる（さらに高い温度（約４００℃）では溶解する）性状を呈し、また、高温から温度低下する際には、２００℃付近でも硬質を保つものとなっている。
【００２２】
図３は、この基材７を製作する手順を示している。まず、（ａ）に示すようにフィルム８の表面（上面）に貼付けられた導体箔この場合銅箔１０に対して、エッチングにより導体パターン３を形成する工程が実行される。このとき、図１に示すように、最下層に位置される基材７については、べたパターンからなる放熱パターン６が導体パターン３と一体的（同時）に形成されるようになる。
【００２３】
この導体パターン３の形成後、フィルム８の裏面（下面）には、例えばポリエチレンナフタレート（ＰＥＮ）製の保護フィルム１１が貼付される（ｂ）。そして、保護フィルム１１側からの例えば炭酸ガスレーザの照射により、フィルム８の要所に導体パターン３を底面とする有底のビアホール８ａ（便宜上、図３にのみ符号を付す）を形成する工程が実行される（ｃ）。この場合、炭酸ガスレーザの出力及び照射時間の調整により、導体パターン３に穴が開かないようにしている。
【００２４】
引続き、前記ビアホール８ａ内に、導電ペースト９を充填する工程が実行される（ｄ）。この導電ペースト９は、銅、銀、スズ等の金属粒子に、バインダ樹脂や有機溶剤を加えて混練してペースト状としたものであり、例えばメタルマスクを用いたスクリーン印刷によりビアホール８ａ内に印刷充填される。このとき、図１で上から２層目を構成する基材７については、半導体ベアチップ５の各電極に対応した位置にも、ビアホール８ａが形成されて導電ペースト９が充填されるようになる。導電ペースト９の充填後、フィルム８から保護フィルム１１剥がされる（ｅ）。
【００２５】
さらに、この基材形成工程においては、基材７のうち、前記半導体ベアチップ５が配置される部分に、該半導体ペアチップ５に対応した穴７ａが形成される。この場合、図１に示すように、上から３，４，５層目を構成する３枚の基材７に対して、その中央部分に半導体ペアチップ５に対応した四角形の穴７ａが形成されるようになる。
【００２６】
次に、上記のようにして形成された複数枚の基材７を、多層配線基板１の最終形態に応じた形態に上下に積層する積層工程が実行される。この積層工程においては、図１に示すように、６枚の基材７が上下に積層されるのであるが、これと共に、半導体ベアチップ５が、基材７間の所定位置即ち上から２層目の基材７と最下層の基材７との間に挟まれて３枚の基材７の穴７ａ内に嵌るようにして、半導体ベアチップ５がその電極面を上面として配置されるようになる。
【００２７】
また、このとき、半導体ベアチップ５の図で上面の各電極には、前記ビアホール８ａ内に充填されたものと同等の導電ペースト９が塗布されるようになっている。さらに、最下層に位置される基材７の放熱パターン６の上面にも、同等の導電ペースト９が塗布されるようになっている。尚、図示はしないが、図１で最上層を構成する基材７の表面（導体パターン３の露出面）には、例えばポリエチレンナフタレート（ＰＥＮ）製のフィルムからなるカバーレイヤが配置されるようになっている。
【００２８】
次いで、上記した積層物を一括して熱プレスする工程が実行される。この熱プレス工程では、上記積層物が図示しない真空加圧プレス機にセットされ、例えば２００〜３５０℃に加熱されながら、０．１〜１０Ｍｐａの圧力で上下方向に加圧される。このとき、上記各基材７を構成するフィルム８は、図４に示すような温度に対する弾性率変化を生ずるので、この熱プレスの工程により、各フィルム８が熱により一旦軟化した状態で加圧されることによって相互に融着し、その後結晶化（硬化）して一体化するようになる。
【００２９】
これにて、図２に示すように、多層の絶縁層２間に導体パターン３が埋込まれると共に、ビアホール８ａ内の導電ペースト９が硬化して層間接続部４が形成されるようになる。これと同時に、半導体ベアチップ５が、その各電極が上から２層目の絶縁層２の層間接続部４（ひいては導体パターン３）に接続され、また裏面側の放熱面が最下層の絶縁層２上の放熱パターン６に熱的に接続された状態で、絶縁層２内に埋込まれるようになり、以て、多層配線基板１が構成されるのである。
【００３０】
このとき、半導体ベアチップ５の上側部分においては、半導体ベアチップ５の電極に塗布された導電ペースト９が、ビアホール８ａ内の導電ペースト９と一体化して層間接続部４を構成するようになり、同種の材質同士の接合により、半導体ベアチップ５の電気的接続が行われることになり、高い接合性を得ることができる。
【００３１】
また、半導体ベアチップ５の下面側では、放熱パターン６の表面に導電ペースト９が塗布されていたことにより、その導電ペースト９の層が熱プレス工程におけるクッションとなって、半導体ベアチップ５に過大な力がかかることを防止でき、また、多少の寸法誤差を吸収して半導体ベアチップ５と放熱パターン６とを密着させることができる。
【００３２】
そして、基材７のうち、半導体ベアチップ５が配置される部分に穴７ａを形成しておいたことにより、熱プレス工程において半導体ベアチップ５が、基材７（フィルム８）の材料（熱可塑性樹脂）を押しのけて多層配線基板１の変形を招く等の弊害の発生を未然に防止することができるのである。
【００３３】
このように本実施例によれば、熱可塑性樹脂のフィルム８を主体とした基材７を複数枚積層する際に、基材７間の所定位置に半導体ベアチップ５を配置し、熱プレスを行うことにより、絶縁層２内に半導体ベアチップ５を埋込んだ形態で備える多層配線基板１を製造することができた。このとき、埋込まれた半導体ベアチップ５と導体パターン３との間の電気的な接合安定性は高いものとなり、また、多層配線基板１の表面の面積の有効利用を図ることができる。そして、工程を特に複雑化することなく済ませることができ、多層配線基板１を容易に製造することができるものである。
【００３４】
特に本実施例では、多層配線基板１内に、電子部品として半導体ベアチップ５を埋込んだ形態に設けるようにしたので、絶縁層２（多層配線基板１自体）によって半導体ベアチップ５の保護を図ることができてパッケージの形成を不要とすることができると共に、多層配線基板１内に埋込む部品を、より小さいもので済ませることができる。
【００３５】
さらに、特に本実施例では、上述のように、基材７に予め半導体ベアチップ５に対応した穴７ａを形成しておくようにしたので、基板１の変形などを未然に防止することができ、また、半導体ベアチップ５の電極に導電ペースト９を塗布しておいたことにより、接合の安定性を一層高めることができる。そして、放熱パターン６を導体パターン３と一体的に設けるようにしたので、半導体ベアチップ５の放熱を良好に行うことができ、また別途の工程を不要とすることができ、しかも、放熱パターン６上に導電ペースト９を塗布しことにより、熱プレス工程において半導体ベアチップ５に過大な力がかかることを防止でき、多少の寸法誤差を吸収して半導体ベアチップ５と放熱パターン６とを密着させることができるといった利点も得ることができるものである。
【００３６】
図５は、本発明の第２の実施例に係る多層配線基板２１の要部構成を概略的に示すものであり、この第２の実施例が上記第１の実施例と異なるところは次の点にある。即ち、この多層配線基板２１は、やはり結晶転移型の熱可塑性樹脂材料からなる多層（図では便宜上８層）の絶縁層２を積層して構成されており、導体パターン３及び層間接続部４を有すると共に、電子部品たる半導体ベアチップ５が、図で上から４、５、６層目に位置して埋込まれた形態に設けられている。また、半導体ベアチップ５の各電極は、上から３層目の絶縁層２内の層間接続部４に対して接続され、さらには、下から２層目の絶縁層２の上面部に半導体ベアチップ５の放熱面に密着する放熱パターン６が設けられている。
【００３７】
そして、本実施例では、上から２層目に位置する絶縁層２の上面、及び、最下層に位置する絶縁層の上面に、半導体ベアチップ５の上面側及び下面側を夫々覆うように、銅箔のべたパターンからなるからなる電磁シールド用のシールドパターン２２及び２３が、やはり導体パターン３と一体的に設けられている。尚、詳しく図示はしないが、これらシールドパターン２２、２３は、グランドに接続されている。
【００３８】
この多層配線基板２１を製造するにあたっては、上記第１の実施例と同様に、基材形成工程、積層工程、熱プレス工程が順に実行されるのであるが、ここでは、基材形成工程において、上から２層目の基材７、及び、最下層の基材７に、シールドパターン２２及び２３が銅箔１０のエッチングにより導体パターン３と一体的に形成される。そして、積層工程、熱プレス工程を経ることに多層配線基板２１が形成されるのである。
【００３９】
このような第２の実施例によっても、上記第１の実施例と同様の作用、効果を得ることができ、これに加えて、半導体ベアチップ５の電磁シールド用のシールドパターン２２、２３を容易に形成することができると共に、多層配線基板２１に埋込まれた半導体ベアチップ５の放射ノイズの低減を図ることができ、基板１外部に対策部品を不要として、機器設計の容易化を図ることができるといった効果を得ることができる。
【００４０】
尚、上記各実施例では、電子部品として半導体ベアチップ５を採用したが、それ以外でも各種の電子部品（センサ類を含む）を多層配線基板内に埋込んだ形態に設けることができる。また、上記各実施例では絶縁層２（基材７のフィルム８）を構成する結晶転移型の熱可塑性樹脂として、ＰＥＥＫ樹脂とＰＥＩ樹脂とを混合したものを採用したが、ＰＥＥＫ樹脂単体、あるいはＰＥＩ樹脂単体、さらにはそれらにフィラーを添加したもの等を採用することも可能であるなど、本発明は要旨を逸脱しない範囲内で適宜変更して実施し得るものである。
【図面の簡単な説明】
【図１】 本発明の第１の実施例を示すもので、基材の積層時の様子を概略的に示す縦断正面図
【図２】 多層配線基板の構成を概略的に示す縦断正面図
【図３】 基材形成工程を説明するための図
【図４】 結晶転移型の熱可塑性樹脂の温度変化と弾性率との関係を示す図
【図５】 本発明の第２実施例を示すもので、多層配線基板の要部の構成を概略的に示す縦断正面図
【符号の説明】
図面中、１、２１は多層配線基板、２は絶縁層、３は導体パターン、４は層間接続部、５は半導体ベアチップ（電子部品）、６は放熱パターン、７は基材、７ａは穴、８はフィルム、８ａはビアホール、９は導電ペースト、１０は銅箔、２２，２３はシールドパターンを示す。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer wiring board and a multilayer wiring board having a multilayer insulating layer made of a thermoplastic resin, and having a conductor pattern formed between the layers and an interlayer connection portion connecting the conductor patterns.
[0002]
[Prior art]
For example, in a mounting board incorporated in various small electronic devices, a small and high-density package type semiconductor component (such as a BGA (Ball Grid Array) type or a CSP (Chip Size Package) type) is provided on the surface of a multilayer wiring board (for example). Electronic components) are being mounted. Further, the multilayer wiring board has a multilayer insulating layer mainly composed of a thermosetting resin such as an epoxy resin, and has a conductor pattern between the surface and the interlayer, and is formed on a land formed on the surface. The solder bumps of the semiconductor component are joined (soldered).
[0003]
However, in such mounting boards, stress is applied to the solder joints (solder bumps) due to repeated temperature changes due to differences in thermal expansion coefficients between the multilayer wiring board and each part of the electronic component. For example, a crack is generated at an interface with the land on the surface of the multilayer wiring board in the solder joint portion, resulting in inferior connection reliability such as peeling. For this reason, in order to ensure the stability of bonding, it is necessary to make the mounting conditions severe, and there is a problem that requires a lot of time for evaluation.
[0004]
[Problems to be solved by the invention]
By the way, in the multilayer wiring board as described above, if the electronic component can be provided in an embedded form, the electrical joint stability between the electronic component and the substrate can be improved, and In addition, it can be expected to effectively use the surface area of the substrate. However, in the conventional multilayer wiring board, it is expected that the manufacturing process of the multilayer wiring board will be considerably complicated (complex) if it is provided in a form in which electronic parts are embedded therein.
[0005]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer wiring board manufacturing method and a multilayer wiring board capable of easily manufacturing a multilayer wiring board provided with an embedded electronic component. There is.
[0006]
[Means for Solving the Problems]
The present applicant has developed a method for producing a multilayer wiring board using a film made of a crystal transition type thermoplastic resin such as polyether ether ketone (PEEK) resin or polyether imide (PEI) resin. Such a thermoplastic resin becomes soft at, for example, around 200 ° C., but becomes hard at lower or higher temperatures (dissolves at higher temperatures (about 400 ° C.)), and when the temperature decreases from a high temperature. Has a property of maintaining hardness even at around 200 ° C. (see FIG. 4).
[0007]
For this reason, a multilayer wiring board can be easily formed by laminating a base material on which a conductor pattern or a portion to be an interlayer connection portion is formed on such a film made of a thermoplastic resin and collectively heat-pressing at about 200 ° C. Can be manufactured. Moreover, by using such a manufacturing method, for example, several tens of layers can be manufactured in a lump and productivity can be greatly improved, and dimensional accuracy compared to the case of using a thermosetting resin. It is possible to obtain great merits such as excellent recyclability and recyclability.
[0008]
The present inventor has confirmed that it is possible to easily manufacture a multilayer wiring board provided with an embedded electronic component by applying such a method of manufacturing a multilayer wiring board, and accomplished the present invention. .
[0009]
That is, the method for manufacturing a multilayer wiring board of the present invention includes a base material forming step for forming a base material, a laminating step for laminating the base material, and a heat pressing step. by placing the semiconductor bare chip, electrically connected to the semiconductor bare chip to the conductor pattern, provided in a form embedded in the insulating layer, the substrate forming step, the semiconductor bare chip is disposed within the base A hole corresponding to the semiconductor bare chip is formed in the portion, and a heat radiation pattern for heat radiation is integrally formed with the conductor pattern in a portion of the base material that contacts the heat radiation surface of the semiconductor bare chip. on the surface of the characterized in it was so applying the conductive paste (first aspect of the present invention). The multilayer wiring board of the present invention comprises a semiconductor bare chip electrically connected to a conductor pattern in a form embedded in a hole of a multilayer insulating layer made of a thermoplastic resin, and heat dissipation of the semiconductor bare chip. The present invention is characterized in that a heat radiation pattern that is in thermal contact with the surface via a hardened layer of a conductive paste is provided integrally with the conductor pattern (invention of claim 4 ).
[0010]
According to this, when laminating a plurality of base materials mainly composed of a thermoplastic resin film, the semiconductor bare chips are arranged in a predetermined position between the base materials, and are subjected to hot pressing, whereby the semiconductor bare chips are formed in the insulating layer. Can be manufactured. At this time, the electrical bonding stability between the embedded semiconductor bare chip and the conductor pattern is high, and the surface area of the multilayer wiring board can be effectively used. In the stacking step, the semiconductor bare chip is arranged at a predetermined position, so that the semiconductor bare chip can be provided in an embedded form. Therefore, the process is not particularly complicated, and the manufacturing is facilitated.
[0011]
In this case, it is possible to eliminate the need for formation of packages can be protected in the semiconductor bare chip by insulation layers (multi-layer wiring substrate itself), a component embedded in the multilayer wiring board, dispensed with smaller ones be able to.
[0012]
In the manufacturing method described above, when a base material is present in the portion where the semiconductor bare chip is disposed, the material of the base material (thermoplastic resin) is equivalent to the thickness (volume) of the semiconductor bare chip in the hot press step. May cause various adverse effects such as deformation of the substrate. However , in the base material forming step, since holes corresponding to the semiconductor bare chips are formed in the portion of the base material where the semiconductor bare chips are arranged, it is possible to prevent such adverse effects.
[0014]
By the way, when the semiconductor bare chip is embedded in the insulating layer, if the heat generated by the semiconductor bare chip is trapped inside, there is a risk of causing adverse effects such as deterioration of the insulating layer. Therefore, the substrate forming step, the part in contact with the heat radiating surface of the semiconductor bare chip of the substrate, by forming the heat radiation pattern for radiating integrally with the conductor patterns, the multilayer wiring substrate, the semiconductor bare chip of the radiator Ru can be provided the heat radiation pattern for.
[0015]
Thereby, the semiconductor bare chip can be radiated well, and a separate process for providing a radiating pattern can be eliminated. Further, at this time, since the conductive paste is applied to the surface of the heat dissipation pattern, the layer of the conductive paste serves as a cushion in the hot press process, and it is possible to prevent an excessive force from being applied to the semiconductor bare chip . By absorbing the dimensional error, the semiconductor bare chip and the heat radiation pattern can be brought into close contact with each other.
[0016]
In addition, a conductive paste can be applied to the electrodes of the semiconductor bare chip in the stacking step, and the electrodes can be connected to the interlayer connection portion (invention of claim 2). According to this, since the semiconductor bare chip is electrically connected by bonding the same kind of materials, the stability of the bonding can be further improved.
Further, in the substrate forming step, the portion to be located above and below the semiconductor bare chip of the substrate, by forming the shield pattern of the electromagnetic shielding of the semiconductor bare chip integrally with the conductor patterns, a multilayer wiring board, A shield pattern for electromagnetic shielding of the semiconductor bare chip can be provided (inventions of claims 3 and 5 ). According to this, the radiation noise of the semiconductor bare chip embedded in the multilayer wiring board can be reduced, and no countermeasure parts are required outside the board, thereby facilitating device design.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described below with reference to FIGS. First, FIG. 2 schematically shows (schematically) the configuration of the multilayer wiring board 1 according to the present embodiment. The multilayer wiring board 1 includes a number of insulating layers 2 made of a thermoplastic resin material to be described later. A conductive pattern 3 made of, for example, copper foil is formed between the surface (upper surface) and each insulating layer 2, and an interlayer conductive pattern 3 is electrically connected to a key point. An interlayer connection 4 to be connected is provided.
[0018]
In this multilayer wiring board 1, a semiconductor bare chip 5 as an electronic component is provided in such a manner that the electrode surface is embedded in the drawing with the upper surface side in the drawing. In this case, each electrode on the upper surface in the drawing of the semiconductor bare chip 5 is connected to the interlayer connection portion 4 in the insulating layer 2 that is the second layer from the top, and is thus electrically connected to the conductor pattern 3.
[0019]
Further, in this embodiment, the lower surface side of the semiconductor bare chip 5 is a heat radiating surface, and a heat radiating pattern 6 made of copper foil is provided in close contact with the heat radiating surface. Although not shown, the heat radiation pattern 6 is connected to a predetermined heat radiation path for heat radiation to the outside of the multilayer wiring board 1. In practice, the number of layers of the insulating layer 2 may be several tens to several tens, but here, six layers are shown for convenience. For the sake of convenience, the thickness dimension of the semiconductor bare chip 5 is substantially equal to the thickness of the three insulating layers 2.
[0020]
Now, a manufacturing method according to this embodiment for manufacturing the multilayer wiring board 1 having the above-described configuration will be described with reference to FIGS. In manufacturing the multilayer wiring board 1, first, a base material forming step for forming the base material 7 as shown in FIGS. 1 and 3 is executed. This base material 7 is formed by forming a conductor pattern 3 on a film 8 made of a crystal transition type thermoplastic resin that constitutes the insulating layer 2, and a via hole for constituting an interlayer connection portion 4 at a key point. 8a is formed and a conductive paste 9 is filled in the via hole 8a.
[0021]
At this time, the film 8 is made of a material containing, for example, 35 to 65% by weight of polyetheretherketone (PEEK) resin and 35 to 65% by weight of polyetherimide (PEI) resin (trade name “PAL-CLAD”). ”), A rectangular shape corresponding to the size of the multilayer wiring board 1 having a thickness of, for example, 25 to 75 microns. As shown in FIG. 4, this resin material becomes soft at, for example, around 200 ° C., but becomes hard at a lower temperature or higher temperature (dissolves at a higher temperature (about 400 ° C.)). Further, when the temperature is lowered from a high temperature, it remains hard even at around 200 ° C.
[0022]
FIG. 3 shows a procedure for manufacturing the base material 7. First, as shown to (a), the process which forms the conductor pattern 3 by the etching with respect to the copper foil 10 in this case the conductor foil affixed on the surface (upper surface) of the film 8 is performed. At this time, as shown in FIG. 1, with respect to the base material 7 positioned at the lowermost layer, the heat radiation pattern 6 composed of a solid pattern is formed integrally (simultaneously) with the conductor pattern 3.
[0023]
After the formation of the conductor pattern 3, a protective film 11 made of, for example, polyethylene naphthalate (PEN) is attached to the back surface (lower surface) of the film 8 (b). And the process of forming the bottomed via-hole 8a (it attaches | subjects a code | symbol only to FIG. 3 for convenience) with the conductor pattern 3 in the bottom of the film 8 by the irradiation of the carbon dioxide laser from the protective film 11 side is performed. (C). In this case, a hole is not formed in the conductor pattern 3 by adjusting the output of the carbon dioxide laser and the irradiation time.
[0024]
Subsequently, a step of filling the via hole 8a with the conductive paste 9 is performed (d). This conductive paste 9 is a paste obtained by adding a binder resin or an organic solvent to metal particles such as copper, silver, tin, etc. to form a paste, and is printed in the via hole 8a by screen printing using a metal mask, for example. Filled. At this time, with respect to the base material 7 constituting the second layer from the top in FIG. 1, via holes 8 a are formed at positions corresponding to the respective electrodes of the semiconductor bare chip 5 to be filled with the conductive paste 9. After filling with the conductive paste 9, the protective film 11 is peeled off from the film 8 (e).
[0025]
Further, in this base material forming step, a hole 7 a corresponding to the semiconductor pair chip 5 is formed in a portion of the base material 7 where the semiconductor bare chip 5 is disposed. In this case, as shown in FIG. 1, a square hole 7a corresponding to the semiconductor pair chip 5 is formed at the center of the three base materials 7 constituting the third, fourth, and fifth layers from the top. It becomes like this.
[0026]
Next, a stacking step is performed in which the plurality of base materials 7 formed as described above are stacked up and down in a form corresponding to the final form of the multilayer wiring board 1. In this laminating step, as shown in FIG. 1, six base materials 7 are stacked one above the other. At the same time, the semiconductor bare chip 5 is located at a predetermined position between the base materials 7, that is, the second layer from the top. The semiconductor bare chip 5 is disposed with its electrode surface as the upper surface so that it is sandwiched between the base material 7 and the lowermost base material 7 and fits into the holes 7a of the three base materials 7. .
[0027]
At this time, the conductive paste 9 equivalent to the one filled in the via hole 8a is applied to each electrode on the upper surface in the figure of the semiconductor bare chip 5. Furthermore, an equivalent conductive paste 9 is also applied to the upper surface of the heat radiation pattern 6 of the base material 7 located in the lowermost layer. Although not shown, a cover layer made of a film made of polyethylene naphthalate (PEN), for example, is disposed on the surface of the base material 7 (exposed surface of the conductor pattern 3) constituting the uppermost layer in FIG. It has become.
[0028]
Subsequently, the process of carrying out the hot press of the above-mentioned laminated body collectively is performed. In this hot pressing step, the laminate is set in a vacuum press machine (not shown) and is pressed in the vertical direction at a pressure of 0.1 to 10 MPa while being heated to 200 to 350 ° C., for example. At this time, the film 8 constituting each of the substrates 7 changes in elastic modulus with respect to the temperature as shown in FIG. 4, so that the film 8 is pressed in a state where each film 8 is once softened by heat. As a result, they are fused to each other and then crystallized (cured) to be integrated.
[0029]
Thereby, as shown in FIG. 2, the conductive pattern 3 is embedded between the multilayer insulating layers 2, and the conductive paste 9 in the via hole 8a is cured to form the interlayer connection portion 4. At the same time, each electrode of the semiconductor bare chip 5 is connected to the interlayer connection portion 4 (and consequently the conductor pattern 3) of the second insulating layer 2 from the top, and the heat radiation surface on the back side is the lowermost insulating layer 2 In a state where it is thermally connected to the upper heat radiation pattern 6, it is buried in the insulating layer 2, thereby forming the multilayer wiring board 1.
[0030]
At this time, in the upper part of the semiconductor bare chip 5, the conductive paste 9 applied to the electrodes of the semiconductor bare chip 5 is integrated with the conductive paste 9 in the via hole 8 a to form the interlayer connection portion 4. By joining the materials, the semiconductor bare chip 5 is electrically connected, and high joining properties can be obtained.
[0031]
Further, since the conductive paste 9 is applied to the surface of the heat radiation pattern 6 on the lower surface side of the semiconductor bare chip 5, the layer of the conductive paste 9 serves as a cushion in the hot pressing process, and excessive force is applied to the semiconductor bare chip 5. In addition, the semiconductor bare chip 5 and the heat radiation pattern 6 can be brought into close contact with each other by absorbing some dimensional errors.
[0032]
And since the hole 7a was formed in the part in which the semiconductor bare chip 5 is arrange | positioned among the base materials 7, the semiconductor bare chip 5 is the material (thermoplastic resin) of the base material 7 (film 8) in a hot press process. The occurrence of adverse effects such as causing deformation of the multilayer wiring board 1 by pushing off the) can be prevented in advance.
[0033]
As described above, according to the present embodiment, when a plurality of base materials 7 mainly composed of the thermoplastic resin film 8 are laminated, the semiconductor bare chip 5 is disposed at a predetermined position between the base materials 7 and hot pressing is performed. Thus, the multilayer wiring board 1 provided with the semiconductor bare chip 5 embedded in the insulating layer 2 could be manufactured. At this time, the electrical bonding stability between the embedded semiconductor bare chip 5 and the conductor pattern 3 is high, and the surface area of the multilayer wiring board 1 can be effectively used. Further, the process can be completed without making the process particularly complicated, and the multilayer wiring board 1 can be easily manufactured.
[0034]
In particular, in this embodiment, since the semiconductor bare chip 5 is provided as an electronic component embedded in the multilayer wiring board 1, the semiconductor bare chip 5 is protected by the insulating layer 2 (multilayer wiring board 1 itself). As a result, the formation of a package can be eliminated, and the components embedded in the multilayer wiring board 1 can be made smaller.
[0035]
Further, particularly in the present embodiment, as described above, since the hole 7a corresponding to the semiconductor bare chip 5 is previously formed in the base material 7, deformation of the substrate 1 can be prevented in advance. Further, since the conductive paste 9 is applied to the electrodes of the semiconductor bare chip 5, the bonding stability can be further improved. Since the heat radiation pattern 6 is provided integrally with the conductor pattern 3, the semiconductor bare chip 5 can be radiated favorably, and a separate process can be dispensed with. By applying the conductive paste 9, the semiconductor bare chip 5 can be prevented from being applied with an excessive force in the hot pressing process, and a slight dimensional error can be absorbed to bring the semiconductor bare chip 5 and the heat radiation pattern 6 into close contact with each other. Such advantages can also be obtained.
[0036]
FIG. 5 schematically shows a main configuration of a multilayer wiring board 21 according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in the following points. In the point. That is, the multilayer wiring board 21 is formed by laminating a plurality of insulating layers 2 (eight layers for convenience in the figure) made of a crystal transition type thermoplastic resin material, and the conductor pattern 3 and the interlayer connection portion 4 are formed. In addition, the semiconductor bare chip 5 as an electronic component is provided in a form embedded in the fourth, fifth and sixth layers from the top in the drawing. Each electrode of the semiconductor bare chip 5 is connected to the interlayer connection portion 4 in the insulating layer 2 that is the third layer from the top, and further, the semiconductor bare chip 5 is formed on the upper surface portion of the insulating layer 2 that is the second layer from the bottom. A heat radiation pattern 6 is provided in close contact with the heat radiation surface.
[0037]
In this embodiment, the upper surface side and the lower surface side of the semiconductor bare chip 5 are covered with the upper surface of the insulating layer 2 located in the second layer from the top and the upper surface of the insulating layer located in the lowermost layer, respectively. The shield patterns 22 and 23 for the electromagnetic shield made of a solid pattern of foil are also provided integrally with the conductor pattern 3. Although not shown in detail, the shield patterns 22 and 23 are connected to the ground.
[0038]
In manufacturing this multilayer wiring board 21, as in the first embodiment, the base material forming step, the laminating step, and the hot pressing step are sequentially performed. In this case, in the base material forming step, The shield patterns 22 and 23 are integrally formed with the conductor pattern 3 by etching the copper foil 10 on the second base material 7 and the lowermost base material 7 from above. And the multilayer wiring board 21 is formed through a lamination process and a hot press process.
[0039]
According to the second embodiment, the same operation and effect as the first embodiment can be obtained. In addition, the shield patterns 22 and 23 for the electromagnetic shield of the semiconductor bare chip 5 can be easily provided. In addition to being able to be formed, the radiation noise of the semiconductor bare chip 5 embedded in the multilayer wiring substrate 21 can be reduced, and no countermeasure parts are required outside the substrate 1, thereby facilitating device design. Such effects can be obtained.
[0040]
In each of the above embodiments, the semiconductor bare chip 5 is adopted as an electronic component. However, other various electronic components (including sensors) can be provided in a form embedded in a multilayer wiring board. In each of the above embodiments, a mixture of PEEK resin and PEI resin is used as the crystal transition type thermoplastic resin constituting the insulating layer 2 (film 8 of the base material 7). The present invention can be implemented with appropriate modifications within a range not departing from the gist of the invention, such as the PEI resin alone, or those obtained by adding fillers thereto.
[Brief description of the drawings]
FIG. 1 shows a first embodiment of the present invention, and is a longitudinal front view schematically showing a state in which substrates are laminated. FIG. 2 is a longitudinal front view schematically showing a configuration of a multilayer wiring board. FIG. 3 is a diagram for explaining a substrate forming process. FIG. 4 is a diagram showing the relationship between temperature change and elastic modulus of a crystal transition type thermoplastic resin. FIG. 5 is a diagram showing a second embodiment of the present invention. Fig. 2 is a longitudinal front view schematically showing the configuration of the main part of the multilayer wiring board.
In the drawings, 1 and 21 are multilayer wiring boards, 2 is an insulating layer, 3 is a conductor pattern, 4 is an interlayer connection part, 5 is a semiconductor bare chip (electronic component), 6 is a heat dissipation pattern, 7 is a base material, 7a is a hole, 8 is a film, 8a is a via hole, 9 is a conductive paste, 10 is a copper foil, and 22 and 23 are shield patterns.

Claims (5)

熱可塑性樹脂からなる多層の絶縁層を有すると共に、層間に形成された導体パターン及びそれら導体パターン間を接続する層間接続部を有する多層配線基板を製造する方法であって、
結晶転移型の熱可塑性樹脂からなり前記絶縁層を構成するフィルムに、前記導体パターンを形成すると共に、前記層間接続部となるビアホールを形成しその内部に導電ペーストを充填して基材を形成する基材形成工程と、
前記基材を多数枚積層する積層工程と、
積層された前記基材を一括して加熱しながら加圧することにより一体化する熱プレス工程とを含むと共に、
前記積層工程において、前記多数枚の基材間の所定位置に半導体ベアチップを配置することにより、前記導体パターンに電気的に接続された前記半導体ベアチップを、前記絶縁層内に埋込まれた形態で設けるようにし、
前記基材形成工程において、前記基材のうち前記半導体ベアチップが配置される部分に、該半導体ベアチップに対応した穴を形成すると共に、前記基材のうち前記半導体ベアチップの放熱面に接触する部分に、放熱用の放熱パターンを、前記導体パターンと一体的に形成し、更に、前記放熱パターンの表面に、導電ペーストを塗布することを特徴とする多層配線基板の製造方法。A method of manufacturing a multilayer wiring board having a multilayer insulating layer made of a thermoplastic resin, and having a conductor pattern formed between layers and an interlayer connection portion connecting between the conductor patterns,
The conductor pattern is formed on a film made of a crystal transition type thermoplastic resin and constituting the insulating layer, and a via hole to be the interlayer connection portion is formed, and a conductive paste is filled therein to form a substrate. A base material forming step;
A laminating step of laminating a large number of the base materials;
Including a hot press step of integrating the stacked base materials by heating and pressurizing them together,
In the laminating step, the by arranging the semiconductor bare chip at a predetermined position between the large number of substrates, the semiconductor bare chip which is electrically connected to the conductor pattern, with the embedded insulating layer form To provide ,
In the base material forming step, a hole corresponding to the semiconductor bare chip is formed in a portion of the base material where the semiconductor bare chip is disposed, and a portion of the base material that is in contact with a heat radiating surface of the semiconductor bare chip is formed. A method for producing a multilayer wiring board , wherein a heat radiation pattern for heat radiation is formed integrally with the conductor pattern, and a conductive paste is applied to a surface of the heat radiation pattern . 前記積層工程においては、前記半導体ベアチップの前記放熱面とは反対の電極面の各電極に導電ペーストが塗布された状態とされると共に、それら電極が前記層間接続部に接続されるように構成されていることを特徴とする請求項１記載の多層配線基板の製造方法。 In the laminating step, a conductive paste is applied to each electrode on the electrode surface opposite to the heat dissipation surface of the semiconductor bare chip, and the electrodes are connected to the interlayer connection portion. The method for producing a multilayer wiring board according to claim 1, wherein: 前記基材形成工程において、前記基材のうち前記半導体ベアチップの上下に位置される部分に、前記半導体ベアチップの電磁シールド用のシールドパターンを、前記導体パターンと一体的に形成することを特徴とする請求項１又は２記載の多層配線基板の製造方法。 In the base material forming step, a shield pattern for electromagnetic shielding of the semiconductor bare chip is integrally formed with the conductor pattern on portions of the base material positioned above and below the semiconductor bare chip. The manufacturing method of the multilayer wiring board of Claim 1 or 2. 熱可塑性樹脂からなる多層の絶縁層を有すると共に、層間に形成された導体パターン及びそれら導体パターン間を接続する層間接続部を有する多層配線基板において、In a multilayer wiring board having a multilayer insulating layer made of a thermoplastic resin, and having a conductor pattern formed between layers and an interlayer connection portion connecting between the conductor patterns,
前記導体パターンに電気的に接続された半導体ベアチップを、前記絶縁層の穴内に埋込まれた形態で備えると共に、前記半導体ベアチップの放熱面に導電ペーストの硬化層を介して熱的に接触する放熱パターンが、前記導体パターンと一体的に設けられていることを特徴とする多層配線基板。A semiconductor bare chip electrically connected to the conductor pattern is provided in a form embedded in a hole of the insulating layer, and heat dissipation is in thermal contact with the heat dissipation surface of the semiconductor bare chip via a hardened layer of conductive paste. A multilayer wiring board, wherein a pattern is provided integrally with the conductor pattern. 前記半導体ベアチップの電磁シールド用のシールドパターンが、前記導体パターンと一体的に設けられていることを特徴とする請求項４記載の多層配線基板。The multilayer wiring board according to claim 4, wherein a shield pattern for electromagnetic shielding of the semiconductor bare chip is provided integrally with the conductor pattern.
JP2002317664A 2002-10-31 2002-10-31 Multilayer wiring board manufacturing method and multilayer wiring board Expired - Fee Related JP4103549B2 (en)

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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019340A (en) * 2004-06-30 2006-01-19 Tdk Corp Board with built-in semiconductor ic
JP2006019441A (en) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in electronic substrate
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JP4016039B2 (en) * 2005-06-02 2007-12-05 新光電気工業株式会社 Wiring board and method for manufacturing wiring board
KR100714196B1 (en) * 2005-07-11 2007-05-02 삼성전기주식회사 Printed Circuit Board Having Embedded Electric Element and Fabricating Method therefor
US8101868B2 (en) 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
JP5188816B2 (en) 2005-12-16 2013-04-24 イビデン株式会社 Multilayer printed wiring board and manufacturing method thereof
JP5075424B2 (en) * 2007-02-19 2012-11-21 株式会社フジクラ Manufacturing method of wiring board with built-in electronic components
JP2008300560A (en) * 2007-05-30 2008-12-11 Sony Corp Semiconductor device, and manufacturing method thereof
KR101143837B1 (en) * 2007-10-15 2012-07-12 삼성테크윈 주식회사 Electronic chip embedded circuit board and method of manufacturing the same
KR100923501B1 (en) * 2007-11-13 2009-10-27 삼성전기주식회사 Manufacturing method of package board
JP5459134B2 (en) * 2009-07-31 2014-04-02 大日本印刷株式会社 Semiconductor package built-in wiring board and manufacturing method of semiconductor package built-in wiring board
JPWO2011089936A1 (en) * 2010-01-22 2013-05-23 日本電気株式会社 Functional element built-in board and wiring board
JP5333634B2 (en) * 2010-04-28 2013-11-06 株式会社デンソー Multilayer substrate manufacturing method
JP2012009828A (en) 2010-05-26 2012-01-12 Jtekt Corp Multilayer circuit board
JP2012074497A (en) * 2010-09-28 2012-04-12 Denso Corp Circuit board
JP2012186279A (en) * 2011-03-04 2012-09-27 Fujikura Ltd Laminated print circuit board incorporating electronic component and manufacturing method of the same
JP5354394B2 (en) * 2011-03-30 2013-11-27 Ｔｄｋ株式会社 Component built-in substrate and manufacturing method thereof
JP2013004576A (en) * 2011-06-13 2013-01-07 Shinko Electric Ind Co Ltd Semiconductor device
JP2015015350A (en) * 2013-07-04 2015-01-22 株式会社ジェイテクト Semiconductor device
CN206879237U (en) * 2014-09-26 2018-01-12 株式会社村田制作所 Layered module substrate and layered module
US9837484B2 (en) 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
WO2018066324A1 (en) * 2016-10-07 2018-04-12 株式会社村田製作所 Multilayer substrate
CN107068634A (en) * 2017-01-23 2017-08-18 合肥雷诚微电子有限责任公司 A kind of multi-chip power amplifier architecture for minimizing high-cooling property and preparation method thereof
CN108735678B (en) * 2018-07-27 2024-02-06 本源量子计算科技（合肥）股份有限公司 Quantum bare chip three-dimensional packaging structure and packaging method thereof
CN111200899B (en) * 2018-11-20 2023-09-15 奥特斯科技(重庆)有限公司 Component carrier and method for producing the same
CN111372369B (en) * 2018-12-25 2023-07-07 奥特斯科技(重庆)有限公司 Component carrier with component shielding and method for producing the same
DE102020111996A1 (en) 2020-05-04 2021-11-04 Unimicron Germany GmbH Process for the production of a printed circuit board and printed circuit board with at least one embedded electronic component
CN113543493B (en) * 2021-07-12 2023-05-09 上海嘉捷通电路科技股份有限公司 Preparation method of Z-direction interconnection printed circuit board

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