TWI307550B - Polygonal, rounded, and circular flip chip ball grid array board - Google Patents
Polygonal, rounded, and circular flip chip ball grid array board Download PDFInfo
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- TWI307550B TWI307550B TW095117543A TW95117543A TWI307550B TW I307550 B TWI307550 B TW I307550B TW 095117543 A TW095117543 A TW 095117543A TW 95117543 A TW95117543 A TW 95117543A TW I307550 B TWI307550 B TW I307550B
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- 238000002474 experimental method Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000011247 coating layer Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15162—Top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
1307550 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種覆晶球柵陣列(a flip chip ball grid array,以下稱為「覆晶BGA」)板,且特定係關於一 種藉由均勻地除去一四邊形板的多個角來使熱變形減至最 低的覆晶B G A板。
【先前技'術】 習知的封裝(亦即,藉由將一晶片黏接至一鉛框上,將 該晶片的襯墊與鉛相連,接續以樹脂密封)不僅體型大且 重,同時還需要足夠長度的連線以供架設用。為解決這些 問題,而研發了覆晶B G A封裝,其係將晶片黏接在環氧樹 脂或鈽板上,並以圓形焊球來取代鉛。 一典型覆晶BGA封裝的製作方法可參照附圖第1(a) 至1(h)來說明。 (a)在一半導體晶片1上形成鋁墊2,且以一保護層3 來覆蓋該半導體晶片1。(b)以濺鍍方式形成一金屬層 4 並與鋁墊2相連。(c)施加光阻5使得只有鋁墊2的區域 被暴露出來。(d)在未被光阻5所遮住的該鋁墊2的區域 上施加鉛塗層6。(e)將光阻5除去。(f)蝕刻除了有鉛塗 層 6的部分之外的區域來移除該金屬層 4。(g)加熱使錯 塗層 6變成球形。(h)將以上述方式製備的凸塊晶片 (bumped chip)與覆晶BGA板8相接合。接合方法包括在一 重流裝置中進行沉積,將該板8加熱至一高溫以熔化該鉛 5 1307550 塗層6,並讓該覆晶BGA板8的接觸墊10與該晶片1的 I呂塾2接觸。之後,利用一下填方法(an underfilling process) 並使用樹脂來填充該覆晶B G A板8與該晶片1之間的空 隙。
如以上所討論的,製造一覆晶B G A板時需使用到大量 的熱,例如在步驟(g)使鉛塗層6變成球形狀期間及在步驟 (h)的重流(reflow)期間。特別是在重流期間,因需將鉛塗 層6熔解,一般需用到約2 2 5 °C的高溫,其將造成該覆晶 BGA板8歪斜變形(warpage)。 第2圖為一傳統覆晶BGA封裝的示意圖。該習知的覆 晶BGA板8 —般係為四邊形。 第3圖示出在製造過程後該覆晶BGA板8上所出現的 歪斜變形情況。如第3圖所示,歪斜變形的程度以該覆晶 BGA板8的邊緣最嚴重,其因為受熱而變成往中央凹陷。 此因受熱所致的歪斜變形(如第3圖所示)在核心厚度約0.4 毫米或更少的薄板(如,UTFCB(超薄彈性電路板))上會更 明顯。 該覆晶BGA板8愈薄,其可能因受熱而產生的歪斜變 形的程度就愈嚴重。因此,雖然最近的趨勢傾向小尺寸、 多功能,但此因熱所致的歪斜變形不僅使其無法架設晶 片,也導致晶片容易自板上剝離。此外,此歪斜變形也變 成製造薄型板的一大挑戰。 【發明内容】 6 1307550 為解決上述問題,本發明方案之一係提供一種作成多 邊形、磨圓的或圓型的覆晶BGA板,以將因受熱所致的歪 斜變形降至最低。
依據本發明第一實施例,可藉由均勻地去除覆晶B GA 封裝用的一覆晶 BGA板上的各個角來使該板形成一多邊 形。因此,藉由除去一習知覆晶B G A板的每一個角,可使 該板因受熱所致的歪斜變形降至最低。可將該板製成許多 不同形狀,例如六角形或八角形。 在本發明第二實施例中,覆晶B G A封裝用的一覆晶 BGA板,可藉由將該板上的每一角磨圓使曲度半徑相等方 式(in equal radii of curvature)來製作。 在本發明第三實施例中,覆晶 BGA封裝用的一覆晶 BGA板可以是圓形的。 本發明其他的方案及優點將參照附圖詳述在以下的說 明中,或可藉由實施本發明得知。 【實施方式】 以下,將參照附圖進一步說明已去角的BGA板。 第4圖顯示依據本發明一實施例所製成的一磨圓的 (rounded)覆晶BGA板10。該覆晶BGA板10的四個角已 被均勻的磨圓。較佳是,每一角落的曲度半徑都相等或非 常類似,以儘可能防止因受熱所致的歪斜變形,使其降至 最低。在此,儘可能使曲度半徑變大,以使該板形狀儘可 能接近圓形,其係最能防止歪斜變形的形狀,此現象將在 7 1307550 實驗條件: 將中心部份厚度為0.1毫米且大小為3 7 . 毫米之聚合物類型的覆晶BGA板,堆疊成6 , °C開始降低溫度至2 5 °C。 毫米X 3 7.5 ,並從1 75
實驗情況1至3 測量該板因為熱而產生的歪斜變形程度, 況1所用的為一磨圓的覆晶BGA板10,實驗 的為一多邊形的覆晶BGA板20,且實驗情況 一圓形的覆晶BGA板30。 其中實驗情 情況2所用 3所用的為 比較實施例 測量一四邊形覆晶B G A板(如,第2圖的 因受熱所產生的歪斜變形程度。 晶BGA板)
實驗結果 每一實驗情況之覆晶 B G A板的歪斜變形 第7a-7c圖。比較實施例之四邊形覆晶BGA板 生的歪斜變形程度則繪示於第3圖。在第3、‘ ( + :)符號代表該板在往上方向的歪斜變形程度, 表該板在往下方向的歪斜變形程度。 如第1圖習知四邊形板,歪斜變形主要發 上0 程度繪示於 因受熱所產 7 a - 7 c圖中, 且(-)符號代 生在每一角 參照第7a-7c圖,多邊形覆晶BGA板(實驗情況2)因 1307550 受熱所產生的歪斜變形程度遠低於一磨圓的覆晶 BGA板 (實驗情況1)。此外,圓形覆晶B G A板(實驗情況3)因受熱 所產生的歪斜變形程度也遠低於一多邊形覆晶BGA板(實 驗情況2)。 相較於比較實施例,實驗情況1至3的相對歪斜變形 程度總結於下表1。 表1 板的形狀 相較於四邊形板的歪斜變形程度 磨圓(實驗情況1) 17.81% 多邊形(實驗情況2) 13.05% 圓形(實驗情況3 ) 12.61%
如表1所示,歪斜變形程度會隨著BGA板上的角的移 除(由磨圓至多邊形至圓形)而逐步下降。 依據本發明,提供一覆晶B G A板,其之角落已被均勻 地移除,使得因受熱所致之變形可減至最低。 有了本發明的覆晶BGA板,即可製作較薄的板,因為 因受熱所致之變形程度已被減至最低。再依據本發明,可 提供一高可靠性的覆晶B G A板,因為晶片可能自板上脫離 的風險已被減至最低。 本發明已參照實施例詳述如上,但是,習知技藝人士 在參閱本說明書後,可知其中尚有諸多等效變化及置換, 10 1307550 3 保護層 4 金屬層 5 光阻 6 鉛塗層 8 、 10 、 20 覆晶B G A板
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Claims (1)
1307550 _籮號蔚d案11年月修正 月/碣修(更)正本 十、申請專剩 1 . 一種覆晶BGA封裝用之覆晶BGA板,其中該板的 多個角被均勻地移除以形成一多邊形。 2.如申請專利範圍第1項所述之覆晶BGA板,其中該 覆晶BGA板為八邊形。
3. 一種覆晶BGA封裝用之覆晶BGA板,其中該板的 多個角被磨圓使其具有相同曲度半徑(in equal radii of curvature) ° 4. 一種覆晶BGA封裝用之覆晶BGA板,其中該板為 圓形。
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KR1020050062274A KR100652549B1 (ko) | 2005-07-11 | 2005-07-11 | 다각형, 라운드 및 원형 플립칩 볼 그리드 어레이 기판 |
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TW200703608A TW200703608A (en) | 2007-01-16 |
TWI307550B true TWI307550B (en) | 2009-03-11 |
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TW095117543A TWI307550B (en) | 2005-07-11 | 2006-05-17 | Polygonal, rounded, and circular flip chip ball grid array board |
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US (1) | US20070018335A1 (zh) |
JP (1) | JP2007027699A (zh) |
KR (1) | KR100652549B1 (zh) |
CN (1) | CN1897263A (zh) |
TW (1) | TWI307550B (zh) |
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US20080014911A1 (en) * | 2006-07-13 | 2008-01-17 | Jonathan William Medved | Group sharing of media content |
US10211175B2 (en) | 2012-11-30 | 2019-02-19 | International Business Machines Corporation | Stress-resilient chip structure and dicing process |
JP6269573B2 (ja) * | 2015-05-18 | 2018-01-31 | 株式会社デンソー | 半導体装置 |
US10090259B2 (en) * | 2015-12-26 | 2018-10-02 | Intel Corporation | Non-rectangular electronic device components |
KR20210028773A (ko) * | 2019-09-04 | 2021-03-15 | 삼성디스플레이 주식회사 | 표시 장치 |
KR20210138223A (ko) | 2020-05-12 | 2021-11-19 | 삼성전자주식회사 | 반도체 패키지 |
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JP3519453B2 (ja) * | 1994-06-20 | 2004-04-12 | 富士通株式会社 | 半導体装置 |
JP3550787B2 (ja) * | 1995-03-30 | 2004-08-04 | 株式会社エンプラス | Icソケット |
JP3170199B2 (ja) * | 1996-03-15 | 2001-05-28 | 株式会社東芝 | 半導体装置及びその製造方法及び基板フレーム |
US6166435A (en) * | 1998-12-10 | 2000-12-26 | Industrial Technology Research Institute | Flip-chip ball grid array package with a heat slug |
US6664620B2 (en) * | 1999-06-29 | 2003-12-16 | Intel Corporation | Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer |
TW565529B (en) * | 2002-01-24 | 2003-12-11 | Scs Hightech Inc | Probe card and method for testing the proceed function or speed of electronic devices |
-
2005
- 2005-07-11 KR KR1020050062274A patent/KR100652549B1/ko not_active IP Right Cessation
-
2006
- 2006-05-17 TW TW095117543A patent/TWI307550B/zh not_active IP Right Cessation
- 2006-06-08 CN CNA2006100833970A patent/CN1897263A/zh active Pending
- 2006-06-09 JP JP2006161238A patent/JP2007027699A/ja active Pending
- 2006-07-11 US US11/483,844 patent/US20070018335A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
KR100652549B1 (ko) | 2006-12-01 |
JP2007027699A (ja) | 2007-02-01 |
US20070018335A1 (en) | 2007-01-25 |
CN1897263A (zh) | 2007-01-17 |
TW200703608A (en) | 2007-01-16 |
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