TWI281734B - Wafer level chip-scale package and manufacturing method thereof - Google Patents
Wafer level chip-scale package and manufacturing method thereof Download PDFInfo
- Publication number
- TWI281734B TWI281734B TW090131218A TW90131218A TWI281734B TW I281734 B TWI281734 B TW I281734B TW 090131218 A TW090131218 A TW 090131218A TW 90131218 A TW90131218 A TW 90131218A TW I281734 B TWI281734 B TW I281734B
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- wiring
- size package
- conductive layer
- opening
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000000465 moulding Methods 0.000 claims abstract description 4
- 235000012431 wafers Nutrition 0.000 claims description 202
- 239000010410 layer Substances 0.000 claims description 49
- 229910000679 solder Inorganic materials 0.000 claims description 22
- 239000012790 adhesive layer Substances 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000012778 molding material Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 2
- 102100035353 Cyclin-dependent kinase 2-associated protein 1 Human genes 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 239000003292 glue Substances 0.000 abstract 2
- 239000010949 copper Substances 0.000 description 11
- 239000010936 titanium Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
128剛 1. 10 ip A7 B7 五、發明説明(1 ) 發明的技術領域 本發明係與封裝(package)以及其製造方法相關,更具體而 言,係與在晶圓狀態下,製造晶圓級晶圓尺寸封裝(wafer level chip scale package),以及其製造方法相關。 先前技術 如同一般廣為人知,將由晶圓的薄膜成長技法所製造的晶片 (chip),自晶圓切斷(sawing)分離之後,將所分離的晶片以屏 蔽(shield)或模塑以防止外部的濕氣或不純物質;尚且,將設置 有為與外部電路接續之引線之封裝型態予以商品化。 於該封裝中,以大部分空間由晶片佔據之規模,而將其模塑 化之晶圓尺寸的封裝本身,作為單一的微型元件(micro device) 而加以商品化,而在提高電路基板上之安裝密度、應用特定型 積體電路(ASIC : Application Specific 1C)等之各種積體電路 方面十分有用。 圖1係為顯TF先前的晶圓級晶圓尺寸封裝之剖面圖。 先前的晶圓級晶圓尺寸封裝,如圖1所示般,係由下列各項所 構成·形成多數晶片勢之晶圓狀態的半導體晶片100、在半導體 晶片100上與晶片墊102接續,且在延長的一部上具有球形地(圖 中未顯示)之金屬配線、在金屬配線的一部上所形成的 UBM(under-bump metallurgy)、為自夕卜部環境保護上述產物 之絕緣體、以及固定在球形地之上的導電性球。 該先前之晶圓級晶圓尺寸封裝的製造方法,如圖1所示一般, 首先在晶圓狀態之半導體晶片100上,將氧化矽以化學氣相蒸發 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 五、發明説明(2 ) 後,使晶片墊102露出且予以圖案蚀刻,形成第1絕緣膜106。 晶圓狀態的半導體晶片1〇〇,則形成晶片墊102以及形成在晶片 墊之間的保護膜104。 其後,在第1絕緣膜106上,將鈦(Ti)、或是釩(V)等之金屬藉 由丨賤射(sputtering)法蒸發之後,使晶片塾102露出,並圖案姓 刻而形成第1配線1 0 8。 其次,為使第1絕緣膜106之安裝的一部分露出,而加以圖案 蝕刻以形成第2絕緣膜110。 接著,在第2絕緣膜110上,將鈦(Ti)、或是釩(V)等之金屬藉 由濺射法蒸發後,將露出的第2絕緣膜部位覆蓋般地,選擇性的 蝕刻以形成第2配線112。於此之際,第2配線112藉由第1配線 108,與晶片墊102作電氣接觸,並成為其後固定導電性球之球 形地。 其次,將導電性球120固定於第2配線112之後,將導電性球 120安裝於基板140上,以完成封裝製造。 發明所欲解決之問題 惟於上述般的先前之技術中,將導電性球安裝於基板的情況 下’基板的熱膨服係數約為1 8 p p m ’而半導體晶片的熱膨腺係 數約為3〜4 ppm之故,由於上述熱膨脹係數之差,使得在與導 電性球相接的基板以及晶圓之介面上,會產生破裂的問題。 又,在先前的技術上,隨著2次之為使第1、第2配線形成之金 屬濺射步騾,也會產生使封裝製造程序複雜化的問題。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) I2817M4 t A7 B7 r jt- 五、發明説明(3 ) 從而,本發明之目的,係為解決上述以前技術的問題點,提 供一種晶圓級晶圓尺寸封裝以及其製造方法,其可以縮短為形 成配線之金屬濺射工程數,而使封裝製造單純化。 又,本發明之其他目的則在於提供一種晶圓級晶圓尺寸封裝 以及其製造方法,其可以藉由防止破裂之發生,而提高製品的 信賴性。 解決問題之手段 為達成上述目的,本發明之晶圓級晶圓尺寸封裝,其特徵為 具備下列各項:形成多數晶片墊的晶圓狀態之半導體晶片、為 使上述半導體晶片上之上述晶片墊露出而設置的開口部、在延 長的一部上具有球形地而形成的配線、介於上述半導體晶片與 上述配線之間的粘著層、使上述晶片墊與上述配線作電氣接觸 般,填充、覆蓋上述開口部之導電層、為使上述球形地露出, 覆蓋上述配線以及導電層的模塑體、固定於上述球形地的導電 性球、以及安裝有上述導電性球的基板。 又,為達成上述目的,本發明之晶圓級晶圓尺寸封裝,其特 徵為具備下列各項:形成多數晶片墊的晶圓狀態之半導體晶 片、為使上述半導體晶片上之上述晶片墊露出而設置的開口 部、在延長的一部上形成具有球形地的配線、介於上述半導體 晶片與上述配線之間的粘著層、為使上述晶片墊與上述配線作 電氣接觸,而形成填充、覆蓋開口部之導電層、為使上述球形 地露出,覆蓋上述配線以及導電層的模塑體、安裝有上述球形 地的基板、以及介於上述球形地與上述基板之間的焊料膠。 為達成上述目的,本發明之晶圓級晶圓尺寸封裝之製造方 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1281 1281
A7 B7 五、發明説明(4 ) 法,其特徵為具備下列各項:提供形成多數晶片墊的晶圓狀態 之半導體晶片的步騾、使粘著層介於上述半導體晶片之上,且 使上述晶片墊露出般地設置開口部、形成具有半蝕刻球形地之 配線的步騾、為使上述晶片墊與上述配線作電氣接觸,而形成 填充、覆蓋開口部之導電層之步騾、為使上述球形地露出而形 成覆蓋上述配線以及導電層的模塑體之步騾、在上述球形地之 上塗抹焊料膠並使導電性球固定之步騾、以及將上述導電型球 安裝於基板上之步騾。 又,為達成上述目的,本發明之晶圓級晶圓尺寸封裝之製造 方法,其特徵為具備下列各項:提供形成多數晶片墊的晶圓狀 態之半導體晶片的步騾、使粘著層介於上述半導體晶片之上, 形成具有使上述晶片墊露出所設置之開口部的配線之步騾、將 上述開口部予以半蝕刻,並形成球形地的步騾、為使上述晶片 墊與上述配線作電氣接觸,而形成填充、覆蓋開口部之導電層 之步騾、為使上述球形地露出而形成覆蓋上述配線以及導電層 的模塑體之步騾、使焊料膠介於基板上,將上述球形地安裝之 步騾、以及將上述球形地安裝於基板上之步騾。 發明之實施型態 其次,與本發明相關之晶圓級晶圓尺寸封裝及其製造方法, 其實施型態的具體實例,一面參照圖式,一面說明。 圖2係為本發明之第1實施例之晶圓級晶圓尺寸封裝的剖面 圖,圖3〜圖9係為說明第1實施例之晶圓級晶圓尺寸封裝的製造 程序的剖面圖。 本發明之第1實施例之晶圓級晶圓尺寸封裝,如圖2所示一 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1281 探4 A7
發明説明
\ .rlL 般’係由下列各項所構成:形成多數晶片塾2()2之晶圓狀態的半 導體晶片200、在半導體晶片2〇〇之上,使晶片墊2〇2露出所形 成的粘著層206、在粘著層2〇6上,為使晶片墊2〇2露出所設置 的開口部214、在延長的一部上具有球形地21〇所形成的配線 209、為使晶片墊202與配線209作電氣接觸,而填充、覆蓋開 口部214的導電層216、使球形地2 10露出般,覆蓋配線209以及 導電層216的模塑體230、以及固定在球形地21〇上的導電性球 220。 於此,配線209如圖10以及圖11所示一般,則成為接續下列 各項的接績配線212 :露出晶片墊2〇2的開口部214、使開口部 214成為環狀包圍著的金屬環(metal dng)2〇3、在延長的一部 上形成球形地210、金屬環2〇3、以及球形地21〇。 圖3至圖9係為說明本發明之第丨實施例之晶圓級晶圓尺寸封裝 之製造程序的剖面圖。 具有上述構造之本發明第1實施例之晶圓級晶圓尺寸封裝的製 造万法’如圖3所示一般,將在晶圓狀態之半導體晶片200上, 使晶片墊202露出而圖案化的粘著層2〇6,以低溫的熱壓著方式 黏附此時,在枯著層206上,則利用多硫亞氨(p〇iyimide)系 列的樹脂。 又’在晶圓狀態之半導體晶片200上,則形成覆蓋在多數晶片 墊202以及晶片墊2〇2之間的部分之絕緣層204。 其次,在粘著層206上,則黏附銅(Cu)金屬膜208。 接著’如圖4以及圖1〇所示一般,將銅(Cu)金屬膜2〇8選擇式 地蚀刻’形成使晶片墊202露出的開口部214。 -8- 本紙張尺度適财@ ®家榡準(CNS) A4規格(21〇 X 297公釐) 1281 A7 B7
-晋換頁 92. L 10 n /1 B 五、發明説明(6 ) 由於粘著層206係以低溫壓著方式而形成,因此形成配線用之 Cu金屬膜208不會受到因為熱而收縮等之影響。 其後,如圖5所示一般,將Cu金屬膜選擇性的半蝕刻(half etching)以形成配線209。 在上述配線209中,如圖11所示一般,經過以後之程序而形成 固定導電性球的球形地210、包圍晶片墊202的金屬環203、金 屬環203與球形地210接續的金屬配線212各自圖案化。 接著,如圖6所示一般,利用焊料注入裝置250,在開口部 214上擠壓焊料以形成焊料層214。 其後,如圖7所示一般,使焊料層2 14再流動,並形成接績晶 片墊202與配線209的導電層216。 其次如圖8所示,如覆蓋住包含配線209以及導電層216的成 品物般,將液狀封止材加以旋轉覆蓋後,使球形地210露出加以 圖案蝕刻,而形成模塑體230。模塑體230在球形地2 10與其相 鄰之球形地之間的部分(包含配線209以及導電層2 16的部分), 具有平坦的形狀。 其次,在球形地210上固定焊料球等的導電性球220之後,如 圖9所示,將導電性球220安裝在基板240上,便完成封裝製 造。 此時,在基板240與導電性球220之間,具備有電鍍層238。 圖12係為本發明之第2實施例的晶圓級晶圓尺寸封裝的剖面 圖。 本發明之第2實施例的晶圓級晶圓尺寸封裝,如圖12所示,係 由下列各項所構成:形成多數晶片墊302的晶圓狀態之半導體晶 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1281734 , / 〇,, i . V- A7 一———.............. …、 B7 五、發明説明(7 ) 片3 00、在半導體晶片300上露出晶片墊302而形成的粘著層 306、在粘著層306上為露出晶片墊3 02所設置之開口部314、在 延長的一部上為具有球形地3 10而形成的配線309、為使晶片墊 3 02與配線309作電氣接觸,填充、覆蓋開口部3 14之導電層 3 16、為使球形地3 10露出而覆蓋配線309以及導電層316,並具 有在球形地3 10與球形地之間的部分(覆蓋住球形地間的配線3 09 以及導電層316之空間)膨脹之凸面形狀的模塑體330、固定在球 形地310之導電性球320、以及介於基板340與導電性球320之間 的電鍍層33 8。 具有上述構造的本發明之第2實施例之晶圓級晶圓尺寸封裝的 製造方法,在將模塑體330旋轉覆蓋後,除下列各項以外,係與 本發明之第1實施例相同:在球形地310與球形地之間的部分(覆 蓋在球形地間的配線309以及導電層3 16的空間),形成具有凸面 形狀、以及使焊料膠338介於基板340與導電性球320之間。 上述模塑體則依下列之處理順序加以進行而形成:在球形地 3 10與球形地之間的部分(覆蓋住球形地間的配線3 09以及導電層 3 16之空間),具有凸面形狀將模塑物質加以旋轉覆蓋與打點處 理。 又,於基板340與導電性球320之間藉由焊料膠33 8之存在, 不僅可以強化基板340與導電性球320之間的粘著力,亦可以調 節封裝的厚度。 圖1 3係為本發明之第3實施例中的晶圓級晶圓尺寸封裝的剖面 圖。 本發明之第3實施例中的晶圓級晶圓尺寸封裝,如圖13所示, -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)
B7 五、發明説明(8 ) 係由下列各項所構成:形成多數晶片墊4〇2的晶圓狀態之半導體 晶片400、在半導體晶片4〇〇上露出晶片墊4〇2而形成的粘著層 406、在粘著層406上為露出晶片塾4〇2所設置之開口部4 14、在 延長的一部上為具有球形地41〇而形成的配線4〇9、為使晶片墊 402與配線409作電氣接觸,填充、覆蓋開口部414之導電層 416、為使球形地41〇露出而覆蓋配線4〇9以及導電層416之模塑 體430、固定球形地41〇的基板44〇、以及介於球形地41〇與基板 440之間的焊料膠438。 ,具有上述構成的本發明之第3實施例的晶圓級晶圓尺寸封裝之 製造方法,在不使用導電性球之情況下,將球形地41〇直接安裝 在基板440上,除了將焊料膠438介於球形地41〇與基板之間 外,其餘係與本發明之第丨與第2之實施例相同。又球形地41〇亦 已經電鍍處理。 發明之功效 如上述般,本發明係利用在基板上藉由粘著層黏附著形成配 線^之Cu金屬膜,使控制配線的厚度變得容易;無須別的濺射 工私,可使封裝的製造程序單純化,又使粘著層的厚度加厚, 可以確保烊料接缝的信賴性。 又,本發明由於係以低溫壓著方式形成粘著層,因此可以防 止配線用Cu金屬膜因為熱而收縮的現狀。 又,於本發明中,由於使焊料膠介於基板與導電性球之間, 了以使Cu金屬膜形成十分地厚,因此可以防止發生破裂。 接著,於本發明中,藉由以焊料射出方式形成與晶片墊接續 的導電層,可以確保高的電氣特性。 -11 - 本感«咖巾i^^(CNS) A4規格(21〇X297公董) -- 五、發明説明(9 ) 圈面之簡單說明 圖1係為顯示先前的晶圓級晶圓尺寸封裝之剖面圖。 圖2係為本發明之第1實施例之晶圓級晶圓尺寸封裝之剖面 圖。 圖3係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖4係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖5係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖6係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖7係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖8係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖9係為說明本發明之第1實施例之晶圓級晶圓尺寸封裝之製 造程序的剖面圖。 圖10係為顯示本發明之第1實施例的配線製作過程之斜面圖。 圖11係為顯示本發明之第1實施例的配線製作過程之斜面圖。 圖12係為本發明之第2實施例之晶圓級晶圓尺寸封裝之剖面 圖。 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
A7 B7 五、發明説明(10 ) 圖13係為本發明之第2實施例之晶圓級晶圓尺寸封裝之剖面 圖。 符號說明 200、300、400半導體晶片 202、302、402 晶片塾 203 金屬環 204、304、404 絕緣層 206 ' 306、406 粘著層 裝 208 銅(Cu)金屬膜 209、309 ' 409 配線 210、3 10、4 10 球形地 212 接續配線
214、314、414 開口部 215 焊料 216、316、416 導電層 220、320、420導電性球 230、330、430模塑體 240、340、440 基板 250 焊料注入裝置 238 電鍍層 33 8、438 焊料膠 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
Claims (1)
- 128 1^^^131218號專利申請案 中文申請專利範圍替換本(9 6年1月) 六、申請專利範園 1. 一種晶圓級晶圓尺寸封裝,其特徵為:包含一晶圓狀態半導 體晶片,其具有複數個晶片墊; 開口,其用以曝露該半導體晶片上的晶片墊; 一配線,在其延長部分上具有球形地; 一粘著層,其介於該半導體晶片與該配線之間;一導電 層,其用以填充與覆蓋該等開口,以將該等晶片墊電性連接 該配線; 一模塑體,其用以覆蓋該配線及該導電層以曝露該等球形 地; 導電球,其被固定在該等球形地上;及 一基板,其具有該等導電性球。 2. 如申請專利範圍第1項之晶圓級晶圓尺寸封裝,其中上述配線 係作為包圍上述開口部之金屬環之用,以及成為使上述金屬 環與上述球形地接續的接續配線。 3. 如申請專利範圍第1項之晶圓級晶圓尺寸封裝,其中上述導電 層的材質係為焊料。 4. 如申請專利範圍第1項之晶圓級晶圓尺寸封裝,其中尚且在上 述基板與上述導電性球之間具備有電鍍層。 5. 如申請專利範圍第1項之晶圓級晶圓尺寸封裝,其中尚且在上 述基板與上述導電性球之間具備有焊料膠。 6. —種晶圓級晶圓尺寸封裝,其特徵為:包含形成複數個晶片 塾之晶圓狀態的半導體晶片; 為使上述半導體晶片上之上述晶片墊露出所設置的開口 部、及在延長的一部上具有球形地而形成的配線; 75484-960117.DOC -1 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1281734 美· n/j A BCD ·:, Ί:* i 六、申請專利範圍 介於上述半導體晶片與上述配線之間的粘著層; 上述晶片墊與上述配線作電氣接觸而填充、覆蓋上述開口 部的導電層; 為使上述球形地露出而覆蓋上述配線及導電層的模塑體; 安裝上述導電性球的基板;及 介於上述球形地與上述基板之間的焊料膠。 7. 如申請專利範圍第6項之晶圓級晶圓尺寸封裝,其中上述配線 係作為包圍上述開口部之金屬環之用,以及成為使上述金屬 環與上述球形地接續的接續配線。 8. —種製造晶圓級晶圓尺寸封裝之方法,其特徵為:包含提供 形成多數晶片塾之晶圓狀態的半導體晶片步驟; 形成具有被半蝕刻之球形地及用以曝露該等晶片墊之開口 的配線之步驟,其中該步騾使該粘著層介於該配線與該半導 體晶片之間; 為使上述晶片墊與上述配線作電氣接觸,而形成填充、覆 蓋上述開口部的導電層之步驟; 為使上述球形地露出,而形成覆蓋上述配線以及導電層的 模塑體之步驟; 於上述球形地上塗抹焊料膠並使導電性球固定之步驟;及 將上述導電性球安裝在基板上的步驟。 9. 如申請專利範圍第8項之製造晶圓級晶圓尺寸封裝之方法,其 中尚且具有下列各步驟:在上述球形地形成之時,包圍上述 開口部的金屬環、將上述金屬環與上述球形地接續的接續配 線的形成步驟I。 75484-960117.DOC -2- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1281734 1正替換頁 年月’ ^曰 ABCD 六、申請專利範圍 10·如申請專利範圍第8項之製造晶圓級晶圓尺寸封裝之方法,其 中上述導電層係在上述開口部上以射出焊料方式擠壓形成。 11.如申請專利範圍第8項之製造晶圓級晶圓尺寸封裝之方法,其 中上述模塑體係以旋轉覆蓋方式而形成。 12·如申請專利範圍第8項之製造晶圓級晶圓尺寸封裝之方法,其 中上述模塑體,係將覆蓋上述球形地間的上述配線以及導電 層之空間,以及將模塑物質依照旋轉覆蓋以及打點處理的順 序實施,並且形出凸面。 13. —種製造晶圓級晶圓尺寸封裝之方法,其特徵為:包含提供 形成多數晶片塾之晶圓狀態的半導體晶片步驟; 形成具有用以曝露上述晶片的開口部之配線之步驟,其中 該步驟使該粘著層介於該配線與該半導體晶片之間; 將上述開口部被半蝕刻,並形成球形地步驟; 為使上述晶片墊與上述配線作電氣接觸,而形成填充、.覆 蓋開口部之導電層之步驟; 為使上述球形地露出,而形成覆蓋上述配線以及導電層的 模塑體之步驟; 使焊料膠介於基板間,並安裝上述球形地的步驟;及 將上述球形地安裝在基板上的步驟。 14. 如申請專利範圍第13項之製造晶圓級晶圓尺寸封裝之方法, 其中上述導電層係在上述開口部上,以射出焊料方式擠壓而 形成。 15. 如申請專利範圍第13項之製造晶圓級晶圓尺寸封裝之方法, 其中上述模塑體,係將覆蓋上述球形地間的上述配線以及導 75484-960117.DOC -3- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)8 8 8 8 A BCD 1281734 六、申請專利範圍 電層之空間,以及將模塑物質以旋轉覆蓋方式處理,而形成 平面狀。 75484-960117.DOC 本紙張尺度適用中國國家標準(CNS) A4規格(210 χ 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0032874A KR100412133B1 (ko) | 2001-06-12 | 2001-06-12 | 웨이퍼 레벨 칩크기 패키지 및 그의 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TWI281734B true TWI281734B (en) | 2007-05-21 |
Family
ID=19710707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090131218A TWI281734B (en) | 2001-06-12 | 2001-12-17 | Wafer level chip-scale package and manufacturing method thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US20020185743A1 (zh) |
JP (1) | JP4185688B2 (zh) |
KR (1) | KR100412133B1 (zh) |
TW (1) | TWI281734B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103928410A (zh) * | 2013-01-11 | 2014-07-16 | 精材科技股份有限公司 | 封装结构及其制作方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030042820A (ko) * | 2001-11-24 | 2003-06-02 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지, 그 제조방법 및 상기 반도체 패키지를적층한 적층형 반도체 패키지 |
TWI255568B (en) * | 2005-09-15 | 2006-05-21 | Chipmos Technologies Inc | Light emitting diode and fabricating method thereof |
JP4876618B2 (ja) * | 2006-02-21 | 2012-02-15 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
JP5080067B2 (ja) * | 2006-11-24 | 2012-11-21 | 新光電気工業株式会社 | 半導体装置の製造方法 |
KR101997022B1 (ko) * | 2012-01-26 | 2019-07-08 | 서울반도체 주식회사 | 발광 모듈 및 그것을 제조하는 방법 |
TWI512851B (zh) * | 2012-09-01 | 2015-12-11 | Alpha & Omega Semiconductor | 帶有厚底部基座的晶圓級封裝器件及其製備方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3362545B2 (ja) * | 1995-03-09 | 2003-01-07 | ソニー株式会社 | 半導体装置の製造方法 |
US5851911A (en) * | 1996-03-07 | 1998-12-22 | Micron Technology, Inc. | Mask repattern process |
KR100352112B1 (ko) * | 1996-12-06 | 2003-01-08 | 앰코 테크놀로지 코리아 주식회사 | 칩싸이즈반도체패키지의구조및그제조방법 |
JPH11145208A (ja) * | 1997-11-13 | 1999-05-28 | Seiko Epson Corp | 半導体装置 |
JP2000150703A (ja) * | 1998-11-06 | 2000-05-30 | Sony Corp | 半導体装置及びその組立方法 |
JP2000286283A (ja) * | 1999-03-30 | 2000-10-13 | Seiko Epson Corp | 半導体装置の製造方法 |
-
2001
- 2001-06-12 KR KR10-2001-0032874A patent/KR100412133B1/ko not_active IP Right Cessation
- 2001-12-17 TW TW090131218A patent/TWI281734B/zh not_active IP Right Cessation
- 2001-12-21 JP JP2001390603A patent/JP4185688B2/ja not_active Expired - Fee Related
- 2001-12-21 US US10/024,371 patent/US20020185743A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103928410A (zh) * | 2013-01-11 | 2014-07-16 | 精材科技股份有限公司 | 封装结构及其制作方法 |
CN103928410B (zh) * | 2013-01-11 | 2017-01-04 | 精材科技股份有限公司 | 封装结构及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100412133B1 (ko) | 2003-12-31 |
JP4185688B2 (ja) | 2008-11-26 |
US20020185743A1 (en) | 2002-12-12 |
KR20020094594A (ko) | 2002-12-18 |
JP2003007908A (ja) | 2003-01-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100222299B1 (ko) | 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법 | |
US6841853B2 (en) | Semiconductor device having grooves to relieve stress between external electrodes and conductive patterns | |
US6118183A (en) | Semiconductor device, manufacturing method thereof, and insulating substrate for same | |
US6717252B2 (en) | Semiconductor device | |
JP2000036509A (ja) | 半導体装置の製造方法 | |
JP2006310530A (ja) | 回路装置およびその製造方法 | |
JP2001110831A (ja) | 外部接続突起およびその形成方法、半導体チップ、回路基板ならびに電子機器 | |
JPH05251455A (ja) | 半導体装置 | |
TW200913216A (en) | Semiconductor device and manufacturing method thereof | |
TWI240977B (en) | Structure and formation method for conductive bump | |
TWI281734B (en) | Wafer level chip-scale package and manufacturing method thereof | |
TW200532750A (en) | Circuit device and method for making same | |
TWI588954B (zh) | 晶片封裝體及其製造方法 | |
JP3877150B2 (ja) | ウェーハレベル・チップスケール・パッケージの製造方法 | |
JP2003007906A (ja) | チップスケールパッケージ及びその製造方法 | |
JP2005217445A (ja) | 半導体装置の製造方法 | |
JPS62136049A (ja) | 半導体装置の製造方法 | |
JP5238929B2 (ja) | 半導体装置及びその製造方法 | |
KR100927749B1 (ko) | 반도체 디바이스 및 그 제조 방법 | |
KR100343454B1 (ko) | 웨이퍼 레벨 패키지 | |
JP4168494B2 (ja) | 半導体装置の製造方法 | |
JP2003017655A (ja) | 半導体実装体およびそれを用いた半導体装置 | |
KR20010004041A (ko) | 칩 사이즈 패키지의 제조 방법 | |
JP4817548B2 (ja) | 半導体装置およびその接続構造 | |
JPH0837204A (ja) | 半導体装置および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |