TWI281720B - Electronic part mounted body, method for manufacturing the same and optoelectronic device - Google Patents
Electronic part mounted body, method for manufacturing the same and optoelectronic device Download PDFInfo
- Publication number
- TWI281720B TWI281720B TW094111059A TW94111059A TWI281720B TW I281720 B TWI281720 B TW I281720B TW 094111059 A TW094111059 A TW 094111059A TW 94111059 A TW94111059 A TW 94111059A TW I281720 B TWI281720 B TW I281720B
- Authority
- TW
- Taiwan
- Prior art keywords
- bump
- substrate
- electronic component
- conductor
- exposed
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 55
- 230000005693 optoelectronics Effects 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 188
- 239000004020 conductor Substances 0.000 claims abstract description 115
- 229920005992 thermoplastic resin Polymers 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims description 72
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 230000001681 protective effect Effects 0.000 claims description 23
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- 238000010438 heat treatment Methods 0.000 claims description 10
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- 238000001312 dry etching Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 238000009434 installation Methods 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 3
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- 239000010408 film Substances 0.000 description 52
- 239000004973 liquid crystal related substance Substances 0.000 description 24
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- E—FIXED CONSTRUCTIONS
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- E02B—HYDRAULIC ENGINEERING
- E02B3/00—Engineering works in connection with control or use of streams, rivers, coasts, or other marine sites; Sealings or joints for engineering works in general
- E02B3/04—Structures or apparatus for, or methods of, protecting banks, coasts, or harbours
- E02B3/12—Revetment of banks, dams, watercourses, or the like, e.g. the sea-floor
- E02B3/14—Preformed blocks or slabs for forming essentially continuous surfaces; Arrangements thereof
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- G—PHYSICS
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- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
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- A01G—HORTICULTURE; CULTIVATION OF VEGETABLES, FLOWERS, RICE, FRUIT, VINES, HOPS OR SEAWEED; FORESTRY; WATERING
- A01G9/00—Cultivation in receptacles, forcing-frames or greenhouses; Edging for beds, lawn or the like
- A01G9/02—Receptacles, e.g. flower-pots or boxes; Glasses for cultivating flowers
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- E02D17/205—Securing of slopes or inclines with modular blocks, e.g. pre-fabricated
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G03F7/70—Microphotolithographic exposure; Apparatus therefor
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- G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- E—FIXED CONSTRUCTIONS
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- E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
- E02D2600/00—Miscellaneous
- E02D2600/20—Miscellaneous comprising details of connection between elements
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- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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- H—ELECTRICITY
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Description
(3) 1281720 板的凸塊的前端與導電焊墊之間產生樹脂殘渣,則有可能 凸塊與導電焊墊不會完全連接。於是,以往的技術在製造 電子零件安裝體時,爲了提高良品率及安裝效率,而必須 更加改善。 本發明是有鑑於上述情事而硏發者,其目的是在於提 供一種可容易且低成本及高電性可靠度來有效率地製造將 電子零件安裝於電路基板上而成的電子零件安裝體之方法 (用以解決課題的手段) 爲了解決上述課題,本發明之電子零件安裝體的製造 方法’係將具備作爲外部安裝端子的凸塊之電子零件安裝 於由熱可塑性樹脂所構成的基材, 其特徵係含: 凸塊埋設工程,其係對基材加熱推壓上述電子零件, # 藉此來將上述凸塊埋入上述基材,使上述凸塊的一部份露 出於與上述電子零件相反側的基材面;及 導電體形成工程,其係於上述凸塊的一部份露出的基 材面配置導電材料,藉此來形成與上述凸塊導電連接的導 電體。 若利用此製造方法,則首先會使電子零件的凸塊貫通 基材,而令凸塊的前端部露出於基材的相反面側,然後對 此露出後的凸塊形成所定平面形狀的導電體,因此可形成 一種可針對以任意的大小及間距所形成的凸塊來正確地對 -6- (4) 1281720 位之導電體,可使凸塊與導電體的導電連接構造之電性的 可靠度提高。 又,如先前專利文獻1所記載的技術,一邊對事先被 . 形成圖案的導電體進行對位,一邊進行凸塊的埋設時,導 電體或凸塊在狹間距化時,會有難以對位的問題,但在本 發明的製造方法中,由於基材與電子零件的對位不需要, 因此不會發生如此的對位問題。 φ 本發明的製造方法中,最好上述基材爲使用其厚度與 上述電子零件的凸塊之來自上述電子零件的表面的突出高 度同等或1 0 μηα以下厚度者,又,更理想是上述基材爲使 用其厚度與上述電子零件的凸塊之來自上述電子零件的表 面的突出高度同等或5 μπι以下厚度者。 在將上述基材的厚度形成上述範圍之下,對基材加熱 推壓電子零件時,基材會被熱溶著於形成於凸塊側的電子 零件的主動面,基材與電子零件的封接會更確實。 • 本發明之電子零件安裝體的製造方法,可在上述凸塊 埋設工程中,將上述凸塊埋入上述基材後,部份去除與上 述電子零件相反側的基材表面,藉此來使上述凸塊的一部 份露出於與上述電子零件相反側的基材面。 若利用此製造方法,則即使凸塊的突出高度或基材的 厚度產生不均,照樣可去除基材表面來使凸塊確實地露出 於基材面。並且,在加熱加壓狀態下,雖會因爲凸塊被壓 入’而使得在凸塊前端側的基材面產生凹凸,但藉由部份 去除基材表面,可使該凹凸平坦化,因此可提高凸塊與導 (5) 1281720 電體的連接構造的可靠度,且經由該基材來對其他電路基 板等的安裝也能以高可靠度來進行。 本發明之電子零件安裝體的製造方法中,最好部份去 除上述基材表面的工程爲化學硏磨工程或乾蝕刻工程。 若爲含該等處理的製造方法,則在去除基材的表面時 ,可高精度控制其去除量,因此可使凸塊的前端部良好地 露出於基材表面,且可容易控制成其露出高度不會過大。 0 本發明之電子零件安裝體的製造方法中,可在上述導 電體形成工程中,藉由金屬電鍍法來形成上述導電體。 藉由金屬電鍍法來形成導電體,可容易形成數μηι程 度的厚膜的導電體,因此處理速度及製造成本皆合適。 本發明之電子零件安裝體的製造方法中,可在上述導 電體形成工程之前,具有在含貫通上述基材而露出的凸塊 的一部份之基材面區域形成金屬基底膜的工程。 若利用此製造方法,則會因爲在凸塊與導電體之間介 # 在金屬基底膜,所以可提高凸塊與導電體的密著性,且上 述兩構件的材質的選擇範圍會擴大,因此導電體及凸塊的 低電阻化等的效果也可容易取得。此外,當複數個凸塊設 置於電子零件時,因爲會有金屬基底膜橫跨形成,所以凸 塊彼此形成短路的狀態,可有效防止在導電體形成工程中 的靜電所造成的電路破壊。 本發明之電子零件安裝體的製造方法中,可在上述金 屬基底Θ旲上藉由電解電鍍法來形成上述導電體,或藉由無 電解電鍍法來形成上述導電體。 (6) 1281720 導電體可藉由電解電鍍法或無電解電鍍法來形成,但 在具備上述金屬基底膜時,若藉由以該金屬基底膜作爲電 極使用的電解電鍍法來形成,則可提高導電體的形成效率 〇 本發明之電子零件安裝體的製造方法中,可在上述導 電體形成工程中包含: 在上述凸塊的一部份露出的基材面使光罩材形成圖案 φ 的工程;及 使用上述光罩材作爲光罩,在上述基材上選擇性配置 上述導電體的工程。 若利用此製造方法,則可容易形成具備所定平面形狀 的導電體。又’若將該光罩材形成於上述金屬基底膜上, 則可形成容易藉由以該金屬基底膜作爲電極的電解電鍍來 圖案化的導電體。 本發明之電子零件安裝體的製造方法中,可使上述光 # 罩材形成圖案的工程包含··在上述基材上配置光阻劑的工 程,及使該光阻劑曝光,顯像的工程; 且以貫通上述基材而露出的凸塊的一部份爲基準來進 行上述光阻劑的曝光。 若利用此製造方法,則因爲是對電子零件的凸塊來直 接進行對位’而來進行光罩材的形成,所以可極高精度形 成光罩材’因此所取得的導電體的位置精度亦佳。藉此, 可提高凸塊與導電體的連接構造之電性的可靠度。上述光 阻劑可使用塗佈於基材上的液狀者,或者在基材上當作疊 -9 - (7) 1281720 片使用的乾薄膜形態者。 本發明之電子零件安裝體的製造方法中,在進行上述 光阻劑的曝光時,爲了供以進行該曝光工程的對位,可以 設置於上述電子零件的基準凸塊作爲基準使用。 亦即,在貫通基材的凸塊中,可利用事先作爲基準凸 塊而設置的凸塊來進行曝光工程的對位。若利用如此的基 準凸塊’則在使連接導電體的凸塊形成微細化及狹間距化 時特別有效。亦即,機能相異的基準凸塊的尺寸或間距可 任意設定,因此可經常作爲對位的基準,成爲適當的基準 凸塊,進行高精度的對位。 本發明之電子零件安裝體的製造方法中,可使上述光 罩材形成圖案的工程包含:在上述基材上配置光阻劑的工 程,及使該光阻劑曝光,顯像的工程; 且以貫通上述基材而露出的凸塊爲基準來設置供以進 行上述光阻劑的曝光之基準標記。 亦即,只要曝光工程的對位基準是相對性地對凸塊進 行對位即可,因此可在離凸塊所配列的區域之位置設置基 準標記,對此來進行曝光的對位。 本發明之電子零件安裝體的製造方法,可在配置上述 光阻劑之前,具有形成保護構件的工程,該保護構件係覆 蓋貫通上述基材而露出的凸塊的一部份,且在含上述保護 構件的上述基材上形成上述光阻劑之後,具有去除上述保 護構件的工程; 且以藉由去除上述保護構件而露出的上述凸塊爲基準 -10- (8) 1281720 ,進行上述光阻劑的曝光。 此製造方法是事先藉由保護構件來遮蔽(masking ) 在光阻劑的曝光工程中作爲對位基準的凸塊’在塗佈光阻 劑之後剝離該保護構件而使凸塊露出’因此與對光阻劑的 下層側的凸塊進‘行對位時相較之下,可容易且高精度進行 對位作業。所以,若利用本製造方法,則可高精度形成上 述光罩材,進而能夠高精度形成導電體。 B 本發明之電子零件安裝體的製造方法中’最好在上述 凸塊埋設工程中,貫通上述基材而露出的凸塊的高度爲 1 μ m以上。 藉由使凸塊露出1 μηι以上的高度,可適於作爲先前 曝光工程的對位基準用。 其次,本發明是在於提供一種光電裝置的製造方法’ 其特徵爲直接或經由其他的電路基板來將藉由先前記載之 本發明的電子零件安裝體的製造方法所取得的電子零件安 # 裝體予以安裝於構成光電面板的基板上。 若利用此製造方法,則可容易製造一驅動電路等會以 高可靠度來安裝之光電裝置。 其次,本發明之電子零件安裝體,係於一面側具有導 電體的基材安裝有具備作爲外部安裝端子的凸塊之電子零 件,其特徵爲: 上述電子零件的凸塊爲貫通上述基材而露出至相反側 露出於上述基材表面的凸塊與上述導電體會經由金屬 -11 - (9) 1281720 基底膜來導電連接。 若利用此構成,則可提供一種能以高精度且高可靠度 來導電連接凸塊與導電體之電子零件安裝體。 . 其次,本發明可提供一種光電裝置’其特徵爲:先前 所記載之本發明的電子零件安裝體會直接或經由其他的電 路基板來安裝。 若利用此構成,則可提供一種具備具有可靠度佳的安 φ 裝構造的電子零件之光電裝置。 其次,本發明是在於提供一種具備先前記載之本發明 的電子零件安裝體,以及本發明的光電裝置之電子機器。 該電子機器可藉由對狹間距的凸塊高精度形成導電連接構 造之電子零件安裝體來取得高可靠度。具備該電子零件安 裝體’得以形成一具備由可實現高可靠度的光電裝置所構 成的顯示部。 # 【實施方式】 其次,參照圖面來説明本發明的實施形態。 在以下説明所參照的各圖面是表示本發明的各實施形 態的構成模式’其形狀或尺寸比爲適當變更顯示。 <電子零件安裝體的製造方法> 本發明之電子零件安裝體的製造方法,係將具備作爲 外部安裝端子的凸塊之電子零件安裝於由熱可塑性樹脂所 構成的基材’藉由連接基材表面的導電體與上述電子零件 -12- (10) 1281720 來取得電子零件安裝體之方法,其特徵係含: 凸塊埋設工程,其係一邊加熱上述電子零件的凸塊, 一邊推壓埋入上述基材’使該凸塊的一部份露出於上述基 材的相反側面;及 § 導電體形成工程’其係於上述凸塊的一部份露出的基 材面配置導電材料,藉此來形成與上述凸塊導電連接的導 電體。 φ 以下,說明本發明之電子零件安裝體的製造方法,但 在本說明書中是將本發明的製造方法分成前段的凸塊埋設 工程與後段的導電體形成工程來進行説明,在前段的凸塊 埋設工程的説明中是針對其第1實施形態〜第3實施形態 來進行說明,然後,在後段的導電體形成工程的説明中是 針對其第1實施形態及第2實施形態來進行說明。 (凸塊埋設工程;第1實施形態) φ 首先,參照圖1的剖面工程圖來說明有關本發明的實 施形態。以下,詳細說明有關本發明之電子零件安裝體的 製造方法中,凸塊埋設工程的第1實施形態。 本實施形態,首先,如圖1 ( a )所示,準備一具備 形成外部連接端子的複數個(圖示爲7個)凸塊1 1之1C 晶片(電子零件)1 〇,及由熱可塑性樹脂所構成的基材 1 3。此1C晶片1 0是藉由例如矽單結晶或化合物半導體單 結晶等的半導體基板,或於複數的陶瓷層之間夾著導體層 而積層的陶瓷基板等所構成,其凸塊Π形成面側爲形成 -13· (11) 1281720 具有電t電路構造的主動面。1C晶片〗〇的厚度,若:是半 導體基板’則爲1 0 0〜8 0 0 μ m程度’若是陶瓷基板,則爲 1〜5 m m程度。 凸塊1 1只要是由導電材料所形成者即可,但爲了推 壓埋入後述的基材1 3 ’$父理想是藉由具有充分強度的金 屬材料來形成。具體而言,可適用Cu,Ni,Au,Ag,Ai 等的金屬材料。或,亦可使用藉由電鍍法來形成由C u, φ Ni,A1等所構成的芯體,在此芯體的表面覆蓋au,Ag, S η等的薄膜之構成的凸塊1 1。凸塊1 1,例如寬度爲1 〇〜 20μηι程度,突出高度爲1〇〜25μηι程度,以15〜30μηι程 度的間距來形成於IC晶片1 0。並且,在設有凸塊1 1的 區域以外的I C晶片1 〇的主動面’由氧化矽或氮化矽等所 構成鈍化膜會以保護電路爲目的來形成。 基材1 3是由熱可塑性樹脂所構成,其構成材料可使 用聚酯樹脂,聚醯胺樹脂,芳香族聚酯樹脂,芳香族聚醯 Φ 胺樹脂,四氟乙烯’聚醯亞胺樹脂等。在本實施形態中, 基材13對凸塊11的突出高度而言是形成同等或稍微厚, 例如凸塊1 1的突出局度爲2 2 μ m時’最好爲2 2〜3 2 μ m的 範圍,更理想爲2 2〜2 7 ^m的範圍。在如此將基材1 3的 厚度形成與凸塊11的突出尚度同等或稍微厚之下’可使 凸塊1 1容易貫逋基材1 3 ’可有效率地進行後段的工程。 若基材1 3與凸塊1 1的突出高度同等或厚5 程度’則 熱可塑性樹脂的基材1 3會與1C晶片1 0的主動面溶著, 可使基材1 3與IC晶片1 〇的封接確實。 -14- (13) 1281720 〔凸塊埋設工程的第2實施形態〕 其次,參照圖2來説明凸塊埋設工 。在本實施形態中所使用的I C晶片(’ 材13是與圖1所示者大致同樣。本實 形態而言不同的地方是在於加熱推壓的 材面露出的露出方法。 首先,如圖2 ( a )所示,準備IC ,利用圖示省略的加熱推壓手段,如圓 1C晶片1 0對基材1 3推壓。如此一來, 1 3會被加熱至構成基材1 3的熱可塑性 ,因此凸塊11會被***基材13中。 本實施形態是針對上述實施形態的 使加熱温度降低所定量,以及使推壓時 此於加熱推壓後以基板能夠覆蓋凸塊之 其次,實施部份去除基材1 3之與 φ 側面(圖示下面)之處理。此處理可例 的化學硏磨法或使用電漿等的乾蝕刻法 等的方法,則可只以所望的量來去除基 藉由以上的工程,如圖2 ( d )所开 份會露出於基材1 3表面,在與基材面 於所定高度的階差1 1 a。由於本實施形 揷入後,藉由部份去除基材1 3的表面5 因此具有可高精度控制來自基材面之凸 的優點。又,若利用本實施形態的工程 程的第2實施形態 子零件)1 〇及基 施形態對上述實施 條件及自凸塊的基 晶片1 〇及基材13 3 2 ( b )所示,使 1C晶片10或基材 樹脂的軟化點以上 加熱推壓條件中, 間縮短所定量,藉 方式來加熱推壓。 1C晶片10呈相反 如藉由使用硏磨液 來進行,若利用該 材1 3的表面。 c,凸塊1 1的一部 之間,可形成控制 態是在凸塊1 1的 艮使凸塊1 1露出, 塊11的突出高度 ,則可有效防止因 -16- (14) 1281720 爲凸塊1 1的突出局度不均或基材丨3的厚度不均所造成凸 塊1 1的露出狀態不均。又,亦可實現圖案的高精度化。 又’由於凸塊1 1是藉由加熱推壓來***基材1 3,因 此有時被***凸塊1 1的周邊的基材1 3會大幅度變形,在 圖2 ( c )所示的狀態中,於基材1 3的下面產生仿效凸塊 1 1的凹凸,但如上述若部份去除基材1 3的表面,則可使 凸塊1 1露出’且可達成基材表面的平滑化,在後續的工 φ 程可容易且以高可靠度來導電連接凸塊11與導電體。 〔凸塊埋設工程的第3實施形態〕 其次,參照圖1來説明上述凸塊埋設工程的第3實施 形態。本實施形態中所使用的IC晶片(電子零件)1 0及 基材1 3是與圖1所示者同樣。本實施形態與第1實施形 態不同的點是在於先前第1實施形態所述的凸塊埋設工程 中更追加一藉由化學硏磨或乾蝕刻來部份去除基材表面的 • 工程。 本實施形態是藉由與圖1 ( a )〜(c )所示者同樣的 工程,對基材13***IC晶片1 0的凸塊1 1,使凸塊1 1 的前端部露出於基材1 3的相反側面(與1C晶片1 0呈相 反側的一面)。然後,實施部份去除露出凸塊Π的前端 部之基材1 3的表面的處理。此處理’可例如藉由使用硏 磨液的化學硏磨法或使用電漿等的乾餓刻法來進行’若利 用該等的方法,則可只以所望的量來去除基材1 3的表面 -17- (15) 1281720 由於凸塊l 1是藉由加熱推壓來***基材1 3 ’ 時被***凸塊π的周邊的基材1 3會大幅度變形’ (c )所示的狀態中,特別是在凸塊1 1的周邊會產 ,但若如上述部份去除基材1 3的表面,則可控制I 的露出高度,且可達成基材表面的平滑化,在後續 可容易且以高可靠度來導電連接凸塊11與導電體 ,先前的第2實施形態是藉由化學硏磨法或乾蝕刻 φ 未露出於基材1 3表面的凸塊1 1的前端部露出,但 形態是在事先使凸塊1 1的前端露出的狀態下進行^ 表面的部份去除,上述化學硏磨工程或乾蝕刻工程 時間與第2實施形態的方法相較之下可以短縮,進 謀求製造效率的提升。 又,若利用本實施形態的製造方法,則可高精 來自基材面之凸塊11的突出高度,且可有效防止 塊1 1的突出高度不均或基材1 3的厚度不均所造 φ 1 1的露出狀態不均。又,亦可實現圖案的高精度化 (導電體形成工程;第1實施形態) 其次,參照圖3及圖4來說明有關本發明之電 安裝體的製造方法中,導電體形成工程的第1實施 圖 3(a)〜(f),圖 4(a)〜(c)是表示連續 之剖面構成圖。 在以下的導電體形成工程中,使用一藉由圖1 所示工程取得的IC晶片1 0與基材1 3爲一體接合 因此有 在圖1 生凹凸 a塊11 的工程 。此外 法來使 本實施 g材1 3 的處理 而能夠 度控制 因爲凸 成凸塊 子零件 形態。 的工程 或圖2 的構件 -18- (16) 1281720 ,在本實施形態中是針對配置於1C晶片1 0的一面側的凸 塊1 1中,配置於圖示兩端的凸塊1 1 b,1 1 b爲不與後述的 導電體連接的虛擬凸塊來進行説明。此虛擬凸塊1 1 b亦於 基材1 3的表面露出其前端部,且在與基材面之間具有階 差 1 1 c 〇 首先,如圖3 ( a )所示,若藉由先前的凸塊埋設工 程來取得將1C晶片1 〇固定於基材1 3的構件,則會如圖 φ 3(b)所示,在露出凸塊11及虛擬凸塊lib的基材13的 表面(圖示上面)藉由濺鍍法或蒸鍍法來形成金屬基底膜 14。此金屬基底膜可使用 Cu,TiW,或Cr,Mo,MoW, Au,Ag等的金屬材料來形成。在後續的工程中,可發揮 使導電連接於凸塊1 1的導電體與凸塊1 1的密著性提高的 作用,且藉由電解電鍍法來形成導電體時可作爲電極用。 又,由於該金屬基底膜1 4會使凸塊1 1間形成短路,因此 在工程中即使發生靜電,照樣可以有效地保護1C晶片1 0 φ 的電路構造。 其次,如圖3 ( c )所示,以能夠覆蓋金屬基底膜14 之方式來塗佈光阻劑1 5。此光阻劑是形成在後續的工程 中用以將導電體形成圖案之光罩材。本實施形態中雖是針 對使用正片型的光阻劑時來進行説明,但亦可爲負片型的 光阻劑。 接著,如圖3 ( d )所示,對光阻劑1 5進行光罩曝光 ,而於光阻劑1 5中形成曝光部1 5 X。此曝光部1 5 X是形 成於包含凸塊Π上的區域之區域。 -19- (17) 1281720 在本實施形態的製造方法中,爲了形成光罩材,而對 光阻劑進行曝光時,會以突出於棊材1 3上的虛擬凸塊 1 1 b作爲曝光時的對位基準之基準凸塊使用。例如,只要 在虛擬凸塊1 1 b與基材1 3表面之間的階差1 1 c設定基準 點,而進行光阻劑1 5的光罩曝光,便可極高精度地形成 曝光部1 5x。藉此,可提高以圖案化的光阻劑1 5作爲光 罩材使用來形成導電體時之電性的可靠度。 φ 其次,如圖3 ( e )所示,對光阻劑1 5進行顯像,而 去除曝光部1 5x,在凸塊1 1上的區域形成開口部1 5a。此 刻,在凸塊1 1的位置,成膜於凸塊1 1上的金屬基底膜 14會露出。其次,如圖3 ( f)所示,利用電鍍法來對開 口部1 5a選擇性地配置Cu或Au,Sn等的金屬材料,形 成所定平面形狀的導電體16。在凸塊11上未形成有金屬 基底膜14時,基於與凸塊1 1的材質關係,導電體1 6的 形成材料的選擇範圍恐會有變窄之虞,但本實施形態中因 φ 爲設有金屬基底膜1 4,所以導電體1 6的形成材料可使用 各種的材料,且凸塊1 1與導電體1 6的連接構造之電性的 可罪度,亦不受限於兩者的構成材料,皆可提升。 其次,如圖4 ( a )所示,剝離光阻劑1 5,接著如圖 4 ( b )所示,從導電體1 6側來實施蝕刻處理,藉此來去 除基材13表面,及虛擬凸塊lib表面的金屬基底膜14。 其次’如圖4(c)所示,在導電體ι6的表面藉由電 解電鍍法等在保護絶緣膜以外的區域形成表面保護層^ 7 。只要在基材1 3上以既設的金屬基底膜1 4及導電體! 6 -20- (18) 1281720 作爲電極來進行電解電鍍’便可在導電體1 6的表面選擇 性地將表面保護層1 7形成所望的膜厚。此表面保護層1 7 是藉由Au等的安定金屬材料來形成Ο.ΟΙμηι〜〇·5μηι程度 的厚度。又,若藉由具有良好的導電性的材料來形成該表 面保護層1 7,則可降低與導電體1 6 —起構成的配線等的 電阻。 其次,在包含藉由表面保護層I7所覆蓋的導電體16 ,及虛擬凸塊1 1 b的區域塗佈形成保護絶緣膜2 5,取得 本發明的電子零件安裝體10P。 此保護絶緣膜2 5是因應所需而設置者。就不設置保 護絶緣膜2 5的形態而言,例如有利用基材1 3來將電子零 件安裝體1 0P與其他電路基板等接合時。此情況,是使設 有導電體1 6的一側之基材1 3的表面部份軟化或溶融,而 使固著於其他的電路基板,藉此可容易將該電子零件安裝 體1 op接合於其他的電路基板,進而能夠極爲有效率地安 # 裝電子零件。 〔導電體形成工程的第2實施形態〕 其次,參照圖5及圖6來說明有關導電體形成工程的 第2實施形態。圖5(a)〜(f) ’圖6(a)〜(e)是 表示連續的工程之剖面構成圖。 在本實施形態的導電體形成工程中,亦與上述實施形 態同樣使用IC晶片1 〇與基材1 3爲一體接合的構件。因 此,配置於1C晶片1 〇兩端的凸塊1 1 b,1 1 b是作爲曝光 -21 · (19) 1281720 時的基準凸塊使用的虛擬凸塊。 在本實施形態的導電體形成工程中,首先如圖5 ( a )所示,準備一 IC晶片1 0與基材1 3會經由凸塊1 1來一 體接合的構件,其次如圖5 ( b )所示,形成分別覆蓋虛 擬凸塊1 1 b,1 1 b的保護構件1 8,1 8。此保護構件1 8是 例如以遮蔽帶等可容易剝離者來構成。當虛擬凸塊1 1 b爲 極微細者時,雖難以貼著遮蔽帶,但由於虛擬凸塊1 1 b與 φ 凸塊Η機能相異,因此即使凸塊1 1狹間距化時亦不必微 細化,只要在離凸塊1 1某程度的位置具有充分的尺寸大 小,便不會有問題。 其次,如圖5 ( c )所示,以能夠覆蓋包含上述保護 構件1 8及凸塊1 1的基材1 3上之方式來形成金屬基底膜 1 4,接著以能夠覆蓋金屬基底膜1 4之方式來塗佈光阻劑 19。 其次,如圖5 ( d )所示,剝離虛擬凸塊1 1 b上的保 φ 護構件1 8。如此一來,積層於保護構件1 8上的金屬基底 膜1 4及光阻劑1 9的一部份會與保護構件1 8 —起被去除 ,露出虛擬凸塊lib,lib。 其次,如圖5 ( e )所示,以上述工程中所露出的虛 擬凸塊lib作爲基準凸塊用,進行光阻劑19的光罩曝光 ’在包含凸塊Π上的所定區域形成曝光部19x。本實施 形態是在虛擬凸塊1 1 b露出的狀態下進行利用其階差1 1 c 等的對位,因此與圖3所示先前實施形態的曝光工程相較 Z下’可局精度地定位曝光光罩,即使凸塊1 1是以狹間 -22 - (20) 1281720 距來配列,還是能夠在正確的位置形成曝光部1 9x < 其次,如圖5 ( f).所示,對光阻劑1 9進行顯 去除曝光部1 9x,在包含凸塊1 1上的區域形成開口 。藉由該曝光部1 9x的去除,在開口部1 9 a的底部 屬基底膜1 4。 其次,如圖6 ( a )所示,藉由電解電鍍法來 Cu等的金屬材料所構成的導電體20。之所以利用 φ 鍍法,那是因爲以金屬基底膜1 4作爲電極來成膜 容易形成對應於開口部1 9a的形狀的導電體20。 其次,如圖6 ( b )所示,去除光阻劑1 9,接 6 ( c )所示,去除基材1 3上的金屬基底膜1 4。金 膜1 4的一部份會殘留於導電體20的下層側,當作 1 1的密著層用。 其次,如圖6 ( d )所示,藉由電解電鍍法在 20的表面形成表面保護層2 1。此表面保護層2 1的 φ 與先前實施形態的表面保護層1 7同樣。如圖6 ( e ,在包含導電體16及虛擬凸塊11的基材13上的 成保護絶緣膜25,藉此取得本發明的電子零件安裝 〇 如以上詳細説明,本發明的製造方法,首先是 塊埋設工程中,使1C晶片1 0的仏塊1 1貫通於基才 使其前端部從基材1 3的表面突出,因此在後段的 成形工程的曝光處理時,能以從基材突出的凸塊1 基準來進行對位,因此可容易且高精度進行導電體 像,而 部19a 露出金 形成由 電解電 時,可 著如圖 屬基底 與凸塊 導電體 構成是 )所示 區域形 體1 0P 在其凸 才1 3, 導電體 1作爲 的選擇 -23- (21) 1281720 形成,藉此能以高電性可靠度來取得導通連接凸塊1 1與 導電體16的電子零件安裝體10P。 先前專利文獻1中所§己載的技術是針對基材中既設白勺 導電圖案對準凸塊來進丫了 ic晶片的安裝’因此當凸塊或 導電圖案被狹間距化時’該等對位的困難性會有顯著増加 的問題,但若利用本製造方法,則可針對露出於基材13 的表面的凸塊1 1以高位置精度來配置導電體1 6,即使凸 φ 塊1 1的配列間距狹窄’照樣能以充分的精度來配置導電 體16。 又,上述實施形態中,雖是說明有關以設置於1C晶 片1 〇的虛擬凸塊Η b作爲基準凸塊用來進行光阻劑的曝 光處理時,但當然亦可以和導電體1 6導電連接的凸塊1 1 的1個或複數個作爲基準凸塊用。又,亦可藉由雷射加工 等來將針對突出於基材1 3上的凸塊1 1對位的基準標記形 成於光阻劑1 5,針對該基準標記來進行曝光光罩的對位 <光電裝置> 其次,參照圖7〜圖1 1來說明有關本發明之光電裝 置的實施形態。 (第1構成例) 圖7是表示本發明之光電裝置的第1構成例的立體構 成圖,圖8是表示沿著圖7的B - B ’線之部份剖面構成圖 -24- (22) 1281720 圖7所示的.光電裝置〗〇 〇是具備藉由先前實施形態的 製造方法所取得的電子零件安裝體1 0 P。在此,電子零件 安裝體10P是最好在其電子構造區域包含一產生供以驅動 光電裝置的驅動信號之電路者(亦即,液晶驅動用1C晶 片的安裝體)。 本實施形態的光電裝置1 00爲液晶顯示裝置,如圖7 φ 及圖8所示,具備光電面板(液晶面板)π 〇,及安裝於 該面板的電路基板(可撓性配線基板)1 2 0。光電面板 1 1 〇是藉由密封材1 1 3來使由玻璃或塑膠等所構成的一對 基板1 1 1 1 1 2貼合,且在兩基板1 1 1與1 1 2之間封入液 晶(光電物質)1 1 4。在基板1 1 1的内面上,配列形成有 由ITO (銦錫氧化物)等的透光性導電材料所構成的複數 個畫素電極1 1 1 a,且於其上形成有配向膜1 1 1 b。此外, 在基板1 1 2的内面上形成有與上述同樣材料構成的透明電 φ 極112a,且於其上覆蓋配向膜112b。另外,雖圖示省略 ,但實際上可於基板Π 1及1 1 2的外面側配設偏光板或相 位差板。 另一方面,電路基板120具備在絶緣基材121的表面 (圖示下面)上由Cu等所構成的配線圖案1 2 1 a。絶緣基 材1 2 1是由環氧或聚醯亞胺等的熱硬化性樹脂,或聚酯, 聚醯胺,芳香族聚酯,芳香族聚醯胺,四氟乙烯,聚醯亞 胺等的熱可塑性樹脂所構成。配線圖案1 2 1 a是除了對光 電面板1 1 0之連接端子部1 2 1 b等的端子部份以外’藉由 -25- (24) 1281720 (第2構成例) 其次,參照圖9來說明有關本發明之光電裝置的第2 構成例。圖9是表示本構成例之光電裝置的部份剖面構成 圖,對光電裝置的全體構成而言,是相當於沿著圖7的 B-B’線之剖面構造。 光電裝置(液晶顯示裝置)200具有:光電面板210 φ ,及安裝於該面板的電路基板220。光電面板210具有與 上述第1構成例的光電面板1 1 0大致同樣的構造’由於基 板211,212,畫素電極 211a,透明電極212a,配向膜 2 1 1 b,2 1 2 b,配線2 1 1 c,密封材2 1 3,液晶(光電物質) 2 1 4,及各向異性導電膜2 1 7是與第1構成例所述者同樣 的構件,因此省略説明。但,本構成例中,電路基板2 2 0 所導電連接的輸入配線2 1 1 d是與配線2 1 1 c另外形成。 又,由於電路基板220中,絶緣基材221,配線圖案 φ 221a,連接端子部221b,保護膜222,連接焊墊部223, 224,225,226,及,電子零件 227,228,229也是與第 1構成例所述者同樣的構件,因此省略説明。 此構成例的光電裝置2 0 0與先前的構成例不同的點是 在於構成光電面板2 1 0的一方基板2 1 1的表面上直接安裝 上述電子零件安裝體10P。亦即,電子零件安裝體10P是 與上述同樣地針對引出至基板2 1 1的基板突出部上的配線 2 1 1 c及上述輸入配線2 1 1 d在使導電體3 5,3 6導電連接 的狀態下直接安裝於基板2 1 1。基板2 1 1是以玻璃或塑膠 -27- (25) 1281720 等所構成,在本實施形態中是將電子零件安裝體1 OP配置 於基板2 1 1上,藉由加壓加熱狀態來使由熱可塑性樹脂所 構成的基材1 3的表層部軟化或溶融,藉此來對基板2 1 1 密著固定。 又,由於本發明的電子零件安裝體10P係1C晶片10 的凸塊11與導電體35,36爲高精度且高可靠度連接,因 此可寄與提升光電裝置200的可靠度。 φ 又,由於本發明的電子零件安裝體10P可直接安裝於 光電面板2 1 0的基板2 1 1上,因此可在不使用各向異性導 電膜的情況下進行安裝,可降低安裝成本,且能夠有效率 地進行安裝。 (第3構成例) 其次,參照圖1 0來說明有關本發明之光電裝置的第 3構成例。圖1 0是表示本構成例之光電裝置的部份剖面 φ 構成圖,對光電裝置的全體構成而言,是相當於沿著圖7 的B-B’線之剖面構造。 光電裝置(液晶顯示裝置)3 0 0具有:光電面板3 1 0 ,及安裝於該面板的電路基板320。光電面板310具有與 上述第1構成例的光電面板Π 〇大致同樣的構造’由於基 板311,312,透明電極311a,畫素電極312a,配向膜 3 1 1 b,3 1 2 b,配線3 1 1 c,密封材3 1 3,液晶(光電物質) 3 1 4,及各向異性導電膜3 1 7是與第1構成例所述者同樣 的構件,因此省略説明。 -28 - (26) 1281720 又,由於電路基板3 2 0中,絶緣基材3 2 1,配線圖案 32U,保護膜3 2 2,連接焊墊部3 23,3 2 5,3 26,及,電 子零件3 2 7,3 2 8也是與第1構成例所述者同樣的構件, 因此省略説明。 此構成例之光電裝置3 00的形態是在光電面板3 1 0的 配線3 1 1 c,及電路基板3 2 0的連接焊墊3 2 3安裝電子零 件安裝體1 〇 P,其結果,電路基板3 2 0會經由電子零件安 φ 裝體10P來連接至光電面板310。在圖示例中,電子零件 安裝體1 0P的一端是與先前的第1實施形態同樣直接安裝 於電路基板3 20上,另一端是經由各向異性導電膜317來 導電連接至配線3 1 1 c。但,當然亦可將電子零件安裝體 1 0P的導電體3 5直接連接至配線3 1 1 c。 又,由於本發明的電子零件安裝體10P係1C晶片1〇 的凸塊Π與導電體35,36爲高精度且高可靠度連接,因 此可寄與提升光電裝置3 00的可靠度。 (第4構成例) 其次,參照圖1 1來說明有關本發明之光電裝置的第 4構成例。圖1 1是表示本構成例之光電裝置的部份剖面 構成圖,對光電裝置的全體構成而言,是相當於圖7的 B-B’線之剖面構造。 本例的光電裝置(液晶顯示裝置)40 0具有:光電面 板4 1 0,及安裝於該面板的電路基板4 2 0。光電面板4 1 0 具有與上述第2構成例的光電面板2 1 0大致同樣的構造, -29- (27) 1281720 由於基板411,412,透明電極411a,畫素電極412a,配 向膜4 1 1 b,4 1 2 b,配線4 1 1 c,密封材4 1 3,液晶(光電 物質)4 1 4,及各向異性導電膜41 7是與第2構成例所述 者同樣的構件,因此省略説明。 又’由於電路基板4 2 0中,絶緣基材4 2 1,配線圖案 421a,連接端子部421b,保護膜422,連接焊墊部423, 424,425’ 426,及,電子零件427,428,429也是與第 馨 2構成例所述者同樣的構件,因此省略説明。 此構成例的光電裝置400與第1構成例不同的點是在 於構成光電面板410的一方基板411的表面上直接安裝上 述電子零件安裝體10P,在電子零件安裝體10P的1C晶 片側基材面與電路基板420連接的這點是與第2構成例不 同。 電子零件安裝體10P是與上述同樣地針對引出至基板 4 1 1的基板突出部上的配線4 1 1 c在使導電體3 5導電連接 φ 的狀態下直接安裝於基板4 1 1。基板4 1 1是以玻璃或塑膠 等來構成,在本實施形態中是將電子零件安裝體1 0P配置 於基板4 1 1上,藉由加壓加熱狀態來使由熱可塑性樹脂所 構成的基材1 3的表層部軟化或溶融,藉此來對基扳4 1 1 密著固定。 此外,在電子零件安裝體10P設有與設於基材13表 面的導電體3 6連接的連接焊墊部3 6E。在該連接焊墊部 3 6E導電連接電路基板420的連接端子部421b。本構成例 是在光電面板411的基板411上直接安裝電子零件安裝體 -30- (28) Ϊ281720 1 OP,且於此電子零件安裝體10P安裝電路基板42 0,因 此具有一次完成對光電面板4 1 0的安裝之優點。 又’由於本發明的電子零件安裝體1 0P係1C晶片1 0 的凸塊11與導電體35,36爲高精度且高可靠度連接,因 此可寄與提升光電裝置4 0 0的可靠度。又,由於本發明的 電子零件安裝體10P可直接安裝於光電面板410的基扳 4 1 1上’因此可在不使用各向異性導電膜的情況下進行安 % 裝,可降低安裝成本,且能夠有效率地進行安裝。 <電子機器> 其次,參照圖1 2及圖1 3來說明有關本發明之電子機 器的實施形態。此實施形態是說明有關具備作爲顯示手段 的上述光電裝置(液晶裝置200 )之電子機器。 (第1構成例) # 圖12是表示本實施形態的電子機器之液晶裝置200 的控制系(顯示控制系)的全體構成的槪略構成圖。在此 所示的電子機器具有含顯示資訊輸出源29 1,顯示資訊處 理電路292,電源電路293,時序產生器294,光源控制 電路2 9 5的顯示控制電路2 9 0。並且,在與上述同樣的液 晶裝置2 0 0中設有驅動具備上述構成的液晶面板2 1 0的驅 動電路2 1 0D。此驅動電路2 1 0D是以上述直接安裝於液晶 面板2 1 0的電子零件安裝體1 0P的半導體1C晶片所構成 。但,驅動電路2 1 0D除了上述那樣的形態以外,亦可藉 -31 - (29) 1281720 由形成於面板表面上的電路圖案,或導電連接於液晶面板 的電路基板中所安裝的半導體I C晶片或電路圖案等所構 成。 顯示資訊輸出源291具備:ROM ( Read only memory )或R A Μ ( R a n d o m A c c e s s M e m ο ι· y )等所構成的記憶體’ 磁碟或光碟等所構成的儲存單元,及調諧輸出數位畫像信 號的調諧電路,且根據藉由時序產生器294所產生的各種 φ 時脈信號,以所定格式的畫像信號等的形式來供給顯示資 訊至顯示資訊處理電路292。 顯示資訊處理電路2 9 2具備:串列-並列變換電路’ 増幅 反轉電路,旋轉電路,加瑪補正電路,及箝位電路 等的習知各種電路,執行輸入後的顯示資訊的處理,然後 將該畫像資訊與時脈信號CLK 一起供應給驅動電路2 1 0D 。驅動電路2 1 0D包含掃描線驅動電路,信號線驅動電路 及檢查電路。並且,電源電路2 93會分別供應所定的電壓 礓^ 給上述各構成要素。 光源控制電路29 5會根據自外部導入的控制信號來將 由電源電路29 3所供給的電力供應給照明裝置2 8 0的光源 部28 1 (具體而言爲發光二極體等)。此光源控制電路 2 9 5會按照上述控制信號來控制光源部28 1的各光源的點 燈/非點燈。並且,可控制各光源的亮度。自光源部281 所放出的光會經由導光板2 8 2來照射至液晶面板2 1 0。 (第2構成例) -32- (30) 1281720 其次,圖1 3是表示本發明的電子機器之一實施形態 ,亦即行動電話的外觀。此電子機器1 3 0 0具有:顯示部 1 3 0 1,操作部1 3 0 2,受話部1 3 0 3,及送話部1 3 0 4,顯示 部1 3 0 1是藉由上述液晶裝置2 0 0來構成,因此具備與液 晶面板2 1 0連接的電路基板2 2 0。在顯示部1 3 0 1的表面 ’可視出藉由電路基板2 2 0上的IC晶片來驅動控制的液 晶面板2 1 0。 ^ 本發明並非僅限於上述圖示例,只要不脫離本發明的 主旨範圍,亦可實施各種的變更。例如,上述光電裝置除 了被動矩陣型以外,同樣可適用於主動矩陣型的液晶顯示 裝置(例如具備以TFT (薄膜電晶體)或TFD (薄膜二極 體)作爲開關元件的液晶顯示裝置)。又,並非限於液晶 顯示裝置’在電激發光裝置,有機電激發光裝置,電漿顯 示器裝置,電泳顯示器裝置,及使用電子放出元件的裝置 (Field Emittion Display 及 Surface-Conduction Electron-Φ Emitter Display )等各種的光電裝置中亦可同樣適用本發 明的電子零件安裝體,及光電裝置的製造方法。 【圖式簡單說明】 圖1是用以說明實施形態之凸塊埋設工程的剖面構成 圖。 圖2是用以說明同凸塊埋設工程之其他形態的剖面構 成圖。 圖3是用以說明實施形態之導電體形成工程的剖面構 -33- (31) 1281720 成圖。 圖4是用以說明實施形態之導電體形成工程的剖面構 成圖。 圖5是用以說明同導電體形成工程之其他形態的剖面 構成圖。 圖6是用以說明同導電體形成工程之其他形態的剖面 構成圖。 圖7是表示光電裝置之一構成例的^體構成圖。 圖8是表示沿著圖7的B-B’線的剖面構成圖。 圖9是表示光電裝置之第2構成例的剖面構成圖。 圖1 0是表示同第3構成例的剖面構成圖。 圖1 1是表示同第4構成例的剖面構成圖。 圖1 2是表示光電裝置的控制系的説明圖。 圖1 3是表示電子機器之一例的立體構成圖。 【主要元件符號說明】 1 0 :電子零件 1 1 :凸塊 1 1 a,1 1 c :露出部 j i b :基準凸塊 1 3 :基材 ! 4 :金屬基底膜 1 5,1 9 :光罩材 1 5 X,1 9 X ··曝光部 -34- (32) 1281720 15a 16, 17, 18: 25 : ,1 9 a :開口部 20 :電路圖案(導電體) 21 :表面保護層 保護構件 保護絶緣膜(密封構件)
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Claims (1)
1281720 (1) 十、申請專利範圍 第94 1 1 1 059號專利申請案 中文申請專利範圍修正本 民國95年7月20日修正 !· 一種電子零件安裝體的製造方法,係將具備作爲外 部安裝端子的凸塊之電子零件安裝於由熱可塑性樹脂所構 成的基材,
其特徵係含: 凸塊埋設工程,其係對基材加熱推壓上述電子零件, 藉此來將上述凸塊埋入上述基材,使上述凸塊的一部份露 出於與上述電子零件相反側的基材面;及 導電體形成工程,其係於上述凸塊的一部份露出的基 材面配置導電材料,藉此來形成與上述凸塊導電連接的_ 電體; 上述基材爲使用其厚度與上述電子零件的凸塊之來自上述 9^ 電子零件的表面的突出高度同等或10 μπι以下厚度者。 2·如申請專利範圍第1項的任一項所記載之電子零件 安裝體的製造方法,其中在上述凸塊埋設工程中,將上述 ^ 凸塊埋入上述基材後,部份去除與上述電子零件相反側的 ’ 基材表面,藉此來使上述凸塊的一部份露出於與上述電子 零件相反側的基材面。 3.如申請專利範圍第2項之電子零件安裝體的製造方 法,其中部份去除上述基材表面的工程爲化學硏磨工程或 乾蝕刻工程。 (2) 1281720 4.如申請專利範圍第1〜3項的任一項所記載之電子 零件安裝體的製造方法,其中在上述導電體形成工程中, 藉由金屬電鍍法來形成上述導電體。 5 ·如申請專利範圍第1〜3項的任一項所記載之電子 零件安裝體的製造方法,其中在上述導電體形成工程之前 ,具有在含貫通上述基材而露出的凸塊的一部份之基材面 區域形成金屬基底膜的工程。
6.—種電子零件安裝體的製造方法,係將具備作爲外 部安裝端子的凸塊之電子零件安裝於由熱可塑性樹脂所構 成的基材, 其特徵係含: 凸塊埋設工程,其係對基材加熱推壓上述電子零件, 藉此來將上述凸塊埋入上述基材,使上述凸塊的一部份露 出於與上述電子零件相反側的基材面;及 導電體形成工程,其係於上述凸塊的一部份露出的基 材面配置導電材料,藉此來形成與上述凸塊導電連接的導 電體; 在上述導電體形成工程之前,有在包含貫通前述基材而露 出的凸塊的一部份之基材面區域形成金屬基底膜的工程, 在上述金屬基底膜上藉由電解電鍍法來形成上述導電體。 7.—種電子零件安裝體的製造方法,係將具備作爲外 部安裝端子的凸塊之電子零件安裝於由熱可塑性樹脂所構 成的基材, 其特徵係含: -2- (3) 1281720 凸塊埋設工程,其係對基材加熱推壓上述電子零件, 藉此來將上述凸塊埋入上述基材,使上述凸塊的一部份露 出於與上述電子零件相反側的基材面;及 導電體形成工程,其係於上述凸塊的一部份露出的基 材面配置導電材料,藉此來形成與上述凸塊導電連接的導 電體; 藉由無電解電鍍法來形成上述導電體。
8 ·如申請專利範圍第1〜3項的任一項所記載之電子 零件安裝體的製造方法,其中在上述導電體形成工程中包 含·: 在上述凸塊的一部份露出的基材面使光罩材形成圖案 的工程;及 使用上述光罩材作爲光罩,在上述基材上選擇性配置 上述導電體的工程。 9 · 一種電子零件安裝體的製造方法,係將具備作爲外 ^ 部安裝端子的凸塊之電子零件安裝於由熱可塑性樹脂所構 成的基材, 其特徵係含: 凸塊埋設工程,其係對基材加熱推壓上述電子零件, * 藉此來將上述凸塊埋入上述基材,使上述凸塊的一部份露 出於與上述電子零件相反側的基材面;及 導電體形成工程,其係於上述凸塊的一部份露出的基 材面配置導電材料’藉此來形成與上述凸塊導電連接的導 電體; -3- (4) 1281720 於上述導電體形成工程,具有:在上述凸塊的一部份露出 的基材面使光罩材形成圖案的工程,與將前述光罩材做爲 遮罩使用,而選擇性將上述導電體配置於上述基材上之工 程; 使上述光罩材形成圖案的工程包含:在上述基材上配置光 阻劑的工程,及使該光阻劑曝光,顯像的工程,
以貫通上述基材而露出的凸塊的一部份爲基準來進行 上述光阻劑的曝光。 10·如申請專利範圍第9項之電子零件安裝體的製造 方法,其中在進行上述光阻劑的曝光時,以設置於上述電 子零件的基準凸塊爲基準來進行對位。 1 1 · 一種電子零件安裝體的製造方法,係將具備作爲 外部安裝端子的凸塊之電子零件安裝於由熱可塑性樹脂所 構成的基材, 其特徵係含: ^ 凸塊埋設工程,其係對基材加熱推壓上述電子零件, 藉此來將上述凸塊埋入上述基材,使上述凸塊的一部份露 出於與上述電子零件相反側的基材面;及 導電體形成工程,其係於上述凸塊的一部份露出的基 ^ 材面配置導電材料,藉此來形成與上述凸塊導電連接的導 電體; 於上述導電體形成工程,具有:在上述凸塊的一部份露出 的基材面使光罩材形成圖案的工程,與將前述光罩材做爲 遮罩使用’而選擇性將上述導電體配置於上述基材上之工 -4 - (5) (5)
1281720 程; 使上述光罩材形成圖案的工程包含:在上述基材上配置光 阻劑的工程,及使該光阻劑曝光,顯像的工程, 以貫通上述基材而露出的凸塊爲基準來設置供以進行 上述光阻劑的曝光之基準標記。 12.如申請專利範圍第1〜3項的任一項所記載之電子 零件安裝體的製造方法,其中在上述凸塊埋設工程中,貫 通上述基材而露出的凸塊的高度爲Ιμιη以上。 1 3 .如申請專利範圍第1 0或1 1項之電子零件安裝體 的製造方法,其中在配置上述光阻劑之前,具有形成保護 構件的工程,該保護構件係覆蓋貫通上述基材而露出的凸 塊的一部份,且在含上述保護構件的上述基材上形成上述 光阻劑之後,具有去除上述保護構件的工程, 以藉由去除上述保護構件而露出的上述凸塊爲基準, 進行上述光阻劑的曝光。 14· 一種光電裝置,係電子零件安裝體直接或者透過 其他電路基板被安裝而成的光電裝置,其特徵爲上述電子 零件安裝體於一面側具有導電體的基材安裝有具備作爲外 部安裝端子的凸塊之電子零件, 上述電子零件的凸塊 爲貫通上述基材而露出至相反側, 露出於上述基材表面的凸塊與上述導電體會經由金屬 基底膜來導電連接。 -5-
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US9148957B2 (en) * | 2011-03-04 | 2015-09-29 | Sharp Kabushiki Kaisha | Electronic circuit substrate, display device, and wiring substrate |
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