1278264 九、發明說明： 【發明所屬之技術領域】 技術領域 本發明係有關於一種配線基板之製造方法，詳而言 5 之，係有關於可對形成於配線基板之配線圖案之外表面進 行所需之無電解電鍍的配線基板製造方法。 【先前技術】 背景技術 第6圖顯示在核心基板10兩面形成有配線層12之印刷 10 電路板的結構例。圖示例之配線層12係隔著絕緣層13積層 配線圖案14而形成者。又，配線圖案14係透過通孔15在層 間電氣連接。 印刷電路板的最外面形成有包含連接用端子等配線圖 案，且該等配線圖案之所需部位表面形成有鎳電鍍層或金 15 電鍍層等。又，該等電鍍層係為了防止配線表面氧化、確 保金製電線之線結合性等而作成者。 對形成於配線基板表面之端子等配線圖案進行鎳電鍍 或金電鍍等方法有以無電解電鍍來進行電鍍和以電解電鍍 來進行電鍍兩種。 20 以無電解電鍍來進行電鍍的方法有如第11圖所示及如 第7A圖所示者。第11圖顯示在絕緣層13的表面形成配線圖 案14後，將防焊油墨16塗佈在基板表面，並使防焊油墨16 之圖案形成後再進行電鍍的方法。第7A圖顯示在絕緣層13 的表面形成端子等配線圖案14後，僅進行無電解電鍍而對 1278264 配線圖案14之露出部分進行電鍍的方法。 專利文獻1特開2003-188496號公報 【發明内容】 發明揭示 5 如第11圖所示，使用防焊油墨16後再以無電解電鐵對 配線圖案14進行電鍍的方法存在著一個問題，即，形成配 線圖案14之精密度會受制於防焊油墨16曝光及顯像後形成 圖案之精密度。又，形成防焊油墨16之圖案之精密度(解折 度）約為ΙΟΟμιη，因此，比這更細微的圖案，如在配線圖案 10 14之配線間隔為40μιη等時，就不能使用防焊油墨形成圖案 後再進行電錢的方法。 另外，如第7Α圖所示，於絕緣層13的表面形成配線圖 案14後直接對配線圖案14的表面進行電鍍的方法中，如第8[Technical Field] The present invention relates to a method of manufacturing a wiring board, and more specifically to a surface of a wiring pattern formed on a wiring board. A method of manufacturing a wiring board that requires electroless plating. [Prior Art] Fig. 6 shows a configuration example of a printed circuit board in which a wiring layer 12 is formed on both surfaces of a core substrate 10. The wiring layer 12 of the example is formed by laminating the wiring pattern 14 via the insulating layer 13. Further, the wiring pattern 14 is electrically connected to the layers through the through holes 15. A wiring pattern including a terminal for connection is formed on the outermost surface of the printed circuit board, and a nickel plating layer or a gold plating layer is formed on the surface of a desired portion of the wiring pattern. Further, these plating layers are formed to prevent oxidation of the wiring surface, ensure the wire bonding property of the gold wires, and the like. Nickel plating or gold plating is performed on a wiring pattern such as a terminal formed on the surface of the wiring board, and plating is performed by electroless plating and electroplating. 20 The method of electroplating by electroless plating is as shown in Fig. 11 and as shown in Fig. 7A. Fig. 11 shows a method in which the wiring pattern 14 is formed on the surface of the insulating layer 13, and the solder resist ink 16 is applied on the surface of the substrate, and the pattern of the solder resist ink 16 is formed and then electroplated. Fig. 7A shows a method of plating the exposed portion of the 1278264 wiring pattern 14 by electroless plating only after the wiring pattern 14 such as a terminal is formed on the surface of the insulating layer 13. Patent Document 1 JP-A-2003-188496 DISCLOSURE OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION As shown in Fig. 11, there is a problem in the method of plating the wiring pattern 14 with electroless iron after using the solder resist ink 16, that is, The precision of forming the wiring pattern 14 is subject to the precision of pattern formation after exposure and development of the solder resist ink 16. Further, the precision (deflection degree) of the pattern in which the solder resist ink 16 is formed is about ΙΟΟμιη, and therefore, a finer pattern than this, such as when the wiring interval of the wiring pattern 10 14 is 40 μm, etc., the solder resist ink cannot be used. A method of making money after forming a pattern. Further, as shown in Fig. 7, a method of directly plating the surface of the wiring pattern 14 after forming the wiring pattern 14 on the surface of the insulating layer 13, as in the eighth
利用前述製辭_，可進行使電職制更容易析 2觸媒處理，作為於絕緣層13的表轉成魏保護層之 别处理，諸而謂是崎將__㈣在絕緣層时 面所進行之處理。Χ ’吸附在絕緣層13表面之_媒核會 圖所示，進行使電鍍保護層形成於絕緣層13表面之無電解 15電鑛(步驟1) ’且在基板上塗佈感光性総劑，並形成感光 性光阻劑圖案’以露出形成配線圖案14的部位(步驟2)，再 將電鍍保護層作為電鍍饋電層來進行電解銅電鑛，以形成 配線圖案14(步驟3)，然後將感光性光阻劑除去(步驟4)，再 藉祕刻除去電鍍保護層基板露出在外面的部位(步 最後再進行無電解鎳電鍍及無電解金電鑛(步獅）。 !278264 ^藉由餘刻來除去⑽健層基板露出在外面的部位(步 驟5)時與㈣保護層1被除去。但是，為提高配線圖案 14與絕緣層13之間的密著性，絕緣層13的表面已預先進行 過表面粗化處理，故無法藉由蝕刻處理來除去進入絕緣層 13表面之粗化面内部的觸媒核，而有觸媒核殘留在絕緣層 13表面的情形。 m緣層13表面有觸_殘留的㈣下進行無電解 • 金電鍍(步驟6)的話，電鍍層就會附著在鄰接之配線圖 案Η中間，即原本未使電錢層㈣在絕緣層郎面的部 10 、势 位，導致鄰接之配線圖案14間產生短路等問題。 ’ π f7B圖說明性地顯示絕緣層13的表面形成粗化面，且 一 彖層13上有不必要之電錄層18a附著在鄰接之 14間的狀態。 15 20 第9圖係顯示從配線圖案的截面方向來看電鍵層附 在配線圖賴之狀態_面照片，而第糊係顯示有不 要之樹脂附著在配線_間之《的電子紐鏡照片。 门、絕緣層13的表面之所以會有不必要之電鐘層附著， 二為以對配線圖案14表面進行電鍍形成無電解電鍍層的 =，若_電解電鑛則配線圖_間之絕緣層13表面就 :析出不必要之電鑛層。然而，在進行電解電錢時，會 生必須將f顧之料線路連接於各配線圖 案14上、必 保用來在基板形成讀電線路的區域，及必須在進行電 電錢後將饋電線路和案斷路等麻煩。 本發明係為解決這些問題而作成者，並以提供即使 7 1278264 密度地形成配線圖案時，也能藉由無電 =购案之外表面進行電錢的配線基板之㈣ 5 10 15 20 為達成前述目的，本發明包含有以下步驟。By using the above-mentioned vocabulary _, it is possible to make the electric service system more susceptible to the analysis of the two catalysts, and to perform the process of converting the surface of the insulating layer 13 into the Wei protective layer, which is said to be the surface of the insulating layer when the insulating layer is __(4) Processing. Χ ' adsorbed on the surface of the insulating layer 13 as shown in the figure of the dielectric layer, the electroplating protective layer is formed on the surface of the insulating layer 13 of electroless 15 electric ore (step 1) 'and a photosensitive tincture is coated on the substrate, And forming a photosensitive photoresist pattern ' to expose a portion where the wiring pattern 14 is formed (step 2), and then electroplating the protective layer as a plating feed layer to perform electrolytic copper ore to form the wiring pattern 14 (step 3), and then The photosensitive photoresist is removed (step 4), and the electroplated protective layer substrate is exposed to the outer portion by the secret engraving (the step is followed by electroless nickel plating and electroless gold ore (step lion). !278264 The protective layer 1 is removed from the (4) exposed portion (step 5) and the (four) protective layer 1 is removed by the remainder. However, in order to improve the adhesion between the wiring pattern 14 and the insulating layer 13, the surface of the insulating layer 13 Since the surface roughening treatment has been performed in advance, the catalyst core that has entered the inside of the roughened surface of the surface of the insulating layer 13 cannot be removed by the etching treatment, and the catalyst core remains on the surface of the insulating layer 13. The m-edge layer 13 The surface has a touch _ residual (four) under the electroless In the case of electroplating (step 6), the plating layer adheres to the middle of the adjacent wiring pattern ,, that is, the portion 10 of the insulating layer (4) is not in the insulating layer, and the potential is generated, resulting in a short circuit between the adjacent wiring patterns 14. The problem is that the surface of the insulating layer 13 is illustratively shown to have a roughened surface, and an unnecessary layer 18a is attached to the adjacent 14 in a layer 13 of the adjacent layer. 15 20 Fig. 9 shows The electric contact layer is attached to the state of the wiring pattern from the cross-sectional direction of the wiring pattern, and the second paste shows the electron photon of the unnecessary resin attached to the wiring. The surface of the door and the insulating layer 13 The reason is that there is an unnecessary connection of the electric clock layer, and the second is to form an electroless plating layer by electroplating the surface of the wiring pattern 14. If the electrolysis ore is used, the surface of the insulating layer 13 between the wiring patterns is: unnecessary precipitation The electric ore layer. However, when electrolyzing the electricity money, it is necessary to connect the material line of the material to each wiring pattern 14, and it is necessary to use the area for forming the reading line on the substrate, and the electric power must be made. After the feeder line and the case The present invention is made in order to solve these problems, and to provide a wiring board capable of performing electricity money on the surface other than the electricity-free purchase case even when a wiring pattern is formed at a density of 7 1278264 (4) 5 10 15 20 To achieve the foregoing objects, the present invention encompasses the following steps.
解二進行觸媒處理之絕緣層表面進行無電 來形成電鍍保護層;於該電鍍保護層表面形成J 广光阻劑圖案作為光罩電解電_電鍍俾臂 形成配線圖案;及在將前述光阻二 =去後^核鐘保護層之露出部位除去，再利心 鑛對财述配線圖案之外表面進行無電解電鑛者，二 在將前述電鑛保護層之露出部位除去後，利用 /、向〖生乾姓刻對前述絕緣芦 + 用益電解⑽部位進行蝕刻，然後利 …電解屯錢對料配線圖案之外表面進行電鑛者 把觸2，在對前述絕緣層表面進行表面粗化處理後，使 又=附在前述絕緣層表面，作為前述觸媒處理。 错由热電解鋼電财形成钱保護層。 前述行無電解鎳電鍍和無電解金電鍍作為對 配線圖案之/表面進行之無電解電鍍的方法，可提高 發明效果 分的耐錄，謂獲得良好之線結合性。 露出部分2明之配線基板之製造方法，將電娜護層之 部分進^後’藉由異向性祕刻對絕緣層之露出 錢層附著/，可在對配線_之外表面進行電鐘時讓電 '巴緣層表面以防止配線圖案短路。藉此，即使 8 1278264 在高密度地形成配線圖案時，也能防止配線圖案短路，而 可確實地對配線圖案進行無電解電鍍之電鍍。 圖式簡單說明 第1A圖至第1F圖係顯示本發明之配線基板之製造方 5 法的說明圖。 第2A圖、第2B圖係顯示本發明之配線基板之製造方法 的說明圖。 第3圖係顯示本發明之配線基板之製造方法的流程圖。 第4圖係顯示進行異向性乾蝕刻後絕緣層之狀態的截 10 面照片。 第5圖係顯示相對於絕緣層之蝕刻量而殘留在絕緣層 表面之把量的圖表。 第6圖係顯示配線基板之截面圖。 第7A圖、第7B圖係顯示對配線圖案進行無電解電鍍前 15 後之狀態的說明圖。 第8圖係顯示習知配線基板之製造方法的流程圖。 第9圖係顯示無電解電鍍層附著在絕緣層表面之狀態 的截面照片。 第10圖係顯示無電解電鍍層附著在絕緣層表面之狀態 20 的電子顯微鏡照片。 第11圖係顯示將防焊油墨塗佈在絕緣層表面後再對配 線圖案表面進行電鍍之習知方法的說明圖。 【實施方式】 實施發明之最佳形態 1278264 第1A圖至第IF圖、第2A圖、第2B圖係顯示本發明之配 線基板之製造方法的製造步驟說明圖，以下同時說明第3圖 所示之製造步驟圖。 第1A圖至第1F圖係顯示配線圖案14在絕緣層13表面 5 形成為止之製造方法的步驟。 第1A圖係顯示在基板最表層形成絕緣層13，且對絶緣 層13進行表面粗化後，再對絕緣層13表面進行觸媒處理的 狀態。而之所以要對絕緣層13進行表面粗化，是為了提高 配線圖案14與絕緣層13的密接性，且可藉由過錳酸處理來 1〇進行表面粗化。又，觸媒處理係在對非導體之樹脂進行無 電解電鍍時，可加速藉由因化學還原反應之金屬初期之析 出的操作處理，而在本實施形態中則係指使鈀觸媒核吸附 於絕緣層13表面的處理。第1A圖係說明顯示絕緣層13已進 行表面粗化且成為觸媒處理面13a的情形。 15 接著，對絕緣層13進行無電解電鍍以使絕緣層13表面 形成電鍍保護層20(步驟1 :第1B圖）。雖然電鍍保護層20係 以極薄之形狀成形，但在第1B圖中為了方便說明則以較厚 之電鍍保護層20來表示。 其次，將感光性光阻劑塗佈在電鍍保護層20表面或將 2〇感光性光阻劑薄膜疊層在電鍍保護層20表面，藉由曝光及 顯像知作來形成光阻劑圖案22，以使形成配線圖案14之部 位露出（步驟2 :第1C圖）。 然後，將電鍍保護層20作為饋電層進行電解銅電鍍， 然後在電錄保護層20之露出部分將銅電鍍層增厚，以形成 1278264 配線圖案14(步驟3 :第ID圖）。 接著，將光阻劑圖案22除去（步驟4)。第1E圖係顯示將 光阻劑圖案22除去後，配線圖案14形成在電鍍保護層20表 面之預定圖案上的狀態。 5 然後，藉由蝕刻將電鍍保護層20中露出在外面的部分 除去（步驟5)。因電鍍保護層20係以遠比配線圖案14薄之形 狀成形，故不需對配線圖案14施以光罩，而可使用銅蝕刻 劑選擇性地將電鍍保護層20中露出在外面的部分除去。第 1F圖係顯示將鄰接之配線圖案14中間部分的電鑛保護層如 10 除去後露出絕緣層13的情形。 第1A圖至第1F圖之步驟與第8圖所示之習知步驟工到 步驟5之步驟相同。 在本貫施形態中具特徵性的步驟為第⑽、第2b圖所 15 示之步驟。即’第2A圖係顯示對基板進行異向雜刻時， 先=緣層⑽出的部位進行_後，再將吸附在絕 表面之觸姆去的步驟(步㈣）。又 不影___而只對絕緣層 = 對絕緣層13朝厚度方向進行麵刻之操作。刻且 如第2 A圖所示，在難士 行餘刻時，先對夾在配_==性_裝置對基板進 分進行钕刻以干深^14中間之絕緣層13之露出部 觸媒核除去。 r再將吸附於絕緣層η表面之 第4圖係顯示對形成有配 向性乾蝕刻後的狀態截面照片 線圖案14之絕緣層13進行異 (400倍）。由此圖可知，絕緣 20 1278264 層13在鄰接之配線圖案14之中間部分的蝕刻深度約為 5μιη 〇 第2Β圖係顯示進行異向性蝕刻後，進行有無電解鎳電 鍍及無電解金電鍍的狀態（步驟7)。藉由對基板進行異向性 5 蝕刻可將觸媒核從鄰接之配線圖案14之中間部分的絕緣層 13表面除去，使電鍍層18只形成在配線圖案14露出在外部 之側面和上面。又，藉由對配線圖案14之外表面進行無電 解鎳電鍍及無電解金電鍍，可確實地防止配線圖案14表面 氧化。 10 第5圖係顯示藉由X射線光電子分光術(X P S)測量殘留 在絕緣層13表面之鈀量所得之結果，且該鈀量係相對於藉 由異向性蝕刻對絕緣層13所蝕刻之深度(蝕刻量）者，且該圖 亦顯示在初期狀態中令鈀份量為1時之鈀殘留量。而該實驗 結果顯示，殘留之鈀量會因絕緣層13之蝕刻量增加而減 15 少。根據實驗，若令絕緣層13之蝕刻量為2.5μιη，則電鍍金 於鄰接之配線圖案14中間之絕緣層13表面的析出量幾乎為 0 ° 如此，因可藉由異向性乾蝕刻有效地將殘留在絕緣層 13表面之觸媒核除去，故在對配線圖案14進行無電解鎳電 20 鍍及無電解金電鍍時，可有效地防止電鍍層附著在絕緣層 13表面。 如前述，因使用防焊油墨後再對配線圖案14之露出部 位進行電鍍之方法會使防焊油墨之解析度受到限制，故配 線圖案14之配線密度為一定以上時就會無法適用。而相對 12 1278264 於此情形，根據本發明之方法，即使在高密度地配置配線 圖案時，也能確實地對配線圖案之露出部分進行無電解電 鍍，而可作為高密度地形成配線圖案之配線基板之製造方 法來加以有效地利用。 5【圖式簡單說明】 第1A圖至第1F圖係顯示本發明之配線基板之製造方 法的說明圖。 第2A圖、第2B圖係顯示本發明之配線基板之製造方法 的說明圖。 10 第3圖係顯示本發明之配線基板之製造方法的流程圖。 第4圖係顯示進行異向性乾蝕刻後絕緣層之狀態的截 面照片。 第5圖係顯示相對於絕緣層之蝕刻量而殘留在絕緣層 表面之I巴量的圖表。 15 第6圖係顯示配線基板之截面圖。 第7A圖、第7B圖係顯示對配線圖案進行無電解電鍍前 後之狀態的說明圖。 第8圖係顯示習知配線基板之製造方法的流程圖。 第9圖係顯示無電解電鐘層附著在絕緣層表面之狀態 20 的截面照片。 第10圖係顯示無電解電鍍層附著在絕緣層表面之狀態 的電子顯微鏡照片。 第11圖係顯示將防焊油墨塗佈在絕緣層表面後再對配 線圖案表面進行電鍍之習知方法的說明圖。 13 1278264 【主要元件符號說明】 ίο...核心基板 12…配騎 13…絕緣層 13a...觸媒處理面 14…配線圖案 15···通孔 16…防焊油墨 18···電鐘層 18a···不需要之電鍵層 20…電鐘保護層 22...光阻劑圖案Solving the surface of the insulating layer subjected to the catalyst treatment to form a plating protective layer without electricity; forming a J-wide photoresist pattern on the surface of the plating protective layer as a photomask electro-electroplating/electroplating arm forming wiring pattern; and After the second=removal, the exposed part of the protective layer of the core clock is removed, and then the core of the core is electrolessly electrolyzed to the surface of the wiring pattern. Second, after removing the exposed portion of the protective layer of the electric ore, the /, Etching the surface of the above-mentioned insulating reed + usli electrolysis (10) to the 〖 dry name, and then electrolyzing the outer surface of the wiring pattern to perform the electrician's touch 2, and roughening the surface of the insulating layer Thereafter, it is attached to the surface of the insulating layer as the aforementioned catalyst treatment. Wrong by the hot electrolytic steel electricity to form a money protection layer. The above-described electroless nickel plating and electroless gold plating are methods for electroless plating of the wiring pattern/surface, and the effect of the invention can be improved, that is, good line bonding is obtained. In the method of manufacturing the wiring substrate of the exposed portion 2, the portion of the electric protective layer is brought into the rear, and the adhesion layer of the insulating layer is adhered by the anisotropic secret, and the electric clock can be applied to the outer surface of the wiring Let the electric's edge layer surface prevent the wiring pattern from being short-circuited. Thereby, even when the wiring pattern is formed at a high density in the case of 8 1278264, it is possible to prevent the wiring pattern from being short-circuited, and it is possible to surely perform electroless plating on the wiring pattern. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1F are explanatory views showing a method of manufacturing a wiring board of the present invention. 2A and 2B are explanatory views showing a method of manufacturing the wiring board of the present invention. Fig. 3 is a flow chart showing a method of manufacturing the wiring board of the present invention. Fig. 4 is a cross-sectional photograph showing the state of the insulating layer after the anisotropic dry etching. Fig. 5 is a graph showing the amount of the remaining amount on the surface of the insulating layer with respect to the etching amount of the insulating layer. Fig. 6 is a cross-sectional view showing the wiring substrate. Fig. 7A and Fig. 7B are explanatory views showing a state after the electroless plating of the wiring pattern. Fig. 8 is a flow chart showing a method of manufacturing a conventional wiring board. Fig. 9 is a photograph showing a cross section of a state in which an electroless plating layer is attached to the surface of an insulating layer. Fig. 10 is an electron micrograph showing a state in which an electroless plating layer is attached to the surface of the insulating layer. Fig. 11 is an explanatory view showing a conventional method of plating the surface of the wiring pattern after applying the solder resist ink to the surface of the insulating layer. [Embodiment] The best mode for carrying out the invention is 1278264. Fig. 1A to Fig. IF, Fig. 2A and Fig. 2B are diagrams showing the manufacturing steps of the method for manufacturing the wiring board of the present invention, and Fig. 3 is also described below. Manufacturing step diagram. Figs. 1A to 1F show the steps of a manufacturing method in which the wiring pattern 14 is formed on the surface 5 of the insulating layer 13. Fig. 1A shows a state in which the insulating layer 13 is formed on the outermost layer of the substrate, and the surface of the insulating layer 13 is roughened, and then the surface of the insulating layer 13 is subjected to a catalyst treatment. The reason why the surface of the insulating layer 13 is roughened is to improve the adhesion between the wiring pattern 14 and the insulating layer 13, and the surface can be roughened by permanganic treatment. Further, in the catalyst treatment, when electroless plating is performed on the non-conductor resin, the operation of initial precipitation of the metal by the chemical reduction reaction can be accelerated, and in the present embodiment, the palladium catalyst core is adsorbed to The treatment of the surface of the insulating layer 13. Fig. 1A illustrates a case where the insulating layer 13 has been roughened and becomes the catalyst-treated surface 13a. Next, the insulating layer 13 is subjected to electroless plating to form the plating resist 20 on the surface of the insulating layer 13 (step 1: Fig. 1B). Although the plating resist 20 is formed in an extremely thin shape, it is represented by a thick plating resist 20 for convenience of description in Fig. 1B. Next, a photosensitive photoresist is applied on the surface of the plating resist 20 or a 2 Å photosensitive photoresist film is laminated on the surface of the plating resist 20, and the photoresist pattern 22 is formed by exposure and development. The portion where the wiring pattern 14 is formed is exposed (step 2: FIG. 1C). Then, the plating resist 20 is subjected to electrolytic copper plating as a feed layer, and then the copper plating layer is thickened at the exposed portion of the galvanic protective layer 20 to form a 1278264 wiring pattern 14 (step 3: ID drawing). Next, the photoresist pattern 22 is removed (step 4). Fig. 1E shows a state in which the wiring pattern 14 is formed on a predetermined pattern on the surface of the plating resist layer 20 after the photoresist pattern 22 is removed. 5 Then, the portion of the plating resist 20 exposed to the outside is removed by etching (step 5). Since the plating resist 20 is formed in a shape far smaller than the wiring pattern 14, it is not necessary to apply a mask to the wiring pattern 14, and a portion exposed to the outside of the plating resist 20 can be selectively removed using a copper etchant. Fig. 1F shows a case where the electric ore protective layer such as 10 in the middle portion of the adjacent wiring pattern 14 is removed to expose the insulating layer 13. The steps of Figs. 1A to 1F are the same as those of the conventional steps shown in Fig. 8 to step 5. The characteristic steps in the present embodiment are the steps shown in Figs. 10(10) and 2b. That is, the 'Fig. 2A' shows a step (step (4)) in which the portion of the edge layer (10) is subjected to the omni-directional singulation of the substrate, and then the contact is adsorbed on the surface of the substrate (step (4)). It does not affect ___ but only the insulating layer = the operation of engraving the insulating layer 13 in the thickness direction. Engraved and as shown in Fig. 2A, in the case of the hard time, the exposed portion of the insulating layer 13 in the middle of the middle of the substrate is engraved with the _===_ device The media core is removed. Further, the fourth drawing of the surface of the insulating layer η is shown to be different (400 times) from the insulating layer 13 in the state of the cross-sectional photo line pattern 14 in which the alignment dry etching is formed. As can be seen from the figure, the etching depth of the insulating layer 20 1278264 layer 13 in the middle portion of the adjacent wiring pattern 14 is about 5 μm. The second drawing shows the state of performing electroless nickel plating and electroless gold plating after performing anisotropic etching. (Step 7). The catalyst core can be removed from the surface of the insulating layer 13 in the middle portion of the adjacent wiring pattern 14 by anisotropic etching of the substrate, so that the plating layer 18 is formed only on the side and the upper surface of the wiring pattern 14 exposed to the outside. Further, by performing electroless nickel plating and electroless gold plating on the outer surface of the wiring pattern 14, the surface of the wiring pattern 14 can be surely prevented from being oxidized. 10 Fig. 5 shows the result of measuring the amount of palladium remaining on the surface of the insulating layer 13 by X-ray photoelectron spectroscopy (XPS), and the amount of palladium is etched with respect to the insulating layer 13 by anisotropic etching. The depth (etching amount) is also shown, and the figure also shows the amount of palladium remaining when the amount of palladium is 1 in the initial state. As a result of the experiment, the amount of residual palladium was reduced by 15 due to an increase in the etching amount of the insulating layer 13. According to the experiment, if the etching amount of the insulating layer 13 is 2.5 μm, the deposition amount of the plating gold on the surface of the insulating layer 13 in the middle of the adjacent wiring pattern 14 is almost 0°, because it can be effectively dried by anisotropic dry etching. Since the catalyst core remaining on the surface of the insulating layer 13 is removed, when the wiring pattern 14 is subjected to electroless nickel plating and electroless gold plating, the plating layer can be effectively prevented from adhering to the surface of the insulating layer 13. As described above, the method of plating the exposed portions of the wiring pattern 14 after the use of the solder resist ink restricts the resolution of the solder resist ink. Therefore, the wiring pattern 14 has a wiring density of a certain level or more. According to the method of the present invention, even when the wiring pattern is disposed at a high density, the exposed portion of the wiring pattern can be surely electrolessly plated, and the wiring pattern can be formed as a wiring pattern with high density. The method of manufacturing the substrate is effectively utilized. [Brief Description of the Drawings] Figs. 1A to 1F are explanatory views showing a method of manufacturing the wiring board of the present invention. 2A and 2B are explanatory views showing a method of manufacturing the wiring board of the present invention. 10 Fig. 3 is a flow chart showing a method of manufacturing the wiring board of the present invention. Fig. 4 is a cross-sectional photograph showing the state of the insulating layer after the anisotropic dry etching. Fig. 5 is a graph showing the amount of I bar remaining on the surface of the insulating layer with respect to the etching amount of the insulating layer. 15 Fig. 6 shows a cross-sectional view of the wiring substrate. Fig. 7A and Fig. 7B are explanatory views showing a state before and after electroless plating of the wiring pattern. Fig. 8 is a flow chart showing a method of manufacturing a conventional wiring board. Figure 9 is a cross-sectional photograph showing a state in which the electroless clock layer is attached to the surface of the insulating layer 20. Fig. 10 is an electron micrograph showing the state in which the electroless plating layer is attached to the surface of the insulating layer. Fig. 11 is an explanatory view showing a conventional method of plating the surface of the wiring pattern after applying the solder resist ink to the surface of the insulating layer. 13 1278264 [Description of main component symbols] ίο...core substrate 12...with ride 13...insulation layer 13a...catalyst treatment surface 14...wiring pattern 15···through hole 16...soldering ink 18···Electric Clock layer 18a··· unnecessary key layer 20...electric clock protection layer 22...resist pattern
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