200938048 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種配線基板之製造方法，尤其是關於在 形成鍍覆阻劑之狀態下，進行無電解鍍銅而形成配線圖案 的配線基板之製造方法。 【先前技術】 近年來，隨著電子機器之小型化、高性能化，已要求電 子元件之高密度構裝化，適合於達成如此之高密度構裝 化，配線基板的多層化技術已受到重視。使用多層化技術 之具體例，習知爲一種印刷配線基板（所謂層疊（bulid-up ) 配線基板），其係在已設置貫穿孔（through hole)部之核心 基板的單面或雙面，設置已交替積層形成樹脂絕緣層與導 體之層叠層。此種印刷配線基板中之層疊層，例如能夠利 用如下之順序加以製作： 首先，在樹脂絕緣層之整個表面形成鍍銅層。接著，將 具有感光性之乾膜材黏貼於鍍銅層上之後，進行曝光及因 鹼所造成之顯像，形成既定圖案之鍍覆阻劑。接著，進行 鍍銅而在鍍覆阻劑之開口部形成配線圖案層之後，使用鹼 剝離液以剝離鑛覆阻劑。接著，藉由進行位於鍍覆阻劑正 下方之鍍銅層的蝕刻，形成所希望形狀之配線圖案層。其 後，在配線圖案層上更形成樹脂絕緣層，進行通孔貫穿後， 再進行鏟銅而形成通孔導體（via conductor)及鍍銅層。而 且，必要時藉由重複數次如此之製程，使層疊層朝向多層 化。還有，針對如此之層疊製程，具有習知數個例子（例 -4- 200938048 如，參照專利文獻1 )。還有，近年來，尋求配線圖案層 之微細間距化的要求正逐漸升高，例如，使配線圖案層之 線寬與相鄰接之配線圖案間之線間隔成爲2〇μιη以下（期 望爲15μηι以下）。因而，於鍍覆阻劑中，也尋求正確形 成同樣的微細阻劑圖案。 專利文獻1:日本專利特開2005-150554號公報 【發明內容】 發明所欲解決之技術問題 ❹ 然而，於上述習用技術中，隨著配線圖案層之微細間距 化，針對阻劑開口部，高度（深度）/寬度之比爲大的，成 爲所謂的’高深寬比圖案。而且，鍍覆阻劑之表面，通常爲 了形成精細之配線圖案層而提高疏水性。根據此等事實， 發生如下之問題：於鍍覆阻劑之表面，電解鍍銅液將被彈 開，電解鍍銅液變得難以滲入阻劑開口部內，發生導致所 謂的溶液交換效率降低，均勻的鍍膜厚度變得難以得到的 〇 問題。 因此，於習用技術中，爲了使鍍覆厚度之均勻性得以提 高，例如已實施鍍覆液攪拌處理等，因此，攪拌裝置成爲 必要，將有設備成爲高價且大規模之擔憂。 本發明係有鑑於上述課題而進行，其目的在於提供一種 配線基板之製造方法，既容易且確實，還有也不會伴隨高 成本化而能夠形成均勻厚度之微細配線圖案層。 解決問題之技術手段 200938048 爲了解決上述課題之手段（手段1)係一種配線基板之 製造方法’其係形成配線圖案層的配線基板之製造方法， 其特徵係包含下列步驟： 無電解鍍銅步驟，進行無電解鍍銅而在樹脂絕緣層之表 面形成無電解鍍銅覆層； 阻劑形成步驟，將丙烯酸系乾膜材緊貼於該無電解鍍銅 覆層i:之後’進行曝光與顯像以形成既定圖案之鍍覆阻劑； 表面改質步驟，於該阻劑形成步驟之後，進行乾灰化（dry 〇 ashing )處理，整體殘留該鍍覆阻劑的同時，也改質其表 面； > 電解鍍銅步驟，於該表面改質步驟之後，進行電解鎪銅 而在該鍍覆阻劑之開口部形成該配線圖案層； 阻劑剝離步驟，使用剝離液以剝離該鍍覆阻劑；及 圖案分離步驟，去除位於該鍍覆阻劑正下方之該無電解 鏟銅覆層以分離該配線圖案層。 〇 另外’爲了解決上述課題之其他手段（手段2)係一種 配線基板之製造方法，其係形成配線圖案層的配線基板之 製造方法，其特徵係包含下列步驟： 無電解鍍銅步驟，進行無電解鍍銅而在樹脂絕緣層之表 面形成無電解鍍銅覆層； 阻劑形成步驟，將丙烯酸系乾膜材緊貼於該無電解鍍銅 覆層上之後’進行曝光與顯像以形成既定圖案之鍍覆阻劑； 表面改質步驟，於該阻劑形成步驟之後，進行使該鍍覆 200938048 阻劑表面之水的接觸角成爲50°以下之親水化處理，改質該 鍍覆阻劑之表面； 電解鍍銅步驟，於該表面改質步驟之後，進行電解鍍銅 而在該鍍覆阻劑之開口部形成該配線圖案層； 阻劑剝離步驟，使用剝離液以剝離該鍍覆阻劑；及 圖案分離步驟，去除位於該鍍覆阻劑正下方之該無電解 鍍銅覆層以分離該配線圖案層。 因而，若根據上述手段1、2揭示之發明，疏水性高的鍍 ❹ 覆阻劑之表面係藉由乾灰化處理或親水化處理予以改質， 濕潤性將增加，於電解鍍銅步驟時，電解鍍覆液在鍍覆阻 劑之表面將變得難以被彈開。其結果，即使作成含有高深 寬比圖案之阻劑開口部，也由於電解鍍銅液變得容易滲入 其內部，溶液交換效率將提高，均勻鍍覆厚度將變得容易 得到。另外此情形下，能夠省略用以提高鏟覆厚度均勻性 的鍍覆液攪拌處理等，故能夠削減爲了此處理之設備費。 Q 以上之結果，若根據上述手段1、2之製造方法，既容易且 確實，還有也不會伴隨高成本化而能夠形成均勻厚度之微 細配線圖案層。 於上述手段之如此製造方法中，首先，進行無電解鍍銅， 在樹脂絕緣層之表面進行形成無電解鏟銅覆層的無電解鍍 銅步驟。選擇無電解鍍銅覆層係由於導電性爲高的，而且 低成本。無電解鍍銅覆層之表面狀態並未予以特別限定而 爲任意的，例如可以作成表面粗糙度Ra爲〇.2μιη以上、 200938048 0 ·4μΐη以下之粗糙面。此情形下，鍍覆層表面之凹凸程度 將變小、曝光時之光散射影響變小的結果，成爲容易實現 高解像度。還有，若表面粗糙度Ra成爲低於0.2 μιη時，由 於具有乾膜材之緊貼性成爲不足夠之可能性而不佳。 於無電解鍍銅步驟後之阻劑形成步驟中，將丙烯酸系乾 膜材緊貼於該無電解鍍銅覆層上之後，進行曝光及顯像， 形成既定圖案之鍍覆阻劑。 於阻劑形成步驟中，使用具有感光性之丙烯酸系乾膜 ❹ 材。該乾膜材可以爲負型或正型中任一種，於此，適合選 擇負型。由於負型係藉由增加溫度而使剝離性降低，雖然 具有必須利用既定之剝離液加以剝離的缺點，但具有有利' 於形狀佳之圖案形成的優點。另外，如此之丙烯酸系乾膜 材較佳爲具有耐鹼性。於此，所謂「具有耐鹼性」係指具 有對氫氧化鈉等之強鹼完全不膨潤，或是具有較習知物更 難膨潤之性質。如此性質之差異係歸因於例如乾膜材主要 ❹ 成分之樹脂材料的交聯密度高低的差異。亦即，相較於習 知物，具有耐鹼性之上述手段的乾膜材樹脂材料之交聯密 度將變高。但是，上述手段之乾膜材不具有對有機胺之耐 性，若予以曝露於有機胺時，具有些微溶解其中之性質。 此係意指對於上述乾膜材，因爲無法將通常之鹼作爲剝離 液使用，有機胺能夠作爲取代鹼之剝離液使用。 於此，丙烯酸系乾膜材，其平面較佳爲平滑的，具體而 言，表面粗糙度Ra較佳爲0.1 μιη以下’尤以0.01 μιη以上、 200938048 Ο.ίμιη以下特別理想。將如此之丙烯酸系乾膜材作爲起始 材料以形成鍍覆阻劑，若進一步改質其表面的話，因而濕 潤性之提高將變得容易期待。 於貼附乾膜材之後，進行曝光，進一步進行因鹼所造成 之顯像，形成既定圖案之鍍覆阻劑。在線寬與線間隔皆形 成1 5 μιη以下之微細配線圖案之情形下，與此相一致，必 須預先設定微細阻劑圖案的寬度與相鄰接之微細阻劑圖案 I 間的間隙尺寸。還有，此情形下之微細阻劑圖案間之開口 〇 部將成爲所謂的高深寬比。 於阻劑形成步驟後之表面改質步驟中，進行乾灰化處理 或親水化處理以改質鍍覆阻劑之表面。 1 一般而言，所謂乾灰化處理，其係指使用臭氧或氧電漿 等之反應氣體而於氣相中處理有機物（乾膜材），再將之 加以分解、去除的處理。乾灰化處理之優點係與濕式之方 法不同，因爲不使用藥劑，配線基板不受污染，於後段步 〇 驟中，也不須要進行藥劑及殘渣之洗淨。但是，於上述手 段1、2中之乾灰化處理中，雖然使用反應氣體而於氣相中 處理乾膜材，但是整體殘留乾膜材（鍍覆阻劑）的同時， 也僅進行改質其表面。亦即，相較於通常所進行之乾灰化 處理，刻意設定穩定之條件以進行其處理。 進行乾灰化處理之際的壓力環境並未予以特別限定而爲 任意的，相較於減壓下，較佳於常壓下進行處理。其理由 係因爲整體殘留鍍覆阻劑的同時，也適合於確實改質其表 200938048 面。相反的，若爲減壓下時’具有使處理效果達成必要以 上之可能性，由於鎪覆阻劑材之分解量變多’因而具有整 體殘留鍍覆阻劑成爲困難之憂慮。 還有，乾灰化處理中之反應氣體狀態並未予以特別限定 而爲任意的，基於生產性提高等之觀點，較佳爲使用電漿 狀態的反應氣體。 於親水化處理中，進行使鍍覆阻劑表面上之水的接觸角 成爲50°以下的處理。其理由係：若水之接觸低至此程度 〇 的話，親水性將變成足夠高的狀態，因而鍍覆阻劑表面之 濕潤性將變高。針對於此，若接觸角超過50°時，將變得無 法充分提高鑛覆阻劑之濕il性，無法使電解鍍銅液之溶液 交換效率得以充分提高。於如此之親水化處理中，更佳爲 進行使該接觸角成爲45°以下之處理，尤以使其成爲20°以 上、35°以下之處理特別理想。 親水化處理只要爲能夠減少鍍覆阻劑材表面中之疏水基 Q 比率而增加親水基比率之處理的話，並未予以特別限定， 可以爲物理性處理，也可以爲化學性處理。還有，進行上 述電漿灰化處理之情形，其結果，由於鍍覆阻劑表面上之 水的接觸角將減低，能夠掌握如此之處理也爲親水化處理 的一種。 該表面改質步驟之後，可以不特別進行其他之處理，而 立即進行電解鍍銅步驟，之前也可以進行例如酸洗淨處理 或界面活性劑處理等。由於此等之處理也爲能使鍍覆阻劑 •10- 200938048 之濕潤性得以提高之處理，能夠期待與該表面改質步驟之 相乘效果，因而進一步使電解鍍銅液之溶液交換效率得以 進一步提高》合倂此種處理而進行之情形，也可以依照此 順序進行酸洗淨處理及界面活性劑處理。若此順序相反的 話，將有經由酸洗淨而使界面活性劑洗出之可能性，因而 上述相乘效果將變得無法充分得到。 於表面改質步驟後之電解鍍銅步驟中，進行電解鍍銅在 鍍覆阻劑之開口部形成配線圖案層。若經歷此步驟時，電 ❹ 解鍍銅將析出於鍍覆阻劑之開口部底面所曝露之無電解鏟 銅覆層上，結果會使該部分均勻變厚。 於電解鍍'銅步驟後之鍍覆阻劑剝離步驟中，使用既定之 剝離液以剝離鍍覆阻劑。此情形之剝離液並未予以特別限 定，例如適宜使用有機胺系剝離液。於有機胺系剝離液中， 作爲主要成分所含之有機胺，例如，可舉出：單乙醇胺、 二乙醇胺、三乙醇胺、單甲胺、二甲胺、三甲胺、乙二胺、 〇 異丙胺、異丙醇胺、2-胺基-2-甲基-1-丙醇、2-胺基-2-甲基 -1,3-丙二醇等。此等有機胺之中，特別理想之有機胺爲含 有單乙醇胺之剝離液。其理由係含有單乙醇胺之剝離液已 確認滲透於具有耐鹼性之上述乾膜材中，能夠將其加以溶 解，與上述手段關聯之製造方法中，因而在使用上之爲適 合。還有，於鍍覆阻劑剝離步驟中所用之有機胺系剝離液 中，也可以添加一些肼或TMH等添加劑。 於鍍覆阻劑剝離步驟後之圖案分離步驟中，去除鍍覆阻 -11- 200938048 劑正下方之無電解鍍銅覆層以分離配線圖案層。於此步驟 中，使用能溶解銅之蝕刻液以進行蝕刻’若經歷此步驟時， 無電解鍍銅覆層將被部分切離，關聯的配線圖案層彼此間 相互獨立。 【實施方式】 以下，基於第1圖〜第13圖，以詳細說明使本發明具體 化之一實施形態的配線基板κ及其製造方法。 ^ 如第1圖所示，本實施形態的配線基板K係在表背兩面 〇 具有層疊（bulid-up )層BUI、BU2之所謂的層疊多層印刷 配線基板。構成此配線基板K之核心基板1係顯示具有表 '' 面2及背面3之平板狀。 於核心基板1之表面2側所配置之層疊層BU 1係具有交 替積層樹脂絕緣層12、16、30與配線圖案層10、28、28a、 34、 34a之構造。於樹脂絕緣層12中形成有通孔形成用孔 1 2a，於其內部形成有使配線圖案層1 〇與內層配線層4予 〇 以導通的場連絡導體（field via conductor)14。於樹脂絕緣層 1 6中形成有通孔形成用孔1 8，於其內部形成有使配線圖案 層10、28間予以導通之場連絡導體26。 於核心基板1之背面3側所配置之層疊層BU2係具有交 替積層樹脂絕緣層13、17、31與配線圖案層11、29、29a、 35、 35a之構造。於樹脂絕緣層13中形成有通孔形成用孔 13a，於其內部形成有使配線圖案層11與內層配線層5予 以導通之場連絡導體15»於樹脂絕緣層17中，形成有通 -12- 200938048 孔形成用孔19，於其內部形成有使配線圖案層11、29間 予以導通之場連絡導體27。 樹脂絕緣層30係藉由在既定位置上具有開口部36之阻 焊劑3 2而予以整體被覆。此等之開口部3 6係使樹脂絕緣 層30上所形成的配線圖案層34曝露於第1主面32a側， 其結果，使該配線圖案層34得以發揮作爲第1主面側脊槽 (land)之功能。另一方面，樹脂絕緣層31係藉由在既定位 置上具有開口部37之阻焊劑33而予以整體被覆。此等之 開口部37係使樹脂絕緣層31上所形成的配線圖案層35曝 露於第2主面3 3 a側，其結果，使該配線圖案層3 5得以發 揮作爲第2主面側脊槽之功能。 另外，於第1主面側脊槽之配線圖案層34上，形成有較 第1主面3 2a爲高突出的焊錫凸塊38。然後，於此等之焊 錫凸塊38上，便可能透過焊錫而接合未圖示之1C晶片等 之電子元件。另一方面，第2主面側脊槽之配線圖案層35 Ο 係成爲與未圖示之母板等之印刷配線基板電性相連結。 如第1圖所示’於此配線基板K之內部設置有貫穿孔。 本實施形態之貫穿孔係使圓筒狀之貫穿孔導體7析出於貫 穿核心基板1及樹脂絕緣層1 2、1 3之貫穿孔形成用孔6之 內壁面的同時，也具有利用塡充樹脂9以塡補其貫穿孔導 體7之空洞部的構造。然後，藉由此貫穿孔之貫穿孔導體 7’期望核心基板1之表面2側的層疊層BU1中之導體部 分與核心基板1之背面3側的層疊層BU2中之導體部分之 -13- 200938048 間的導通。 接著，基於第2圖〜第13圖之觀點，說明本實施形態之 配線基板K的製造方法。 第2圖係以雙馬來酸酐縮亞胺三畊（BT)樹脂作爲主體 之厚度約爲〇.7mm之核心基板1的槪略剖面圖。於核心基 板1之表面2及背面3,預先黏貼有厚度約70 μιη之銅箔4a、 5a。利用習知之手法（於此爲扣除（subtractive)法），以 將如此核心基板1的銅箔4a、5a圖案化，在表面2上及背 面3上形成內層配線層4、5(參照第3圖）。還有，使用 採取許多個具有數個核心基板1的面板，也可以對於各核 心基板1進行同樣之步驟》 接著，如第4圖所示，藉由在核心基板1中之表面2上 及背面3上，被覆由含有無機塡料之環氧樹脂而成的絕緣 性薄膜，形成樹脂絕緣層1 2、1 3。如此之樹脂絕緣層1 2、 13，其厚度約爲40μπι，含有30重量％〜50重量％之由約 φ 略球狀之二氧化矽而成的無機塡料。還有，上述無機塡料 之平均粒徑較佳爲1.0 μιη以上、10.0 μιη以下。 接著，相對於樹脂絕緣層12、13之表面上的既定位置， 沿著其厚度方向以照射未圖示之雷射（於本實施形態爲二 氧化碳氣體雷射）。其結果，如第5圖所示，貫穿樹脂絕 緣層12、13而形成有使內層配線層4、5裸露於其底面的 約略圓錐形之通孔形成用孔12a、13a。再者，藉由使用鑽 孔機以鑿穿既定之位置’形成貫穿核心基板1及樹脂絕緣 -14- 200938048 層12、13之內徑約200 μιη的貫穿孔形成用孔6。 接著，於含有通孔形成用孔12a、13a之樹脂絕緣層12、 13的整個表面及貫穿孔形成用孔6之內壁面，塗布含有鈀 等之鍍覆觸媒後，再於其上實施無電解鍍銅及電解鍍銅。 其結果，如第6圖所示，在樹脂絕緣層12、13的整個表面 形成有鍍銅覆膜8a、8b，於貫穿孔形成用孔6內形成有厚 度約40 μιη且約略圓筒狀之貫穿孔導體7。同時，藉由在通 ^ 孔形成用孔12a、13a內，實施追加的鍍銅以形成場連絡導 體 1 4、1 5。 接著，如第6圖所示，將含有無機塡料之塡充樹脂9之糊 塡充於貫穿孔導體7之空洞部內之後，使其熱硬化。還有， 用以形成塡充樹脂9之糊也可以爲含有金屬粉末之導電性 糊。再者，如第7圖所示，進行電解鍍銅液而在鍍銅覆膜8a、 8b上形成鍍銅覆膜l〇b、lib。此時，同時作成利用鍍覆蓋 l〇a、11a以覆蓋塡充樹脂9之兩端面。還有，鍍銅覆膜8a、 〇 10b及鍍銅覆膜8b、1 lb之厚度分別約爲15μπι。 接著，利用習知之扣除法以蝕刻鍍銅覆膜8a、10b及鍍 銅覆膜8b' lib’分別形成如第8圖所示之配線圖案層1〇、 11。還有，此等之配線圖案層10、11係成爲層疊層BU1、 BU2中之第1層的配線圖案層’位於其內層側之樹脂絕緣 層係成爲第1層之樹脂絕緣層。 接著，如第9圖所示，將上述同樣之絕緣性薄膜貼附於 第1層的樹脂絕緣層12及第1層的配線圖案層1〇之上， -15- 200938048 形成第2層的樹脂絕緣層16。同樣的，將上述同樣之絕緣 性薄膜貼附於第1層的樹脂絕緣層1 3及第1層的配線圖案 層11之上，形成第2層的樹脂絕緣層17。再者，對於上 述樹脂絕緣層16、17之表面上的既定位置，藉由沿著其厚 度方向而照射該同樣之雷射（未圖示），形成約略圓錐形 之通孔形成用孔1 8、1 9。通孔形成用孔1 8、1 9係貫穿樹 脂絕緣層16、17的同時，也使配線圖案層10、11之一部 分露出其底面。然後，預先將上述同樣的鍍覆觸媒塗布於 含有上述通孔形成用孔1 8、1 9之內壁面的樹脂絕緣層1 6、 17之整個表面上之後，實施無電解鍍銅（無電解鑛銅步 驟）。若經歷如此之金屬層形成步驟時，形成有厚度約〇.5μιη 之無電解鍍銅覆層20、21(參照第9圖中之虛線）。於此 時點之無電解鍍銅覆層 20、21之表面粗糙度 Ra約爲 0.2 μ m。 接著，如第10圖所示，將以丙烯酸系樹脂爲主體的厚度 Q 約25μιη之感光性及絕緣性之負型乾膜材22、23黏貼於無 電解鍍銅覆層20、21之整個表面。相較於以環氧樹脂爲主 體之習知物的乾膜材，於本實施形態所選擇的乾膜材22、 23係具備於強鹼中較難以膨潤之性質，因此，具有耐鹼性。 還有，此乾膜材22、23之表面粗糙度Ra約爲0.08μιη。將 未圖示之曝光用光罩配置於如此之乾膜材22、23上之狀態 下曝光，其後，使用氫氧化鈉溶液等之鹼顯像液以進行顯 像。然後，依照如上述之乾膜材黏貼、曝光及顯像的各步 -16- 200938048 驟，形成如第11圖所示之既定圖案的鍍覆阻劑2h、22b、 23a、23b (阻劑形成步驟）。 此等鍍覆阻劑22a、22b、23a、23b之中，針對狹小的鍍 覆阻劑22b、23b，成爲線寬爲15μιη以下（於本實施形態 之情形爲1 Ομιη )之微細阻劑圖案。另外，狹小的鍍覆阻劑 22b、22b間，或是23b、23b間之開口部24a、25a之尺寸 (亦即，線間隔）成爲1 5 μιη以下（於本實施形態之情形 ▲ 爲ΙΟμιη)，成爲所謂的高深寬比圖案。還有，狹小的鍍覆 ❹ 阻劑22b與相鄰於此之鍍覆阻劑22a之間，或是狹小的鍍 覆阻劑23b與相鄰於此之鍍覆阻劑23a之間的開口部24b、 25b之尺寸也成爲同樣之尺寸。同時，在鄰接於通孔形成 用孔18、19之左右的無電解鍍銅覆層20、21之表面上， 形成有較廣面積之開口部24、25。 接著，進行乾灰化處理，改質鍍覆阻劑22a、22b、23a、 23b之表面（表面改質步驟）。於本實施形態中，更具體 〇 而言，利用氧電漿反應氣體之習知乾電漿灰化裝置，於常 壓下進行處理。於此，設定一般處理條件（輸出500W、15 分鐘）之大約W4程度的穩定處理條件（輸出200W、5分 鐘），整體殘留鍍覆阻劑22a、22b、23a、23b的同時，也 僅進行其表面之改質。其結果，將處理前約爲72。之鍍覆阻 劑22a、22b、23a、23b表面上之水的接觸角減低至50。以 下（於本實施形態之情形爲3 1 ° )。此係認爲歸因於藉由上 述之乾電漿灰化，鏟覆阻劑22a、22b、23a、23b表面上之 -17- 200938048 疏水基的比率將減少，親水基之比率增加。 接著，進行酸洗淨處理之後，必要時，進行水洗及乾燥， 進一步進行界面活性劑處理。其結果，使鍍覆阻劑22a、 22b、23a、23b之濕潤性得以更爲提高。 接著，對於位於開口部24、24a、25、25a之底面或通孔 形成用孔18、19之底面的無電解鍍銅覆層20、21，利用 習知之手法以進行電解鍍銅而使鍍銅析出。其結果，如第 12圖所示，場連絡導體26、27將形成於通孔形成用孔18、 19內，與連絡導體26、27 —體之配線圖案層28、29將形 成於開口部24、25中。同時，剖面爲縱向長的長方形、寬 ’度爲15 μιη以下（於本實施形態之情形爲1〇 μιη)、厚度約 爲25 μι»之微細配線圖案層28a、29a形成於各開口部24a、 25a中（電解鍍銅步驟）。 接著’如第13圖所示’使用以單乙醇胺作爲主要成分所 含之有機胺系剝離液（0.5重量％以上、5〇°C以上），剝離 〇 鍍覆阻劑2 2 a、2 2 b、2 3 a、2 3 b (阻劑剝離步驟）。其後， 利用蝕刻液以軟蝕刻處理位於鍍覆阻劑2 2 a、2 2 b、2 3 a、2 3 b 之正下方的無電解鍍銅覆層20(21)後而加以去除（圖案 分離步驟）。若經歷此步驟時，無電解鍍銅覆層20(21) 將被切離。由以上之結果’含有線寬及線間隔皆約爲10μιη 之微細配線圖案層28a、29a的配線圖案層28、28a、29、 29a將予以形成。 再者，於形成有配線圖案層28、28a之第2層樹脂絕緣 -18- 200938048 層16之表面上將形成新的樹脂絕緣層（第3層樹脂絕緣層） 30。另一方面，於形成有配線圖案層29、29a之第2層樹 脂絕緣層1 7之表面上將形成新的樹脂絕緣層（第3層樹脂 絕緣層）31。然後，於此等樹脂絕緣層30、31上之既定位 置，根據上述方法而形成未圖示之通孔形成用孔。其後， 在樹脂絕緣層30、31之表面及通孔形成用孔內形成無電解 镀銅覆層，進行由如上述之乾膜材黏貼、曝光及顯像之各 ^ 步驟而成的鏟覆阻劑形成步驟，除了進一步進行表面改質 ❹ 步驟之外，也進行配線圖案層形成步驟、鍍覆阻劑剝離步 驟、蝕刻步驟。其結果，含有線寬及線間隔皆約爲ΙΟμιη 之微細配線圖案層34a、35a的配線圖案層34、34a、35、 3 5 a將分別形成於第3層樹脂絕緣層3 0、31上。 進一步分別將厚度25μιη之阻焊劑32、33設置於第3層 樹脂絕緣層30、31上的同時，也在開口部36之底面所曝 露之配線圖案34上形成焊錫凸塊38:在開口部37之底面 〇 所曝露之配線圖案35上實施鎳-金鍍覆。以上之結果，能 夠得到於如第1圖所示之表背兩面具備層疊層BUI、BU2 的配線基板Κ。 因而，若根據本實施形態，能夠得到以下之效果： (1 )若根據本實施形態之配線基板Κ之製造方法，疏水 性高的鍍覆阻劑22a、22b、23a、23b之表面係經由乾電獎 灰化處理（親水化處理）而予以改質，其濕潤性將增力口。 藉此，於電解鍍銅步驟之際，在鍍覆阻劑22a、22b、23a、 -19- 200938048 23b之表面，電解鍍覆液將變得難以被彈開。其結果，即 使含有高深寬比圖案的阻劑之開口部2 4 a、2 5 a，由於電解 鍍銅液變得容易滲入其內部，電解鏟銅液之溶液交換效率 將提高，均勻之鍍覆厚度也將變得容易得到。另外此情形 下，能夠省略爲了鍍覆厚度均勻性提高之鍍覆液攪拌處理 等，故能夠削減爲了此處理之設備費。以上之結果，若根 據本實施形態之配線基板K的製造方法，既容易且確實， 還有也不會伴隨高成本化而能夠形成均勻厚度之微細配線 ❹ 圖案層28a、29a。 還有，本發明之實施形態也可以變更爲如下之方式： • 於上述實施形態中，雖然選擇BT樹脂作爲形成核心 基板1之材料，但是並不受此樹脂所限定，例如，也可以 使用環氧樹脂、聚醯亞胺樹脂等，或是，也可以使用於具 有連續氣孔之PTFE等三次元網狀構造的氟系樹脂中含有 玻璃纖維等之複合材料等。還有，核心基板1可以爲氧化 〇 鋁、氮化矽、氮化硼、氧化鈹、矽酸、玻璃陶瓷、氮化鋁 等之由陶瓷等而成的高溫燒結基板以外，也可以爲於約 1000°C以下之較低溫進行燒結的低溫燒結基板。再者，核 心基板1也可以爲由銅合金或Fe-42wt%Ni合金等而成的金 屬核心基板。另外，於本發明中，由於核心基板1並非必 要的構造，例如，採用無核心基板之形態也被容許。 • 於上述實施形態中，雖然選擇銅作爲形成配線圖案層 1〇、U或連絡導體26、27等導電部的金屬材料，但是並 -20- 200938048 不受銅所限定，也可能採用銀、鎳、金、銅合金、鐵鎳合 金等。或是利用塗布導電性樹脂等之方法，以替代使用金 屬之鍍覆層而形成上述導體部。 • 於上述實施形態中，雖然連絡導體26、27之形態係 採用以導體完全塡補內部之場連絡導體，當然也可以採用 內部並未完全被導體所塡補之倒圓錐形的準型（conformal) 連絡導體。 • 於上述實施形態中，雖然乾灰化處理係進行乾電漿灰 化處理，使用不利用電漿型之乾灰化裝置也爲可能的。 • 於上述實施形態中，雖然使用負型之乾膜材22、23, 也能夠使用正型之乾膜材。 Λ 接著，除了於申請專利範圍所揭示之技術性思想之外， 以下列舉根據上述之實施形態所掌握之技術性思想： (1) 一種配線基板之製造方法，其係利用半附加法 (semi-additive)以形成配線圖案層的配線基板之製造方 Q 法，其特徵係包含下列步驟： 無電解鍍銅步驟，進行無電解鍍銅而在樹脂絕緣層之表 面形成無電解鍍銅覆層； 阻劑形成步驟，將負型之丙烯酸系乾膜材緊貼於該無電 解鍍銅覆層上之後，進行曝光與顯像以形成既定圖案之鍍 覆阻劑； 表面改質步驟，於該阻劑形成步驟之後’進行乾電漿灰 化處理，整體殘留該鍍覆阻劑的同時’也改質其表面； -21 - 200938048 電解鍍銅步驟，於該表面改質步驟之後’進行電解鍍銅 而在該鍍覆阻劑之開口部形成該配線圖案層； 阻劑剝離步驟，使用剝離液以剝離該鍍覆阻劑；及 圖案分離步驟，去除該鍍覆阻劑正下方之該無電解鑛銅 覆層以分離該配線圖案層。 【圖式簡單說明】 第1圖係顯示將本實施形態予以具體化之一實施形態配 ^ 線基板的部分槪略剖面圖。 Ο 第2圖係用以說明上述配線基板之製程的部分槪略剖面 圖。 第3圖係用以說明上述配線i板之製程的部分槪略剖面 圖。 第4圖係用以說明上述配線基板之製程的部分槪略剖面 圖。 第5圖係用以說明上述配線基板之製程的部分槪略剖面 〇 圖。 第6圖係用以說明上述配線基板之製程的部分槪略剖面 圖。 第7圖係用以說明上述配線基板之製程的部分槪略剖面 圖。 第8圖係用以說明上述配線基板之製程的部分槪略剖面 圖。 第9圖係用以說明上述配線基板之製程的部分槪略剖面 -22- 200938048 圖。 第1 〇圖係用以說明上述配線基板之製程的部分槪略剖 面圖。 第11圖係用以說明上述配線基板之製程的部分槪略剖 面圖。 第12圖係用以說明上述配線基板之製程的部分槪略剖 面圖。 ❹ 第1 3圖係用以說明上述配線基板之製程的部分槪略剖 面圖。 【主要元件符號說明】 1 ' 核心基板 2 表面 3 背面 ❹ 4、5 4a、5 a 6 7 8a、8b、l〇b、1 lb 9 10a' 11a 內層配線層 銅箱 貫穿孔形成用孔 貫穿孔導體 鍍銅覆膜 塡充樹脂 鍍覆蓋 10、 11、 28、 28a、 29、 29a、 34、 34a、 35、 35a 配線圖案層 1 2、1 3、1 6 ' 1 7、3 Ο、3 1 樹脂絕緣層 -23- 200938048 12a > 13a、 18、 19 14、 15、 26 > 27 20、2 1 22、23 22a 、 22b 、 23a 、 23b 24、24a、24b、 、 25 通孔形成用孔 場連絡導體 無電解鑛銅覆層 丙烯酸系乾膜材 鍍覆阻劑 25a 25b 、 36 、 37 鍍覆阻劑之開口部 28a ' 29a 配線圖案層中之微細配線 〇 圖案層 32 ' 33 阻焊劑 32a 第1主面 33a 第2主面 3 8 焊錫凸塊 K 配線基板[Technical Field] The present invention relates to a method of manufacturing a wiring board, and more particularly to a wiring board in which a wiring pattern is formed by electroless copper plating in a state in which a plating resist is formed. Production method. [Prior Art] In recent years, with the miniaturization and high performance of electronic equipment, high-density mounting of electronic components has been required, which is suitable for achieving such high-density mounting, and multilayer technology of wiring boards has been paid attention to. . A specific example of the multilayering technique is a printed wiring board (a so-called bulid-up wiring board) which is provided on one or both sides of a core substrate on which a through hole portion is provided. A laminated layer of a resin insulating layer and a conductor is alternately laminated. The laminated layer in such a printed wiring board can be produced, for example, in the following order: First, a copper plating layer is formed on the entire surface of the resin insulating layer. Next, the photosensitive dry film material is adhered to the copper plating layer, and then exposed and developed by alkali to form a plating resist of a predetermined pattern. Next, copper plating is performed to form a wiring pattern layer in the opening portion of the plating resist, and then an alkali stripping liquid is used to peel off the mineral coating agent. Next, a wiring pattern layer having a desired shape is formed by etching a copper plating layer located directly under the plating resist. Thereafter, a resin insulating layer is further formed on the wiring pattern layer, and after the through holes are penetrated, copper is etched to form a via conductor and a copper plating layer. Moreover, the layering layer is oriented in multiple layers by repeating such a process several times as necessary. Further, there are a number of conventional examples for such a lamination process (for example, -4-200938048, see, for example, Patent Document 1). Further, in recent years, the demand for fine pitch of the wiring pattern layer is increasing. For example, the line width between the wiring pattern layer and the adjacent wiring pattern is 2 μm or less (expected to be 15 μm). the following). Therefore, in the plating resist, it is also sought to correctly form the same fine resist pattern. [Problem to be Solved by the Invention] However, in the above-described conventional technique, with respect to the fine pitch of the wiring pattern layer, the height of the resist opening portion The ratio of (depth)/width is large and becomes a so-called 'high aspect ratio pattern. Further, the surface of the plating resist is usually formed by forming a fine wiring pattern layer to improve hydrophobicity. According to these facts, the following problem occurs: on the surface of the plating resist, the electrolytic copper plating solution is bounced off, and the electrolytic copper plating solution becomes difficult to penetrate into the opening portion of the resist, which causes a so-called solution exchange efficiency to be lowered and uniform. The coating thickness becomes a problem that is difficult to obtain. Therefore, in the conventional technique, in order to improve the uniformity of the plating thickness, for example, a plating solution agitation treatment or the like has been performed. Therefore, a stirring apparatus is required, and there is a concern that equipment is expensive and large-scale. The present invention has been made in view of the above problems, and an object of the invention is to provide a method of manufacturing a wiring board which is easy and reliable, and which can form a fine wiring pattern layer having a uniform thickness without increasing the cost. Means for Solving the Problems 200938048 In order to solve the above problems (method 1) is a method for manufacturing a wiring board, which is a method for manufacturing a wiring board in which a wiring pattern layer is formed, and the method includes the following steps: an electroless copper plating step, Performing electroless copper plating to form an electroless copper plating layer on the surface of the resin insulating layer; a resist forming step of adhering the acrylic dry film to the electroless copper plating layer i: after performing exposure and development a plating resisting agent for forming a predetermined pattern; a surface modifying step, after the resist forming step, performing a dry ashing treatment, and the surface resisting agent is also left as a whole, and the surface thereof is also modified; > electrolytic copper plating step, after the surface modification step, electrolytic copper bismuth is formed to form the wiring pattern layer in the opening portion of the plating resist; a resist stripping step, using a stripping liquid to peel off the plating resist And a pattern separating step of removing the electroless copper plating layer directly under the plating resist to separate the wiring pattern layer. Further, another means (method 2) for solving the above problems is a method of manufacturing a wiring board, which is a method of manufacturing a wiring board in which a wiring pattern layer is formed, and the method includes the following steps: an electroless copper plating step, and no Electrolytic copper plating to form an electroless copper plating layer on the surface of the resin insulating layer; a resist forming step of adhering the acrylic dry film material to the electroless copper plating layer to perform exposure and development to form a predetermined a plating resisting agent for the pattern; a surface modifying step, after the resist forming step, performing a hydrophilization treatment to change the contact angle of the water of the surface of the resisting layer of 200938048 to 50° or less, and modifying the plating resist a surface; an electrolytic copper plating step, after the surface modification step, performing electrolytic copper plating to form the wiring pattern layer in the opening portion of the plating resist; a resist stripping step, using a stripping liquid to peel off the plating resist And a pattern separating step of removing the electroless copper plating layer directly under the plating resist to separate the wiring pattern layer. Therefore, according to the invention disclosed in the above means 1, 2, the surface of the highly hydrophobic rhodium-plated coating agent is modified by dry ashing treatment or hydrophilization treatment, and the wettability is increased in the electrolytic copper plating step. The electrolytic plating solution will become difficult to bounce off on the surface of the plating resist. As a result, even if the resist opening portion including the high aspect ratio pattern is formed, the electrolytic copper plating solution easily penetrates into the inside, the solution exchange efficiency is improved, and the uniform plating thickness is easily obtained. Further, in this case, the plating liquid stirring treatment or the like for improving the uniformity of the thickness of the shovel can be omitted, so that the equipment cost for the treatment can be reduced. As a result of the above, according to the manufacturing methods of the above-described means 1 and 2, it is easy and reliable, and it is possible to form a fine wiring pattern layer having a uniform thickness without increasing the cost. In the manufacturing method of the above means, first, electroless copper plating is performed, and an electroless copper plating step of forming an electroless copper plating layer is performed on the surface of the resin insulating layer. The electroless copper plating is selected because of its high electrical conductivity and low cost. The surface state of the electroless copper plating layer is not particularly limited and may be any, and for example, a rough surface having a surface roughness Ra of 〇.2 μm or more and 200938048 0 · 4 μΐη or less may be obtained. In this case, the degree of unevenness on the surface of the plating layer is reduced, and the effect of light scattering at the time of exposure becomes small, and high resolution is easily achieved. Further, when the surface roughness Ra is less than 0.2 μm, it is not preferable because the adhesion of the dry film material is insufficient. In the resist forming step after the electroless copper plating step, the acrylic dry film is adhered to the electroless copper plating layer, and then exposed and developed to form a plating resist of a predetermined pattern. In the resist forming step, a photosensitive acrylic dry film material is used. The dry film material may be either a negative type or a positive type, and here, a negative type is suitably selected. Since the negative type lowers the peeling property by increasing the temperature, it has the disadvantage of having to be peeled off by a predetermined peeling liquid, but has an advantage of facilitating the formation of a pattern having a good shape. Further, such an acrylic dry film material preferably has alkali resistance. Here, the term "having alkali resistance" means that the strong base such as sodium hydroxide is not swelled at all or has a property which is more difficult to swell than conventional materials. The difference in such properties is attributed to the difference in the crosslinking density of the resin material such as the main component of the dry film. That is, the cross-linking density of the dry film resin material having the above-described means of alkali resistance becomes higher than that of the conventional one. However, the dry film of the above means does not have resistance to organic amines, and if exposed to an organic amine, it has a slight solubility therein. This means that for the above dry film material, since the usual base cannot be used as a peeling liquid, the organic amine can be used as a peeling liquid for the substituted base. Here, the acrylic dry film material preferably has a smooth surface, and specifically, the surface roughness Ra is preferably 0.1 μm or less, particularly preferably 0.01 μm or more and 200938048 Ο.ίμιη or less. When such an acrylic dry film material is used as a starting material to form a plating resist, if the surface is further modified, the improvement in wettability is expected. After the dry film material is attached, exposure is carried out to further develop the image by the alkali to form a plating resist of a predetermined pattern. In the case where the line width and the line interval are each formed into a fine wiring pattern of 15 μm or less, in accordance with this, the gap size between the width of the fine resist pattern and the adjacent fine resist pattern I must be set in advance. Also, the opening portion between the fine resist patterns in this case will become a so-called high aspect ratio. In the surface modification step after the resist formation step, a dry ashing treatment or a hydrophilization treatment is performed to reform the surface of the resist. 1. In general, the dry ashing treatment refers to a treatment in which an organic substance (dry film material) is treated in a gas phase using a reaction gas such as ozone or oxygen plasma, and then decomposed and removed. The advantage of the dry ashing process is different from that of the wet type. Since the wiring substrate is not contaminated without using a chemical, the cleaning of the drug and the residue is not required in the subsequent step. However, in the dry ashing treatment in the above-described means 1 and 2, the dry film material is treated in the gas phase using the reaction gas, but the dry film material (plating resist) remains as a whole, and only the modified material is modified. Its surface. That is, stable conditions are deliberately set for processing as compared with the dry ashing treatment which is usually performed. The pressure environment at the time of performing the dry ashing treatment is not particularly limited and is arbitrary, and it is preferable to carry out the treatment under normal pressure as compared with the pressure reduction. The reason is because the overall residual plating resist is also suitable for the actual modification of the surface of the 200938048. On the other hand, when it is under reduced pressure, there is a possibility that the treatment effect is required to be achieved, and since the amount of decomposition of the ruthenium-coated material is increased, it is difficult to have an overall residual plating resist. In addition, the state of the reaction gas in the dry ashing treatment is not particularly limited and is arbitrary, and it is preferable to use a reactive gas in a plasma state from the viewpoint of improvement in productivity and the like. In the hydrophilization treatment, a treatment is carried out in which the contact angle of water on the surface of the plating resist is 50 or less. The reason is that if the contact of water is as low as this, the hydrophilicity will become a sufficiently high state, and the wettability of the surface of the plating resist will become high. On the other hand, when the contact angle exceeds 50, the wet ilability of the mineral coating agent cannot be sufficiently increased, and the solution exchange efficiency of the electrolytic copper plating solution cannot be sufficiently improved. In such a hydrophilization treatment, it is more preferable to carry out the treatment for making the contact angle 45 or less, and particularly preferably to be 20 or more and 35 or less. The hydrophilization treatment is not particularly limited as long as it can reduce the ratio of the hydrophobic group Q in the surface of the plating resist to increase the ratio of the hydrophilic group, and may be a physical treatment or a chemical treatment. Further, in the case of the above-described plasma ashing treatment, as a result, the contact angle of water on the surface of the plating resist is reduced, and it is possible to grasp that such treatment is also a hydrophilization treatment. After the surface modification step, the electrolytic copper plating step may be carried out immediately without special treatment, and for example, an acid washing treatment or a surfactant treatment may be performed before. Since such treatment is also a treatment capable of improving the wettability of the plating resist of 10 to 200938048, it is expected to be multiplied by the surface modification step, thereby further improving the solution exchange efficiency of the electrolytic copper plating solution. Further, in the case where the treatment is carried out in combination with this treatment, the acid washing treatment and the surfactant treatment may be carried out in this order. If the order is reversed, there is a possibility that the surfactant is washed out by acid washing, and thus the above multiplication effect is not sufficiently obtained. In the electrolytic copper plating step after the surface modification step, electrolytic copper plating is performed to form a wiring pattern layer in the opening portion of the plating resist. If this step is performed, the copper stripping of the electrode will be deposited on the electroless shovel copper coating exposed on the bottom surface of the opening of the plating resist, and as a result, the portion will be uniformly thickened. In the plating resist stripping step after the electrolytic plating 'copper step, a predetermined stripping liquid is used to peel off the plating resist. The stripping solution in this case is not particularly limited, and for example, an organic amine stripping solution is suitably used. In the organic amine-based stripping solution, examples of the organic amine contained as a main component include monoethanolamine, diethanolamine, triethanolamine, monomethylamine, dimethylamine, trimethylamine, ethylenediamine, and isopropylamine. , isopropanolamine, 2-amino-2-methyl-1-propanol, 2-amino-2-methyl-1,3-propanediol, and the like. Among these organic amines, a particularly preferred organic amine is a stripping solution containing monoethanolamine. The reason for this is that the peeling liquid containing monoethanolamine has been confirmed to permeate into the dry film material having alkali resistance and can be dissolved, and it is suitable for use in the production method associated with the above means. Further, some additives such as hydrazine or TMH may be added to the organic amine-based stripping liquid used in the plating resist stripping step. In the pattern separation step after the plating resist stripping step, the electroless copper plating layer directly under the plating resist -11-200938048 is removed to separate the wiring pattern layer. In this step, an etching solution capable of dissolving copper is used for etching. When this step is performed, the electroless copper plating layer is partially cut away, and the associated wiring pattern layers are independent of each other. [Embodiment] Hereinafter, a wiring board κ and a method of manufacturing the same according to an embodiment of the present invention will be described in detail based on Figs. 1 to 13 . As shown in Fig. 1, the wiring board K of the present embodiment is a so-called laminated multilayer printed wiring board having bud-up layers BUI and BU2 on both sides of the front and back. The core substrate 1 constituting the wiring board K is a flat plate having a front surface 2 and a back surface 3. The laminated layer BU 1 disposed on the surface 2 side of the core substrate 1 has a structure in which the laminated resin insulating layers 12, 16, 30 and the wiring pattern layers 10, 28, 28a, 34, and 34a are alternately formed. A through hole forming hole 12a is formed in the resin insulating layer 12, and a field via conductor 14 for electrically connecting the wiring pattern layer 1 and the inner wiring layer 4 is formed therein. A through hole forming hole 18 is formed in the resin insulating layer 16 to form a field contact conductor 26 for conducting the wiring pattern layers 10 and 28 therebetween. The laminated layer BU2 disposed on the back surface 3 side of the core substrate 1 has a structure in which the laminated resin insulating layers 13, 17, 31 and the wiring pattern layers 11, 29, 29a, 35, and 35a are alternately formed. A through hole forming hole 13a is formed in the resin insulating layer 13, and a field connecting conductor 15» for electrically connecting the wiring pattern layer 11 and the inner wiring layer 5 is formed in the resin insulating layer 17 to form a through- 12-200938048 The hole forming hole 19 is formed therein with a field contact conductor 27 that electrically connects the wiring pattern layers 11 and 29. The resin insulating layer 30 is entirely covered by the solder resist 32 having the opening 36 at a predetermined position. In the opening portion 36, the wiring pattern layer 34 formed on the resin insulating layer 30 is exposed on the first main surface 32a side, and as a result, the wiring pattern layer 34 is used as the first main surface side ridge groove ( Land) function. On the other hand, the resin insulating layer 31 is entirely covered by the solder resist 33 having the opening portion 37 in the positioning position. In the opening portion 37, the wiring pattern layer 35 formed on the resin insulating layer 31 is exposed on the second main surface 3 3 a side, and as a result, the wiring pattern layer 35 is used as the second main surface side ridge. The function of the slot. Further, on the wiring pattern layer 34 of the first main surface side land groove, solder bumps 38 which are higher than the first main surface 32a are protruded. Then, on the solder bumps 38, it is possible to bond electronic components such as 1C wafers (not shown) by soldering. On the other hand, the wiring pattern layer 35 of the second main-surface-side ridge groove is electrically connected to a printed wiring board such as a mother board (not shown). As shown in Fig. 1, a through hole is provided inside the wiring board K. In the through hole of the present embodiment, the cylindrical through-hole conductor 7 is deposited through the inner wall surface of the through-hole forming hole 6 of the core substrate 1 and the resin insulating layers 1 2 and 13 and also has a resin-filled resin. 9 is to compensate for the structure of the cavity portion of the through-hole conductor 7. Then, the conductor portion in the laminated layer BU1 on the surface 2 side of the core substrate 1 and the conductor portion in the laminated layer BU2 on the back surface 3 side of the core substrate 1 are desired by the through-hole conductor 7' of the through-hole 13-200938048 Conduction between. Next, a method of manufacturing the wiring board K of the present embodiment will be described based on the viewpoints of Figs. 2 to 13 . Fig. 2 is a schematic cross-sectional view of a core substrate 1 having a thickness of about 77 mm, which is mainly composed of a bismaleimide imide three-pill (BT) resin. On the surface 2 and the back surface 3 of the core substrate 1, copper foils 4a and 5a having a thickness of about 70 μm are adhered in advance. The copper foils 4a and 5a of the core substrate 1 are patterned by a conventional method (in this case, a subtractive method), and the inner wiring layers 4 and 5 are formed on the front surface 2 and the back surface 3 (see the third Figure). Further, by using a plurality of panels having a plurality of core substrates 1, the same steps can be performed for each of the core substrates 1. Next, as shown in Fig. 4, on the surface 2 and the back surface in the core substrate 1. 3, an insulating film made of an epoxy resin containing an inorganic tantalum is coated to form a resin insulating layer 1 2, 13 . Such a resin insulating layer 1 2, 13 has a thickness of about 40 μm and contains 30% by weight to 50% by weight of an inorganic tantalum material of about φ slightly spherical cerium oxide. Further, the inorganic crucible preferably has an average particle diameter of 1.0 μm or more and 10.0 μm or less. Then, with respect to a predetermined position on the surface of the resin insulating layers 12 and 13, a laser (not shown) is irradiated along the thickness direction (in the present embodiment, a carbon dioxide gas laser). As a result, as shown in Fig. 5, approximately the through-hole forming holes 12a and 13a for causing the inner wiring layers 4 and 5 to be exposed on the bottom surface thereof are formed through the resin insulating layers 12 and 13. Further, a through hole forming hole 6 having an inner diameter of about 200 μm penetrating through the core substrate 1 and the resin insulating -14 - 200938048 layers 12, 13 is formed by using a boring machine to cut through a predetermined position. Then, the entire surface of the resin insulating layers 12 and 13 including the through hole forming holes 12a and 13a and the inner wall surface of the through hole forming hole 6 are coated with a plating catalyst containing palladium or the like, and then the substrate is coated thereon. Electrolytic copper plating and electrolytic copper plating. As a result, as shown in Fig. 6, copper plating films 8a and 8b are formed on the entire surfaces of the resin insulating layers 12 and 13, and a thickness of about 40 μm and a substantially cylindrical shape are formed in the through hole forming holes 6. Through the hole conductor 7. At the same time, additional copper plating is performed in the via hole forming holes 12a, 13a to form the field interconnect conductors 14 and 15. Next, as shown in Fig. 6, the paste containing the inorganic tantalum-filled resin 9 is filled in the cavity of the through-hole conductor 7, and then thermally cured. Further, the paste for forming the filling resin 9 may be a conductive paste containing a metal powder. Further, as shown in Fig. 7, an electrolytic copper plating solution is formed to form copper plating films l〇b and lib on the copper plating films 8a and 8b. At this time, both end faces of the filling resin 9 are covered by plating plating l〇a, 11a. Further, the thicknesses of the copper plating film 8a, the crucible 10b, and the copper plating films 8b and 1 lb are each about 15 μm. Next, the wiring pattern layers 1 and 11 shown in Fig. 8 are formed by etching the copper plating films 8a and 10b and the copper plating film 8b' lib' by a conventional subtraction method. In addition, the wiring pattern layers 10 and 11 are the resin insulating layers in which the resin insulating layer on the inner layer side of the wiring layer layer 1 of the first layer of the layered layers BU1 and BU2 is the first layer. Next, as shown in Fig. 9, the same insulating film is attached to the resin insulating layer 12 of the first layer and the wiring pattern layer 1 of the first layer, and -15-200938048 forms the resin of the second layer. Insulation layer 16. Similarly, the same insulating film as described above is attached to the resin insulating layer 13 of the first layer and the wiring pattern layer 11 of the first layer to form a resin insulating layer 17 of the second layer. Further, the predetermined position on the surface of the resin insulating layers 16 and 17 is irradiated with the same laser (not shown) along the thickness direction thereof to form a substantially conical through hole forming hole 18. , 19. The through hole forming holes 18 and 19 penetrate the resin insulating layers 16 and 17, and also expose one of the wiring pattern layers 10 and 11 to the bottom surface thereof. Then, the same plating catalyst as described above is applied to the entire surface of the resin insulating layers 16 and 17 including the inner wall surfaces of the through hole forming holes 18 and 19, and then electroless copper plating is performed (electroless plating). Mine copper step). When subjected to such a metal layer forming step, an electroless copper plating layer 20, 21 having a thickness of about 0.5 μm is formed (see a broken line in Fig. 9). At this time, the surface roughness Ra of the electroless copper plating layers 20 and 21 is about 0.2 μm. Next, as shown in Fig. 10, the photosensitive and insulating negative dry film materials 22 and 23 having a thickness Q of about 25 μm mainly composed of an acrylic resin are adhered to the entire surface of the electroless copper plating layers 20 and 21. . The dry film materials 22 and 23 selected in the present embodiment have a property of being less likely to swell in a strong alkali than the dry film material of the conventional epoxy resin-based material, and therefore have alkali resistance. Further, the dry film materials 22 and 23 have a surface roughness Ra of about 0.08 μm. The exposure mask (not shown) is placed in such a state as to be placed on the dry film members 22 and 23, and then an alkali developing solution such as a sodium hydroxide solution is used for development. Then, according to the steps of the dry film pasting, exposure and development as described above, the plating resists 2h, 22b, 23a, 23b of the predetermined pattern as shown in Fig. 11 are formed in each step -16-200938048 (resistance formation) step). Among the plating resists 22a, 22b, 23a, and 23b, a fine resist pattern having a line width of 15 μm or less (in the case of the present embodiment, 1 Ο μηη) is formed for the narrow plating resists 22b and 23b. Further, the size (i.e., the line interval) between the narrow plating resists 22b and 22b or between the openings 23a and 25b between 23b and 23b is 15 μm or less (in the case of the present embodiment, ▲ is ΙΟμηη) Become a so-called high aspect ratio pattern. Further, between the narrow plating resist 22b and the plating resist 22a adjacent thereto, or the opening between the narrow plating resist 23b and the plating resist 23a adjacent thereto The sizes of 24b and 25b are also the same size. At the same time, the openings 24, 25 having a wide area are formed on the surfaces of the electroless copper plating layers 20, 21 adjacent to the right and left through hole forming holes 18, 19. Next, dry ashing treatment is performed to reform the surfaces of the plating resists 22a, 22b, 23a, and 23b (surface modification step). In the present embodiment, more specifically, a conventional dry plasma ashing apparatus using an oxygen plasma reaction gas is treated under normal pressure. Here, the stable processing conditions (output: 200 W, 5 minutes) of about W4 in general processing conditions (output: 500 W, 15 minutes) are set, and the plating resists 22a, 22b, 23a, and 23b remain as a whole, and only the same is performed. Surface modification. As a result, it will be approximately 72 before processing. The contact angle of the water on the surface of the plating resists 22a, 22b, 23a, 23b is reduced to 50. The following (in the case of this embodiment, it is 3 1 °). This is considered to be attributed to the fact that by the above dry plasma ashing, the ratio of the -17-200938048 hydrophobic group on the surface of the shovel resists 22a, 22b, 23a, 23b is reduced, and the ratio of the hydrophilic groups is increased. Next, after the acid washing treatment, if necessary, it is washed with water and dried, and further subjected to surfactant treatment. As a result, the wettability of the plating resists 22a, 22b, 23a, and 23b is further improved. Next, the electroless copper plating layers 20 and 21 located on the bottom surfaces of the openings 24, 24a, 25, and 25a or the bottom surfaces of the through hole forming holes 18 and 19 are subjected to electrolytic copper plating to form copper plating by a conventional method. Precipitate. As a result, as shown in Fig. 12, the field contact conductors 26 and 27 are formed in the via hole forming holes 18 and 19, and the wiring pattern layers 28 and 29 which are the body of the contact conductors 26 and 27 are formed in the opening portion 24. 25 in. At the same time, the cross section is a rectangular shape having a longitudinal length, a width 'degree of 15 μm or less (in the case of the present embodiment, 1 μm), and a fine wiring pattern layer 28a and 29a having a thickness of about 25 μm are formed in each opening 24a. 25a (electrolytic copper plating step). Then, as shown in Fig. 13, 'the organic amine-based stripping liquid (0.5% by weight or more, 5 〇 ° C or more) contained in monoethanolamine as a main component is used, and the ruthenium plating resist 2 2 a, 2 2 b is peeled off. 2 3 a, 2 3 b (resist stripping step). Thereafter, the electroless copper plating layer 20 (21) located directly under the plating resists 2 2 a, 2 2 b, 2 3 a, 2 3 b is removed by soft etching using an etching solution (pattern) Separation step). If this step is performed, the electroless copper plating layer 20 (21) will be cut away. From the above results, the wiring pattern layers 28, 28a, 29, and 29a including the fine wiring pattern layers 28a and 29a each having a line width and a line interval of about 10 μm are formed. Further, a new resin insulating layer (third resin insulating layer) 30 is formed on the surface of the second resin insulating layer -18-200938048 layer 16 on which the wiring pattern layers 28 and 28a are formed. On the other hand, a new resin insulating layer (third resin insulating layer) 31 is formed on the surface of the second resin insulating layer 17 on which the wiring pattern layers 29 and 29a are formed. Then, on the resin insulating layers 30 and 31, the through hole forming holes (not shown) are formed by the above method. Thereafter, an electroless copper plating layer is formed on the surfaces of the resin insulating layers 30 and 31 and the through hole forming holes, and the shovel is formed by the steps of adhering, exposing, and developing the dry film as described above. In the resist forming step, in addition to the step of further performing the surface modification, the wiring pattern layer forming step, the plating resist stripping step, and the etching step are also performed. As a result, the wiring pattern layers 34, 34a, 35, and 35a including the fine wiring pattern layers 34a and 35a each having a line width and a line pitch of about ΙΟμη are formed on the third resin insulating layers 30 and 31, respectively. Further, while the solder resists 32 and 33 having a thickness of 25 μm are respectively provided on the third resin insulating layers 30 and 31, the solder bumps 38 are formed on the wiring pattern 34 exposed on the bottom surface of the opening 36: in the opening portion 37. Nickel-gold plating is applied to the wiring pattern 35 exposed on the bottom surface. As a result of the above, the wiring board 具备 having the laminated layers BUI and BU2 on both sides of the front and back sides as shown in Fig. 1 can be obtained. Therefore, according to the present embodiment, the following effects can be obtained: (1) According to the method of manufacturing the wiring board according to the embodiment, the surfaces of the plating resists 22a, 22b, 23a, and 23b having high hydrophobicity are dried. The electric prize ashing treatment (hydrophilization treatment) is modified, and the wettability is increased. Thereby, at the time of the electrolytic copper plating step, on the surfaces of the plating resists 22a, 22b, 23a, -19-200938048 23b, the electrolytic plating solution becomes difficult to be bounced. As a result, even if the opening portion 24a, 25a of the resist containing the high aspect ratio pattern easily penetrates into the inside of the electrolytic copper plating solution, the solution exchange efficiency of the electrolytic shovel copper liquid is improved, and uniform plating is performed. Thickness will also become readily available. Further, in this case, it is possible to omit the plating liquid stirring treatment or the like for improving the uniformity of the plating thickness, so that the equipment cost for the treatment can be reduced. As a result of the above, according to the method for manufacturing the wiring board K of the present embodiment, it is possible to form the fine wiring 图案 pattern layers 28a and 29a having a uniform thickness without being costly. Further, the embodiment of the present invention may be modified as follows: In the above embodiment, the BT resin is selected as the material for forming the core substrate 1, but it is not limited by the resin. For example, a ring may be used. An oxygen resin, a polyimide resin, or the like may be used, or a composite material such as glass fiber may be used in a fluorine-based resin having a three-dimensional network structure such as PTFE having continuous pores. Further, the core substrate 1 may be a high-temperature sintered substrate made of ceramic such as yttrium aluminum oxide, tantalum nitride, boron nitride, hafnium oxide, tantalum acid, glass ceramics or aluminum nitride, or may be about A low-temperature sintered substrate which is sintered at a lower temperature of 1000 ° C or lower. Further, the core substrate 1 may be a metal core substrate made of a copper alloy or a Fe-42 wt% Ni alloy. Further, in the present invention, since the core substrate 1 is not necessarily a structure, for example, a form in which a coreless substrate is used is also allowed. • In the above embodiment, copper is selected as the metal material for forming the wiring portions such as the wiring pattern layer 1〇, U or the contact conductors 26 and 27. However, -20-200938048 is not limited by copper, and silver or nickel may be used. , gold, copper alloys, iron-nickel alloys, etc. Alternatively, the conductor portion may be formed by a method of applying a conductive resin or the like instead of using a metal plating layer. • In the above embodiment, the form of the contact conductors 26 and 27 is a field-connected conductor in which the conductor is completely compensated, and it is of course possible to use an inverted conical shape in which the inside is not completely compensated by the conductor. ) Contact the conductor. • In the above embodiment, although the dry ashing treatment is performed by dry plasma ashing, it is also possible to use a dry ashing apparatus that does not use a plasma type. • In the above embodiment, a positive dry film material can be used even if the negative dry film materials 22 and 23 are used. Λ Next, in addition to the technical ideas disclosed in the scope of the patent application, the following is a technical idea that is based on the above-described embodiments: (1) A method of manufacturing a wiring board using a semi-additive method (semi- The manufacturing method of the wiring substrate for forming a wiring pattern layer, comprising the following steps: an electroless copper plating step, performing electroless copper plating to form an electroless copper plating layer on the surface of the resin insulating layer; a step of forming a coating, after the negative acrylic dry film is adhered to the electroless copper plating layer, performing exposure and development to form a plating resist of a predetermined pattern; and a surface modifying step on the resist After the forming step, 'dry plasma ashing treatment, while leaving the plating resist as a whole, 'also modified its surface; -21 - 200938048 electrolytic copper plating step, after the surface modification step 'electrolytic copper plating Forming the wiring pattern layer in the opening portion of the plating resist; a resist stripping step, using a stripping liquid to peel off the plating resist; and a pattern separating step to remove the plating resist The electroless copper coating is applied to separate the wiring pattern layer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a portion of an embodiment of a wiring substrate in which the embodiment is embodied. Ο Fig. 2 is a schematic partial cross-sectional view for explaining the process of the above wiring board. Fig. 3 is a schematic partial cross-sectional view showing the process of the wiring board i. Fig. 4 is a schematic partial cross-sectional view for explaining the process of the above wiring board. Fig. 5 is a partial schematic cross-sectional view for explaining the process of the above wiring board. Fig. 6 is a schematic partial cross-sectional view for explaining the process of the above wiring board. Fig. 7 is a schematic partial cross-sectional view for explaining the process of the above wiring board. Fig. 8 is a schematic partial cross-sectional view for explaining the process of the above wiring board. Fig. 9 is a view showing a partial outline of the process of the above wiring board -22-200938048. Fig. 1 is a schematic cross-sectional view showing a process of the above wiring board. Fig. 11 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 12 is a schematic cross-sectional view showing the process of the wiring board described above. ❹ Fig. 13 is a schematic cross-sectional view showing the process of the wiring board described above. [Description of main component symbols] 1 ' Core substrate 2 Surface 3 Back surface ❹ 4, 5 4a, 5 a 6 7 8a, 8b, l〇b, 1 lb 9 10a' 11a Inner wiring layer Copper box through hole forming hole Hole conductor copper plating film filled with resin coating 10, 11, 28, 28a, 29, 29a, 34, 34a, 35, 35a wiring pattern layer 1 2, 1 3, 1 6 ' 1 7 , 3 Ο, 3 1 Resin insulating layer -23- 200938048 12a > 13a, 18, 19 14, 15, 26 > 27 20, 2 1 22, 23 22a, 22b, 23a, 23b 24, 24a, 24b, 25 through hole forming hole Field contact conductor electroless copper coated acrylic dry film plating resist 25a 25b, 36, 37 plating resist opening portion 28a ' 29a fine wiring pattern in wiring pattern layer 32 ' 33 solder resist 32a First main surface 33a second main surface 3 8 solder bump K wiring substrate
-24--twenty four-