200939927 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種配線基板及其製造方法，尤其彳系關 於作爲基底的無電解鑛銅層上，形成具有積層電解鍍銅j層 而成之構造的配線圖案層之配線基板及其製造方法。 【先前技術】 近年來，伴隨電子機器之小型化及高性能化而要求電 子零件之高密度裝配化，欲達成此高密度裝配化，配線基 ® 板之多層化技術被視爲很重要。使用多層化技術的具體範 例，習知一種印刷配線基板（所謂積累層配線基板），其在 設置有穿孔部的核芯基板的單面或雙面，設置樹脂絕緣層 及導體交互地積層而形成之積累層（build up)的。此種印刷 配線基板之積累層，例如能以如以下之程序製作。 首先，在樹脂絕緣層之表面全體形成鍍銅層。其次， 在鍍銅層上貼附具有感光性的乾膜材之後，進行曝光及鹼 式顯影，而形成既定圖案之抗鍍光阻。其次，進行鍍銅而 W 在抗鍍光阻的開口部形成配線圖案層後，使用鹼剝離液將 抗鍍光阻加以膨潤而剝離。其次，進行蝕刻而將位於抗鍍 光阻正下方的鍍銅層加以除去，藉以形成所期望形狀之配 線圖案層。其後，更在配線圖案層上形成樹脂絕緣層，並 進行導通孔的開孔後，進行鍍銅而形成通路導體及鍍銅 層。其後，因應於需要而使此種過程反覆地進行多數次， 藉以使積累層逐漸地多層化。關於此積累層過程，習知有 多個範例（例如參照專利文獻1)。 -4- 200939927 近年來，配線圖案層之精細節距化的需求提高’例如 要求將配線圖案層之線寬及相鄰的配線圖案之間的線間隔 作成20μιη以下（較佳爲作成15/zm以下）。因而，在抗鍍 光阻中亦要求正確地形成同樣精細之抗鍍光阻圖案。 又，近年來，爲了在樹脂絕緣層與配線圖案層之間賦 予高度密著性而提高可靠度，預先進行配線圖案層之表面 糙化，而在表面形成微小的錨狀部之後，進行樹脂絕緣層 之形成。 ^ 【專利文獻1】日本特開2005-150554號公報 【發明内容】 【發明欲解決之課題】 但是，在上述先前技術之情況，當進行銅表面之糙化 時，配線圖案層會一部分被溶解而除去，因而變形爲l//m 般細條狀。因此，無法精度良好地形成特別之精細的配線 圖案層，而使配線圖案層的尺寸誤差變大。 本發明係鑑於上述之課題而開發者，其目的在提供一 〇 種配線基板及其製造方法，即使不進行表面糙化時，亦可 在樹脂絕緣層與配線圖案層之間賦予高度密著性，而且可 形成在形狀上優異的精細配線圖案層》 【解決課題之手段】 作爲用於解決上述課題的手段（手段1)，係在作爲基底 的無電解鍍銅層上將電解鍍銅層加以積層而成，並在底部 形成具有下切部之配線圖案層的配線基板之製造方法，其 特徵爲包含有下列步驟：無電解鍍銅步驟，進行無電解鍍 銅而在樹脂絕緣層上形成上述無電解鍍銅層；光阻形成步 -5- 200939927 驟，在上述無電解鏟銅層上形成既定圖案之抗鍍光阻；電 解鍍銅步驟，進行電解鍍銅而在上述抗鑛光阻之開口部析 出電解鍍銅層；光阻剝離步驟，使用剝離液將上述抗鑛光 阻剝離；圖案形成步驟I使用溶解電解鍍銅比溶解無電解 鍍銅更容易的蝕刻液，而選擇地除去位於上述抗鍍光阻正 下方的上述無電解鍍銅層，藉以在底部形成具有下切部的 配線圖案層；金屬表面改質步驟，在上述圖案形成步驟之 後，將樹脂黏著層形成於上述配線圖案層之表面上，以將 Q 該表面進行改質；及樹脂絕緣層形成步驟，在上述金屬表 面改質步驟之後，以覆蓋上述配線圖案層的方式而形成樹 脂絕緣層。 Λ 因而，當依照上述手段1的製造方法，藉進行金屬表 面改質步驟而在配線圖案層之表面上形成樹脂黏著層，結 果，該表面被改質爲可提高與樹脂絕緣層之黏著性的狀 態。而且，藉由圖案形成步驟而形成的上述配線圖案層， 係爲在底部具有下切部之截面形狀，因此可期待以樹脂絕 G 緣層封入下切部附近之間隙方式之錨定效果。由以上，即 使不進行表面糙化，亦可將充分的密著性賦予精細配線圖 案層與樹脂絕緣層之間。又，藉由不進行表面糙化，可避 免由糙化液造成的圖案之細條化，而可形成在形狀上優異 的精細配線圖案層。 上述手段1的製造方法係進行在作爲基底的無電解鍍 銅層上將電解鍍銅層加以積層而成，並進行在底部具有下 切部之配線圖案層的形成。當爲此種形狀之配線圖案層 時’可期待如上述之錨定效果，因此適合作爲將充分的密 -6- 200939927 著性賦予精細配線圖案層（尤其精細配線圖案層）與樹脂絕 緣層之間的構造。 在此製造方法中’首先’進行無電解鍍銅而在樹脂絕 緣層之表面進行形成無電解鍍銅層的無電解鍍銅步驟。選 擇無電解鍍銅層係因爲導電性高且低成本之故。無電解鍍 銅層之表面狀態並未特別限定而爲任意，例如表面粗度Ra 可作成0.2从m以上0.4 M m以下的粗面。此時鍍層表面之 凹凸的程度變小，在曝光時之光的散亂之影響變小，結果， H 變的容易實現高解析度。此外，當表面粗度Ra爲未滿0.2 Am時，由於乾膜材之密著性有成爲不充分之可能性，因 而較不適宜。 在無電解鍍銅步驟後之光阻形成步驟，係在無電解鍍 銅層上形成既定圖案之抗鍍光阻。抗鍍光阻並未特別限 定，例如可使用丙烯酸系乾膜材，在其貼附之後進行曝光 及顯影，以形成既定圖案之抗鍍光阻爲較佳。 在此光阻形成步驟中，係使用具有感光性的丙烯酸系 〇 乾膜材。該乾膜材雖可爲負型或正型之任一種，但在此以 選擇負型爲較佳。負型雖然有增加溫度時其剝離性降低， 因此必須以既定的剝離液進行剝離之缺點，但有利於形成 形狀優異的圖案之優點。又，相關的丙烯酸系乾膜材，以 具有耐鹼性爲宜。在此所謂「具有耐鹼性」係指具有對氫 氧化鈉等之強鹼完全不膨潤，或者與先前技術品比較下不 易膨潤的性質。此性質之不同，來自例如係由於屬乾膜材 之主成分的樹脂材料之交聯密度大小的不同。即，具有耐 鹼性之上述手段的乾膜材，與先前技術品比較有較高之樹 200939927 脂材料之交聯密度。但是，上述手段的乾膜材對有機胺並 不具有耐性，具有當暴露於有機胺時或多或少會溶解之性 質。此乃通常之鹼對上述乾膜材無法作爲剝離液使用，因 此有機胺可取代而作爲剝離液使用之意。 在將乾膜材貼附之後，進行曝光，進一步利用鹼進行 顯影而形成既定圖案之抗鍍光阻。在形成線寬及線間隔均 爲1 5 /z m以下之精細配線圖案之情況，同時必須預先設定 精細光阻圖案之寬度及相鄰之精細光阻圖案間的間隙之尺 ❹ 寸。此外，此情況之精細光阻圖案間的開口部，係爲所謂 的高縱橫比（aspect)。 在光阻形成步驟後之電解鍍銅步驟中，進行電解鍍銅 而在抗鍍光阻之開口部析出電解鍍銅層。經過此步驟時， 在抗鍍光阻之開口部的底面顯露之電解鍍銅層上析出電解 鍍銅，結果，該部分變成均勻地變厚。 在電解鍍銅步驟後之光阻剝離步驟中，使用既定的剝 離液將抗鍍光阻剝離。雖然此情況之剝離液並未特別加以 〇 限定，但是例如以使用有機胺系剝離液爲較佳。有機胺系 剝離液中被包含以作爲主要成分之有機胺，例如可舉出： 單乙醇胺、二乙醇胺、三乙醇胺、一甲基胺、二甲基胺、 三甲基胺、乙二胺、異丙胺、異丙醇胺、2-胺基·2-甲基— 1-丙醇、2-胺基-2-甲基-1,3-丙二醇等。其等之中，尤其以 含有係有機胺之單乙醇胺之剝離液爲較佳。其理由係含有 單乙醇胺之剝離液，已確認可滲透具有耐鹼性之上述乾膜 材並將其溶解，使用在上述手段相關的製造方法中係好方 法之故。此外，在光阻剝離步驟中使用的有機胺系剝離液 -8- 200939927 中，亦可添加若干稱爲胼聯胺或TMH等之添加劑° 在光阻剝離步驟後之圖案形成步驟中’使用溶解電解 鍍銅比溶解無電解鑛銅更容易的蝕刻液，而選擇地除去位 於上述抗鍍光阻正下方的上述無電解鍍銅層。藉由此處 理，無電解鍍銅層局部地被切離，相連的諸配線圖案層彼 此互相孤立，同時形成在底部具有下切部之配線圖案層。 在圖案形成步驟後的金屬表面改質步驟，係將樹脂黏 著層形成於配線圖案層之表面上，以將該表面進行改質。 φ 在此所謂「樹脂黏著層」係指爲了提高配線圖案層對樹脂 絕緣層之黏著性而使用的比較薄的層之意。相關樹脂黏著 層之合適例方面，例如可舉出：藉由進行藥液處理而形成 該樹脂黏著層，並在其組成中含有金屬氧化物者。即，金 屬氧化物之氧原子與樹脂材料中之氫氧基的親和性高，且 金屬氧化物之金屬原子與金屬材料之親合性高，因此在樹 脂·金屬之界面存在有樹脂黏著層時，可導致兩者之密著性 的提高。此外，此情況中之金屬氧化物，以氧化錫或氧化 〇 銅等具有某程度之導電性的金屬氧化物爲宜。 而在另外的樹脂黏著層之合適例方面，可舉出藉由進 行使用矽烷偶合劑的矽烷偶合處理而形成者。砂院偶合劑 係一有機矽化物’其在一分子中具有與樹脂材料反應結合 的有機官能基及與金屬材料反應結合的官能基（加水分解 基）。藉此二個官能基而達成樹脂-金屬之界面的密著性之 提高。 在除此之外的樹脂黏著層方面，亦可藉由在由銅所形 成配線圖案層之表層的氧化處理而形成的黑化層（氧化銅 -9- 200939927 層）等。又’爲了形成樹脂黏著層，雖然在上述多個處理（金 屬氧化物形成處理、矽烷偶合處理、表層銅氧化處理）之中 選擇一個實施即已足夠，但是例如亦可將複數個處理加以 組合而實施。依後者的話，可期待有相乘效果。其較佳的 組合方面，可舉出金屬氧化物形成處理及矽烷偶合處理之 組合，尤其在金屬氧化物形成處理後實施矽烷偶合處理較 適合。 此外，在上述金屬表面改質步驟之後及樹脂絕緣層形 D 成步驟之前，因應於需要，亦可進行將殘餘的樹脂黏著層 加以除去的酸洗淨處理。此情況所謂之「殘餘的樹脂黏著 層」，例如係指並非附著在配線圖案層表面而係附著在樹脂 絕緣層表面之樹脂接著層之謂。即，附著在此部分之樹脂 黏著層，由於並非位於樹脂-金屬之界面，因此即使存在時 不僅對密著性之提高不會有幫助，相反的更恐有使樹脂-金 屬之界面的密著性降低之可能性。此外，附著在由金屬形 成的配線圖案層表面之樹脂黏著層也同樣地，以均勻且適 〇 量爲宜。 雖然金屬表面改質步驟亦可在圖案形成步驟之後緊接 著進行，但是亦可在金屬表面改質步驟之前進行洗淨。此 時之洗淨方法雖然並未特別限定而可係任意的，但是以進 行酸洗淨取代水洗時可充分地將蝕刻液去除，而可提高金 屬表面改質步驟的處理效率。 或者，亦可在金屬表面改質步驟之前，進行針對將電 解鍍銅層作爲主體之上述配線圖案層蝕刻處理。但是’在 此階段之蝕刻處理，必須在穩定的條件下進行’具體上係 -10- 200939927 進行蝕刻將配線圖案層之表層只比0.2#m少之量之快速 蝕刻處理（軟蝕刻處理）即可。只要係此程度之蝕刻處理的 話，由於銅的溶解除去量極少，因此不致引起配線圖案層 之細條化等，而不致降低精細之配線圖案層的形成精度。 又，依相關之處理的話，藉由配線圖案層表層之氧化銅皮 膜之除去，可使表面活性化，而成爲適於爲了表面改質之 樹脂黏著層之形成的狀態。此外，當蝕刻量變成以 上時，恐有精細之配線圖案層的形成精度降低之虞而較不 0 適用。 其後，在金屬表面改質步驟後之樹脂絕緣層形成步驟 中，係以覆蓋經f面改質之配線圖案層的方式形成樹脂絕 緣層。由於在配線圖案層之表面上形成樹脂絕緣層，由於 此樹脂絕緣層之介在而可使配線圖案層及樹脂絕緣層密 著。又’樹脂絕緣層之一部分封入到位於配線圖案層底部 之下切部附近之間隙，可期待此封入所成之錨定效果。由 以上’不特別進行表面糙化，亦可將充分的密著性賦予精 Ο 細之配線圖案層與樹脂絕緣層之間。 作爲用於解決上述課題之另外的手段（手段2)，係一種 配線基板，其特徵爲具備有··第1樹脂絕緣層；精細配線 圖案層’其配置在上述第1樹脂絕緣層上，由在作爲基底 之無電解鍍銅層上積層電解鍍銅層而成，並於底部具有下 切部’線寬及線間隔均爲以下；金屬表面改質用之 樹脂黏著層，形成於上述精細配線圖案層之表面上；及第 2樹脂絕緣層’作成覆蓋上述精細配線圖案層的方式而積 層配置在上述第1樹脂絕緣層上；上述第2樹脂絕緣層之 -11- 200939927 一部分係封入於上述精細配線圖案層之上述下切部與上述 第1樹脂絕緣層之間隙中。 此時’上述金屬表面改質用之樹脂黏著層，在其組成 中可含有金屬氧化物，或者亦可藉由進行矽烷偶合處理而 形成。又’上述樹脂黏著層亦可不形成在上述第2樹脂絕 緣層之表面上。 【實施方式】 [第1實施形態] 〇 以下，將根據第1圖〜第12圖詳細地說明將本發明加 以具體化之一實施形態的配線基板K1及其製造方法。 , 如第1圖所示，本實施形態的配線基板K1，係在表背 兩面具有積累層BU1,BU2,即所謂積累層多層印刷配線基 板。構成此配線基板K1的核芯基板1，係爲具有表面2及 背面3之平板狀。 配置於核芯基板1之表面2側的積累層BU1，係具將 樹脂絕緣層12，16，30、配線圖案層10, 28，28a，34，34a Ο 交互地積層之構造》在樹脂絕緣層12形成有導通孔形成用 孔12a，在其內部形成有導通配線圖案層10及內層配線層 4的場通路導體14。在樹脂絕緣層16形成有導通孔形成用 孔18,在其內部形成有導通配線圖案層1〇, 28之間的場通 路導體26。 配置於核芯基板1之背面3側的積累層BU2 ’係具將 樹脂絕緣層13，17，31、配線圖案層11, 29，29a，35，35a 交互地積層之構造。在樹脂絕緣層13形成有導通孔形成用 孔13a，在其內部形成有導通配線圖案層11及內層配線層 -12- 200939927 5的場通路導體15。在樹脂絕緣層17形成有導通孔形成用 孔19,在其內部形成有導通配線圖案層11，29之間的場通 路導體27。 樹脂絕緣層30係藉由在既定處具有開口部36的銲阻 32而全體地被覆。此等開口部36係將形成於樹脂絕緣層 30上的配線圖案層34顯露在第1主面32a側。其結果， 該配線圖案層34係作爲第1主面側島部（land)的功能。另 一方面，樹脂絕緣層31係藉由在既定處具有開口部37的 φ 銲阻33而全體地被覆。此等開口部37係將形成於樹脂絕 緣層31上的配線圖案層35顯露在第2主面33a側。其結 果，該配線圖案層35係作爲第2主面側島部的功能。 又，在屬於第1主面側島部的配線圖案層34之上，形 成有突出比第1主面32a更高的銲接凸塊38。其後，在此 等銲接凸塊38上，經由銲劑而可接合未圖示之1C晶片等 之電子零件。另一方面，屬於第2主面側島部的配線圖案 層35，係與未圖示之主機板（mother board)等之印刷配線基 〇 板作電性連接。 如第1圖所示，在此配線基板K1之內部設置有貫穿 孔。本實施形態之貫穿孔係具有在貫通核芯基板1及樹脂 絕緣層12，13的貫穿孔形成用孔6之內壁面析出圓筒狀之 貫穿孔導體7，同時以充塡樹脂9埋入此貫穿孔導體7之 空洞部的構造。其後，藉由此貫穿孔之貫穿孔導體7，而 達成核芯基板1之表面2側的積累層BU1之導體部分、及 核芯基板1之背面3側的積累層BU2之導體部分之間的導 通。 -13- 200939927 如第1圖及第2圖所示，本實施形態之配線基板ΚΙ 之配線圖案層28, 28a，29, 29a，係具有在無電解鍍銅層20a 上積層電解鍍銅層2〇b的層構造。在此，特別在線寬及線 間隔均爲1 5μιη以下之配線圖案層（即精細配線圖案層），賦 予28 a，29a之元件符號。在配線圖案層28, 28a，29, 29a之 底部，換言之，在無電解鍍銅層20a之部分，產生越朝向 核芯基板1側越細的逆推拔（taper)狀之下切部U1。又，在 配線圖案層28, 28 a，29, 29a之表面上形成其組成中含有金 〇 屬氧化物的樹脂黏著層41，藉由此樹脂黏著層41將配線 圖案層28，28a，29, 29a之表面進行改質。其後，在表面2 側之積累層BU1的樹脂絕緣層16(第1樹脂絕緣層）上，樹 脂絕緣層30(第2樹脂絕緣層）係作成以覆蓋配線圖案層 2 8a的方式而積層配置。在背面3側之積累層BU2的樹脂 絕緣層17(第1樹脂絕緣層）上，樹脂絕緣層31(第2樹脂絕 緣層）係作成以覆蓋配線圖案層29a的方式而積層配置。 又，樹脂絕緣層30之一部分被封入到配線圖案層28，28a ❹ 之下切部U 1與樹脂絕緣層1 6之間隙。同樣地，樹脂絕緣 層31之一部分被封入到配線圖案層29，29a之下切部U1 與樹脂絕緣層17之間隙。以上之結果，可顯現有助於配線 圖案層28, 28a與樹脂絕緣層16之密著性、配線圖案層29, 2 9a與樹脂絕緣層17之密著性的提高之錨定效果。 其次，將根據第3圖~第12圖說明本實施形態之配線 基板K1的製造方法。 首先，準備以雙馬來醯亞胺三嗪（BT)樹脂爲主體之厚 度約爲0.7mm之核芯基板1。在核芯基板1之表面2及背 -14- 200939927 面3,預先貼附厚度約70μηι的銅箔。以先前技術周知的方 法（在此爲消減法）將此基板1之銅箔加以圖案化，而在表 面2上及背面3上形成內層配線層4，5。此外，亦可使用 採取多數個具有複數核芯基板1之面板，對各核芯基板1 之進行同樣的步驟。 其次，在核芯基板1之表面2及背面3上，被覆由含 有無機充塡料的環氧樹脂所形成的絕緣性膜，藉以形成樹 脂絕緣層12，13。相關之樹脂絕緣層12，13，厚度約爲 0 40μιη，係含有大致球狀的矽所形成的無機充塡料30重量 %~50重量％。此外，上述無機充塡料的平均粒徑可爲Ι.Ομηι 以上ΙΟ.Ομιη以下。 其次，在樹脂絕緣層12, 13之表面的既定位置，沿著 其厚度方向照射未圖示之雷射（本實施形態中爲碳酸氣體 雷射）。其結果，形成貫穿樹脂絕緣層12, 13並在其底面形 成露出內層配線層4，5之大致圓錐狀之導通孔形成用孔 12a，13a。進一步，使用鑽頭將既定位置進行鑽孔，藉以形 〇 成貫穿核芯基板1及樹脂絕緣層12，13之內徑約200 μιη的 貫穿孔形成用孔6。 其次，在含有導通孔形成用孔12a, 13a的樹脂絕緣層 12, 13之表面全體及貫穿孔形成用孔6之內壁面，塗布含 有鈀等之電鍍觸媒後，在其上實施無電解鍍銅及電解鑛 銅。其結果，在樹脂絕緣層12, 13之表面全體形成鍍銅膜， 在貫穿孔形成用孔6內形成厚度約40 μιη之大致圓筒形的 貫穿孔導體7。同時，在導通孔形成用孔12a，13a內，藉 實施追加之鍍銅而形成場通路導體14，15。 -15- 200939927 其次，在貫穿孔導體7之空洞部內充塡含有無機充塡 料的充塡樹脂9之糊膏後，將其進行熱硬化。此外，用於 充塡樹脂9之形成的糊膏，亦可爲含有金屬粉末的導電性 糊膏。又，進行電解鍍銅且更在鍍銅膜上形成鍍銅膜。此 時，同時地作成以蓋鍍l〇a，11a將充塡樹脂9之兩端面加 以覆蓋。此外，分爲兩次進行的鍍銅膜的厚度，係分別爲 約 1 5 μ m。 其次，藉由先前技術周知的消減法將此等2層之鍍銅 〇 膜加以蝕刻，而分別形成如第3圖所示之配線圖案層1 0, 11。此外，此等配線圖案層10, 11係成爲積累層BU1，BU2 之第1層的配線圖案層，位於其內層側的樹脂絕緣層則爲 第1層之樹脂絕緣層。 其次，如第4圖所示，在第1層之樹脂絕緣層12及第 1層之配線圖案層10之上貼附上述同樣的絕緣性薄膜，而 形成第2層之樹脂絕緣層16。同樣地，在第1層之樹脂絕 緣層13及第1層之配線圖案層11之上貼附上述同樣的絕 〇 緣性薄膜，而形成第2層之樹脂絕緣層17。進一步，對樹 脂絕緣層16，17之表面的既定位置，沿著其厚度方向照射 未圖示之雷射（未圖示），藉以形成大致圓錐狀之導通孔形 成用孔18, 19。導通孔形成用孔18, 19貫穿樹脂絕緣層16, 17,同時在其底面露出配線圖案層10,11之一部分。其後， 在包含上述導通孔形成用孔18, 19之內壁面的樹脂絕緣層 16，17之表面全體，預先塗布上述同樣的鍍觸媒之後，實 施無電解鍍銅（無電解鏟銅步驟）。當通過此種金屬層形成 步驟時，形成厚度約0.5 μηι的無電解鍍銅層20 a(參照第4 -16- 200939927 圖）。在此時點，無電解鍍銅層20a之表面粗度Ra約爲 0.2 μιη 〇 其次，如第5圖所示，在無電解鑛銅層2 0a之表面全 體，黏著以丙烯酸系樹脂作爲主體厚度之約25 μπι之具感 光性及絕緣性之乾膜材22。在本實施形態選擇的乾膜材 22，和以環氧樹脂作爲主體的習知品之乾膜材比較，具有 對強鹼難以膨潤的性質，因而具有耐鹼性。在相關的乾膜 材22上配置未圖示之曝光用光罩的狀態下曝光，其後使用 φ 氫氧化鈉溶液等之鹼顯像液進行顯影。結果，藉由如上述 乾膜材22之貼附、曝光及顯影的各步驟，而形成如第6圖 所示之既定圖案的0鍍光阻22a, 22b(光阻形成步驟）。 此等之抗鍍光阻22a，22b之中，狹小的抗鍍光阻22b 成爲線寬15μπι以下（本實施形態爲ΙΟμιη)之精細光阻圖 案。又，狹小的抗鍍光阻22b，22b之間的開口部24a之尺 寸（即線間隔）爲15μιη以下（在本實施形態爲ΙΟμιη)。此外， 狹小的抗鍍光阻22b及與其相鄰的抗鍍光阻22a之間的開 〇 口部24b之尺寸，亦爲同樣的尺寸。同時，在鄰接於導通 孔形成用孔18，19之左右的無電解鍍銅層2 0a之表面，形 成具比較寬之面積的開口部24。 其次，對位於開口部24, 24a之底面或導通孔形成用孔 18, 19之底面的無電解鍍銅層20a，利用先前技術周知之方 法進行電解鍍銅而析出電解鍍銅層20b(參照第7圖之電解 鍍銅步驟）。 其次，如第8圖所示，使用含有以單乙醇胺爲主成分 的有機胺系剝離液（〇 . 5重量％，5 0 °C以上）將抗鍍光阻2 2 a， -17- 200939927 2 2b剝離（光阻剝離步驟）。其後，使用既定蝕刻液將位於抗 鍍光阻22a, 22b之正下方的無電解鍍銅層20a進行軟蝕刻 處理而選擇地除去（圖案形成步驟）。此時，上述既定之蝕 刻液，係使用溶解無電解鍍銅層2〇a比溶解電解鍍銅層20b 更容易的以往周知之市販的蝕刻液。藉由此處理，如第9 圖等所示，無電解鍍銅層20a被局部地切離，形成相連的 諸配線圖案層28, 28a，29, 29a彼此互相孤立，同時在底部 具有下切部U1之配線圖案層28，28 a, 29，29a。以上之結 φ 果，可形成包含線寬及線間隔均爲1〇 μηι左右之精細配線 圖案層28a，29a的配線圖案層28，28a，29，29a。 其次，使用既定之洗淨液（例如美克公司製商品名稱爲 > 「美克布萊特CA-5 3 3 0A」）進行酸洗淨及水洗。其後，使 用既定之藥液進行化學處理，並在配線圖案層28, 28 a，29, 29a之表面上形成在組成中包含金屬氧化物（氧化錫或氧化 銅等）之樹脂黏著層41 (參照第10圖等之虛線，金屬表面改 質步驟）。其結果，配線圖案層28，28a，29，29a之表面被 Q 改質，由於該表面可提高配線圖案層28, 28 a，29, 29a對樹 脂絕緣層3 0, 3 1之黏著性，故爲適合的狀態。在本實施形 態中，表面改質用之藥液，例如可使用黏著性促進劑 (adhesion promoter) ° 此後，再度進行酸洗淨及水洗且進行乾燥之後，如第 11圖所示，在具有表面改質後之配線圖案層28, 28a之第2 層之樹脂絕緣層16(第1樹脂絕緣層）之表面上，形成新的 第3層之樹脂絕緣層3 0(第2樹脂絕緣層），以此樹脂絕緣 層30將配線圖案層28，28a全體加以覆蓋。另一方面，在 -18- 200939927 具有表面改質後之配線圖案層29, 29a之第2層之樹脂絕緣 層17(第1樹脂絕緣層）之表面上，形成新的第3層之樹脂 絕緣層31(第2樹脂絕緣層），以此樹脂絕緣層31將配線圖 案層29，29a全體加以覆蓋。此時，藉由樹脂黏著層41之 介在可達成配線圖案層28，28a與樹脂絕緣層30之密接， 且可達成配線圖案層29, 29a與樹脂絕緣層31之密接。又， 樹脂絕緣層30, 31之一部分被封入位於配線圖案層28, 28a， 2 9, 29a之底部的下切部U1附近之間隙中，可期待藉由此 φ 封入之錨定效果。 進一步，在此等樹*脂絕緣層3 0，3 1之既定位置，利用 上述方法形成未圖示之導通孔形成用孔。其後，在樹脂絕 緣層3 0，31之表面及導通孔形成用孔內形成無電解鍍銅 層，並進行如上述乾膜材之無電解鍍銅層材黏著、曝光及 顯影之各步驟，更進一步進行電解鍍銅步驟、光阻剝離步 驟、圖案形成步驟等。結果，包含線寬及線間隔均爲ΙΟμιη 左右的精細配線圖案層34a，35a的配線圖案層34，34a，35, ❹ 35a分別在第3層之樹脂絕緣層30，31上形成。 進一步，在第3層之樹脂絕緣層30，31上分別設置厚 度爲25μιη之抗焊光阻32，33，同時在開口部36之底面顯 露的配線圖案層34上形成銲接凸塊38，在開口部37之底 顯露的配線圖案層35上實施鎮-金電鑛。以上之結果，在 如第1圖所不之表背兩面’可獲得具備積累層BUl，BU2 的配線基板Κ 1。 因而，依本實施形態的話，可獲得以下之效果。 (1)在第12圖所示之先前技術的配線基板之製造方 -19- 200939927 法中，通常在進行形成於樹脂絕緣層105上之配線圖案層 102A，103A的表面糙化之後，形成樹脂絕緣層106。因此， 藉由糙化處理將配線圖案層102A，103A加以部分溶解除 去，而變形爲Ιμιη左右之細條（參照第12圖之構件號碼102, 1 〇3)，故無法精度良好地形成精細的配線圖案層1 〇3。 相對於此，依本實施形態的配線基板Κ1時，藉由進行 金屬表面改質步驟，而在配線圖案層28, 28a, 29, 29a之表 面上形成樹脂黏著層41，結果，該表面被改質爲可提高與 ❹ 樹脂絕緣層30，31之黏著性的狀態。而且，藉由圖案形成 步驟形成的上述配線圖案層28，28a, 29，29a，係爲在底部 具有下切部U1的剖面形狀。因此，可期待藉由樹脂絕緣層 3〇, 31之封入下切部U1附近的間隙之錨定效果。亦即，封 入間隙中的樹脂部分被下切部U1鉤住而形成抵抗，因此樹 脂絕緣層3 0，3 1變成不易剝離。由以上之事，即使不進行 配線圖案層2 8, 28a，29, 29a之表面糙化時，亦可在配線圖 案層2 8, 28a，29，29a(尤其精細配線圖案層28a，29a)與樹 Ο 脂絕緣層3 0，3 1之間充分地賦予密接性。又，由於不進行 表面糙化，可避免由糙化液造成的圖案變細，而可形成在 形狀上優異的精細配線圖案層28a，29a。 [第2實施形態] 其次，說明將本發明具體化之第2實施形態，在本實 施形態中，在上述第1實施形態之金屬表面改質步驟之 前，對配線圖案層2 8, 28a，29, 29a進行快速蝕刻處理，而 將其表層蝕刻爲Ο.ίμιη〜0.2μιη左右。其後，藉由此處理除 去配線圖案層28, 28a, 29, 29a表層之氧化銅皮膜，將表面 -20- 200939927 加以活化之後，進行表面改質用之樹脂黏著層之形成。 如此之本實施形態的製造方法，亦可達成與上述第1 實施形態同樣的作用效果。即，即使不進行表面糙化時， 亦可在配線圖案層28 a，29a與樹脂絕緣層30, 31之間充分 地賦予密接性，而且可形成形狀優異的精細配線圖案層28, 29a。又，倂用快速蝕刻處理的話，亦可賦予更高的密接性。 [第3實施形態] 其次，說明將本發明具體化之第3實施形態，在本實 Q 施形態中，係取代在上述第1實施形態中使用之表面改質 用之藥液，而使用習知之市販的矽烷偶合劑。其後，使用 此矽烷偶合劑進行矽烷偶合處理，以形成樹脂黏著層。此 > 外，在本實施形態中，矽烷偶合劑係使用阿托科技（Atotech) 公司製造的矽烷偶合劑。 如此之本實施形態的製造方法，亦可達成與上述第1 實施形態同樣的作用效果。即，即使不進行表面糙化時， 亦可在配線圖案層28 a，29a與樹脂絕緣層30, 31之間充分 〇 地賦予密接性，而且可形成形狀優異的精細配線圖案層2 8 a， 2 9 a 〇 [第4實施形態] 其次，說明將本發明具體化之第4實施形態，在本實 施形態中，係在上述第1實施形態中進行金屬氧化物層形 成處理之後，進一步進行第3實施形態之矽烷偶合處理’ 藉以形成樹脂黏著層。因而’依此等2種之處理的組合的 話，可期待金屬表面之改質相關的相乘效果’而可確實地 在配線圖案層28a，29a與樹脂絕緣層30，31之間充分地賦 -21- 200939927 予密接性。 此外，本發明的實施形態，亦可作如下之變更。 在上述實施形態，雖然形成核芯基板1的材料係選擇 BT樹脂，但是並不限於此，例如，亦可使用環氧樹脂、聚 亞醯胺樹脂等，或者亦可使用在具有連續氣孔的PTFE等 之三次元網目構造之氟系樹脂中含有玻璃纖維的複合材 料。此外，核芯基板1除了可使用由礬土、氮化矽、氮化 硼、氧化鈹、矽酸、玻璃陶瓷、氮化鋁等之陶瓷形成的高 0 溫燒成基板之外，亦可爲以約1〇〇〇°C以下之較低溫度燒成 的低溫燒成基板。進一步，核芯基板1可爲由銅合金或BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board and a method of manufacturing the same, and more particularly to forming an electroless copper plating layer on an electroless copper layer as a substrate. A wiring board of a wiring pattern layer having a structure and a method of manufacturing the same. [Prior Art] In recent years, with the miniaturization and high performance of electronic equipment, high-density assembly of electronic components is required. In order to achieve this high-density assembly, the multilayer technology of wiring base ® boards is considered to be important. A specific example of the multilayering technique is a printed wiring board (so-called build-up wiring board) in which a resin insulating layer and a conductor are alternately laminated on one or both sides of a core substrate provided with a through-hole portion. Build up. The buildup layer of such a printed wiring board can be produced, for example, by the following procedure. First, a copper plating layer is formed on the entire surface of the resin insulating layer. Next, after attaching a photosensitive dry film to the copper plating layer, exposure and alkali development are carried out to form a photoresist having a predetermined pattern. Next, copper plating is performed to form a wiring pattern layer in the opening portion where the photoresist is resisted, and then the plating resist is swollen and peeled off using an alkali stripping solution. Next, etching is performed to remove the copper plating layer directly under the plating resist to form a wiring pattern layer of a desired shape. Thereafter, a resin insulating layer is formed on the wiring pattern layer, and after the via holes are formed, copper plating is performed to form a via conductor and a copper plating layer. Thereafter, the process is repeated a plurality of times in response to the need, whereby the accumulation layer is gradually multi-layered. There are many examples of this accumulation layer process (for example, refer to Patent Document 1). -4-200939927 In recent years, the demand for fine pitch of the wiring pattern layer has increased. For example, it is required to set the line width of the wiring pattern layer and the line spacing between adjacent wiring patterns to 20 μm or less (preferably 15/zm). the following). Therefore, it is also required to form the same fine anti-plating resist pattern correctly in the anti-plating photoresist. In addition, in recent years, in order to improve the reliability by providing high adhesion between the resin insulating layer and the wiring pattern layer, the surface of the wiring pattern layer is roughened in advance, and a minute anchor portion is formed on the surface, and then resin insulation is performed. Formation of layers. [Patent Document 1] JP-A-2005-150554 SUMMARY OF INVENTION [Problem to be Solved by the Invention] However, in the case of the above prior art, when the copper surface is roughened, a part of the wiring pattern layer is dissolved. And removed, and thus deformed into a thin strip of l//m. Therefore, it is not possible to form a particularly fine wiring pattern layer with high precision, and the dimensional error of the wiring pattern layer is increased. The present invention has been made in view of the above problems, and an object of the invention is to provide a wiring board and a method of manufacturing the same, which can provide high adhesion between a resin insulating layer and a wiring pattern layer even when surface roughening is not performed. Further, a fine wiring pattern layer excellent in shape can be formed. [Means for Solving the Problem] As a means for solving the above problem (means 1), an electrolytic copper plating layer is applied to an electroless copper plating layer as a base. A method of manufacturing a wiring board in which a wiring pattern layer having an undercut portion is formed on a bottom portion, and the method includes the steps of: electroless copper plating, electroless copper plating, and formation of the above-described non-resin on the resin insulating layer Electrolytic copper plating layer; photoresist formation step-5-200939927, forming a predetermined pattern of anti-plating resistance on the electroless copper layer; electrolytic copper plating step, performing electrolytic copper plating on the opening of the above-mentioned anti-mineral photoresist Partially depositing an electrolytic copper plating layer; a photoresist stripping step, stripping the above-mentioned anti-mineral photoresist with a stripping liquid; pattern forming step I using dissolved electrolytic copper plating to dissolve without electrolysis An easier etching solution for copper, and selectively removing the electroless copper plating layer directly under the anti-plating resistance, thereby forming a wiring pattern layer having an undercut portion at the bottom; a metal surface modification step in the pattern forming step Thereafter, a resin adhesive layer is formed on the surface of the wiring pattern layer to modify the surface of Q, and a resin insulating layer forming step is performed to cover the wiring pattern layer after the metal surface modification step. A resin insulating layer is formed. Therefore, when the metal surface modification step is performed to form a resin adhesive layer on the surface of the wiring pattern layer in accordance with the manufacturing method of the above-described means 1, as a result, the surface is modified to improve the adhesion to the resin insulating layer. status. Further, since the wiring pattern layer formed by the pattern forming step has a cross-sectional shape having an undercut portion at the bottom portion, it is expected that the anchoring effect of the gap in the vicinity of the undercut portion is sealed by the resin insulating edge layer. From the above, even if the surface is not roughened, sufficient adhesion can be imparted between the fine wiring pattern layer and the resin insulating layer. Further, by not roughening the surface, it is possible to avoid the thinning of the pattern by the roughening liquid, and it is possible to form a fine wiring pattern layer excellent in shape. In the method of manufacturing the above-described means 1, an electrolytic copper plating layer is laminated on an electroless copper plating layer as a base, and a wiring pattern layer having an undercut portion at the bottom is formed. When it is a wiring pattern layer of such a shape, the anchoring effect as described above can be expected, and therefore it is suitable to impart a sufficient fine wiring pattern layer (especially a fine wiring pattern layer) and a resin insulating layer as sufficient density. The structure between the two. In this production method, electroless copper plating is performed first, and an electroless copper plating step of forming an electroless copper plating layer on the surface of the resin insulating layer is performed. The electroless copper plating layer is selected because of its high electrical conductivity and low cost. The surface state of the electroless copper plating layer is not particularly limited and is arbitrary, for example, the surface roughness Ra can be made 0. 2 from m above 0. Rough surface below 4 M m. At this time, the degree of unevenness on the surface of the plating layer is small, and the influence of the scattering of light at the time of exposure becomes small, and as a result, it is easy to achieve high resolution with H change. In addition, when the surface roughness Ra is less than 0. At 2 Am, the adhesion of the dry film is not sufficient, and it is not suitable. The photoresist forming step after the electroless copper plating step forms a photoresist having a predetermined pattern on the electroless copper plating layer. The resist plating resistance is not particularly limited. For example, an acrylic dry film material can be used, and after exposure, exposure and development are carried out to form a photoresist having a predetermined pattern. In this photoresist forming step, a photosensitive acrylic dry film material having photosensitivity is used. Although the dry film material may be either a negative type or a positive type, it is preferred to select a negative type here. Although the negative type has a reduced peeling property when the temperature is increased, it is necessary to perform the peeling by a predetermined peeling liquid, but it is advantageous in forming a pattern having an excellent shape. Further, the related acrylic dry film material preferably has alkali resistance. The term "having alkali resistance" as used herein means a property which does not swell completely with a strong base such as sodium hydroxide or is not easily swellable in comparison with the prior art. This difference in properties comes from, for example, the difference in the crosslink density of the resin material which is a main component of the dry film material. That is, the dry film material having the above-mentioned means of alkali resistance has a higher crosslink density than the prior art product 200939927. However, the dry film of the above means is not resistant to organic amines and has a property of more or less dissolution when exposed to an organic amine. Therefore, the above-mentioned dry base material cannot be used as a peeling liquid, and thus the organic amine can be used as a peeling liquid instead. After the dry film material is attached, exposure is carried out, and further development is carried out using an alkali to form a plating resist having a predetermined pattern. In the case of forming a fine wiring pattern having a line width and a line interval of 1 5 /z m or less, the width of the fine photoresist pattern and the gap between the adjacent fine resist patterns must be set in advance. Further, the opening portion between the fine resist patterns in this case is a so-called high aspect ratio. In the electrolytic copper plating step after the photoresist forming step, electrolytic copper plating is performed to deposit an electrolytic copper plating layer in the opening portion of the plating resist. When this step is performed, electrolytic copper plating is deposited on the electrolytic copper plating layer exposed on the bottom surface of the opening portion against the plating resist, and as a result, the portion becomes uniformly thick. In the photoresist peeling step after the electrolytic copper plating step, the plating resist is peeled off using a predetermined peeling liquid. Although the stripping liquid in this case is not particularly limited, it is preferred to use an organic amine stripping solution, for example. The organic amine-based stripping solution contains an organic amine as a main component, and examples thereof include monoethanolamine, diethanolamine, triethanolamine, monomethylamine, dimethylamine, trimethylamine, ethylenediamine, and the like. Propylamine, isopropanolamine, 2-amino-2-methyl-1-propanol, 2-amino-2-methyl-1,3-propanediol, and the like. Among them, a stripping liquid containing monoethanolamine which is an organic amine is preferable. The reason for this is a peeling liquid containing monoethanolamine, and it has been confirmed that the above-mentioned dry film having alkali resistance can be infiltrated and dissolved, and it is a method of use in the production method according to the above means. Further, in the organic amine-based stripping liquid -8-200939927 used in the resist stripping step, a plurality of additives called hydrazine or TMH may be added. In the pattern forming step after the photoresist stripping step, 'dissolution is used. Electrolytic copper plating selectively removes the above-mentioned electroless copper plating layer directly under the above-mentioned anti-plating resist, compared to an etching liquid which is easier to dissolve the electroless copper ore. By this, the electroless copper plating layer is partially cut away, and the connected wiring pattern layers are isolated from each other while forming a wiring pattern layer having an undercut portion at the bottom. In the metal surface modification step after the pattern forming step, a resin adhesive layer is formed on the surface of the wiring pattern layer to modify the surface. φ Here, the term "resin adhesive layer" means a relatively thin layer used to improve the adhesion of the wiring pattern layer to the resin insulating layer. As a suitable example of the relevant resin adhesive layer, for example, a resin adhesive layer is formed by chemical liquid treatment, and a metal oxide is contained in the composition. That is, since the oxygen atom of the metal oxide has high affinity with the hydroxyl group in the resin material, and the metal atom of the metal oxide has high affinity with the metal material, when the resin adhesive layer exists at the interface between the resin and the metal Can lead to an increase in the adhesion of the two. Further, the metal oxide in this case is preferably a metal oxide having a certain degree of conductivity such as tin oxide or beryllium oxychloride. Further, as a suitable example of the other resin adhesive layer, a decane coupling treatment using a decane coupling agent can be used. The sand yard coupling agent is an organic telluride which has an organic functional group reactively reacted with a resin material in one molecule and a functional group (hydrolyzed group) which reacts with the metal material. Thereby, the adhesion of the resin-metal interface is improved by the two functional groups. In addition to the resin adhesive layer, a blackening layer (copper oxide-9-200939927 layer) formed by oxidation treatment of a surface layer of a wiring pattern layer formed of copper may be used. Further, in order to form the resin adhesive layer, it is sufficient to select one of the plurality of processes (metal oxide formation treatment, decane coupling treatment, surface copper oxidation treatment), but for example, a plurality of treatments may be combined. Implementation. In the latter case, it is expected to have a multiplication effect. The preferred combination of the metal oxide formation treatment and the decane coupling treatment is particularly suitable for the decane coupling treatment after the metal oxide formation treatment. Further, after the metal surface modification step and before the step of forming the resin insulating layer D, an acid cleaning treatment for removing the residual resin adhesive layer may be performed as needed. In this case, the "residual resin adhesive layer" means, for example, a resin adhesive layer which adheres to the surface of the wiring pattern layer and adheres to the surface of the resin insulating layer. That is, since the resin adhesive layer attached to this portion is not located at the resin-metal interface, it does not contribute to the improvement of the adhesion even if it exists, and conversely, the resin-metal interface is densely adhered. The possibility of reduced sexuality. Further, the resin adhesive layer adhered to the surface of the wiring pattern layer formed of a metal is also preferably uniform and suitable. Although the metal surface modification step may be performed immediately after the pattern forming step, it may be washed before the metal surface modification step. Although the washing method at this time is not particularly limited, it may be arbitrary. However, when the acid washing is used instead of the water washing, the etching liquid can be sufficiently removed, and the treatment efficiency of the metal surface modification step can be improved. Alternatively, the wiring pattern layer etching treatment for the electrolytic copper plating layer as a main body may be performed before the metal surface modification step. However, the etching treatment at this stage must be carried out under stable conditions. Specifically, the etching is performed to etch the surface layer of the wiring pattern layer only to 0. 2#m is a small amount of rapid etching treatment (soft etching treatment). As long as the etching treatment is performed to such an extent, since the amount of copper removal and removal is extremely small, the wiring pattern layer is not thinned or the like, and the formation precision of the fine wiring pattern layer is not lowered. In addition, the surface of the surface of the wiring pattern layer is removed by the removal of the copper oxide film on the surface of the wiring pattern layer, and the surface is activated to form a resin-adhesive layer suitable for surface modification. Further, when the etching amount becomes equal to or higher, there is a fear that the formation precision of the fine wiring pattern layer is lowered and it is less than 0. Thereafter, in the resin insulating layer forming step after the metal surface reforming step, a resin insulating layer is formed so as to cover the f-face modified wiring pattern layer. Since the resin insulating layer is formed on the surface of the wiring pattern layer, the wiring pattern layer and the resin insulating layer can be adhered to each other due to the interposition of the resin insulating layer. Further, a part of the resin insulating layer is sealed to a gap in the vicinity of the cut portion below the bottom of the wiring pattern layer, and the anchoring effect by the sealing can be expected. From the above, the surface roughening is not particularly performed, and sufficient adhesion can be imparted between the fine wiring pattern layer and the resin insulating layer. Another means (means 2) for solving the above-mentioned problems is a wiring board including a first resin insulating layer, and a fine wiring pattern layer disposed on the first resin insulating layer. An electrolytic copper plating layer is laminated on the electroless copper plating layer as a base, and has a lower cut portion at the bottom portion having a line width and a line spacing; and a resin adhesive layer for modifying the metal surface is formed on the fine wiring pattern. And the second resin insulating layer ′ is disposed on the first resin insulating layer so as to cover the fine wiring pattern layer, and a part of the second resin insulating layer -11-200939927 is sealed in the fine layer. In the gap between the undercut portion of the wiring pattern layer and the first resin insulating layer. At this time, the resin adhesive layer for the metal surface modification described above may contain a metal oxide in its composition, or may be formed by performing a decane coupling treatment. Further, the resin adhesive layer may not be formed on the surface of the second resin insulating layer. [Embodiment] [First Embodiment] Hereinafter, a wiring board K1 and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to Figs. 1 to 12 . As shown in Fig. 1, the wiring board K1 of the present embodiment has accumulation layers BU1 and BU2 on both sides of the front and back, that is, a so-called accumulation layer multilayer printed wiring board. The core substrate 1 constituting the wiring board K1 has a flat plate shape having a front surface 2 and a back surface 3. The accumulation layer BU1 disposed on the surface 2 side of the core substrate 1 is structured to alternately laminate the resin insulating layers 12, 16, 30 and the wiring pattern layers 10, 28, 28a, 34, 34a 》 in the resin insulating layer The via hole forming hole 12a is formed in the 12, and the field via conductor 14 that turns on the wiring pattern layer 10 and the inner layer wiring layer 4 is formed inside. A via hole forming hole 18 is formed in the resin insulating layer 16, and a field path conductor 26 between the conductive wiring pattern layers 1 and 28 is formed inside. The accumulation layer BU2' disposed on the back surface 3 side of the core substrate 1 has a structure in which the resin insulating layers 13, 17, 31 and the wiring pattern layers 11, 29, 29a, 35, 35a are alternately laminated. A via hole forming hole 13a is formed in the resin insulating layer 13, and a field via conductor 15 of the conductive wiring pattern layer 11 and the inner wiring layer -12-200939927 5 is formed inside. A via hole forming hole 19 is formed in the resin insulating layer 17, and a field path conductor 27 between the conductive wiring pattern layers 11, 29 is formed inside. The resin insulating layer 30 is entirely covered by the solder resist 32 having the opening 36 at a predetermined place. These openings 36 expose the wiring pattern layer 34 formed on the resin insulating layer 30 on the first main surface 32a side. As a result, the wiring pattern layer 34 functions as a first main surface side island. On the other hand, the resin insulating layer 31 is entirely covered by the φ solder resist 33 having the opening 37 at a predetermined place. In the openings 37, the wiring pattern layer 35 formed on the resin insulating layer 31 is exposed on the second main surface 33a side. As a result, the wiring pattern layer 35 functions as the second main surface side island portion. Further, on the wiring pattern layer 34 belonging to the first main surface side island portion, solder bumps 38 projecting higher than the first main surface 32a are formed. Thereafter, on the solder bumps 38, electronic components such as 1C wafers (not shown) can be bonded via solder. On the other hand, the wiring pattern layer 35 belonging to the second main surface side island portion is electrically connected to a printed wiring substrate such as a mother board (not shown). As shown in Fig. 1, a through hole is provided inside the wiring board K1. In the through hole of the present embodiment, a cylindrical through-hole conductor 7 is deposited on the inner wall surface of the through hole forming hole 6 penetrating the core substrate 1 and the resin insulating layers 12 and 13, and the filling resin 9 is embedded therein. The structure of the cavity portion of the through-hole conductor 7. Thereafter, the conductor portion of the accumulation layer BU1 on the surface 2 side of the core substrate 1 and the conductor portion of the accumulation layer BU2 on the back surface 3 side of the core substrate 1 are obtained by the through-hole conductor 7 of the through-hole. Turn on. -13- 200939927 As shown in Fig. 1 and Fig. 2, the wiring pattern layers 28, 28a, 29, 29a of the wiring board 本 of the present embodiment have an electrolytic copper plating layer 2 laminated on the electroless copper plating layer 20a. The layer structure of 〇b. Here, the wiring pattern layer (i.e., the fine wiring pattern layer) having a line width and a line spacing of 15 μm or less is assigned to the component symbols of 28 a and 29a. At the bottom of the wiring pattern layers 28, 28a, 29, 29a, in other words, in the portion of the electroless copper plating layer 20a, the tapered lower portion U1 which is thinner toward the core substrate 1 side is generated. Further, on the surface of the wiring pattern layer 28, 28a, 29, 29a, a resin adhesive layer 41 containing a metal oxide is formed in the composition, whereby the wiring pattern layer 28, 28a, 29 is bonded by the resin adhesive layer 41, The surface of 29a was modified. Then, the resin insulating layer 30 (second resin insulating layer) is laminated on the resin insulating layer 16 (first resin insulating layer) of the buildup layer BU1 on the surface 2 side so as to cover the wiring pattern layer 28a. . In the resin insulating layer 17 (first resin insulating layer) of the buildup layer BU2 on the back surface 3 side, the resin insulating layer 31 (second resin insulating layer) is laminated so as to cover the wiring pattern layer 29a. Further, a part of the resin insulating layer 30 is sealed to the gap between the cut portion U 1 and the resin insulating layer 16 under the wiring pattern layer 28, 28a 。. Similarly, a portion of the resin insulating layer 31 is sealed to the gap between the cut portion U1 and the resin insulating layer 17 under the wiring pattern layers 29, 29a. As a result of the above, the anchoring effect of the adhesion between the wiring pattern layers 28, 28a and the resin insulating layer 16 and the adhesion between the wiring pattern layers 29, 29a and the resin insulating layer 17 can be exhibited. Next, a method of manufacturing the wiring board K1 of the present embodiment will be described based on Figs. 3 to 12 . First, the thickness of the bismaleimine triazine (BT) resin is about 0. 7mm core substrate 1. On the surface 2 of the core substrate 1 and the back surface - 14 - 200939927 surface 3, a copper foil having a thickness of about 70 μm is attached in advance. The copper foil of the substrate 1 is patterned by a method known in the prior art (here, the subtractive method), and the inner wiring layers 4, 5 are formed on the front surface 2 and the back surface 3. Further, the same steps can be performed for each of the core substrates 1 by using a plurality of panels having a plurality of core substrates 1. Next, on the surface 2 and the back surface 3 of the core substrate 1, an insulating film formed of an epoxy resin containing an inorganic filler is coated to form the resin insulating layers 12, 13. The related resin insulating layers 12, 13 have a thickness of about 0 40 μm, and are 30% by weight to 50% by weight of the inorganic filler formed by the substantially spherical crucible. In addition, the average particle size of the above inorganic filling material may be Ι. Ομηι above ΙΟ. Ομιη below. Then, at a predetermined position on the surface of the resin insulating layers 12, 13, a laser (not shown) (in the present embodiment, a carbon dioxide gas laser) is irradiated along the thickness direction. As a result, through-holes of the resin insulating layers 12, 13 are formed, and the substantially conical via hole forming holes 12a, 13a which expose the inner wiring layers 4, 5 are formed. Further, a drill is used to drill a predetermined position, and a through hole forming hole 6 having an inner diameter of about 200 μm penetrating through the core substrate 1 and the resin insulating layers 12, 13 is formed. Next, the entire surface of the resin insulating layers 12, 13 including the via hole forming holes 12a, 13a and the inner wall surface of the through hole forming hole 6 are coated with a plating catalyst containing palladium or the like, and then electroless plating is performed thereon. Copper and electrolytic copper. As a result, a copper plating film is formed on the entire surface of the resin insulating layers 12, 13, and a substantially cylindrical through-hole conductor 7 having a thickness of about 40 μm is formed in the through hole forming hole 6. At the same time, field via conductors 14, 15 are formed in the via hole forming holes 12a, 13a by performing additional copper plating. -15- 200939927 Next, the paste of the filling resin 9 containing the inorganic filler is filled in the cavity of the through-hole conductor 7, and then thermally cured. Further, the paste for forming the filling resin 9 may be a conductive paste containing a metal powder. Further, electrolytic copper plating is performed and a copper plating film is formed on the copper plating film. At this time, both ends of the filling resin 9 are covered with a lid plated l〇a, 11a. Further, the thickness of the copper plating film which was divided into two was about 15 μm. Next, the two-layer copper-plated tantalum film is etched by a subtractive method known in the prior art to form wiring pattern layers 10, 11 as shown in Fig. 3, respectively. Further, the wiring pattern layers 10 and 11 are the wiring pattern layers of the first layer of the accumulation layers BU1 and BU2, and the resin insulating layer on the inner layer side is the resin insulating layer of the first layer. Then, as shown in Fig. 4, the same insulating film is attached to the resin insulating layer 12 of the first layer and the wiring pattern layer 10 of the first layer, and the resin insulating layer 16 of the second layer is formed. In the same manner, the same insulating film as described above is attached to the resin insulating layer 13 of the first layer and the wiring pattern layer 11 of the first layer to form the resin insulating layer 17 of the second layer. Further, a predetermined position on the surface of the resin insulating layers 16, 17 is irradiated with a laser (not shown) (not shown) along the thickness direction thereof to form substantially conical via hole forming holes 18, 19. The via hole forming holes 18, 19 penetrate the resin insulating layers 16, 17, while exposing one portion of the wiring pattern layers 10, 11 on the bottom surface thereof. Then, the same plating catalyst is applied to the entire surface of the resin insulating layers 16 and 17 including the inner wall surfaces of the via hole forming holes 18 and 19, and then electroless copper plating is performed (electroless copper plating step). . When the step of forming the metal layer is performed, the thickness is formed to be about 0. 5 μηι of electroless copper plating layer 20 a (refer to Figure 4-16-200939927). At this point, the surface roughness Ra of the electroless copper plating layer 20a is about 0. 2 μιη 〇 Next, as shown in Fig. 5, the surface of the electroless copper ore layer 20a is entirely adhered to the dry film 22 having a photosensitive and insulating property of about 25 μm which is made of an acrylic resin. The dry film material 22 selected in the present embodiment has a property of being hard to swell against a strong alkali as compared with a dry film material of a conventional product mainly composed of an epoxy resin, and thus has alkali resistance. Exposure is carried out in a state in which an exposure mask (not shown) is placed on the relevant dry film 22, and then developed using an alkali developing solution such as φ sodium hydroxide solution. As a result, by the respective steps of attaching, exposing and developing the dry film 22 as described above, the 0 plating resists 22a, 22b (photoresist forming step) of the predetermined pattern as shown in Fig. 6 are formed. Among these anti-plating resists 22a and 22b, the narrow anti-plating resist 22b is a fine resist pattern having a line width of 15 μm or less (in the present embodiment, ΙΟμηη). Further, the size (i.e., the line interval) of the opening portion 24a between the narrow anti-plating resists 22b and 22b is 15 μm or less (in the present embodiment, ΙΟμηη). Further, the size of the opening portion 24b between the narrow anti-plating resist 22b and the adjacent anti-plating resist 22a is also the same size. At the same time, an opening portion 24 having a relatively wide area is formed on the surface of the electroless copper plating layer 20a adjacent to the left and right of the via hole forming holes 18, 19. Next, the electroless copper plating layer 20a is deposited on the bottom surface of the openings 24, 24a or the electroless copper plating layer 20a on the bottom surface of the via hole forming holes 18, 19 by a method known in the prior art to deposit an electrolytic copper plating layer 20b (see 7 electrolytic copper plating step). Next, as shown in Fig. 8, an organic amine-based stripping liquid containing monoethanolamine as a main component is used. 5 wt%, 50 ° C or more) The anti-plating photoresist 2 2 a, -17- 200939927 2 2b is stripped (resistive stripping step). Thereafter, the electroless copper plating layer 20a located directly under the resist plating resists 22a, 22b is subjected to a soft etching treatment using a predetermined etching liquid to be selectively removed (pattern forming step). In this case, the predetermined etching solution is a conventionally known etching liquid which is easier to dissolve the electroless copper plating layer 2〇a than the electrolytic copper plating layer 20b. By this treatment, as shown in Fig. 9, etc., the electroless copper plating layer 20a is partially cut away to form the connected wiring pattern layers 28, 28a, 29, 29a which are isolated from each other while having the undercut U1 at the bottom. Wiring pattern layers 28, 28 a, 29, 29a. According to the above result, the wiring pattern layers 28, 28a, 29, and 29a of the fine wiring pattern layers 28a and 29a each having a line width and a line spacing of about 1 〇 μηι can be formed. Next, acid washing and water washing are carried out using a predetermined washing liquid (for example, the product name > "McBright CA-5 3 30A" manufactured by Meike Co., Ltd.). Thereafter, chemical treatment is performed using a predetermined chemical solution, and a resin adhesive layer 41 containing a metal oxide (tin oxide or copper oxide, etc.) in the composition is formed on the surface of the wiring pattern layer 28, 28 a, 29, 29a ( Referring to the dotted line of Fig. 10 and the like, the metal surface is modified. As a result, the surface of the wiring pattern layers 28, 28a, 29, 29a is modified by Q, and since the surface can improve the adhesion of the wiring pattern layers 28, 28a, 29, 29a to the resin insulating layers 30, 31, For the right state. In the present embodiment, the chemical solution for surface modification can be, for example, an adhesion promoter. Thereafter, after acid washing, water washing, and drying, as shown in Fig. 11, the surface is provided. On the surface of the resin insulating layer 16 (first resin insulating layer) of the second layer of the wiring pattern layers 28 and 28a after the modification, a new third resin insulating layer 30 (second resin insulating layer) is formed. The wiring pattern layers 28, 28a are entirely covered by the resin insulating layer 30. On the other hand, on the surface of the resin insulating layer 17 (first resin insulating layer) of the second layer of the wiring pattern layers 29, 29a having the surface modification after -18-200939927, a new third layer of resin insulation is formed. The layer 31 (second resin insulating layer) covers the entire wiring pattern layers 29 and 29a with the resin insulating layer 31. At this time, the wiring layer layers 28, 28a and the resin insulating layer 30 can be adhered to each other by the resin adhesive layer 41, and the wiring pattern layers 29, 29a and the resin insulating layer 31 can be brought into close contact with each other. Further, one of the resin insulating layers 30, 31 is sealed in a gap in the vicinity of the undercut portion U1 at the bottom of the wiring pattern layers 28, 28a, 29, 29a, and the anchoring effect by the φ encapsulation can be expected. Further, at the predetermined positions of the tree grease insulating layers 30, 31, via holes for forming via holes (not shown) are formed by the above method. Thereafter, an electroless copper plating layer is formed on the surface of the resin insulating layer 30, 31 and the via hole forming hole, and each step of adhering, exposing, and developing the electroless copper plating material of the dry film material is performed. Further, an electrolytic copper plating step, a photoresist peeling step, a pattern forming step, and the like are performed. As a result, the wiring pattern layers 34, 34a, 35, and 35a including the fine wiring pattern layers 34a, 35a having the line width and the line spacing of about ΙΟμη are formed on the resin insulating layers 30, 31 of the third layer, respectively. Further, solder resists 32, 33 having a thickness of 25 μm are respectively provided on the resin insulating layers 30, 31 of the third layer, and solder bumps 38 are formed on the wiring pattern layer 34 exposed on the bottom surface of the opening portion 36, at the openings. The town-gold mine is implemented on the wiring pattern layer 35 exposed at the bottom of the portion 37. As a result of the above, the wiring board Κ 1 having the accumulation layers BU1, BU2 can be obtained on both sides of the front and back sides as shown in Fig. 1. Therefore, according to this embodiment, the following effects can be obtained. (1) In the method of manufacturing the wiring board of the prior art shown in FIG. 12 - 200939927, the resin is usually formed after the surface of the wiring pattern layers 102A, 103A formed on the resin insulating layer 105 is roughened. Insulation layer 106. Therefore, the wiring pattern layers 102A and 103A are partially dissolved and removed by the roughening treatment, and are deformed into thin strips of about Ιμηη (see the member numbers 102 and 1 〇3 in Fig. 12), so that fine wiring cannot be accurately formed. Pattern layer 1 〇3. On the other hand, in the case of the wiring board Κ1 of the present embodiment, the resin adhesion layer 41 is formed on the surface of the wiring pattern layers 28, 28a, 29, 29a by performing the metal surface modification step, and as a result, the surface is changed. The quality is such that the adhesion to the ruthenium resin insulating layers 30, 31 can be improved. Further, the wiring pattern layers 28, 28a, 29, 29a formed by the pattern forming step have a cross-sectional shape having a lower cut portion U1 at the bottom. Therefore, it is expected that the anchoring effect of the gap in the vicinity of the undercut portion U1 is sealed by the resin insulating layers 3?, 31. That is, the resin portion enclosed in the gap is caught by the undercut portion U1 to form a resistance, so that the resin insulating layer 30, 31 becomes less likely to be peeled off. From the above, even when the surface of the wiring pattern layers 2, 28a, 29, 29a is not roughened, the wiring pattern layers 2, 28a, 29, 29a (especially the fine wiring pattern layers 28a, 29a) can be used. The tree Ο grease insulating layer 30, 31 is sufficiently provided with adhesion. Further, since the surface roughening is not performed, the pattern formed by the roughening liquid can be prevented from being thinned, and the fine wiring pattern layers 28a and 29a excellent in shape can be formed. [Second Embodiment] Next, a second embodiment in which the present invention is embodied will be described. In the present embodiment, the wiring pattern layer 2, 28a, 29 is applied before the metal surface modification step of the first embodiment. , 29a performs a rapid etching process, and etches its surface layer into Ο. Μμιη~0. 2μιη or so. Thereafter, by removing the copper oxide film on the surface layer of the wiring pattern layers 28, 28a, 29, 29a, the surface -20-200939927 is activated, and then the resin adhesion layer for surface modification is formed. In the manufacturing method of the present embodiment as described above, the same operational effects as those of the first embodiment described above can be achieved. In other words, even when the surface is not roughened, the adhesion between the wiring pattern layers 28a and 29a and the resin insulating layers 30 and 31 can be sufficiently imparted, and the fine wiring pattern layers 28 and 29a having excellent shapes can be formed. Moreover, if the rapid etching treatment is used, it is possible to impart higher adhesion. [Third Embodiment] Next, a third embodiment of the present invention will be described. In the present embodiment, the chemical solution for surface modification used in the first embodiment is used instead. A decane coupling agent sold by the city. Thereafter, the decane coupling treatment was carried out using the decane coupling agent to form a resin adhesive layer. In addition, in the present embodiment, the decane coupling agent is a decane coupling agent manufactured by Atotech Co., Ltd. In the manufacturing method of the present embodiment as described above, the same operational effects as those of the first embodiment described above can be achieved. In other words, even when the surface is not roughened, the adhesion between the wiring pattern layers 28a and 29a and the resin insulating layers 30 and 31 can be sufficiently provided, and the fine wiring pattern layer 28 8 having excellent shape can be formed. [Fourth Embodiment] Next, a fourth embodiment in which the present invention is embodied will be described. In the present embodiment, after the metal oxide layer forming treatment is performed in the first embodiment, the second embodiment is further performed. 3 The decane coupling treatment of the embodiment ' is formed to form a resin adhesive layer. Therefore, when the combination of the two kinds of treatments is used, the multiplication effect related to the modification of the metal surface can be expected, and the wiring pattern layers 28a and 29a and the resin insulating layers 30 and 31 can be reliably provided. 21- 200939927 Adhesive. Further, the embodiment of the present invention may be modified as follows. In the above embodiment, the material for forming the core substrate 1 is BT resin. However, the BT resin is not limited thereto. For example, an epoxy resin, a polyimide resin, or the like may be used, or a PTFE having continuous pores may be used. A glass fiber composite material is contained in the fluorine-based resin of the three-dimensional mesh structure. In addition, the core substrate 1 may be a high-temperature-fired substrate formed of ceramics such as alumina, tantalum nitride, boron nitride, tantalum oxide, niobic acid, glass ceramics, or aluminum nitride. The substrate is fired at a low temperature which is fired at a lower temperature of about 1 ° C or lower. Further, the core substrate 1 may be made of a copper alloy or
Fe-42wt%Ni合金等形成的金屬核芯基板。又，本發明中之 » 核芯基板1並非必須使用的構成，因此例如，亦可容許採 用非核芯基板之形態。 在上述實施形態，雖然形成配線圖案層10，11或通路 導體26, 27等之導體部的金屬材料係選擇銅，但是並不限 於此，亦可採用銀、鎳、金、銅合金、鐵鎳合金等。或是， 〇 亦可利用塗布導電性樹脂等的方法來取代使用金屬電鍍 層，以形成上述導體部。 在上述實施形態，雖然通路導體26, 27之形態係採用 內部完全以導體埋入之場通路導體，但是當然亦可採用內 部完全未埋入導體的逆圓錐狀之保形（CON FORMAL)通路 導體。 在上述實施形態，雖然在第2層之樹脂絕緣層16，17 上之配線圖案層28, 28 a，29, 29a進行表面改質處理，但是 亦可在第3層之樹脂絕緣層30, 31上之配線圖案層34, 34a， -22- 200939927 35, 35a進行同樣的表面改質處理。 在上述實施形態，在第2層之樹脂絕緣層16，17上之 配線圖案層2 8, 28a，29, 29a進行既定之蝕刻，藉以在底部 作成具有下切部U1之剖面形狀。與此同樣地，亦可在第3 層之樹脂絕緣層30，3 1.上之配線圖案層34，34a，35，35a 進行既定之蝕刻，藉以在底部作成具有下切部U1之剖面形 狀。 其次，除了申請專利範圍中記載的技術思想以外，以 φ 下列舉由上述實施形態所把握的技術思想。 (1) 一種配線基板，其特徵爲具備有：第1樹脂絕緣 層；精細配線圖案層，其配置在上述第1樹脂絕緣層上， 由在作爲基底的無電解鍍銅層上積層電解鑛銅層而成，並 於底部具有下切部，線寬及線間隔均爲1 5 μιη以下；金屬 表面改質用之樹脂黏著層，在組成中含有金屬氧化物，且 形成於上述精細配線圖案層之表面上；及第2樹脂絕緣 層，作成覆蓋上述精細配線圖案層的方式而積層配置在上 〇 述第1樹脂絕緣層上；上述第2樹脂絕緣層之一部分係封 入於上述精細配線圖案層之上述下切部與上述第1樹脂絕 緣層之間隙中。 (2) —種配線基板，其特徵爲具備有：第1樹脂絕緣 層；精細配線圖案層，其配置在上述第1樹脂絕緣層上， 由作爲基底的無電解鍍銅層上積層電解鍍銅層而成，並在 其底部具有下切部，線寬及線間隔均爲15μηι以下；金屬 表面改質用之樹脂黏著層，利用進行矽烷偶合處理而形成 於上述精細配線圖案層之表面上；及第2樹脂絕緣層，作 -23- 200939927 成覆蓋上述精細配線圖案層的方式而積層配置在上述第1 樹脂絕緣層上；上述第2樹脂絕緣層之一部分係封入於上 述精細配線圖案層之上述下切部與上述第1樹脂絕緣層之 間隙中。 (3)如上述思想1或2之配線基板，其中在上述第2 樹脂絕緣層之表面上並未形成上述樹脂黏著層。 【圖式簡單說明】 第1圖係顯示將本發明加以具體化之一實施形態的配 〇 線基板之局部槪略剖面圖。 第2圖係用於說明上述配線基板之配線圖案層之要部 放大槪略剖面圖。 第3圖係用於說明上述配線基板之製造步驟的局部槪 略剖面圖。 第4圖係用於說明上述配線基板之製造步驟的局部槪 略剖面圖。 第5圖係用於說明上述配線基板之製造步驟的局部槪 © 略剖面圖。 第6圖係用於說明上述配線基板之製造步驟的局部槪 略剖面圖。 第7圖係用於說明上述配線基板之製造步驟的局部槪 略剖面圖。 第8圖係用於說明上述配線基板之製造步驟的局部槪 略剖面圖。 第9圖係用於說明上述配線基板之製造步驟的局部槪 略剖面圖。 •24- 200939927 第ι〇圖係用於說明上述配線基板之製造步驟的局部 槪略剖面圖。 第π圖係用於說明上述配線基板之製造步驟的局部 槪略剖面圖。 第1 2圖係用於說明先前技術例之配線基板之製造步 驟的局部槪略剖面圖。 【主要元件符號說明】 12, 13, 16，17，30，3 1 樹脂絕緣層 φ 2〇a 無電解鍍銅層 20b 電解鏟銅層 22a, 22b 抗鍍光阻 24， 24a 抗鍍光阻之開口部 28, 28a，29，29a 配線圖案層 2 8a, 2 9a 配線圖案層之中的精細配線圖案層 41 樹脂黏著層 K 1 配線基板 〇 U1 下切部 -25-A metal core substrate formed of Fe-42 wt% Ni alloy or the like. Further, in the present invention, the core substrate 1 is not necessarily used. Therefore, for example, a form of a non-core substrate can be used. In the above embodiment, the metal material of the conductor portion forming the wiring pattern layers 10, 11 or the via conductors 26, 27 or the like is selected from copper, but is not limited thereto, and silver, nickel, gold, copper alloy, iron nickel may be used. Alloys, etc. Alternatively, a method of applying a conductive resin or the like may be used instead of using a metal plating layer to form the conductor portion. In the above embodiment, the via conductors 26, 27 are in the form of field-conducting conductors in which the conductors are completely embedded in the conductors. However, it is also possible to use a reverse conical conformal conductor in which the conductors are completely buried in the conductors. . In the above embodiment, the wiring pattern layers 28, 28a, 29, 29a on the resin insulating layers 16, 17 of the second layer are subjected to surface modification treatment, but may be in the resin insulating layer 30, 31 of the third layer. The wiring pattern layers 34, 34a, -22- 200939927 35, 35a are subjected to the same surface modification treatment. In the above embodiment, the wiring pattern layers 2, 28a, 29, and 29a on the resin insulating layers 16, 17 of the second layer are subjected to predetermined etching, whereby the cross-sectional shape having the undercut portion U1 is formed at the bottom portion. Similarly to this, the wiring pattern layers 34, 34a, 35, and 35a on the resin insulating layers 30, 3 of the third layer may be subjected to predetermined etching so that the bottom portion has a cross-sectional shape having the undercut portion U1. Next, in addition to the technical ideas described in the patent application scope, the technical idea grasped by the above embodiment is listed by φ. (1) A wiring board comprising: a first resin insulating layer; and a fine wiring pattern layer disposed on the first resin insulating layer, and laminated electrolytic copper on the electroless copper plating layer as a base The layer has a lower cut portion at the bottom, and the line width and the line interval are both 15 μm or less; the resin adhesive layer for modifying the metal surface contains a metal oxide in the composition and is formed in the fine wiring pattern layer. And the second resin insulating layer is laminated on the first resin insulating layer to cover the fine wiring pattern layer, and one of the second resin insulating layers is sealed in the fine wiring pattern layer. The undercut portion is in a gap between the first resin insulating layer and the first resin insulating layer. (2) A wiring board comprising: a first resin insulating layer; a fine wiring pattern layer disposed on the first resin insulating layer, and an electrolytic copper plating layer deposited on the electroless copper plating layer as a base a layer having a lower cut portion at a bottom portion thereof, a line width and a line spacing of 15 μm or less; a resin adhesive layer for modifying a metal surface, which is formed on the surface of the fine wiring pattern layer by performing a decane coupling treatment; The second resin insulating layer is laminated on the first resin insulating layer so as to cover the fine wiring pattern layer, and one of the second resin insulating layers is sealed in the fine wiring pattern layer. The undercut portion is in the gap between the first resin insulating layer and the first resin insulating layer. (3) The wiring board according to the above aspect 1 or 2, wherein the resin adhesive layer is not formed on the surface of the second resin insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial cross-sectional view showing a conjugated wire substrate in which an embodiment of the present invention is embodied. Fig. 2 is an enlarged schematic cross-sectional view showing the principal part of the wiring pattern layer of the wiring board. Fig. 3 is a partial schematic cross-sectional view for explaining the manufacturing steps of the above wiring board. Fig. 4 is a partial cross-sectional view for explaining the manufacturing steps of the above wiring board. Fig. 5 is a partial cross-sectional view for explaining the manufacturing steps of the wiring board described above. Fig. 6 is a partial schematic cross-sectional view for explaining the manufacturing steps of the above wiring board. Fig. 7 is a partial cross-sectional view for explaining the manufacturing steps of the wiring board described above. Fig. 8 is a partial cross-sectional view for explaining the manufacturing steps of the above wiring board. Fig. 9 is a partial cross-sectional view for explaining the manufacturing steps of the above wiring board. • 24-200939927 The first diagram is a partial schematic cross-sectional view for explaining the manufacturing steps of the above wiring board. The πth diagram is a partial schematic cross-sectional view for explaining the manufacturing steps of the wiring board described above. Fig. 2 is a partial schematic cross-sectional view for explaining the manufacturing steps of the wiring substrate of the prior art example. [Main component symbol description] 12, 13, 16,17,30,3 1 Resin insulation layer φ 2〇a Electroless copper plating layer 20b Electrolytic shovel copper layer 22a, 22b Anti-plating photoresist 24, 24a Anti-plating resistance Opening portion 28, 28a, 29, 29a wiring pattern layer 2 8a, 2 9a Fine wiring pattern layer 41 among wiring pattern layers Resin adhesion layer K 1 Wiring substrate 〇 U1 Undercut portion - 25 -