TWI258210B - Method for wafer level package of sensor chip - Google Patents
Method for wafer level package of sensor chip Download PDFInfo
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- TWI258210B TWI258210B TW094112261A TW94112261A TWI258210B TW I258210 B TWI258210 B TW I258210B TW 094112261 A TW094112261 A TW 094112261A TW 94112261 A TW94112261 A TW 94112261A TW I258210 B TWI258210 B TW I258210B
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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1258210 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶片封裝方法，特別是有關於一種 感測晶片的晶圓級封裝方法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a wafer packaging method, and more particularly to a wafer level packaging method for sensing a wafer. [Prior Art]
當積體電路(Integrated Circuit，1C)晶片被設計製造出 來之後，一般來說還必須經過封裝的步驟。封裝之目的是 為了完成積體電路晶片和其他必要之電路零件間的組合， 以達到（1)傳輸電源；（2)傳遞電路訊號；（3)提供散熱途徑； 及(4)承載並保護積體電路晶片等功能。 、心著電子產品的個人化，單晶片時代的來臨，以及可 攜式數位影音產品的興起，為滿足微電子系餘、薄、短、 =新、迷、價廉及環料需求，使得縣技術的發展多 =目前已進衫^尺度的峨ChlpSealePackage, 傳統積體電路晶片的封穿赞 腳 將曰叙在^線木上，以銀膠使其黏著固定，再 以芦由導以極細的金線連接到導線架上之内引 製程密封，以防止外㈣气^亚再經由膜封膠陶_) 刷電路板上，碰枝频紐“黏著於印 完整的積體電路林、π，、成型及去織，即可製成 Β 疋 件。H此’傳統的積體電路晶片封裝 5 1258210 以單顆晶粒進行封裝，而晶圓級的封裝（Wafer-Level Package，WLP)製程則完全不同於傳統的方式，其係將整 片晶圓直接進行封裝，然後再將已封裝完成之晶圓切割成 單顆晶片，以此種晶圓級封裝製程封裝後的晶片尺寸幾乎 和原有晶粒的大小相同。 光電衫像感測為（例如’電荷輕合元件(Charge Coupled Device，CCD)、互補性氧化金屬半導體（ComplementaryAfter an integrated circuit (1C) wafer is designed and manufactured, it is generally necessary to go through a packaging step. The purpose of the package is to complete the combination of the integrated circuit chip and other necessary circuit components to achieve (1) transmission power; (2) transmitting circuit signals; (3) providing heat dissipation paths; and (4) carrying and protecting products. Functions such as bulk circuit chips. The personalization of electronic products, the advent of the single-chip era, and the rise of portable digital audio and video products, in order to meet the needs of microelectronics, thin, short, = new, fans, cheap and ring materials, the county The development of technology is more than the current ChlpSealePackage of the size of the shirt, the sealing of the traditional integrated circuit chip will be described on the ^ line wood, with the silver glue to make it adhere, and then the reed is guided by the fine The gold wire is connected to the inner lead seal on the lead frame to prevent the outer (four) gas from passing through the film sealing pottery _) on the brush circuit board, the touch frequency is "adhered to the printed integrated circuit forest, π, , forming and de-weaving, can be made into Β 。. H 'the traditional integrated circuit chip package 5 1258210 is packaged in a single die, while the Wafer-Level Package (WLP) process is It is completely different from the traditional way of packaging the entire wafer directly, and then cutting the packaged wafer into a single wafer. The wafer size after packaging in this wafer-level packaging process is almost the same. The size of the crystal grains is the same. (E.g. 'charge light engagement element (Charge Coupled Device, CCD), complementary metal oxide semiconductor (Complementary
Metal-Oxide Semiconductor，CMOS))之感測晶片主要著重 在接收電磁輻射的訊號。一般而言，其晶片表面上具有一 用以接收電磁輻射之主動區(ActiveArea)，以及一圍繞於主 動區周圍的電性接腳(例如，銲墊(pad))。當有外來的電磁 輻射抵達此主動區時，該晶片便會將電磁輻射的光訊號轉 變為電訊號，並由銲墊傳出。 上述習知的感測晶片之封裝設計，大多是以打線(Wire Bonding)的方式來做電性連接，然後將晶片以玻璃及結構 物（支承)封裝在其内部，以達到保護及透光的 目的。但由 於此種❹彳晶#在其封裝過程巾必須在料度很高(class 100)的無塵室内進行，因此設備要求及成本較高。此外， 因其封裝結構物佔有—定的體積，因此使得經封裝後之晶 片的封裝結構尺寸無法有效的減小。為此，美國專利第 US=，396，Q43號中，揭露了一種藉由覆晶接合㈣pCh⑻的 封衣方式’其係直接以麵作絲板及透光層，藉以有效 縮減封裝結構的厚度，以及克服覆晶接合法巾晶片透光方 向受限的問題。但其#仍有封裝後的面積較大，以及晶片 6 1258210 需要個別封裝等缺點。 美國專利第US6,528,857號中，揭露了 一種具有晶片 尺寸大小之凸塊(Bump)封裝結構。該封裝結構包含一影像 感測晶片，其上表面上設有一主動區及位於該主動區周圍 之銲墊、一窗口（Wmdow)，其藉由一窗口支承支撐於感測 區上、一步升環（Step Up Ring (Multi-layer LaminatedThe sensing chip of Metal-Oxide Semiconductor (CMOS)) mainly focuses on receiving electromagnetic radiation signals. Generally, the surface of the wafer has an active area for receiving electromagnetic radiation, and an electrical pin (e.g., a pad) surrounding the active area. When external electromagnetic radiation arrives in the active area, the chip converts the electromagnetic radiation signal into an electrical signal and is transmitted from the pad. The package design of the above-mentioned sensing wafers is mostly electrically connected by wire bonding, and then the wafer is encapsulated in glass and structure (support) to achieve protection and light transmission. purpose. However, since such a wafer must be carried out in a clean room with a high degree of material (class 100), the equipment requirements and costs are high. In addition, because the package structure occupies a constant volume, the package structure size of the packaged wafer cannot be effectively reduced. To this end, U.S. Patent No. 6,396, Q43 discloses a method of sealing by means of flip chip bonding (4) pCh (8), which directly serves as a wire plate and a light transmitting layer, thereby effectively reducing the thickness of the package structure. And to overcome the problem of limited transmission direction of the flip chip bonding wafer. However, its # still has a large area after packaging, and the chip 6 1258210 requires individual packaging and other shortcomings. A bump package structure having a wafer size is disclosed in U.S. Patent No. 6,528,857. The package structure includes an image sensing chip, and an active area and a pad around the active area, and a window (Wmdow) supported on the sensing area by a window, and the step is raised. (Step Up Ring (Multi-layer Laminated
Structure)) ’其形成於影像感測晶片的上表面上，且位於感 測區及銲墊之間的區域、一導電線路(外引線)形成於此步 升環上，藉由打線連接至位於影像感測晶片上表面上之銲 墊。藉此，訊號便可經由影像感測晶片上之銲墊、打線、 外引線，傳遞至錫球(SolderBall)。除了打線外，該專利中 亦才曰出了使用覆晶接合的方式，利用凸塊連結步升環下方 之内引線與晶片之銲塾，使得訊號可經由晶片上之銲墊、 凸塊、内引線、孔、外引線至鍚球，最後再利用表面接合 技術(Surface Mount Technology，SMT)將訊號傳至印刷電 路板(PCB)上。藉此，即可使其封裝後之尺寸大致相等於讀 影像感測晶片原有的大小。該專利中所指出之製程係適用 於封裝的批次處理，其可用於同時製造一整批陣列的封事 結構，於晶圓上完成植錫球(Ball Attachment)後再做切巧 (Dicing)。但其仍具有體積較厚、製程複雜及凸塊電極易因 應力造成斷損等缺點。 另外，於美國專利第US6,646,289號中，則揭露了〜 種類似三明治的玻璃夾層晶圓級封裝結構，其係將晶圓正 面與絕緣覆蓋板(玻璃'板)接合後，然後從晶圓背面予以听 1258210 磨，磨薄後之sa圓再以習知钮刻製程處理，以形成一個個 分離的單一晶元(Die)。接著，再以接合劑將第二絕緣封裝 層（玻璃板)接合於該晶圓的背面，以將晶元封裝於兩絕緣 層中。之後，使用特殊的切割工具，於兩相鄰晶元間自第 二絕緣封裝層上切割形成一 V型溝槽，深度恰好至使位於 晶圓上的銲墊邊緣得以露出。再於V型溝槽中形成一金屬 導電層，使銲墊得以電性連接(T-c〇ntact)延伸至第二絕緣封 裝層上，作重分布(Redistribud〇n)與植錫球，最後將每個晶 元進一步切割開以完成晶片的封裝結構。美國專利第 腸，6紙289號中所揭露的封裝方法為一典型之晶圓級封 裝方式’ ^而其仍具有成本較冑(财法紐用兩層玻璃且 須藉由特殊切割工具來執行）、精密切割不易、誤差大、錯 誤率高、糊過程容易污染，以及凸塊電極易因應力糾 斷損箄缺It。Structure)) 'It is formed on the upper surface of the image sensing wafer, and a region between the sensing region and the pad, a conductive line (outer lead) is formed on the step ring, and is connected by wire bonding. The image senses the pads on the upper surface of the wafer. Thereby, the signal can be transmitted to the solder ball (SolderBall) via the pad, the wire and the outer lead on the image sensing wafer. In addition to the wire bonding, the patent uses a flip-chip bonding method in which the bumps are used to connect the inner leads of the step-up ring to the solder pads of the wafer, so that the signals can pass through the pads, bumps, and pads on the wafer. Leads, holes, and outer leads to the ball, and finally the surface mount technology (SMT) is used to transmit the signal to the printed circuit board (PCB). Thereby, the packaged size can be made approximately equal to the original size of the read image sensing wafer. The process specified in this patent is applicable to the batch processing of packages, which can be used to simultaneously manufacture a whole batch of array sealing structures, and then do the Dicing after completing the Ball Attachment on the wafer. . However, it still has the disadvantages of thick volume, complicated process and easy breakage of the bump electrodes due to stress. In addition, U.S. Patent No. 6,646,289 discloses a sandwich-like glass-interlayer wafer-level package structure in which a wafer front surface is bonded to an insulating cover plate (glass 'plate) and then from a wafer. The back side is listened to 1258210, and the thinned sa round is processed by a conventional button engraving process to form a single single die (Die). Next, a second insulating encapsulation layer (glass plate) is bonded to the back surface of the wafer with a bonding agent to encapsulate the wafer in the two insulating layers. Thereafter, a special cutting tool is used to cut a V-shaped trench from the second insulating package between two adjacent cells, such that the edge of the pad on the wafer is exposed. Forming a metal conductive layer in the V-shaped trench, so that the solder pad is electrically connected (Tc〇ntact) to the second insulating encapsulation layer for redistribution and solder ball, and finally each The wafers are further diced to complete the package structure of the wafer. The encapsulation method disclosed in U.S. Patent No. 289, No. 289 is a typical wafer-level packaging method' ^ and it still has a relatively low cost (the two methods of using two layers of glass and must be executed by special cutting tools) ), precision cutting is not easy, the error is large, the error rate is high, the paste process is easy to be polluted, and the bump electrode is easy to be damaged due to stress correction.
【發明内容】 本發明之目的即在於提 ，藉以進行大量生產並 為解決前述習知技術之缺點， 供一種感測晶片之晶圓級封裝方法 降低晶片封裝成本。 根據本發騎指出之晶圓級封裝方法其步驟包含： ⑻提供-晶圓，其中該晶圓包含有複數個晶元區 域，且於該晶圓的第一表面上每個該晶元區域内 分別包含-主動區及—位於該主動區周圍的銲 執： 、 8 1258210 (b) 接合一透光保護層於該晶圓的該第一表面上； (c) 形成一應力緩衝層於該晶圓的該第二表面上； (d) 於兩該晶元區域間的一預設位置上，藉由蝕刻或 雷射鑽孔形成一通孔貫穿該應力緩衝層與該晶 圓’以露出該銲墊或預設於兩該相鄰銲墊間之導 線；以及 (e) 形成複數個凸塊電極於該應力緩衝層上，藉由該 通孔電性連接至該銲墊。 根據本發明所指出之通孔可藉由濕蝕刻（例如，化學蝕 刻）或乾钱刻（例如，反應離子蝕刻（ReactiveSUMMARY OF THE INVENTION The object of the present invention is to provide a mass production and to solve the shortcomings of the prior art, and to provide a wafer level packaging method for sensing wafers to reduce the cost of wafer packaging. The step of the wafer level packaging method according to the present invention includes: (8) providing a wafer, wherein the wafer comprises a plurality of wafer regions, and each of the wafer regions is on the first surface of the wafer Separately including - active region and - soldering around the active region: , 8 1258210 (b) bonding a light-transmissive protective layer on the first surface of the wafer; (c) forming a stress buffer layer on the crystal (d) forming a through hole through the stress buffer layer and the wafer by etching or laser drilling at a predetermined position between the two regions of the wafer to expose the solder a pad or a wire preset between the two adjacent pads; and (e) forming a plurality of bump electrodes on the stress buffer layer, the via being electrically connected to the pad. The vias identified in accordance with the present invention may be wet etched (e.g., chemically etched) or dry etched (e.g., reactive ion etch (Reactive)
Ion Etching, RIE)、電感|馬合電漿離子I虫刻（inductively Coupled Plasma Reactive Ion Etching，ICP))或雷射鑽孔獲得，根據本發明所 指出之方法因無需使用US6,646,289號專利中所指出的高 精密度切割工具，因此較該方法更為簡單方便且精準，並 可有效降低製造成本，此外尚可避免US6,646,289號專利 中於切割過程所造成之污染。 本發明將藉由以下更詳細的解說，進一步說明本發明 的貫施方式。 應理解的是，下述實施方式係用以闡明本發明，並非 用以限定本發明之範圍，任何熟習此技藝者，在不脫離本 發明之精神和範圍内，當可做些許更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 【實施方式】 9 1258210 參閲第一圖及弟 圃，很據本發明所指出一 晶片的晶圓級封裝方法，首先將一包含有 一種感測 H)的晶圓·，於其第-表面102上藉由H固晶元區域 々曰屯黏合劑J 8拔人Ion Etching, RIE), Inductively Coupled Plasma Reactive Ion Etching (ICP) or Laser Drilling, the method indicated in the present invention does not require the use of US 6,646,289 The high-precision cutting tool pointed out is therefore simpler, more convenient and more precise than the method, and can effectively reduce the manufacturing cost, and the contamination caused by the cutting process in the US Pat. No. 6,646,289 can be avoided. The present invention will be further illustrated by the following detailed description. It is to be understood that the following embodiments are not intended to limit the scope of the invention, and that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Embodiment] 9 1258210 Referring to the first figure and the sister-in-law, according to the invention, a wafer-level packaging method for a wafer is first described, which first includes a wafer having a sensing H) on its first surface. 102 on the H solid crystal region 々曰屯 adhesive J 8 pull people
的至少-表面上接合-分色鏡(DiehlOie)、光柵或光波過遽 層，而達到師遙特殊波長電磁波之效果。 可應用於本發明中的黏合劑，在此可舉出的例子包含 環氧樹酯(Epoxy)，但並不僅限於此。作為本發明之較佳實 軛例，该透光保護層16與黏合劑18係為輻射可穿透的。 本發明中該透光保護層16於製程一開始時，即覆蓋於 晶圓100的第一表面102上予以保護，故於後續的製程中 不需要嚴苛之無塵環境要求，且若晶圓需重工(ReW〇rk) -透光保護層16,其中該晶圓第—表面ι〇2上的每^固 該晶疋區域=，分別包含有—主動區12及—位於主動 區η周圍的料Μ。其中，該銲塾！4係作為電性連接用， 以使該主祕12得以經由該銲墊14電性連接至晶元 Κ)的外部。該晶圓100的第一表面1〇2係指晶圓⑽上星 有主動區12關面。可應用於本發明巾作為透光保護層 16的材質包含玻璃、石英、藍寶石(S—)或其他習知適 當的輪射可穿透之絕緣材料，於本發日种並無特別的限 制’但較佳為玻璃。當作為光譜濾波器時，此透光保護層 16亦可被著色或染色。另_方面，亦可於透光保護層π 裝配時，該透光保護層16亦可提供完整之保護，不致使主 動區12受到污染。 另如第二圖所示，作為本發明之另一實施例，可於晶 1258210 圓1θ〇〇接合透光保護層16前，先於兩相鄰晶元區域1〇中 的杯墊14間預設—導線22，然後以透光之黏合劑接合 1光保4層16。其中，該導線22可藉由習知任何可用 、電之物貝所組成’只要是可使該銲墊Μ向晶元區域 ⑺外4做電性連接者，均可被應用於本發 有特別的限制。 ^本發明在此即以含有導線22設計的封裝結構作為一 κ ,例(如圖十六⑷）’用以說明本發明感測晶片之晶圓級 封裝方法的後續製程。錢第三圖至軒五圖，為本發明 晶圓級封裝方法的製程之連續動作實施示意圖。如前所 述L於晶圓100與透光保護層16完成接合後，為使所製得 之晶片有較薄的厚度，可將晶圓100的第二表面104(相對 於第-表面1G2的另-側面)予以研磨至較薄之厚度，例如 100微米。接著，於晶圓1〇〇的第二表面1〇4上形成一第 一應力緩衝層24，然後利用黃光製程之光阻26於第一應 力緩衝f 24上，兩相鄰晶元區域1〇間，定義出通孔2〇 的預定實施位置，如第四圖所示。其中，於第二表面刚 上形成第一應力緩衝層24的方法，可藉由例如習知之旋轉 塗佈(Spin Coating)法來實施。作為上述第一應力緩衝層的 物質’只要是可於晶片組裝時用以減緩晶片與基板⑼二， 有機基板)之間因熱膨脹係數差異所產生之應力，皆可被應 用於本發明中，於本發明中並沒有特別的限制。在此可舉 出的例子’包含聚亞醯胺（P〇lyimide，PI)、笨并環丁院 (Benzocydobutane，BtB)、矽膠或其他可塗佈的高分子材 1258210 料等，但並不僅限於此。於設置完光阻2 M吏，接著以 方式於預設位置上形成—通孔2Q貫穿第—應力緩衝層^ 與晶圓100，以使銲塾Μ或位於相鄰兩銲塾14間的曰 22得以露出’如第五圖所示。在此，根據本發明所指出: 通孔20可藉由濕韻刻或乾姓刻來達成。其中，做為本 濕钱刻關子’包含化學侧，但並不舰於此。做^本 發明乾侧的例子’包含反麟子侧(RIE)及電感輕人带 漿料㈣（ra>)，但並不舰於此。於本發日种通孔= 除可藉由濕_或乾_來達成外，熟f本發明技術領域 者可藉由參考本發明說㈣巾之記載，以其他習知的方式 來達成’可舉出關子包含雷_孔，但並不僅限於此。 接著，於通孔20内壁上形成一絕緣層（未顯示）。之後 移除光阻26 ’濺鑛-第一導電物質28(例如，鈦或銅），如 第六圖所示。然後再以光阻26定義出線路的預定實施位 置’之後电錄第二導電物質3〇(例如，銅)並將通孔2〇填平， 用以增加導電物質厚度並佈線，如第七圖所示。接著如第 =圖所示，移除光阻26及多餘的第一導電物f 28，以於 第一應力緩衝層24上形成預設線路。接著，再於第一廡力 緩衝層24上形成m緩衝層32,並覆蓋先前㈣ =導電物質30於第-應力緩衝層24上所形成之線路，如 第九圖所示。於第一應力缓衝層24上形成第二應力緩衝層 32的方法，可藉由例如習知之旋轉塗佈(SpinC〇atin幻法來 實施。作為上述第二應力缓衝層的物質，只要是可於晶片 組裝時用，緩晶❻基板(例如，有機基板)之間^膨 1258210 祕數差f所產生之應力，皆可被應用於本發明中，於本 西在月ο 1 · · 1 ^ 包含聚亞 月女（Polyimide，PI)、絮并读 τ a 本开壞丁烷（Benzocyclobutane， BCB)、矽膠或其他可塗佑 土佈的同分子材料等，但並不僅限於 此0 以光阻26定義出凸塊底層金屬層（Under Bump Metallurgy，、UBM)34的預定實施位置，並㈣第二應力緩At least the surface-bonding-dichroic mirror (DiehlOie), grating or light wave through the layer, to achieve the effect of the special wavelength electromagnetic wave. The binder which can be used in the present invention may be exemplified by an epoxy resin (Epoxy), but is not limited thereto. As a preferred embodiment of the invention, the light transmissive protective layer 16 and the adhesive 18 are radiation permeable. In the present invention, the transparent protective layer 16 is protected on the first surface 102 of the wafer 100 at the beginning of the process, so that no strict dust-free environment requirements are required in the subsequent process, and if the wafer is ReW〇rk-transparent protective layer 16, wherein each of the wafer regions on the first surface of the wafer has an active region 12 and is located around the active region η Information. Among them, the welding 塾! 4 is used for electrical connection so that the main secret 12 can be electrically connected to the outside of the wafer via the bonding pad 14. The first surface 1 〇 2 of the wafer 100 refers to the star-shaped active region 12 on the wafer (10). The material of the invention as the light-transmissive protective layer 16 comprises glass, quartz, sapphire (S-) or other conventionally suitable radiation-permeable insulating materials, and there is no particular limitation in the present invention. However, it is preferably glass. When used as a spectral filter, the light transmissive protective layer 16 can also be colored or dyed. On the other hand, the light-transmissive protective layer 16 can also provide complete protection during the assembly of the light-transmissive protective layer π without contaminating the active region 12. As another embodiment of the present invention, as another embodiment of the present invention, before the light-transmissive protective layer 16 is bonded to the crystal 1258210, it is pre-prepared between the coasters 14 in the two adjacent wafer regions 1〇. A wire 22 is provided, and then a light-protecting 4 layer 16 is bonded by a light-transmitting adhesive. Wherein, the wire 22 can be composed of any usable, electrically conductive material, as long as the wire can be electrically connected to the outside of the wafer region (7), and can be applied to the present invention. limits. The present invention herein uses a package structure having a wire 22 design as a κ, for example (Fig. 16(4))' to illustrate the subsequent process of the wafer level packaging method of the sensing wafer of the present invention. The third figure of the money to the Xuanwu diagram is a schematic diagram of the continuous operation of the process of the wafer level packaging method of the present invention. After the bonding of the wafer 100 and the transparent protective layer 16 is completed as described above, in order to make the fabricated wafer have a thin thickness, the second surface 104 of the wafer 100 (relative to the first surface 1G2) The other side is ground to a thinner thickness, for example 100 microns. Next, a first stress buffer layer 24 is formed on the second surface 1〇4 of the wafer 1 , and then the photoresist 26 of the yellow light process is used on the first stress buffer f 24 , and two adjacent wafer regions 1 During the day, the predetermined implementation position of the through hole 2〇 is defined, as shown in the fourth figure. Here, the method of forming the first stress buffer layer 24 on the second surface can be carried out, for example, by a conventional spin coating method. The material as the first stress buffer layer can be applied to the present invention as long as it can be used to slow down the stress caused by the difference in thermal expansion coefficient between the wafer and the substrate (9) and the organic substrate during wafer assembly. There is no particular limitation in the present invention. Examples which may be mentioned herein include, but are not limited to, P〇lyimide (PI), Benzocy Dobutane (BtB), tannin or other coatable polymer material 1258210. this. After the photoresist is set to 2 M吏, and then formed in a predetermined position, the through hole 2Q penetrates through the first stress buffer layer and the wafer 100 to make the solder bump or the germanium between the adjacent solder pads 14. 22 was exposed as shown in the fifth picture. Here, it is pointed out in accordance with the invention that the through hole 20 can be achieved by wet or dry name. Among them, as the wet money engraved, the chemical side, but not the ship. The example of the dry side of the invention includes the reverse lining side (RIE) and the inductive light strip slurry (four) (ra>), but it is not here. Through-holes of the present invention can be achieved by the use of wet or dry _, which can be achieved by other known methods by referring to the description of the (four) towel of the present invention. It is not limited to this. Next, an insulating layer (not shown) is formed on the inner wall of the through hole 20. The photoresist 26 'spray-first conductive material 28 (e.g., titanium or copper) is then removed, as shown in Figure 6. Then, after the photoresist 26 defines the predetermined implementation position of the line, the second conductive material 3〇 (for example, copper) is electrically recorded and the via hole 2〇 is filled in, for increasing the thickness of the conductive material and wiring, as shown in the seventh figure. Shown. Next, as shown in Fig. =, the photoresist 26 and the excess first conductive material f 28 are removed to form a predetermined line on the first stress buffer layer 24. Next, an m buffer layer 32 is formed on the first buffer layer 24, and covers the line formed by the previous (four) = conductive material 30 on the first stress buffer layer 24, as shown in FIG. The method of forming the second stress buffer layer 32 on the first stress buffer layer 24 can be carried out, for example, by a spin coating method (SpinC〇atin phantom method). As the material of the second stress buffer layer, as long as it is It can be used in the assembly of wafers, and the stress generated by the cracking of the retardation of the substrate (for example, the organic substrate) can be applied to the present invention in the present invention in the month of ‧ 1 · · 1 ^ Contains Polyimide (PI), flocculation and reading τ a Benzocyclobutane (BCB), silicone or other similar molecular materials that can be coated with soil cloth, but not limited to this The resistor 26 defines a predetermined implementation position of the Under Bump Metallurgy (UBM) 34, and (4) the second stress relaxation
衝層32 — 以使作為線路的第二導電物質μ得以露出，如 第十圖射。之後，移除光阻％於預定實紐置上形成凸 塊底層至屬層34 ’如第十_圖所示。該凸塊底層金屬層科 係與作為線路的第二導電物質3〇電性連接。 熟習本發明技術領域之技藝者，根據本發明之說明亦 可了解柄a月之導電物質在此並沒有特別的限制，只要 疋可用以提供電性連接g卩可，做為本發明實施方式的例 子^含麵(Sputter)、電錢(Electr〇plate)、蒸卿叫 及無電鑛(Electroless plate)等，但並不僅限於此。此外，做 為本發明導電物質材料的例子，包含鈦、銅、鉻、金、鋁、 鎳、釩及銀等，但並不僅限於此。 接著，如第十二至十四圖所示，再以光阻26定義出錫 錯凸塊(Solder Bump)36的預定實施位置。之後，於凸塊底 層金屬層34上形成錫鉛凸塊36。最後，移除光阻％，然 後回銲(Reflow)。做為本發明錫鉛凸塊之一實施例，包含 高溫錫鉛合金、低溫錫鉛合金或無鉛錫球，但並不僅限於 此。此外，於凸塊底層金屬層34上形成錫鉛凸塊36的方式 1258210 電鍍及印刷等，於本發明中亦無任The punch layer 32 is used to expose the second conductive substance μ as a line, as shown in the tenth image. Thereafter, the photoresist is removed by a predetermined amount to form a bump underlayer to the sapphire layer 34' as shown in the tenth figure. The bump underlayer metal layer is electrically connected to the second conductive material 3〇 as a line. A person skilled in the art of the present invention can also understand that the conductive material of the handle a month is not particularly limited as long as it can be used to provide an electrical connection, as an embodiment of the present invention. Examples include, but are not limited to, Sputter, Electr〇plate, Steamed Electroless, and the like. Further, examples of the material of the conductive material of the present invention include titanium, copper, chromium, gold, aluminum, nickel, vanadium, and silver, but are not limited thereto. Next, as shown in the twelfth to fourteenth drawings, the predetermined implementation position of the solder bump 36 is defined by the photoresist 26. Thereafter, a tin-lead bump 36 is formed on the under bump metal layer 34. Finally, remove the photoresist % and then reflow. As an embodiment of the tin-lead bump of the present invention, it includes, but is not limited to, a high-temperature tin-lead alloy, a low-temperature tin-lead alloy or a lead-free solder ball. In addition, the manner in which the tin-lead bumps 36 are formed on the under bump metal layer 34 1258210 is electroplated, printed, etc., and is not included in the present invention.
元區域五圖所示’將晶圓100切割成個別的晶 法所4，Γ可完成晶片之封裝。根據本發明所指出之方 後，晶片封裝結構，正面於接受電磁輻射38的照射 子；曰曰片中的主動區12會將此電磁輻射38轉變為電 經由銲墊14、連接銲墊14的導線22、通孔2〇、 ρ導電物f28和第二導電物㈣及錫錯凸 旅 遞至連結於晶片背面的印刷電路板40上。由於本 月日日片月面a又有錫鉛凸塊36，故可方便於 刷電路板40。 1 在此，進一步說明本發明通孔20其形成位置之幾種型The wafer 100 is diced into individual wafers 4 as shown in the fifth section of the meta-region, and the wafer can be packaged. In accordance with the teachings of the present invention, the wafer package structure is front facing the illuminator that receives the electromagnetic radiation 38; the active region 12 in the cymbal slab converts the electromagnetic radiation 38 into electricity via the pad 14 and the bond pad 14 The wire 22, the through hole 2, the p conductive material f28 and the second conductive material (4) and the solder bump are transferred to the printed circuit board 40 attached to the back surface of the wafer. Since the moon-shaped surface a has a tin-lead bump 36 this month, it is convenient to brush the circuit board 40. 1 Here, the types of formation positions of the through holes 20 of the present invention are further explained.
(植錫球），包含蒸鑛 何特別的限制。 參閱第十六(a)圖，為本發明通孔2〇實施時的一實施 例在此自晶圓1〇〇第二表面1〇4蝕刻形成之通孔2〇係位 於！干墊14正下方的位置上，通孔2()的面積區域係可大於 或小於該銲墊14，以露出鮮墊14 ;在此則、於該銲墊14 為例此日^位於晶片背面的錫錯凸塊36即可經由通孔20 與銲墊14電性連接。 芩閱第十六(b)圖，為本發明通孔2〇實施時的另一實 施例，在此自晶圓100第二表面1〇4蝕刻之通孔2〇，係位 於|干墊14之周圍，以使部分之銲墊14得以露出。藉此， 位於晶片背面的錫錯凸塊36即可經由通孔2〇與銲墊14 電性連接。 ' 1258210 ^參閱第十六(c)圖，為本發明通孔20實施時的又一實 軛例，在此自晶圓100第二表面1〇4蝕刻之通孔2〇，係位 2相鄰兩晶以域Π)之銲墊14間，並使兩相鄰輝塾14 抬有部份或全部得以露出。藉此，位於晶片背面的錫錯凸 鬼36即可經由通孔20與銲墊14電性連接。 〃參閱第十六⑷圖，為本發明通孔20實施時的再 自晶圓100第二表面104钱刻之通孔20,係位 日日元_ H)的銲塾14之間，但並不使辉塾Μ 路，而疋使位於兩相鄰銲墊14間之導線22露出。蕤 ::晶;—凸塊亀由通孔2。二 装:製22 t接至銲墊14。本發明前述後續封 P疋以此種貫施例用以說明。 另外’由於根據本發明所指 她具有-應力緩衝層，因此可二 緩晶片與基板(例如，有機美杯、…曰曰片、，且病有效減 產生 有機基板)之間因熱膨脹係數差異所 作用。〜錢晶片與基板間可維持電性連接發揮應有 >本發明方法中通孔係藉由飯刻方式 订，本發明之晶圓級封裳方法不 ^t二 的製具（Tooling)，妗 、、先封衣而要許夕繁複 (Mask)，以形成所^、甬孔不同的產品設計不同的光罩 由調控_或雷射_::::制开果可藉 特殊工具執行者為古 文，、良率可頭者較以 法無須使用特殊易實施。此外，由於本發明方 具東執行’故可降低晶片封裝的製造成 1258210 本本电明之感測晶片的晶圓級封裝方法，具有防止粒子 污=、增進組裝便利性及解決晶片於直接黏著至印別電路 板時的應力問題等優點。 譜如上所述，由於本發明晶片封裝方法，包含有透光保 ㈢應力_層及觀之設計，故本發明㈣有效避免 術所遭遇之問題。亦即’藉由使用本發明之晶圓級 造裝配1可以防止粒子㈣、增進組裝便糖、降低製 接二=:力圓::裝结構之可靠度及解決晶片直(Planting ball), including steaming, special restrictions. Referring to Fig. 16(a), an embodiment of the through hole 2〇 of the present invention is formed by etching a through hole 2 formed on the second surface 1〇4 of the wafer 1〇〇! In the position directly below the dry pad 14, the area of the through hole 2 () may be larger or smaller than the pad 14 to expose the fresh pad 14; here, the pad 14 is located on the back side of the wafer. The tin bumps 36 can be electrically connected to the pads 14 via the vias 20 . Referring to FIG. 16(b), another embodiment of the through hole 2〇 of the present invention is implemented. Here, the through hole 2〇 etched from the second surface 1 of the wafer 100 is located on the dry pad 14 Around it, a portion of the pad 14 is exposed. Thereby, the tin bumps 36 on the back surface of the wafer can be electrically connected to the pads 14 via the vias 2 . ' 1258210 ^ Refer to the sixteenth (c) figure, which is another embodiment of the yoke in the implementation of the through hole 20 of the present invention. Here, the through hole 2 蚀刻 etched from the second surface of the wafer 100 is 系 2 The pads 14 of the adjacent crystals are placed, and some or all of the adjacent illumines 14 are exposed. Thereby, the tin bump 36 located on the back surface of the wafer can be electrically connected to the pad 14 via the via 20. Referring to the sixteenth (4) figure, the through hole 20 of the second surface 104 of the wafer 100 is etched between the soldering holes 14 of the second surface 104 of the wafer 100 when the through hole 20 is implemented, but The wires 22 located between the adjacent pads 14 are exposed without causing the brilliance.蕤 :: crystal; - bump 亀 by through hole 2. Second install: 22 t is connected to the pad 14. The foregoing subsequent sealing of the present invention is illustrated by such a embodiment. In addition, since she has a stress buffer layer according to the present invention, it is possible to reduce the difference in thermal expansion coefficient between the wafer and the substrate (for example, an organic cup, a tablet, and an effective reduction of the organic substrate). effect. 〜 钱 晶片 晶片 与 与 与 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱妗, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, For the ancient Chinese, the rate can be better than the law without special use. In addition, since the present invention can be implemented in the east, the wafer-level packaging method of the wafer package can be reduced to 1258210, and the wafer-level packaging method of the sensing wafer can be prevented, the particle contamination can be improved, the assembly convenience can be improved, and the wafer can be directly adhered to the printing. Advantages such as stress problems when boards are not in use. As described above, since the wafer encapsulation method of the present invention includes a light-transmissive (three) stress layer and a design, the present invention (4) effectively avoids problems encountered in the art. That is, by using the wafer level assembly 1 of the present invention, it is possible to prevent particles (4), improve assembly of the sugar, and reduce the manufacturing of the second =: force circle:: reliability of the structure and solution of the wafer straight
16 !25821〇 【圖式簡單說明】 •圖為根據本發明所指出之感測晶片的封 、 之晶圓與晶元區域示意圖； '"方法 圖為根據本發明所指出之感測晶片的封壯 之晶圓與透光保護層接合的示意圖；衣方法 圖至第十五目為根據本發明所指出之感列 — 的封裝方法之連續動作實施示意圖； 第十”⑷圖為根據本發明 方法之通孔的-實施方式示㈡:曰片的封裝 第十六帽輕縣糾 方法之通孔的另一實施方式的封裝 第十六⑷方圖法;=Γ所指出之感測晶片的封裝 方法之通孔的再一實施方式示意圖。衣 第 第 第 【主要元件符號說明】 100晶圓 102第一表面 104第二表面 10 晶凡區域 12 主動區 14 銲墊 16 透光保護層 1258210 18 黏合劑 20 通孔 22 導線 24 第一應力緩衝層 26 光阻 28 第一導電物質 30 第二導電物質 32 第二應力緩衝層 34 凸塊底層金屬層（UBM) 36 錫錯凸塊 38 電磁輻射 40 印刷電路板16 258 〇 图 图 图 • • • • • • • • • • • • • • • 感 感 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片Schematic diagram of the bonding of the sealed wafer to the light-transmissive protective layer; the method of the garment to the fifteenth is a schematic diagram of the continuous operation of the packaging method according to the invention; the tenth "(4) diagram is according to the invention Method for the through hole - the embodiment shows (2): the encapsulation of the cymbal package. The sixteenth (4) square diagram method of another embodiment of the through hole of the sixteenth cap light correction method; A schematic diagram of still another embodiment of the through hole of the encapsulation method. [First main symbol illustration] 100 wafer 102 first surface 104 second surface 10 crystal region 12 active region 14 pad 16 transparent protective layer 1258210 18 Adhesive 20 through hole 22 wire 24 first stress buffer layer 26 photoresist 28 first conductive material 30 second conductive material 32 second stress buffer layer 34 bump underlying metal layer (UBM) 36 tin bump 38 electromagnetic radiation 40 Printed electricity Road board
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| CN111200410A (en) * | 2018-11-16 | 2020-05-26 | 开元通信技术（厦门）有限公司 | Wafer-level packaging structure of acoustic wave device and preparation method thereof |
| CN111200410B (en) * | 2018-11-16 | 2023-03-21 | 开元通信技术（厦门）有限公司 | Wafer-level packaging structure of acoustic wave device and preparation method thereof |
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