故、發明說明： 【發明所屬之技術領域】 . 本發明係有關於一種半導體製程，更明確而言，係有關於一 利於監測淺溝槽隔離區（STI)是否有空隙存在之方法。 、種 【先前技術】 在曰益緊密化的半導體裝置之製程中，用以形成各元件之主動 區10之間，係以淺溝槽隔離區（STI)加以分隔開來。主動區與 區10之間係形成淺溝槽，並填以介電質12。此介電層可為氧化 1 句動 例如可為氧化矽。然而，在填入該介電質12時，有時可能會形成 二隙13，如圖1所示。 在dram的製程中，也會發生此種情形，請參見圖2，此為 dram閘極區域結構俯視示意圖。如圖所示，2〇表示主動區 為閘極條，24表示深溝槽。如圖所示，主動區2G彼此相鄰二部= ，短。23表示主動區2〇與主動區2G之間的淺溝槽隔離區所填二 電質中形成的空隙。此種空隙的存在會影響半導體裝置的電性表 王2，，而，由於空隙通常非常小，在製程流程中難以發現，通常要Therefore, the description of the invention: [Technical field to which the invention belongs]. The present invention relates to a semiconductor process, and more specifically, it relates to a method for monitoring whether a shallow trench isolation region (STI) has a gap. [Previous Technology] In the manufacturing process of compact semiconductor devices, the active regions 10 used to form each element are separated by shallow trench isolation regions (STIs). A shallow trench is formed between the active region and the region 10 and is filled with a dielectric 12. The dielectric layer may be oxidized, for example, silicon oxide. However, when the dielectric 12 is filled, a two-gap 13 may be formed, as shown in FIG. 1. This situation also occurs in the process of dram. Please refer to Fig. 2. This is a schematic plan view of the dram gate area structure. As shown in the figure, 20 indicates the active area is a gate bar, and 24 indicates a deep trench. As shown in the figure, the active area 2G is adjacent to each other, and is short. 23 indicates a gap formed in the capacitor by the shallow trench isolation region between the active region 20 and the active region 2G. The existence of such voids will affect the electrical meters of semiconductor devices. However, because the voids are usually very small, it is difficult to find them during the manufacturing process.
目到晶圓製造完成、_成晶纽封裝之後，在電性測試時才能發 現，因此造成製程上的浪費。 X 因此，需要一種能夠早期發現空隙存 不必要的浪費。本發明即滿;^此項需求。 U除製転上 【發明内容】 方法，驻i之目的為提供一種半導體晶圓之淺溝槽隔離區空隙檢測 本方法可早雜現淺溝槽區中是否有空·生，以提早發 不良。口，減少工時與成本之浪費。 檢測之測試Γ、種驗科體晶81之紐獅離區空隙 現令雀辦F = 藉由形成此測試區域並測試該測試區域可早期發 條甲是否有空隙產生。 5 J:\menu\pending-92\92322.doc 1237862 本么月之方面，一種半導體晶圓之淺溝槽隔離區空障檢測方 法包括步财於該晶圓之默區域巾紋__職輯；力與其他區域同 步之製程在朗試區域巾形成主龍以及與料主動㈣叉的閉極 條，該等主魅之間係填人介„，並且轉主祕彼此相鄰的部分至 少達-預定長度；以及測量鱗_條之電性值以判晴等主動區之間 所填入的介電質中是否有空隙產生。 _根據本發日狀又—Μ，—麵於半導體晶®之淺龍隔離區空 隙松測之測試區域結構係以與該晶他部分之結構同步的製程形成 於該晶=，刻試區域結構包括有複_主_，轉主動區之間 係填入介電質，並且該等絲區彼此轉的部分至少達-預定長度； 以及複數個_條，該等酿條雜鱗絲 又’ 【實施方式】 將多…、所附圖式詳細說明本發明之實施例。 翻之實關’係在晶圓上之縣處，較料預定為切 與其餘部分之形成同步的製程，另外製作包含主動 區以及閘極的測試區域。 二圖3因:示’該測試區域中的主動區30係形成為彼此平行的 =的、D主純3G整體彼此相鄰。主純3g與主動區3〇 mti，係、以與形成其他部分之結翻步的製程填入介電 層32如所不者，於本實施例中，主動區3 行的碰。由於_ 3G嶋_嫩長， ”山二二非測试區域的閘極條係以相同的間隔配置。如圖所 ^而二隙33為長形’因此至少會跨過兩條閑極條31，，因此， 舉例而r可由測試區域閘極條31，測量電位便可知道是否有空隙 的存在。 二、 J\menu\pending-92\92322.doc 6After the wafer manufacturing is completed and the wafer package is completed, it can be found during electrical testing, thus causing waste in the process. X Therefore, what is needed is an early detection of unnecessary waste in voids. The present invention is full; ^ this demand. [Abstract] The method of the invention is to provide a method for detecting the gap in the shallow trench isolation region of a semiconductor wafer. This method can early detect whether there is space in the shallow trench region to prevent early hair failure. . Reduce waste of man-hours and costs. The test of the test Γ, the gap between the New Lion's out-of-range area of the seed laboratory body crystal 81. Now let the bird do F = By forming this test area and testing the test area, it can be found whether there is a gap in the clockwork early. 5 J: \ menu \ pending-92 \ 92322.doc 1237862 In terms of this month, a method for detecting the shallow trench isolation region of semiconductor wafers includes a method for detecting the shallow area of the wafer __job series ; The process of synchronizing with other regions forms the main dragon and the closed pole of the active active fork in the Lang test area. The main charms are filled with humans, and the parts adjacent to each other are at least up to -Predetermined length; and measure the electrical value of the scale_bar to determine whether there is a gap in the dielectric filled between the active areas such as sunny. The structure of the test area in the loose area of the shallow dragon isolation zone is formed on the crystal by a process that is synchronized with the structure of the other part of the crystal. The structure of the test area includes a complex _main_. The electric quality, and the parts of the silk areas turning at least to a predetermined length; and a plurality of _ strips, the mixed scales of these sliver strips, and the "embodiment" will be described in detail in the following. Example: The "turn over the truth" is at the county on the wafer, and is expected to be cut with the rest The synchronous process is divided into two parts, and a test area including an active area and a gate electrode is separately produced. The reason of FIG. 3 is that the active area 30 in the test area is formed in parallel with each other, and the D master pure 3G is in phase with each other Adjacent. The main pure 3g and the active area 30mti are used to fill the dielectric layer 32 in a process that is the same as the formation of other parts. In this embodiment, the active area has three rows. Because _ 3G 嶋 _ Tender length, “The gate bars of the Shan Er Er non-test area are arranged at the same interval. As shown in the figure, the second gap 33 is elongated, so it will cross at least two free pole strips 31. Therefore, for example, r can be measured by the gate electrode strip 31 in the test area, and the potential can be determined by the measurement of the potential. J \ menu \ pending-92 \ 92322.doc 6