CN103426865B - Semiconductor article tungsten groove contact resistance test structure and method of testing - Google Patents
Semiconductor article tungsten groove contact resistance test structure and method of testing Download PDFInfo
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- CN103426865B CN103426865B CN201210154658.9A CN201210154658A CN103426865B CN 103426865 B CN103426865 B CN 103426865B CN 201210154658 A CN201210154658 A CN 201210154658A CN 103426865 B CN103426865 B CN 103426865B
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Abstract
The invention discloses a kind of semiconductor article tungsten groove contact resistance test structure, be formed with three active areas the most adjacent on a silicon substrate, three active areas are all N-type or p-type with substrate；X the tungsten groove formed on first active area constitutes the first tungsten groove array with connecing the first metal layer, Y the tungsten groove formed on second active area constitutes the second tungsten groove array with connecing the second metal level, and Z tungsten groove composition the 3rd tungsten groove array that the 3rd active area is formed is same connects the 3rd metal level；Each tungsten groove in three tungsten groove arrays equivalently-sized；Spacing between first tungsten groove array and the second tungsten groove array, equal to the spacing between the second tungsten groove array and the 3rd tungsten groove array；X, Y, Z are positive integer, and X is not equal to Z.The invention also discloses the method utilizing this semiconductor article tungsten groove contact resistance test structure to carry out the test of tungsten groove contact resistance.The present invention can accurately record the contact resistance of tungsten groove.
Description
Technical field
The present invention relates to semiconductor technology, particularly to a kind of semiconductor article tungsten groove contact resistance test
Structure and method of testing.
Background technology
Semiconductor article is as it is shown in figure 1, be generally formed with multiple active area, respectively on silicon substrate 101
Individual active interval isolates with field oxygen 103, during the encapsulation of some semiconductor article, draws lining at chip back
The end, in order to reduce extraction resistance, generally grooving on silicon substrate 101, refill tungsten and form tungsten groove
(W-Sink) 102, tungsten groove 102 there is metal level 105 cover to prevent tungsten exposed, metal level 105
And being isolated by dielectric layer 104 between substrate, this dielectric layer 104 can be oxide, nitride, nitrogen oxygen
Compound etc..It is connected in series (Chain) if, with traditional chain and measures the contact electricity of tungsten groove 102
Resistance, owing to tungsten groove 102 is directly connected with substrate 101, makes any two groups of tungsten grooves 102 on silicon chip all may be used
To be connected by substrate 101, serial number can only have 2 groups, and total resistance value is less, so test error
Greatly；Connect (Kelvin) if, with traditional Kelvin and measure the contact resistance of tungsten groove 102, then because of
The resistance substrate of the middle introducing of test structure cannot be quantified, and the contact resistance of tungsten groove cannot be quantified.
Kelvin connects (or title four end test modes) and carries out the principle of resistance test as shown in Figure 2.Kai Er
Literary composition connects two requirement: have an excitation line F for each test point and one detect line S, two
Person is strictly separated, and each constitutes independent loop；Require that S line must be received one and have high input simultaneously
On the test loop of impedance, make the electric current flowing through detection line S minimum, be approximately zero.R table in Fig. 2
Show the contact resistance sum of lead resistance and probe and test point.Owing to flowing through the electric current of test loop it is
Zero, the pressure drop on r3, r4 is also zero, and the pressure drop that exciting current I is on r1, r2 does not affects
I pressure drop in measured resistance, so voltmeter V can accurately measure the electricity at measured resistance Rt two ends
Pressure value, thus accurately measure the resistance of measured resistance R t.Test result and r are unrelated, effectively subtract
Little measurement error.According to effect and the height of current potential, these four lines are known respectively as high potential and apply
Line (HF), electronegative potential apply line (LF), high potential detection line (HS) and electronegative potential detection line (LS).
Summary of the invention
The technical problem to be solved in the present invention is, can accurately record the contact resistance of tungsten groove.
For solving above-mentioned technical problem, the invention provides a kind of semiconductor article tungsten groove contact resistance and survey
Examination structure, its structure is:
Being formed with three active areas the most adjacent on a silicon substrate, three active areas are all N with substrate
Type or p-type；
Being formed with X tungsten groove on first active area, this X tungsten groove constitutes the first tungsten groove array with connecing
The first metal layer；Being formed with Y tungsten groove on second active area, this Y tungsten groove constitutes the second tungsten groove
Array is with connecing the second metal level；Being formed with Z tungsten groove on 3rd active area, this Z tungsten groove is constituted
3rd tungsten groove array is with connecing the 3rd metal level；
Electric insulation between the first metal layer, the second metal level, the 3rd metal level；
Each tungsten groove in three tungsten groove arrays equivalently-sized；
Spacing between first tungsten groove array and the second tungsten groove array, equal to the second tungsten groove array and the 3rd
Spacing between tungsten groove array；
X, Y, Z are positive integer, and X is not equal to Z.
It is also preferred that the left three active area dimensions are identical, isolate with field oxygen between three active areas.
It is also preferred that the left X, Y, Z are not mutually equal.
It is also preferred that the left by dielectric layer between the first metal layer, the second metal level, the 3rd metal level and silicon substrate
Isolation.
It is also preferred that the left this semiconductor article tungsten groove contact resistance test structure is positioned at the scribe line area of silicon chip
Or test chip region.
For solving above-mentioned technical problem, present invention also offers a kind of described semiconductor article tungsten groove and connect
Tactile resistance test structure carries out the method for tungsten groove contact resistance test, and it comprises the following steps:
One. utilize the of the test structure of semiconductor article tungsten groove contact resistance described in Kelvin's connecting test
Resistance R between one metal level, the second metal levela；Utilize quasiconductor system described in Kelvin's connecting test
Product tungsten groove contact resistance test resistance R between the second metal level of structure, the 3rd metal levelb,
Two. it is calculated the contact resistance R of single tungsten grooveWsink,
The semiconductor article tungsten groove contact resistance test structure of the present invention, including three tungsten groove arrays, three
Each tungsten groove in individual tungsten groove array equivalently-sized, these three tungsten groove arrays lay respectively at three pieces active
Qu Shang, three pieces of active areas are all N-type or p-type doping with substrate.First tungsten groove array is X tungsten groove
Composing in parallel, the second tungsten groove array is that Y tungsten groove composes in parallel, and the 3rd tungsten groove array is Z tungsten groove
Composing in parallel, X, Y, Z are positive integer, and X is not equal to Z, and three tungsten groove arrays are respectively by metal level
Draw, isolated by dielectric layer between metal level and substrate, between the first tungsten groove array and the second tungsten groove array
Spacing equal to spacing between the second tungsten groove array and the 3rd tungsten groove array, between these three tungsten groove arrays
Isolate with field oxygen.Utilize this semiconductor article tungsten groove contact resistance to test structure, Kelvin can be passed through
Connect (Kelvin) and test the resistance R obtained between the first tungsten groove array and the second tungsten groove array respectivelya、
Resistance R between second tungsten groove array and the 3rd tungsten groove arrayb, then according to Ra、RB, X, Z i.e.
The contact resistance of single tungsten groove can be calculated, change the size of single tungsten groove, i.e. available different chis
The contact resistance of very little tungsten groove.Utilize the contact resistance of the tungsten groove that the method obtains, substrate and line
Dead resistance can be shielded, and can try to achieve tungsten groove contact resistance value accurately by measured data, from
And quantify tungsten groove contact resistance value, provide feasibility for on-line monitoring tungsten groove technique.
Accompanying drawing explanation
In order to be illustrated more clearly that technical scheme, attached to use required for the present invention below
Figure is briefly described, it should be apparent that, the accompanying drawing in describing below is only some realities of the present invention
Execute example, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawing can be obtained according to these accompanying drawings.
Fig. 1 is the signal of semiconductor article tungsten groove structural section figure；
Fig. 2 is that Kelvin connects the schematic diagram carrying out resistance test；
Fig. 3 is the semiconductor article tungsten groove contact resistance test structure one embodiment schematic diagram of the present invention；
Fig. 4 is the semiconductor article tungsten groove contact resistance test knot utilizing the Kelvin connecting test present invention
The equivalent circuit of the resistance between the first metal layer of structure, the second metal level；
Fig. 5 is the semiconductor article tungsten groove contact resistance test knot utilizing the Kelvin connecting test present invention
The equivalent circuit of the resistance between the second metal level of structure, the 3rd metal level.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is entered
Row clearly and completely describes, it is clear that described embodiment is only a part of embodiment of the present invention,
Rather than whole embodiments.Should be appreciated that preferred embodiment described herein be merely to illustrate and
Explain the present invention, be not intended to limit the present invention.And in the case of not conflicting, in the present invention
Feature in embodiment and embodiment can be mutually combined.Based on the embodiment in the present invention, this area
The every other embodiment that those of ordinary skill is obtained, broadly falls into the scope of protection of the invention.
Embodiment one
Semiconductor article tungsten groove contact resistance test structure as it is shown on figure 3,
Silicon substrate 101 is formed three active areas the most adjacent, three active areas and substrate 101
Being all N-type or p-type, three active area dimensions are identical, isolate with field oxygen 103 between three active areas；
X tungsten groove (W-Sink) 102 it is formed with, this X tungsten groove (W-Sink) on first active area 111
Constitute the first tungsten groove array with connecing the first metal layer 105；It is formed with Y tungsten on second active area 112
Groove (W-Sink) 102, this Y tungsten groove (W-Sink) constitutes the second tungsten groove array with connecing the second metal
Layer 106；Z tungsten groove (W-Sink) 102 it is formed with, this Z tungsten groove on 3rd active area 113
(W-Sink) the 3rd tungsten groove array is constituted with connecing the 3rd metal level 107；The first metal layer 105, second
Electric insulation between metal level 106 the 3rd metal level 107, each metal level 105,106,107 and silicon substrate
Being isolated by dielectric layer 104 between 101, this dielectric layer 104 can be oxide, nitride, nitrogen oxides
Etc., each tungsten groove in three tungsten groove arrays equivalently-sized, the first tungsten groove array and the second tungsten groove
Spacing between array is equal to the spacing between the second tungsten groove array and the 3rd tungsten groove array, and spacing is A,
X, Y, Z are positive integer, and X is not equal to Z.
It is also preferred that the left X, Y, Z are the positive integer being not mutually equal.
It is also preferred that the left this semiconductor article tungsten groove contact resistance test structure is positioned at the scribe line area of silicon chip
Or test chip region.
Embodiment two
The semiconductor article tungsten groove contact resistance test structure utilizing embodiment one carries out tungsten groove contact resistance
The method of test, comprises the following steps:
One. utilize Kelvin to connect (Kelvin) and test the survey of described semiconductor article tungsten groove contact resistance
Resistance R between the first metal layer 105, second metal level 106 of examination structurea；Kelvin is utilized to connect
(Kelvin) test described semiconductor article tungsten groove contact resistance test structure the second metal level 106,
Resistance R between 3rd metal level 107b,
Two. it is calculated the contact resistance R of single tungsten grooveWsink,
Utilize Kelvin to connect (Kelvin) and test described semiconductor article tungsten groove contact resistance test knot
Resistance R between the first metal layer 105, second metal level 106 of structureaEquivalent circuit as shown in Figure 4:
Ra=R1+R2+RSubstrate parasitics 1, formula 2；
Utilize Kelvin to connect (Kelvin) and test described semiconductor article tungsten groove contact resistance test knot
Resistance R between second metal level the 106, the 3rd metal level 107 of structurebEquivalent circuit as shown in Figure 5:
Rb=R2+R3+RSubstrate parasitics 2, formula 3；
R1 is the total contact resistance after X tungsten groove parallel connection of the first tungsten groove array,
R2 is the total contact resistance after Y tungsten groove parallel connection of the second tungsten groove array,
R3 is the total contact resistance after Z tungsten groove parallel connection of the 3rd tungsten groove array,
RWsinkFor the contact resistance of single tungsten groove, due to the size phase of each tungsten groove in three tungsten groove arrays
With, it is possible to think that the contact resistance of each tungsten groove is identical, be all RWsink；
RSubstrate parasitics 1It is the substrate parasitics resistance between the first tungsten groove array and the second tungsten groove array, RSubstrate parasitics 2
It is the substrate parasitics resistance between the second tungsten groove array and the 3rd tungsten groove array, due to the first tungsten groove array
And between the spacing between the second tungsten groove array is equal between the second tungsten groove array and the 3rd tungsten groove array
Away from, therefore it is believed that RSubstrate parasitics 1Equal to RSubstrate parasitics 2；
Formula 4～6 is brought into formula 2,3, then obtains:
Due to RaAnd RbCan be obtained by test, X and Z is layout design it is known that therefore can be asked by formula 1
Obtain tungsten groove contact resistance RWsink。
The semiconductor article tungsten groove contact resistance test structure of the present invention, including three tungsten groove arrays, three
Each tungsten groove in individual tungsten groove array equivalently-sized, these three tungsten groove arrays lay respectively at three pieces active
Qu Shang, three pieces of active areas are all N-type or p-type doping with substrate.First tungsten groove array is X tungsten groove
Composing in parallel, the second tungsten groove array is that Y tungsten groove composes in parallel, and the 3rd tungsten groove array is Z tungsten groove
Composing in parallel, X, Y, Z are positive integer, and X is not equal to Z, and three tungsten groove arrays are respectively by metal level
Draw, isolated by dielectric layer between metal level and substrate, between the first tungsten groove array and the second tungsten groove array
Spacing equal to spacing between the second tungsten groove array and the 3rd tungsten groove array, between these three tungsten groove arrays
Isolate with field oxygen.Utilize this semiconductor article tungsten groove contact resistance to test structure, Kelvin can be passed through
Connect (Kelvin) and test the resistance R obtained between the first tungsten groove array and the second tungsten groove array respectivelya、
Resistance R between second tungsten groove array and the 3rd tungsten groove arrayB, then according to Ra、RB, X, Z i.e.
The contact resistance of single tungsten groove can be calculated, change the size of single tungsten groove, i.e. available different chis
The contact resistance of very little tungsten groove.Utilize the contact resistance of the tungsten groove that the method obtains, substrate and line
Dead resistance can be shielded, and can try to achieve tungsten groove contact resistance value accurately by measured data, from
And quantify tungsten groove contact resistance value, provide feasibility for on-line monitoring tungsten groove technique.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, all should wrap
Within being contained in the scope of protection of the invention.
Claims (5)
1. a semiconductor article tungsten groove contact resistance test structure, it is characterised in that
Being formed with three active areas the most adjacent on a silicon substrate, three active areas are all N with substrate
Type or p-type；
Being formed with X tungsten groove on first active area, this X tungsten groove constitutes the first tungsten groove array with connecing
The first metal layer；Being formed with Y tungsten groove on second active area, this Y tungsten groove constitutes the second tungsten groove
Array is with connecing the second metal level；Being formed with Z tungsten groove on 3rd active area, this Z tungsten groove is constituted
3rd tungsten groove array is with connecing the 3rd metal level；
Electric insulation between the first metal layer, the second metal level, the 3rd metal level；
Each tungsten groove in three tungsten groove arrays equivalently-sized；
Spacing between first tungsten groove array and the second tungsten groove array, equal to the second tungsten groove array and the 3rd
Spacing between tungsten groove array；
X, Y, Z are positive integer, and X is not equal to Z；
Three active area dimensions are identical, isolate with field oxygen between three active areas；
Isolated by dielectric layer between the first metal layer, the second metal level, the 3rd metal level and silicon substrate.
Semiconductor article tungsten groove contact resistance the most according to claim 1 test structure, its feature
It is,
X, Y, Z are not mutually equal.
Semiconductor article tungsten groove contact resistance the most according to claim 1 test structure, its feature
It is,
Described dielectric layer is oxide, nitride or nitrogen oxides.
Semiconductor article tungsten groove contact resistance the most according to claim 1 test structure, its feature
It is,
This semiconductor article tungsten groove contact resistance test structure is positioned at scribe line area or the test core of silicon chip
Section.
5. utilize the semiconductor article tungsten groove contact resistance test knot described in any one of claim 1 to 4
Structure carries out the method for tungsten groove contact resistance test, it is characterised in that comprise the following steps:
One. utilize the of the test structure of semiconductor article tungsten groove contact resistance described in Kelvin's connecting test
Resistance R between one metal level, the second metal levela；Utilize quasiconductor system described in Kelvin's connecting test
Product tungsten groove contact resistance test resistance R between the second metal level of structure, the 3rd metal levelb,
Two. it is calculated the contact resistance R of single tungsten grooveWsink,
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| CN105223420B (en) * | 2015-09-28 | 2017-07-07 | 深圳市华星光电技术有限公司 | For measuring the TFT of contact resistance and the measuring method of contact resistance |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933020A (en) * | 1996-10-16 | 1999-08-03 | Vlsi Technology, Inc. | Parasitic resistance measuring device |
| US6362638B1 (en) * | 1999-09-01 | 2002-03-26 | Agere Systems Guardian Corp. | Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies |
| CN102200554A (en) * | 2011-03-30 | 2011-09-28 | 上海北京大学微电子研究院 | Resistor test structure and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8451012B2 (en) * | 2009-02-17 | 2013-05-28 | International Business Machines Corporation | Contact resistance test structure and method suitable for three-dimensional integrated circuits |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933020A (en) * | 1996-10-16 | 1999-08-03 | Vlsi Technology, Inc. | Parasitic resistance measuring device |
| US6362638B1 (en) * | 1999-09-01 | 2002-03-26 | Agere Systems Guardian Corp. | Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies |
| CN102200554A (en) * | 2011-03-30 | 2011-09-28 | 上海北京大学微电子研究院 | Resistor test structure and method |
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