TWI234420B - Circuit device and manufacturing method thereof - Google Patents

Circuit device and manufacturing method thereof Download PDF

Info

Publication number
TWI234420B
TWI234420B TW92132371A TW92132371A TWI234420B TW I234420 B TWI234420 B TW I234420B TW 92132371 A TW92132371 A TW 92132371A TW 92132371 A TW92132371 A TW 92132371A TW I234420 B TWI234420 B TW I234420B
Authority
TW
Taiwan
Prior art keywords
conductive pattern
circuit
aforementioned
conductive
patent application
Prior art date
Application number
TW92132371A
Other languages
English (en)
Other versions
TW200421947A (en
Inventor
Yusuke Igarashi
Nobuhisa Takakusaki
Jun Sakano
Noriaki Sakamoto
Original Assignee
Sanyo Electric Co
Kanto Sanyo Semiconductors Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co, Kanto Sanyo Semiconductors Co filed Critical Sanyo Electric Co
Publication of TW200421947A publication Critical patent/TW200421947A/zh
Application granted granted Critical
Publication of TWI234420B publication Critical patent/TWI234420B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1234420 玖、發明說明： 【發明所屬之技術領域】 :發::係有關電路裝置及其製造方法’尤指可將供安 衣專70件的導電圖型作成較厚，而供安裝具有厚度的電 路元件的導電圖型作成較薄，使整體裝置之厚度更薄型化 的電路裝置及其製造方法。 文，寻t化 【先前技術】 —以在，為了將固定在電子機器的電路裝置用於行動電 話、攜帶用電腦等，而需有更為小巧輕薄之電路裝置。 兹例如舉半導體裝置作為電路裝置的例子加㈣ :二半導體裝置而言，最近正開發一種稱為csp(晶片尺 寸大衣晶片尺寸同等大小的晶圓級csp或較晶片尺 寸大一些的CSP。 =3圖是顯示採用麵環氧基板5作為支持基板，較 ^ ώ ^ 3式。於此，就電晶體晶片Τ 衣於玻璃環氧基板65的裝置加以說明。 1此麵環氧基板65的表㈣成第丨電極67、第2 第及晶粒座（diepad)69，f面形成^㈣電極7〇 弟2月面電極71。並且，唾 67與第1背面電極7。，第；=述第1電極 電連接。前述裸電晶體晶片τ;，弟2背面電極71 I# 固疋在晶粒座69上，電晶 :::Ζ第1電極67經由金屬細線72連接。而且，於 =板65上設置樹腊層73,俾覆蓋電晶體晶片Τ。 WCSPW採用麵環氧基板65，不過，其與晶 315244 6 1234420 圓尺寸CSP不同，具有自晶片τ至外 |丨連接用的背面電極 70、71的延伸構造簡單，可低廉製造的優點。 不過，上述CSP66使用玻璃環氧基板65作為中間板 ⑽ten—)，因此，以1>66的小型化及薄型化有其限 因此’ P幵 1發如第Μ圖所示之不需要安裝基板的電路裝置 8〇(例如參考曰本專利文獻1)。 參考第U圖，電路裝置80係由導電圖型81、固定於 導電圖型81上的電路元件82、電性連接電路元件82盘導 電圖型81的金屬細線84、露出導電圖型81背面的電路 件82以及被覆電路元件82和 $導電圖型81的絕緣性樹脂 。*電路裝置80不需要安裳基板來構成，故相較 於C S P 6 6，更為輕薄型小巧。 [專利文獻1 ] 日本專利特開2002-076246 ?虎公 【發明内容】 g弟1圖） [發明所欲解決之問題] 不過，於上述電路裝置80中，導電圖型81係形成— 樣厚。因此，厚度不同的多 ― 電路兀件82固定於導電圖型 81 ^，為了被覆具有厚度的電 樹脂㈣較厚。因此，電路二件所形成之絕緣性 穿署叮、… $路“ 80全體會變厚，使電路 衣置可減輕縮小的尺度受到限制。 若為求裝置的薄型化而作出更薄的導電圖型81，若電 兀件82為會發熱的元件時，有暫態熱阻變大的問題。 本發明是有鑑於上述問題而提出的技術，其主要目的 315244 7 1234420 ::提供即使於内裝較厚電路元件時 王體厚度增加的電路裝置及其製造方法17抑制電路裝』 [用以解決問題之手段] / 。 本發明電路裝置係具有··厚度較 分隔的第1導電圖型；較前述第】導兩’且：第1分隔槽 分隔槽分隔的第2導電圖型；固定於二、圖型薄，並以第2 第1電路元件和固定於前述第 :述弟1導電圖型的 件’·以及’被覆前述電路元件及前^ $的第2電路元 兩導電圖型之背面露出，並且充填於::圖型，而令前述 性樹脂。 述兩分隔槽的絕緣 本發明電路襄置係具有：厚度較大 隔的第1導電圖型；較前述第 以弟1分隔槽分 隔槽分隔而構成微細配線的第雷圖型薄，並以第2分 1導電圖型的電路元件；以及，被承：型；固定於前述第 導電圖型，而令前述兩導電圖型;二1路元件及前述 前述兩分隔槽的絕緣性樹脂。 路出，並且充填於 本發明電路裝置之製造方法 覆第i光阻於前述導電箱表面的步備導電荡，塗 光阻於形成前述第i導電圖型二:精由殘留前述第1 隔前述第丄導電圖型的第進行姓刻，形成分 2導電圖型區域的前述導電簿凹“更二同樣使形成第 阻被覆至少前述第1導電圖型的上：广’糟丄以弟2光 電圖型區域的前述導電羯表面面以及形成前述第2導 述第1分隔槽，並進一步形成J竭’形成深凹的前 烕刀隔前述第2導電圖型的第 315244 8 1234420 」分隔槽的步驟；將電— ——一”等電圖型及 :述第2導電圖型雙方或其中任一方的步驟；形成絕緣性 樹脂，以被覆前述電路元件並充填於前述兩分隔槽的步 驟；以及除去前述導電猪背面直至充填於前述兩分隔槽的 &緣性樹脂露出的步驟。 藉由將第2導電圖型形成得較第1導電圖型 雷欧；. ^ m ^ 件固定於第2導電圖型，可使整個裝置形成得更 溥。由於會伴隨發熱的元件固定於較厚的: /± T % 圚型， 1文件暫態熱阻可因此而減小。 【實施方式】 [發明之實施形態] ("兒明電路裝置之第1實施形態） 、參考第i圖，電路裝置1()Α具有：以帛i > ”的二厚第1導電圖型UA;形成較第！導電圖JUA 第2分隔槽16B分隔的第2導電圖型ιΐβ 弟1導電圖型11A的第Ϊ電路元件 疋方、 圖型的第2電路元件= 和固定於第2導電 電图刑η 以及被覆電路元件12及導 圖i Π而令兩導電圖型u的背面露出 * 隔槽1 6的絕绫性丹庐〗q 卫充填方；兩分 十 、、束 以下詳述該電路裝置之处德 弟UA)圖是電路裝置1〇A 之、、，。構。 圖。 的七見圖’《1(B)圖是其俯視 第1導電圖型HA係考量谭材的附 鍍性而選擇其材料，所採 讀性、電 it Φ 之材枓如以鋼Cu為主材料& —電泪，以鋁Α1為主材料 巧王材枓的 十的¥電泊或由鐵_鎳Fe-Ni等人 315244 9 1234420 金製成的導電落等。於此，f i導電圖型11A形成霖出背 面，埋入絕緣性樹脂13的構造，藉第！分隔槽Μ而電月 性隔絕。第1導電圖型11A的厚度形成較第2導電圖型1二 厚，例如形成在140”（微米）以上。又，於自絕緣性樹脂 13露出的第丨導電圖型11A背面設置由焊錫等焊材構成的 外部電極1 5。 第1導電圖型11A藉第i分隔槽16A而電性隔絕。並 且，由於在第1分隔槽16A的側部設置至少一縮頸部17， 故第1分隔槽16A與絕緣性樹脂13牢固密貼。於此，第^ 導電圖型11A在上面形成安裝第丨電路元件的孤島，以 經由金屬細線14與第}電路元件12A電連接的接合塾乂及 (bonding pad)。又，裝置背面未設置外部電極15處°為光 1 6所被覆。 ' 第2導電圖型11B由與前述第！導電圖型uA相同的 材料構成，其形成較第1導電圖型丨丨A薄。更由於第^、曾 電圖型11A的背面與第2導電圖型11B的背面位於同一導 面上’故第1導電圖型11A的表面形成㈣2導電圖型= 的表面高。於此，雖然具有厚度的第2導電圖型固… 在第2導侧UB上面’不過，亦可進一步構成微細： 線部。又，第2導電圖们1B的具體厚度例如為5心市。 更且’第1導電圖㉟11A與第2導電圖丨nB亦可經由配 於此’第1電路元件12A採用半導體元件，其面朝上 固定於第1導電圖型11A所構成的孤島上。並且，第工電 315244 10 1234420 路凡件12A的電極與第1導電圖型11A所構成的接合墊經 由至屬細線1 4而電性連接。如上所述，第1導電圖型丨工a 形成較厚’故即使第丨電路元件丨2 A是伴生發熱的元件（例 如功率型半導體元件），第i導電圖型iia仍具有散熱片 之功忐，而減低暫態熱阻。又，具體而言，可採用大電流 塑半導體兀件作為第i電路元件丨2 A。在大電流型半導體 元件h形下，會於動作中產生大量的熱。在促進此種大電 流型半導體元件的第i電路元件12A散熱方面，較厚的第 1導電圖型具有較佳的散熱功能。 於此，第2電路元件12B採用具有晶片電阻或晶片電 容器等厚度的晶片構件，以焊錫等導電性焊接劑固定於第 2電路兀件12B上。尤其，前述第！電路元件i2A係採用 大電流型半導體^件，固然於其附近需要阻絕雜訊的大電 容量白"容器，不$，一般大電容量的電容器所形成之高 度軏回。因此，藉由將此種高度較高的大電容量的電容器 固定於較第i導電圖型11A薄的帛2導電圖型上，可使： 個電路裝置1 〇 A的厚度更薄。 絕緣性樹脂13被覆電路元件12、金屬細線14及導電 圖型11，而讓第1導電圖型11A及第2導電圖$ 11B之背 面露出。絕緣性樹月旨13彳全部採用熱硬化性樹脂或熱塑性 樹脂。又，絕緣性樹脂13充填於分隔各導電圖型η的分 隔槽16。更且，本發明電路裝置全體藉絕脂 13支持。 兹說明以上所述之具有厚度不同的第i導電圖型ιια 315244 1234420 及弟2導電圖Μ 11B的優點。薄的第i電路元件uA固定 於較厚的第！導電圖型11A上，厚的電路元件ι2β安裝於 較弟1導電圖㉟11A薄的第2導電圖型UB上。因此，即 ，厚度不同的多種電路元件12建構於電路裝置i〇a内部 時’藉由將厚的電路元件12B安裝於較薄的第2導電圖型 11B上，仍可縮減整體之厚度。 而且，可調整兩導電圖型之高度差距，使第丨導電圖 型HA之高度和帛i電路元件12A之高度相加後的高度， 可與第2導電圖型11B之高度和第2電路元件uB之高度 相加後之高度相同。由於以上之調整，可將塗覆第i導電 圖型11 A等之絕緣性樹脂13作成最小厚度，以產製厚度 更薄之裝置。 第1刀隔槽1 6 A係經由數次蝕刻而於第i導電圖型 ::A間之中間部形成縮頸部17。縮頸部17的橫向寬度較 第1分隔槽16A的其他部位狹窄。由於縮頸部17的側面 對C第1 $電圖型1i a的側面’故藉由絕緣性樹脂】3密 貼％頸部17 ’可提高第！導電圖型i i A與絕緣性樹脂u 的密貼強度。如上述’帛i分隔槽16A係經由數次餘刻導 電圖型U的材料即導電猪的同一部位而形成。因此，第】 分隔槽16A所形成的深度大於其寬度。又，縮頸部㈣ 連續形成於第1分隔槽16A的整個側面部。 ”由於此處之第！分隔槽16A經由兩次敍刻而形成，故 第1分隔槽16A所形成的深度為其寬度的兩倍。更且，經 由數次蝕刻而形成第丨分隔槽16A時，使所用成之深度遠 315244 12 1234420 大於其寬度。又由於第！導電圖型11A的厚度對應於第i 分2槽16A的深度，故本發明可形成厚度較第！分隔槽心 的見度大的第1導電圖型HA。 茲參考第2圖說明其他形態的電路裝置⑽的結 電路裳置刚具有以第1分隔槽W分隔的較厚第;導電 圖型iiA、形成較第}導電圖型nA薄並以第2分隔槽⑽ 勿隔而構成微細配線的第2導電圖型UB、固定於第i省 電圖型UA的電路元件12以及被覆電路元件12及導電= 型11而令兩導電圖型"的背 、， 回 “， 口生11的月面路出，亚且，充填於兩分 匕1 6的絕緣性樹脂1 3。 電路，結構的電路裝f1GB與參考第1圖所說明的 =衣！:的不同點，在於第2導電圖㈣構成微細 至、50。一言’由於第2導電圖型⑽的厚度可形成薄 ，故可經由蝕刻製成微細配線之結構。 揮功=上34結構’可將為使發熱電路元件12的散熱片發 =而形成較厚的第1導電圖型及形成微細配線的第2 i電圖型1 1 R 1 $成於同-電路裝置剛内部。又，亦可採 用與弟1圖中沾笼· ! . i 2。 、 弘路元件1 2 A相同者作為電路元件 (說明電路裝置的製造方法的第2實施形態） 太^ '考第3至第11圖說明電路裝置1G的製造方法。 本發明電路_ $ AA & ^ 、置的1這方法具備··準備導電箔40，塗覆第 1光阻PR1於導雷 留在表面的步驟；將第1光阻PRi殘 在死7成弟1導雷岡别彳 、圖孓11A的區域並進行蝕刻，形成分隔 315244 13 1234420 第1導電圖型11A的第i分隔槽16A，更且，以同 使導電猪40凹陷形成第2導電圖型區域的步驟；以第/ 光阻PR2被覆至少第！導電圖型"八的上面及形成第 電圖型的區域的導電荡4〇表面並進行姓刻，深㈣ 成第1分隔槽16A，更且，形成分隔第2導電圖型UB的 第2分隔槽16B的步驟；使電路元件12固定於第 圖型11A及第2導電圖型^ 1 —者或其中任一方的步驟· 形成絕緣性樹脂13以被覆電路元件12，並且充填前述二 分隔槽16的步驟；以及除去導電羯4〇背面直至充填於： 分隔槽16的絕緣性樹脂13的步驟。以下將詳述上述各: 驟。 义分穸 如第3至第5圖所不，本發明第上步驟係準備導
4〇，塗覆第1光阻PR1於導雷唸 V 力、V電泊40表面，將第j光阻 殘留在形成第1導電圖形〗〗 ㈡1 11A的區域並進行蝕刻，形成八 隔第1導電圖型11A的第丨八p 刀 切道η 隔槽16Α，更且，以同樣方 式使V電ν自40凹陷形成第2導電圖型區域。 方、本ν驟中，百先如第3圖，準備薄片狀導電箱利。 此導電箔40考慮焊材的附荖 、署〖生黏接性、電鑛性選擇复分
料，所採用之材料，以Γι1氈+ uW 乂 CU為主材料的導電箔，以μ 材料的導電箔或由；pe_Ni望沾人人a '
Nl寺的合金製成的導電箔等。導雷 白的厚度考慮後來的餘刻 木日]蝕刻，U l〇//m至3〇〇//m程度 接著參考第4圖，於導雷$ ^ 1 ^ 、V電v自4 0表面形成抗餘遮罩 1光阻PR1，圖型仆笛】企„ ^ 弟先阻PR1，露出形成第1導 型11A區域以外的導雷绞—。， ^ 〕¥電泊40。另外，亦露出第2導電圖型 315244 14 1234420 11B區域的導電箔40表面 區域。 以幵v成薄的第2導電圖型1 1 b >考第5圖以蝕刻方式，形成第1分隔槽16A。叙由 ==的分隔槽16A的深度例如為5一，由於其：面 為粗板面，故可提高與絕緣性樹脂i 3間的黏接性。此處使 用的敍刻劑主要採用氯化鐵或氯化銅，前料Μ於 此蝕刻劑中，4以此蝕刻劑噴淋。由於此際之滿式蝕列、甬 常為非異向性蝕刻，故側面形成彎曲結構。另夕卜，形成： 2導電圖型11Β區域的導電箱4〇亦蝕刻至與第】分隔槽 16Α的深度相同，其表面基本上平坦。 曰 本發明第2步驟如第6至第8圖所示，以第2光阻pR2 被覆至少第}導電圖型11Α的上面及形成第2導電圖型 UB區域的導電箱40表面並進行蝕刻，深蝕形成第i分隔 槽16A，更且，形成分隔第2導電圖型UB的第2 16B。 曰 首先，參考第6圖，在剝離並除去第丨光阻pRi後， 於包含第1分隔槽1 6A表面的導電箔4〇表面形成第2光 阻 PR2。 接著，參考第7(A)圖，第2光阻PR2經曝光顯影後， 使第1分隔槽1 6 A的底部與分隔第2導電圖型丨1 b的第2 分隔槽16B區域露出導電箔40表面。第2光阻pR2係貼 附於第1分隔槽1 6 A之部分側邊上。 其次，參考第7(B)圖，因蝕刻露出第2光阻pR2的導 電箱40，使第1分隔槽16A形成更深的槽溝，並且，形成 315244 1234420 弟2分隔槽16B。對霞屮楚
^ ^ y 。出弟2光阻PR2的第1分隔槽16A 底面進行等向性蝕刻 溝，於其深度方向的中間：二:隔槽16A形成更深的槽 刻而形成的第！分隔形成縮頸部17。經數次姓 5Γ、：？而，可形成與單次-刻所形成分隔槽為相 又之冰刀隔槽。因此，可形成較厚之第1導電圖型 11A:而不會擴大第1分隔槽16A的寬度。 :茶考弟8圖’以說明本步驟中由第2導電圖型11B 形成微細配線部的方法。 首先’參考第8(八）圖 槽16A的底部及^ 弟光阻PR2被覆第1分隔 ,、疋形成的第2導電圖S 11B。此際，第 細配線部細形成’俾使第2導電圖型11B可構成微 形：更：=:(B)圖，刻之方式’使第1分隔措 述第1步驟中，^電且形成第2分隔槽16B°由於前 區域極薄，故可上所形成之第2導電圖型1以 ， 了糟弟2導電圖型11β構成微細配線部。 如：將此處之，第2導電圖型間的間距設為5。二例 本ρ第3步驟如b圖所示，緊固電路元件12 UA及弟2導電圖㉟11B二者或其中任 參考第9(A)圖，此際，安茫電路 圖型HA及第2導雷心衣電路凡件12於弟1導電 12A_ 弟2 ¥電圖型UB二者。宜安裝薄的電路元件 i2R二的第1導電圖型UAjl，安裝厚的第2電路元件 於形成較第1導電圓型]IA薄的第2導電圖型上。此 315244 16 1234420 際’半導體元件的筮
兀仟的弟1電路元件12A 電圖型以構成的孤島上。並且，第固广弟1導 的電極與接合塾亦 弟、路…2A上面 万「弟1導電圖型HA藉全屬細蛣μ予 性連接。於此，m 一 > 猎孟屬細線U電 器等的晶片構件1 牛12B是晶片電阻或晶片電容
,^ 、以焊錫等焊材固定於第2導電圖型11B 上。例如，此虛夕楚彳雨 ^ α ^ 1113 體元件。 ， 电路兀件1 2 Α可採用大電流型半導 '.°又可#用晶片電容器作為第2電路元件12B。 麥考第9(B)圖，由於第2 部，M & i 才电口孓1 1B構成微細配線 安乂電路70件12僅安裝於第1導電圖“A上。就所 =電路元件12的種類而言，可採用與上述第I 12A相同者。 τ 本發明第4步驟如第]0 w . ^ 乂贯戈弟10圖所不，形成絕緣性樹脂13， 卑以被覆電路元件12，並且充填前述二分隔槽16。 參考第10(A)圖，絕緣性樹脂13被覆電路元件a及 複數導電圖型η ’且絕緣性樹脂13充填於導電圖型η門 的分隔槽16’與導電圖型u侧面的彎曲結構嵌合而牢固 結合。並且，導電圖型n藉絕緣性樹脂13支持。 由於寬度狹窄的縮頸部17形成於第！分隔槽16八，因 絕緣性樹脂13密貼於縮頸部17，使絕緣性樹脂Η與導電 圖型11之貼合更為緊密。本步驟可採取移轉模塑（transfei. m〇1d)、射出成形（injection mold)或蘸潰（dipping)等方式。 就樹脂材料而言，環氧樹脂等熱硬化性樹脂可採取移轉模 塑法，聚亞醯胺樹脂、聚硫化苯等熱塑性樹脂可採取射出 成形法。 315244 17 1234420 本步驟的優點在於，於姑受 万、被覆絕緣性樹脂13之前，構成 導電圖型11的導電箔40成Λ古 风馬支持基板。過去採用本來就 不需要的支持基板形成導雷炊 ... ’而本發明巾構成支持基板 的&電W 40則為電極材料所兩 而要的材料。因此，不僅且有 可以極為節省構成材料之方彳 /、 、 竹之方式進行生產作業的優點，更可 達到降低成本的目的。 更且’厚的第1電路元株 件1 2 Α係固定於薄的第2導電 圖型11B上。因此，第2雷敗— 冤路兀件1 2B的最上部與第1電 路元件1 2 A的最上部形成相 J曰0同度。因此，即使在内奘 厚的電路元件1 2 A情形下，彳π 7 4 仍可抑制被覆此電路元件的絕 緣性樹脂1 3的厚度增加。 參考第10(B)圖，第9 i m , ^ V電圖型11 B構成微細配線部， 系巴緣性樹脂1 3充填於分卩5楚〇 槽咖。 真、刀^弟2導電圖型㈣的第2分隔 而，^發明第5步驟係、如第11圖所示，除去導電箱4〇背 面’直至充填於兩分隔6 ㈣耗16的絕緣性樹脂13露出。 參考第11(A)圖，除去導電 1分隔槽16A及第2分厂〜二 ，直至充填於第 、^ 刀隔槽16B的絕緣性樹脂13露出， 以分隔各導電圖型11。太半聰 土本步驟係以化學方式或物理方式降 去導電箔40的背面’而分 式除 ^ ^ V電圖型11。此步驟藉由研 磨、磨削、終雷射的金屬蒸發等實施。由於第由二 槽-較深，故第丨導電圖她亦可於此處形二;旱隔 具體而言’其厚度可至150…上。 厂子。 參考第11(B)圖，藉由盥μ 曰由/、上述相同的方法電性隔絕構 315244 18 1234420 成微細配線部的第2導電圖型11 B。由於形成第2、曾 2 電圖 51 11B的區域的導電箔40藉由前述第1步驟充分薄化 故可構成微細配線部。 於本步驟結束後，以光阻1 6被覆導電圖型丨丨北 曰勺月面， ;所需部位形成外部電極丨5。將矩陣狀的各電路事 的交界部的絕緣性樹脂i 3加以切割，使分割成個 1 、置10。經由上述步驟，製造第丨圖 裴置10。 《所不之電路 參考第12(A)圖及第12(B)圖，藉由局部除去 =面，可分隔各導電圖型U。此際，於藉 ：
Si電？。的之後，以纖除去導電Ml 1“^ ^除去的40的區域係對應於形成分隔槽 辦力導怎以上述局部除去的方法分隔各導電圖型U，可 日加導電圖型π的厚度。因此，可提高 Τ 熱性。 塔展置全體的散 [發明效果] 根據本發明電路裝置，薄 具有厚度的第！墓㈣， 件12Α固定於 於較第1， 上厗的電路元件12B安裝 方；弟1導電圖型^薄的第2導電圖型UB上。二； 式’可減低加上導電圖型u及固定於… 上述 的電路元件12的總厚声。因…“ ¥電圖型11上面 更薄。 因此，整個電路袭置丨。可作得 更且’將功率型半導體元件等發熱元 ‘電圖型11A上，第衣方；尽的第 弟b電圖型UA具有散熱片的功能， 315244 19 1234420 而減低暫態熱阻。 更且，由於可以薄的第2導雷 -P 5 ^ ^ ^ ^ B構成微細配線 '故可k供之電路裝置10B包含：具有 1導雷闰制1 1 A 、》 …、片功月b的弟 、 以及構成配線部的第2導冑_ 本發明電路裝置之製造方法，係使 。 刻導電羯40，而形成第1分隔槽16A，t 、阻PR1餘 第2導電圖型11B預定形成區二：薄=與導… 光阻PR2，再錢料t 4 = ’使用弟2 、， 便弟1分隔槽16A爭嚅， 亚且形成第2分隔槽。因此可形成以第 分隔的厚的第1導電圖们Μ以及以第2分隔^曰八s 的第2導電圖型iiB。 曰 刀^ 【圖式簡單說明】 θ第1(A)圖是說明本發明電路裝置的剖視圖 圖是說明本發明電路裝置的俯視圖。 第2圖是說明本發明電路裝置的剖視圖。 f3圖是說明本發明電路襄置之製造 第4圖是說明本發明電路裝置之 的。1視圖 第5圖是說明本發明電路裝置之 '的剖視圖。 第6圖是說明本發明電路褒：：：：的剖視圖。 圖 圖 第7(A)圖是說明本發明電路裝置二造方：剖視圖。 第圖是說明本發明電路裝 、生《的剖視 衣仏方法的剖視 第8(A)圖是說明本發明電路装置之妒造方、 圖，第8(B)圖是說明本發明電路裝置制^ 1 的心視 衣1^方法的剖視 315244 20 1234420 71 第 2 背 面 電極 72、 84金 屬 細 線 73 樹 脂 層 80 電 路 裝 置 81 導 電 圖 型 82 電 路 元 件 83 絕 緣 性 樹 脂 85 外部 電 極 86 光 阻 87 分 隔 槽 T 電 晶 體 晶 片
22 315244

Claims (1)

1234420 拾 申請專利範圍·· ]· 一種電路裝置，具有·· 以弟1分隔槽分隔的第！導電圖型； 形成較前述第1導電圖型镇、, 的第2導電圖型； …，亚以第2分隔槽分隔 前：：：述第1導電圖型的第1電路元件和固定於 别述弟2導電圖型的第2電路元件；以及 -圖=!述：路元件及前述導電圖型而令前述兩導 ::一出，並充填於前述兩分隔槽的絕緣性樹 2·如申請專利範圍第丨項之電路 電圖型的表面形成較前述第2導、、中，雨述第1導 3. 如申請專利範圍第〗項之電路穿圖：的表面高。 部設置於分隔前述第〗導電圖型分；=少-縮頸 4. 如申請專利範圍第〗項之 刀：槽的側部。 路元件較前述第丨電路元件厚。、置、、巾’前述第2電 5. 如申D月專利祀圍第i項之電路裝置， 一 路元件的高度與前述第1導電圖型的高述第u 度，係和前述第2電路元侔 X σ起來的咼 的高度加起來的高度相等，度與前述第2導電圖型 6·如申請專利範圍第1項之電路裝置，其中一 路元件是半導體元件。 別述第1電 7·如申請專利範圍第1項之電路裝置，其中…、… 路元件是會發熱的元件。 則述第1電 315244 23 1234420 8·如申請專利範圍帛i 路元件是日、之屯路叙置，其中，前述第2電 U丨卞疋晶片電容器。 电 9_如申凊專利範圍帛】項之 你Γ;、’丄 $路衣置’其中’糕支細西？ έ令六 係以可述第2導電圖型構t /、中U、.田配線部 10·-種電路裂置，具有： 以第1分隔槽分隔的第i導電圖刑· 形成較前述第i導電—θ , 而構成彳5 έ $ 圖生潯，並以第2分隔槽分ρ 構成被細配線的第2導電圖型； ”隔 固定於前述第1導雷 被覆前述電路元件=電路元件；以及 電圖型的背面露出，並充二二圖八型:而彻兩導 月旨。 、 之一为隔槽的絕緣性樹 11 ·如申请專利範圍第丨〇 導電圖型的表面 、、，-、路裝置’其中，前述第1 12·如申請專利範圍第 、電圖型的表面高。 頸部設置於分隔前述第'^中’至少一縮 13. 如申請專利範 "1的分隔槽的側部。 现㈤弟10項之電路 元件是半導體元件。 凌置，其中，前述電路 14. 如申請專利範圍第10項之 元件是會發熱的元件。 、置，其中，前述電路 15. 一種電路農置之製造方法，且備· 準備導電蕩，塗覆第以阳— 驟’· 於則述導電箔表面的步 藉由殘留首Γ ;+、& 欠g别述弟】光阻於前述 &電圓型的形成 315244 24 1234420 @域並進杆4占方ί 4，形成分隔前述第1導電圖型的第1分 φ Μ ，同樣使第2導電圖塑的形成區域的前述導 電竭凹陷的步驟； 以—、弟2光阻被覆至少前述第1導電圖型的上面 ^形成前述第2導電圖型區域的前述導電摆表面並 八：：刻’形成深凹的前述第1分隔槽，並進一步形成 刀隔則述第2導電圖型的第2分隔槽的步驟； 雷岡將電路元件固定於前述第1導電圖型及前述第2導 電圖型雙方或其中任一方的步驟； 以被覆前述電路元件並充埴 ^ ^ 干五兄真方《剐述兩分隔槽的方 式形成絕緣性樹脂的步驟；以及 除去前述導電箔背面直至充 维縫Μ：执π十 兄填於W述兩分隔槽的 、、、巴、、彖性树月曰露出的步驟。 16·如申請專利範圍第 給展置之製造方法，豆 中，藉由在以前述第2光阻被覆〃 一 & _ 迷弟1分隔槽的側面 後進行蝕刻，形成縮頸部於前述第]^ ^ # 义罘1分隔槽的側部0 17 ·如申蜎專利範圍第1 5項之電路穿s ^ 一 貝 衣置之製造方法，其 中’精由局部除去前述導電箔的杂 J钆分电/白曰〕月面，而使前述絕緣性 樹脂露出。 315244 25
TW92132371A 2002-12-20 2003-11-19 Circuit device and manufacturing method thereof TWI234420B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002371028A JP4183500B2 (ja) 2002-12-20 2002-12-20 回路装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW200421947A TW200421947A (en) 2004-10-16
TWI234420B true TWI234420B (en) 2005-06-11

Family

ID=32810025

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92132371A TWI234420B (en) 2002-12-20 2003-11-19 Circuit device and manufacturing method thereof

Country Status (5)

Country Link
US (1) US6972477B2 (zh)
JP (1) JP4183500B2 (zh)
KR (1) KR100662687B1 (zh)
CN (1) CN100397641C (zh)
TW (1) TWI234420B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930377B1 (en) * 2002-12-04 2005-08-16 National Semiconductor Corporation Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages
US20070176303A1 (en) * 2005-12-27 2007-08-02 Makoto Murai Circuit device
US7777310B2 (en) * 2007-02-02 2010-08-17 Stats Chippac Ltd. Integrated circuit package system with integral inner lead and paddle
US7833649B2 (en) * 2007-04-11 2010-11-16 Eveready Battery Company, Inc. Battery fluid manager using shape memory alloy components with different actuation temperatures
US8114712B1 (en) * 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package
JP2014164281A (ja) * 2013-02-28 2014-09-08 Fujifilm Corp 微細凹凸構造体の製造方法およびその方法により製造される微細凹凸構造体

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306872A (en) * 1991-03-06 1994-04-26 International Business Machines Corporation Structures for electrically conductive decals filled with organic insulator material
JP2001250887A (ja) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd 回路装置の製造方法
JP3561683B2 (ja) * 2000-09-04 2004-09-02 三洋電機株式会社 回路装置の製造方法
JP3639514B2 (ja) * 2000-09-04 2005-04-20 三洋電機株式会社 回路装置の製造方法
JP3600131B2 (ja) 2000-09-04 2004-12-08 三洋電機株式会社 回路装置の製造方法
JP2002237559A (ja) * 2001-02-09 2002-08-23 Sanyo Electric Co Ltd 半導体装置の製造方法およびそれを用いた混成集積回路装置の製造方法
JP4761662B2 (ja) * 2001-07-17 2011-08-31 三洋電機株式会社 回路装置の製造方法

Also Published As

Publication number Publication date
JP2004207278A (ja) 2004-07-22
CN1510750A (zh) 2004-07-07
TW200421947A (en) 2004-10-16
KR100662687B1 (ko) 2007-01-02
JP4183500B2 (ja) 2008-11-19
US6972477B2 (en) 2005-12-06
US20040159913A1 (en) 2004-08-19
KR20040055590A (ko) 2004-06-26
CN100397641C (zh) 2008-06-25

Similar Documents

Publication Publication Date Title
TW486920B (en) Electric circuit device and method for making the same
TW535462B (en) Electric circuit device and method for making the same
TWI261940B (en) Circuit device and manufacturing method of the same
US11728252B2 (en) Semiconductor device package
US6562660B1 (en) Method of manufacturing the circuit device and circuit device
CN103824836B (zh) 半导体承载元件及半导体封装件
JP4785139B2 (ja) 回路装置およびその製造方法
TWI399836B (zh) 晶圓級晶片尺寸封裝及製造方法
TW200405486A (en) Method for producing wiring substrate
TW200539367A (en) Circuit device and manufacturing method for the same, plate shaped body
CN109427759A (zh) 一种芯片封装结构及其制作方法、电子设备
TWI251246B (en) Circuit device and fabricating method of the same
KR20010023024A (ko) 멀티칩 모듈 구조체 및 그 제작 방법
TW200405779A (en) Circuit device and its manufacture
KR910008814A (ko) 산화 니켈 장벽 스트립을 가지는 rf 트랜지스터 패키지
TW200849537A (en) Etched leadframe structure
TW511399B (en) Semiconductor device and its manufacture method
TWI234420B (en) Circuit device and manufacturing method thereof
TW200405774A (en) Circuit device and method for making the same
TWI253884B (en) Circuit device and manufacturing method thereof
JP3945380B2 (ja) 半導体装置およびその製造方法
TW486799B (en) Semiconductor device and its manufacturing method
JP2002299462A (ja) 半導体装置
US20050263482A1 (en) Method of manufacturing circuit device
JP2019140145A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees