TW200405779A - Circuit device and its manufacture - Google Patents

Circuit device and its manufacture Download PDF

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Publication number
TW200405779A
TW200405779A TW092118684A TW92118684A TW200405779A TW 200405779 A TW200405779 A TW 200405779A TW 092118684 A TW092118684 A TW 092118684A TW 92118684 A TW92118684 A TW 92118684A TW 200405779 A TW200405779 A TW 200405779A
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TW
Taiwan
Prior art keywords
aforementioned
wafer
pad
bonding
circuit device
Prior art date
Application number
TW092118684A
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Chinese (zh)
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TWI240603B (en
Inventor
Kouji Takahashi
Noriaki Sakamoto
Original Assignee
Sanyo Electric Co
Kanto Sanyo Semiconductors Co
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Publication of TW200405779A publication Critical patent/TW200405779A/en
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Publication of TWI240603B publication Critical patent/TWI240603B/en

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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

A circuit device in which a groove 14 is provided on a surface of a die pad 11 at a peripheral portion so as to surround an area a semiconductor element 13 is going to be mounted. Thus, the groove 14 functions as a stop gap to prevent the molten solder 19 which spreads while the semiconductor element 13 is put thereon in a step of mounting the semiconductor element 13 on the die pad 11 through the solder 19 from flowing out. Therefore, the short-circuiting between the die pad 11 and bonding pads 12 caused by the overflowed solder 19 can be prevented.

Description

200405779 玫、發明說明 [發明所屬之技術領域] 本發明係關於一種可防止用以固接 u^ ^ u接+導體元件之銲 才机出之電路裝置及其製造方法。 [先前技術] 話、养槪4 且疋休用於行動 ==等，因此力求小型化、薄型化及輕量化 導體裝= 例來說明電路裳置時，就-般的. 進行封f。’有以在通常以轉注成型法（—fer mol 封破之封裝型半導體裝置。 裝置係安裝在印刷基板PS。 該半導: ^ 料導體裝置6 1係以樹脂層6 Μ覆半^ 端子64 ΓΘ，且從該樹脂層Ο側部導出外部連接用導# 從樹脂層《露^外面，㈣尺寸較大子6 峨、薄型化及輕量化。因此，：=:=能… 溥型化及輕量化而競相：貝j型化、 為CSP(chiD · 知〇種構运，取近開發出一種海 等之曰^ package;晶片尺寸封裝）之與晶片尺寸和 ，iB“CSP ’或尺寸比晶片尺寸略大的CSP。 板，而且12比圖:片用表示採用玻璃環氧基板65作為支持基 在玻璃環氧基板 〜圖。此處將說明 _ ^ 上女裒有電晶體晶片T者〇 極68及晶片:二板65表面形成有第1電極67、第2電 干(epad)69,背面形成有第1背面電極70 314863 5 200405779 和第2背面電極71。然後， 而使前述第】電…第〗=通孔(〜… 第2電㈣與第2背面面電極70作電性連接、使 月面电極71作電性連接。 鮮塾69固接有前述裸露 而且在曰曰片 72遠接雷日妒少日日虹日日片丁，且透過金屬細線 72連接電曰日體之射極和第i電極π 接電晶體之基極和第2電極 ，，屬細線72連 丁的方式將樹脂層73m在@ ,者，以覆蓋電晶體晶片 一 "日層73 6又在破璃環氧基板65上。 前係採用玻璃環氧基板Μ，但與晶圓級⑽ 同’…曰片τ到外部連接用之背面電極7 之延伸構造簡單’而具有可廉價製造之優點。為= 圖所示，前述CSP66係安裝在印刷基板ps。 上裝設有構成電路之電極、配線，且以電性 ㈣ 前述⑽6、封裝型半導體裝置61、晶片 = 電容器CC等。鈇祛，4日日片 各種裝置中。…、οp刷基板構成之電路係安裳在 但是’如上述之半導體裝置中’係藉由熔 片銲墊69上之钽钱笙作u 土种在日曰 上之麵錫寺鲜材之回流（refl〇w)步驟而固 曰 T。因而，將電晶體τ載置於已熔融之銲錫上時，合曰曰 鲜錫從晶片銲墊69上流出，而有晶片銲墊69和；： ^再者為了防止從晶片銲墊69流出之銲錫到達第2 黾極6 8，而使晶片銲塾6 9和第2電極6 8隔開， 致整體裝置大型化。 此會導 [發明内容] 314863 6 200405779 本發明係鑑於上述問題而研發者，本發明之 ί於料材將半導體元件安^片銲墊 才0防止1干材攸晶片銲墊流出之電路裝置。 第1，本發明之特徵為且右· 之半導雜元件大致同等大:二:：與透過銲材而安裝 近接配置之接i(b。d. u μ ;與前述晶片薛塾 的方式形成d〔日η Γ§ pad)’以環繞前述半導體元件 出之、、冓、^.、=ΒΒ>Ι銲墊之周邊部，且防止前述銲材流 而封與…出前述晶片銲塾及前述接合塾之内面 封^述^料、前述接合塾及前述半導體元件。 之厚度淺2。本㉙明之特徵為前述溝道形成比前述晶片銲塾200405779 Rose, description of the invention [Technical field to which the invention belongs] The present invention relates to a circuit device and a manufacturing method thereof that can prevent the welding of a u ^ + u-connected + conductor element. [Prior art] If you want to use it, you can use it for action ==, etc. Therefore, we strive to reduce the size, thickness, and weight of conductors. For example, when you explain the circuit installation, you should seal it as usual. 'There is a package semiconductor device which is usually sealed by transfer molding (—fer mol.) The device is mounted on a printed circuit board PS. The semiconductor: ^ The material conductor device 6 1 is covered with a resin layer 6 M. ^ Terminal 64 ΓΘ, and the external connection guide # is derived from the side of the resin layer 0. From the outside of the resin layer, the size of the puppet is 6 angstroms, which is thinner and lighter. Therefore: =: = 能 ... Lightweight and competitive: J-type, CSP (chiD · know 0 structure operation, and developed a kind of ^ package; chip size package) and the chip size, iB "CSP" or size ratio The chip size is slightly larger than the CSP. The board, and the 12 ratio picture: The film is shown on the glass epoxy substrate using a glass epoxy substrate 65 as a support ~ Figure. Here will be explained _ ^ upper son-in-law has a transistor wafer T. Electrode 68 and wafer: the first electrode 67, the second electric pad (epad) 69 are formed on the surface of the second plate 65, and the first back electrode 70 314863 5 200405779 and the second back electrode 71 are formed on the back surface. Electricity… the second = through hole (~ ... the second electric power is electrically connected to the second back surface electrode 70 to make the moon surface The pole 71 is electrically connected. The fresh noodle 69 is fixedly connected with the aforementioned nakedness and is connected to the thunder and jealousy and the sun and the sun and the sun and the sun on the 72, and the metal electrode 72 is connected to the emitter of the sun and the body. The i electrode π is connected to the base and the second electrode of the transistor, and the resin layer is 73m in the manner of 72-line thin wire, which covers the transistor wafer. The "day layer 73 6" is on the broken glass epoxy substrate. 65. The front system uses a glass epoxy substrate M, but it has the same advantage as wafer-level wafers, "... the extension structure of the chip τ to the back electrode 7 for external connection is simple," and it has the advantage of being inexpensive to manufacture. The aforementioned CSP66 is mounted on the printed circuit board ps. The electrodes and wiring constituting the circuit are mounted on the top and are electrically conductive. The aforementioned ⑽6, packaged semiconductor device 61, chip = capacitor CC, etc. 鈇, various devices on the 4th Japanese film Medium ...., οp The circuit of the brush substrate is An Sang, but in the "semiconductor device as described above", the tantalum Qiansheng on the fuse pad 69 is used as the u soil type on the surface of the temple. The reflow step is solidified to T. Therefore, the transistor τ is placed on the melted When the molten solder is applied, fresh tin flows out from the wafer pad 69, and there are wafer pads 69 and: ^ Furthermore, in order to prevent the solder flowing out of the wafer pad 69 from reaching the second pole 6 8 and Separating the wafer bonding pads 6 9 and the second electrode 6 8 leads to an increase in the size of the overall device. [Summary of the Invention] 314863 6 200405779 The present invention was developed in view of the above-mentioned problems. The component mounting pad is only a circuit device that prevents 1 dry material and wafer pads from flowing out. First, the present invention is characterized in that the semiconducting component on the right side is approximately the same size: 2: is installed through the welding material Proximity configuration i (b. d. u μ; form d [日 η Γ§ pad) 'in a manner similar to that of the aforementioned wafer Xue to surround the periphery of the semiconductor device, 冓, ^., = ΒΒ> 1, and prevent the aforementioned soldering The material flow seals the inner surface of the wafer bonding pad and the bonding pad, the bonding pad, and the semiconductor element. The thickness is shallow 2. The present invention is characterized in that the aforementioned channel formation is better than the aforementioned wafer bonding.

本發明之特徵為前述溝道填充有 前述絕緣性樹 :4’本發明之特徵為前述半導體裝置係IC晶片。 線而盘本i明之特徵為前述半導體元件係透過金屬細 線而：預期之前述導電圖案作電性連接。 1本I月之特徵為前述鮮材係銲錫或銀（Ag)膠。 材。 ^明之特徵為使用絕緣性接著劑代替前述銲 第8，本發明之特徵為在前述 圍繞之區域中再形成溝道。 第9本發明之特徵為在前述 圍繞之區域是以格子狀形成溝道。 第10 本發明之特徵為具有： 晶片銲墊之前述溝道所 晶片銲墊之前述溝道所 準備導電薄片之步驟； 314863 7 200405779 在前述導電薄h形a 數個電路褒置^曰^、厚度為淺的分隔溝而形成構成複 接之半導體元件==:接合塾’同時以環繞預定固 述分隔溝淺的溝道方式而在前述晶片銲塾形成比前 於前述晶片銲塾之㈣ ί過鲜材而將半導體元件固接 接合墊進行打線接二二：刖述+導體兀件和預期之前述 包覆前述半導體元: g)之步驟；以絕緣性樹脂 方式共同成型之牛驟.^充填於前述分隔溝及前述溝道之 述絕緣性樹脂為：：牛ΓΓί導電薄片之背面至露出前 方式:〜各電由切割前述絕緣性樹脂之 淺。弟11 ’本發明之特徵為前述溝道形成比前述晶片鮮塾 ί 明之特徵為前述銲材係薛錫或銀(Α_。 材。本發明之特徵為使用絕緣性接著劑代替^ [實施方式] (說明二路裳置10之構成的第1實施形態）The present invention is characterized in that the trench is filled with the insulating tree: 4 'The present invention is characterized in that the semiconductor device is an IC wafer. It is characterized by the fact that the aforementioned semiconductor elements are passed through thin metal wires and the aforementioned conductive patterns are expected to be electrically connected. 1This month is characterized by the aforementioned fresh material solder or silver (Ag) glue. material. It is characterized in that an insulating adhesive is used in place of the aforementioned solder, and the present invention is characterized in that a channel is further formed in the aforementioned surrounding area. A ninth aspect of the present invention is characterized in that the channel is formed in a grid shape in the surrounding area. The tenth aspect of the present invention is characterized by having: a step of preparing a conductive sheet prepared by the aforementioned channel of the wafer pad of the wafer pad; 314863 7 200405779 placing several circuits in the aforementioned conductive thin h-shaped a ^^^, Shallow separation trenches are formed to form a multiplexed semiconductor element ==: bonding pads, and at the same time, the aforementioned wafer bonding pads are formed in a shallow trench manner around the predetermined fixed separation trenches. Use fresh materials to bond the semiconductor component fixed bonding pads: narration + conductor element and the aforementioned step of encapsulating the aforementioned semiconductor element: g); the step of co-molding with insulating resin. ^ The insulating resin filled in the aforementioned separation trench and the aforementioned channel is: the back of the conductive sheet of the cow ΓΓί to the way before being exposed: ~ each electric cuts the shallowness of the aforementioned insulating resin. Brother 11 'The present invention is characterized in that the aforementioned channel formation is more distinct than the aforementioned wafer, and the aforementioned welding material is Xue Xi or silver (A_. Material. The present invention is characterized by using an insulating adhesive instead of ^ [Embodiment] (Describes the first embodiment of the structure of the two-way clothes set 10)

’恥第1圖說明本發明之電路 圖（A)係電路裝置1〇之俯視— 之構成等。第J 之剖視圖。 弟1 _)係電路裝置10 參知、弟1圖（A)及第]图m、 構成。亦即，電路裝置ίο係由··：::】：广有如下之 裝之半導體元件13大致同等大小：曰’片：銲材19而安 輝墊11近接設置 日日，干塾II ;與晶片 2，以環繞半導體元件13的方 3J4863 200405779 式形成在晶片辉勢11 μ 、、， 1的周邊部，且防止銲材1 9流出之溝 道^ 1 4，以及^，蚀曰 y力曰n 使曰曰片1于墊11及接合墊12之背面露出而封 裝晶片銲塾11、接合墊 王i Z及牛冷體兀件1 3。以下說明上 述之各構成要素。 “晶片銲墊11係安裝有半導體元件13之導電圖案，由 銅薄片等金屬構成，且使背面露出而埋設在絕緣性樹脂 一而且Ba片鲜墊11之平面大小形成地比所安裝的半導 體元件略大，該周邊部形成有溝道14。該圖⑷中，晶片 鋅墊11形成在中央部 、凑 ^ 、邙且透過鋅材19而安裝有由1C晶片 荨構成之半導體元株 、 凡件13。而且，對應安裝有半導體元件13 之區域的晶片銲墊J i # 表面形成有由銀（Ag)等構成之電鍍 膜。 墊1 2係可彳合接金屬細線1 5之導電圖案，且使背 面露出而埋設在絕缕极抖0匕，< 使月 指16°在此處H繞形成在裝 置中央部之晶片銲塾 衣 〇方式形成有多數個圓狀接合墊 12。於该圖（a)中， 曰 ^ y 日日片銲墊11左右兩側之接合墊 1 2 A疋以電性獨立的許 σΧ 。而且，形成在晶片銲墊工i 上下兩側之接合塾】9 P说纟 整12B係與晶片銲塾u相連 以電性方式連接。而且，在 亦 的金屬細線的接著性，而艰士 士 丨怜得 膜。 要者性，而形成有由銀_等構成之電鍍 半導體元件13 m， θ 3係透過鋅材19而安裝在晶片銲墊 表面，在此疋透過銲材19而 型之1C曰片& 衣有在丰¥體凡件中較為大 i之1C日日片。而且，形成 又牡干V月豆兀件13表面的電極和 314863 9 200405779 接&墊1 2疋透過金屬細線 而作電性連接。此外，以電 性方式與晶片銲墊11連接之接人％^ θ八愿 ，C二^俊0塾1 2也是透過金屬細線 1 5而舁半導體元件丨3作 & m △ 〖生連接。此處所使用之銲材可 使用銲錫或銀（Ag)膠等導電性 ,,..Rt 包改接者劑。再者，亦可使用絕 緣性樹脂將半導體元件13安裝在晶片銲塾u。 ，道^以圍繞半導體元件13的方式㈣成在晶片 部’而^充填絕緣性樹脂16。而且，溝道14 的殊度形成地比晶片銲勢 的厗度淺。如此，以環繞安裝 有+ ¥體元件1 3之區域的古斗 ^ ^ m 一方式形成溝道14，藉此可在將 半導體元件13安梦於p卜一丄 衣於已熔融之銲材19上部的步驟中，防Fig. 1 illustrates a circuit diagram (A) of the present invention, which is a plan view of the circuit device 10-and the like. Section J view. Brother 1 _) is a circuit device 10 reference, Figure 1 (A) and Figure 1 m. That is, the circuit device is made by ::::]: There are widely mounted semiconductor elements 13 of approximately the same size: "sheet: soldering material 19 and Anhui pad 11 is set close to the day and day II, and dry II; and The wafer 2 is formed in a 3J4863 200405779 manner around the semiconductor element 13 on the periphery of the wafer glare 11 μ, 1, and 1 to prevent the soldering material 19 from flowing out of the channel ^ 1 4 and ^. n Make the wafer 1 exposed on the back of the pad 11 and the bonding pad 12 to encapsulate the wafer solder pad 11, the bonding pad king Z, and the beef cold body member 13. The following describes each of the constituent elements. "The wafer pad 11 is a conductive pattern on which the semiconductor element 13 is mounted. It is made of a metal such as a copper foil, and the back surface is exposed and buried in an insulating resin. Moreover, the planar size of the Ba fresh pad 11 is larger than the mounted semiconductor element. Slightly larger, a channel 14 is formed in the peripheral portion. In this figure, a wafer zinc pad 11 is formed in the central portion, and the semiconductor elements and components made of 1C wafers are mounted through the zinc material 19. 13. Furthermore, a plating pad made of silver (Ag) or the like is formed on the surface of the wafer pad J i # corresponding to the area where the semiconductor element 13 is mounted. The pad 12 is a conductive pattern capable of bonding the fine metal wires 15 and The back surface is exposed and buried in a tremor trembling 0 d, < a lunar finger 16 ° where H is wound around a wafer welding jacket formed in the center of the device 〇, a plurality of circular bonding pads 12 are formed. In this figure In (a), the bonding pads 1 2 A on the left and right sides of the y-y-chip pad 11 are electrically independent σ ×. Moreover, the bonding pads formed on the upper and lower sides of the wafer pad maker i] 9 P It is said that the 12B series is connected to the chip soldering unit u and is electrically connected. In addition, the adherence of the thin metal wire is difficult, and it is a film. If necessary, a plated semiconductor element composed of silver and the like is formed 13 m, and θ 3 is mounted on the wafer through the zinc material 19 On the surface of the pad, the 1C film & through the welding material 19 is made of 1C Japanese-Japanese film which is relatively large in the body. Also, the surface of the dried V-shaped bean 13 is formed. The electrode and 314863 9 200405779 contact pad 1 2 疋 are electrically connected through a thin metal wire. In addition, the connection connected electrically to the wafer pad 11% ^ θ eight wishes, C 2 ^ Jun 0 塾 1 2 is also a semiconductor element through a thin metal wire 1 5 3 & m △ 〖Green connection. The soldering material used here can use conductive materials such as solder or silver (Ag) glue, ... In addition, the semiconductor element 13 may be mounted on the wafer solder using an insulating resin. The semiconductor element 13 is formed on the wafer portion so as to surround the semiconductor element 13 and is filled with the insulating resin 16. The channel 14 The degree of formation is shallower than the degree of soldering of the wafer. In this way, the area with + ¥ body elements 1 3 is installed around The trench 14 of the domain is formed in such a way that the semiconductor element 13 can be comfortably applied to the upper part of the molten solder 19 in order to prevent the semiconductor element 13 from being dreamed.

:19從晶片料u流出。具體而言，即使銲材B =衣有+導體元件13之區域流出，銲材Η亦將貯存在 執迢二。因而，溝道14係發揮作為防止銲材19從晶片銲 、出之卩且止區域的功能。關於溝道1 4之製造方法將 制二这但溝道14係藉由蝕刻（etching)而和分隔溝9 一起 衣：目而’溝道14之剖面寬度係形成地比分隔溝9之寬 度窄 ° ' 巴、、彖[生树脂16係使晶片銲墊1 1及接合墊1 2之背面露 出、，、而將整體加以封裝。再者，形成在晶片銲墊u表面之 溝道14 /亦填充有絕緣性樹月旨16。在此係封裝帛導體元件 11 12〇 月匕，。材+料可才木用藉由轉注成型法所形成之熱硬化性樹 曰或藉由射出成型法所形成之熱可塑性樹脂。 锌材19係為銲錫或銀（Ag)膠等導電性膠漿（paste)，具: 19 flows out from the wafer stock u. Specifically, even if the welding material B = the area where the + conductor element 13 is provided, the welding material Η will be stored in the second execution. Therefore, the channel 14 functions as a stop region for preventing the welding material 19 from being soldered from the wafer. Regarding the manufacturing method of the channel 14, the second channel 14 is made together with the separation groove 9 by etching: the cross-sectional width of the channel 14 is formed to be narrower than the width of the separation groove 9 ° ',,,,, and [[The green resin 16 is made by exposing the back surfaces of the wafer pads 11 and the bonding pads 12], and the whole is packaged. Furthermore, the trench 14 formed on the surface of the wafer pad u is also filled with an insulating tree 16. Here is a package of plutonium conductor elements. Material + material can be used as a thermosetting resin formed by the injection molding method or a thermoplastic resin formed by the injection molding method. Zinc material 19 is conductive paste such as solder or silver (Ag) glue.

10 314863 有接合丰莫雕- 係為導電性：：和晶片銲墊U之作用。由於銲材19 係以電性方體元件13背面和晶片銲 接合塾12B亦與晶片鋒塾^電曰:上下兩側之 用金屬細線15將半導體元件13之電二 =因而’使 接，藉此可使形A / i j之电極和接合墊12B相連 件…Si::導體元件13表面的電路和半導體元 極17參=:;說明關於形成在電路裝置背面之外部電 合墊12的背ζ。係形成於裝設成圍繞晶片銲墊U之接 個外部電極月Π再者，晶片銲墊U的背面亦裝設有多數 口 W #尾極，因而，外苦 整個區域，以矩陣狀且等；;極17係在電路裝置1〇背面的 外部電極17，將電有複數個。藉此，透過 ^ ^ A ^ a* " 10 女裝在母板（motherboard：)等 女虞基可減少作用在外部電極卩之應力。 2 _)’藉由光阻劑18之開口部規 塾U背面之外部電極”的位置及大小。而且，； 接合墊!2背面之外部電極17的位置及大小係根 ί=背面而形成。作為接合墊12之材料的銅等金屬 ’、、 义好的材料，精由該濕潤性規限外部電極17 置及大小。如此，藉由利用接…之卿來規限= 在接合塾12背面之外部電極17的位置及大小，即使光： μ"8之開口部位置偏移，亦可精確度良好地形成外部電極 17。 本發明之10 314863 There is a bonding Feng Mo carving-is conductive: and the role of the wafer pad U. Since the welding material 19 is based on the welding of the backside of the electric cube element 13 and the wafer, 12B is also connected to the wafer. ^ Electricity: The upper and lower sides of the semiconductor element 13 are electrically connected with a thin metal wire 15 = thus' connect, borrow This can connect the electrode of the shape A / ij to the bonding pad 12B ... Si :: the circuit of the surface of the conductor element 13 and the semiconductor element 17 ==; explain the back of the external electric pad 12 formed on the back of the circuit device ζ. It is formed on an external electrode installed around the wafer pad U. Furthermore, the back of the wafer pad U is also provided with a large number of W # tail poles. Therefore, the entire area is externally and matrix-shaped. The pole 17 is an external electrode 17 on the back of the circuit device 10, and there will be a plurality of electricity. In this way, through ^ ^ A ^ a * " 10 women's wear such as motherboard: can reduce the stress on the external electrodes. 2 _) 'The position and size of the external electrode on the back of the U' are defined by the opening of the photoresist 18. Moreover, the position and size of the external electrode 17 on the back of the bonding pad 2 are formed on the back. Metals such as copper, which are the materials of the bonding pad 12, are good materials that limit the placement and size of the external electrode 17 by this wettability. In this way, it is restricted by using the key of the connection = on the back of the bonding pad 12 The position and size of the external electrode 17 can form the external electrode 17 with good accuracy even if the position of the opening of the light: μ8 is shifted.

特徵在於將溝道14以圍繞半導體元件L 314863 11 / iy 方式而形成在晶片銲墊u 13安裝在已_銲…：:由=體元件 13的重里等而往周圍擴散，但 凡件 會貯存在溝道14中，因& 了 5政到周圍的銲材19It is characterized in that the channel 14 is formed around the semiconductor element L 314863 11 / iy and is formed on the wafer pad u 13 and is mounted on the _solder ... :: It is diffused from the weight of the body element 13 and the like, but all parts will be stored in In the channel 14, due to the & 5 politics to the surrounding welding material 19

的表面^。因/ 防止料19從^鲜墊U 二 可防止由於流出的銲# i"接人塾 2相接觸而引起銲墊彼此發 ° 可使晶片銲墊u形成為盘安的情形。而且’藉此’ - Μ 马共文I在其晶片銲墊11之半導俨 凡件13大致同等。再者，式r上、 ·^牛¥肢 1 2 , ϋ》成使晶片銲墊11和接合墊 12相接近，而可縮小電路裝置10之敕蝴^ 上述藉由在晶片料u表面 Γ"尺寸。再者，如 u , ^ ^ 表面形成溝迢14，而使晶片銲墊 =緣性樹脂16相接觸的面積增加，因此可提高晶片 鋅墊11和絕緣性樹脂16的接著力。 參照第3圖說明其他形態之電路裳置i〇A。第3圖(八 「路裝置1GA之剖視圖，第3圖⑻係第3圖⑷之χ_χ =之剖視圖。電路裝置1GA具有與第1圖所說明之電路裝 10大致同樣之構成，在以形成於晶片銲塾"表面之溝 運14所環繞的區域，更以格子狀形成溝道14A。 ^曰溝迢14係以防止用以固接半導體元件13之銲材19 /曰曰片鋅墊1 1表面流出為目的，而裝設在晶片銲墊11的 2邊部。在此係在以溝道14環繞之區域復以格子狀形成溝 Y 乂釔子狀形成的溝道1 4 A亦具有與溝道1 4相同 、d面，形狀。如此藉由以格子狀形成溝道14的方式，可使 更多量的銲材19貯存在溝道14,因此可防止銲材19從晶 片1于墊11表面流出。再者，由於可更加使晶片銲墊1 1和 12 314863 絕緣性樹脂1 6相接觸的面積择 11和絕緣性樹脂16之密接*。曰口’目此可提高晶片銲墊 接著說明設置溝道14之 (dispenser)等供應銲材之機械 ^點。可使用配料機 π的表面，但是該配料機可供應H19㈣在晶片鲜墊 固疋的。因而，配料機之最小塗 _ 疋 安穿在曰里比將半導體元件13 女表在日日片鲜墊i i時所需銲材旦 從曰）4冷曰孰1】认士 里較多時，銲材19恐有 攸日日片鲜墊11的表面流出之 ^ 可防止銲材19流出。 、卩此，错由裝設溝道14, (說明電路裝置1〇之製造方法的第2實施形態） 在本貫施例中將說明電路裝置1〇 土 施形能中，在！：2 ‘ T 4· 衣k方法。本貫 ώ : 步驟製造電路裝置10。亦即，係 .準備導電薄片40之步驟；在導 ’、 度為淺的分隔溝9而形成構成複數： > 成比其厚 戚歿數個電路裝置部45之晶片 在干墊11及接合墊12，同時 W沾r ^ 守衣％預定固接的半導體元件 1 3的區域的方式而在 、替η止 片干墊U形成比分隔溝9淺的溝 道14之步驟；透過銲 銲塾"之^半以元件二㈣件13賴於晶片 Μ耵千凡件13和預期之接合墊12 ；!#I(Wire ;:::v充填於分隔溝9及溝道“之方式共同成 =步“；去除導電薄片4〇之背面至露出絕緣性樹脂16 驟;以及’藉由切割絕緣性樹脂16而分隔成各電 :=]。之步驟所構成。以下參照第4圖至第10 本發明之各步驟。 314863 13 200405779 如第4圖至第6圖所示，本發明之第i步驟係準備導 電薄片40，在導電薄片40形成比其厚度為淺的分隔溝9 而形成構成複數個電路裝置部45之晶片銲墊丨丨及接合塾 12,同時以環繞預定固接之半導體元件13之區域的方二而 在晶片銲墊1 1形成比分隔溝9淺的溝道14。 在本步驟中，首先準備如第4圖（A)之薄板（sheet)狀導 電薄片40。該導電薄片40係考慮銲材之附著性、接合性、 電鍍性來選擇其材料，材料係採用以銅（Cu)為主要材料之 導電薄片、以鋁（八丨）為主要材料之導電薄片或由鐵（Fe)_鎳 (Ni)等合金所構成之導電薄片等。 導電薄片的厚度若考慮後續的蝕刻處理時，則以約 ΙΟμΓΠ至300μιη為佳，但基本上3〇〇μιη以上或ι〇μιη以下 均可。如後述，若形成比導電薄片4〇的厚度淺的分隔溝9 即可。 其中，薄板狀導電薄片40係準備成以特定寬度例如 45丽捲成滾筒狀，而將其運送到後述各步驟亦可，或是準 備切割成特定大小之細長狀導電薄片40，而運送到後述各 步驟亦可。 ° 具體而e ，如第4圖（Β)所示，在細長狀導電薄片4〇 間隔並列4至5個形成有多數電路裝置部45之方塊42。 各方塊42間設有隙縫43，可吸收在成型步料因加熱處 T而產生之導電薄片40的應力。且在導電薄片40上下周 :以4寸疋間隔设有索引孔（丨以以h〇iy料，使用於各步驟之 疋位。接著，形成導電圖案。 314863 14 200405779 首先，如第5圖所示，在導電 餘刻光罩）PR，且以使除了成㈣ ^形成光阻齊U耐 導電薄片40露出的方式 。木1之區域之外的 一―。接著，如第6\使(^_劑PR進行圖案化 口 V八J所不，伟導雷雀 擇性進行姓刻。在此，導電圖 使¥电缚片40選 之晶片鮮塾u及接合塾12 1形成各電路袭… 右/照第6圖(A)’在形成有溝道Μ及分隔溝9… 有先阻劑之開口部。然後’形成有溝道14之處的： 度會形成地比形成有分隔溝9 。見 一 4办电时 之慝的見度為窄。具體而 …亥見度將形成不到一半。由於藉由㈣去除導電薄片 4〇係以寺方性進行’因此藉由上述將對應溝道μ的光阻 ^開口部形成較窄的方式’可將溝道14之深度形成地比分 溝9為淺。其中，上述#刻步驟可藉由將導電薄片⑽ 浸潰在敍刻液之方式進行。 第6圖（Β)中表不形成晶片銲墊11及接合墊12之導電 圖案51 °本圖係與第4圖（Β)所示之1個方塊42放大者相 對應。1個陰影線部分料丨個電路裝置部45，丨個方塊 42中以2列2行之矩陣（matrix)狀排列多數個電路裝置部 45，在每個電路裝置部45各設有相同的導電圖案51。各 方塊的周邊設有框形圖案46，與其略微間隔而在其内側設 有刀寺之疋位5己號4 7。框形圖案4 6係使用於與成型模 具肷合％ ’且導電薄片40之背面於蝕刻後具有補強絕緣性 樹脂16之作用。此外，於各電路裝置部中，形成在晶片銲 墊11上下兩側之接合墊12係與晶片銲墊11 一體化，而且 314863 15 200405779 兩者亦以電性方式相連接。 如第7圖所示’本發明之第2步驟係透過鲜材μ將 半導體元件13固接在各電路裝置部45之晶片銲塾心 參照第7圖（A)’透過銲材19將半導體元件i3安裝在 晶片鲜塾u。在此，銲材19係使用鲜錫或銀（Ag)膠等 電性膠漿。在本步驟中，因為銲# 19係呈溶融狀態，因此， 藉由將半導體元件13載置於銲材19上部，銲材19會因半 導體元件1 3的重量等而擴散到 ^ 忙政到周圍。在此，由於在晶片銲 塾η周邊部以環繞載置有半導體元件13之區域的方切 成溝道14,因此擴散的銲材19並不會從晶片銲墊u流 出。已到達溝道14之銲材19由於合 、θ ^成流入溝道1 4之形 式，因此溝道14係發揮作為阻 $ + 止鲜錫流出之阻止區域的功 月匕。再者，亦可使用絕緣性樹 片銲墊u。 卞月曰將h體凡件u安裝在晶 如第8圖所示，本發明之第3步驟係對半導體元件Η 和預期的接合墊12進行打線接合。 具體而言，將安裝在各電路裝置部之半導體元件13 的電極和預期的接合墊12 ^rba11 K 扪用猎由熱壓接進行之球形接 口（ball b〇ndlng)及藉由超音 h〇nd\n〇\ ^ ^ 仃之楔形接合（wedge bonchng)而總括進行打線接合。 g 如第9圖所示，本發明之第4 | 覆半導體元件13 ,且埴奋〜係以絕緣性樹脂包 且八充在S隔溝9及溝 共同成型。 久4迢14之方式而 如第9圖（Α)所示，在本| ν驟中’絕緣性樹脂丨6完全 314863 16 200405779 地匕後半導體元件丨3、複數個晶片銲墊11及接合墊1 2， 刀隔溝9及溝道丨4中填充有絕緣性樹脂丨6，且與分隔溝9 甘入a而強固地結合。然後，藉由絕緣性樹脂1 6支撐晶片銲 墊11及接合塾12。 、且在本步驟中，可藉由轉注成型法（transfer m〇id)、射 成型法（injection mold)或膠埋法（p〇uing)而實現。以 树月曰材料❿言，環氧樹脂等熱硬化性樹脂可藉由轉注成型 法而實現，聚醯亞胺樹脂（polyimide resin)、聚苯硫醚（p〇iyThe surface ^. Because / prevent the material 19 from the fresh pad U 2 can prevent the solder pads from causing each other due to the outflow of the solder contact 2 ° can make the wafer pads u can be installed. Moreover, the "Semiconductor" of the "M" Gongwen I on the wafer pad 11 is substantially the same as the semi-conductor 13 on the wafer pad 11. In addition, in the formula r, the chip pad 11 and the bonding pad 12 are close to each other, and the circuit device 10 can be reduced. The above is achieved by using the surface of the wafer material Γ " size. Furthermore, if the grooves 14 are formed on the surface of u, ^^, the area where the wafer pads = the edge resin 16 contact increases, so the adhesion between the wafer zinc pads 11 and the insulating resin 16 can be increased. Referring to Fig. 3, the circuit configuration iOA of another form will be described. Fig. 3 (A cross-sectional view of the circuit device 1GA, Fig. 3 is a cross-sectional view of χ_χ = of Fig. 3). The circuit device 1GA has a structure substantially the same as that of the circuit device 10 described in Fig. 1. The area surrounded by the wafer bond 14 on the surface is formed with a trench 14A in a grid pattern. The trench 14 is used to prevent the solder 19 used to fix the semiconductor element 13 / the zinc pad 1 It is installed on the two sides of the wafer pad 11 for the purpose of outflowing the surface. Here, the channel 1 4 A formed by forming a groove Y in a grid shape in the area surrounded by the channel 14 also has It has the same d surface and shape as the channel 14. In this way, by forming the channel 14 in a grid pattern, a larger amount of solder 19 can be stored in the channel 14, so the solder 19 can be prevented from passing from the wafer 1 to The surface of the pad 11 flows out. Furthermore, since the area where the wafer pads 11 and 12 314863 insulating resin 16 are in contact with each other can be selected to be intimately connected with the insulating resin 11 *. Next, a description will be given of a mechanical supply point for supplying welding materials such as a dispenser 14. The surface of the dispenser π may be used, but The batching machine can supply H19 ㈣ fixed on the wafer fresh pad. Therefore, the smallest coating of the batching machine _ 疋 An wear than in the Ribbi than the semiconductor component 13 female watch in the Japanese-Japanese film fresh pad ii (welding material) () 4 Leng Yue 孰 1] When there are many wardiers, the welding material 19 may have an outflow on the surface of the fresh pad 11 to prevent the welding material 19 from flowing out. Therefore, the channel 14 is incorrectly installed, ( The second embodiment of the method for manufacturing the circuit device 10 will be described in the present embodiment. The circuit device 10 will be described in terms of the shape energy of the circuit device. The 2: T 4 · clothing method. The circuit device 10. That is, the step of preparing the conductive sheet 40; forming a plurality of constituent grooves 9 at a shallow depth 9; > The thickness of the circuit device portion 45 is greater than its thickness. A step of forming a trench 14 shallower than the separation trench 9 on the n-pad dry pad U in a manner that the pad 11 and the bonding pad 12 are simultaneously attached to the region of the semiconductor element 13 that is intended to be fixed; Through soldering, the semi-component element 13 depends on the wafer MEMS element 13 and the expected bonding pad 12; #I (Wire; ::: v The method of filling in the separation trenches 9 and the trenches "combined = steps"; removing the back surface of the conductive sheet 40 to expose the insulating resin 16; and 'separating the electrical resins by cutting the insulating resin 16: =]. The steps are described below. Refer to Figures 4 to 10 of the steps of the present invention. 314863 13 200405779 As shown in Figures 4 to 6, the i step of the present invention is to prepare a conductive sheet 40 and form the conductive sheet 40. The wafer grooves 9 and the bonding pads 12 constituting the plurality of circuit device portions 45 are formed to be shallower than the separation grooves 9 having a thickness smaller than the thickness of the trenches 9 and the wafer pads 1 are formed to surround the area of the semiconductor element 13 to be fixedly bonded. 1 forms a trench 14 shallower than the separation trench 9. In this step, first, a sheet-shaped conductive sheet 40 as shown in FIG. 4 (A) is prepared. The conductive sheet 40 is a material selected by considering the adhesion, bonding, and electroplating properties of the welding material. The material is a conductive sheet with copper (Cu) as the main material, a conductive sheet with aluminum (铝 丨) as the main material, or Conductive flakes made of alloys such as iron (Fe) _nickel (Ni). In consideration of the subsequent etching treatment, the thickness of the conductive sheet is preferably about 10 μΓ˜300 μιη, but basically it can be more than 300 μιη or less than ι〇μιη. As will be described later, it is only necessary to form the separation groove 9 which is shallower than the thickness of the conductive sheet 40. Among them, the thin plate-shaped conductive sheet 40 is prepared to be rolled into a roll with a specific width, for example, 45 mm, and it may be transported to the steps described later, or it may be cut into the elongated conductive sheet 40 of a specific size and transported to the later. Each step is also possible. ° Specifically, as shown in FIG. 4 (B), 4 to 5 blocks 42 having a plurality of circuit device portions 45 are arranged in parallel at an interval of 40 to the elongated conductive sheet 40. A gap 43 is provided between each block 42 to absorb the stress of the conductive sheet 40 generated during the molding step due to the heating place T. And on the upper and lower circumferences of the conductive sheet 40: index holes are provided at intervals of 4 inches (the material used in each step is used for each step. Then, a conductive pattern is formed. 314863 14 200405779 First, as shown in FIG. 5 It is shown that the photoresist is etched on the conductive surface, and the resistive conductive sheet 40 is exposed except that a photoresist is formed. One outside the area of wood 1. Then, as described in Section 6 of the example, the patterning port V8J is not used, and the lead guide is selectively engraved with a surname. Here, the conductive pattern makes the wafer selected by the electric binding sheet 40 and Bonding 塾 12 1 to form each circuit ... Right / according to Figure 6 (A) 'where the trench M and the separation trench 9 are formed ... the opening where the resist is formed first. Then, where the trench 14 is formed: degrees It will form a ground than the formation of the separation trench 9. See the 4 when the electricity is running, the visibility is narrow. Specifically, ... the visibility will be less than half. Because the conductive thin film is removed by the 4O, it is based on the square. Performing the method of forming a narrower opening of the photoresist corresponding to the channel μ through the above-mentioned method can make the depth of the channel 14 shallower than that of the dividing groove 9. Among them, the above-mentioned #etching step can be performed by forming a conductive sheet ⑽ Immersion is performed in the etch solution. Figure 6 (B) shows the conductive pattern of the wafer pads 11 and bonding pads. 51 ° This figure is a block shown in Figure 4 (B) Corresponds to 42 enlargement. One shaded part is a circuit device part 45, and a plurality of circuit device parts are arranged in a matrix of two columns and two rows in a square 42 45. Each circuit device portion 45 is provided with the same conductive pattern 51. A frame-shaped pattern 46 is provided around each block, and a small space 5 is provided on the inner side of each block. The shape pattern 4 6 is used in combination with the molding die, and the back surface of the conductive sheet 40 has the effect of reinforcing the insulating resin 16 after etching. In addition, in each circuit device portion, it is formed on the upper and lower sides of the wafer pad 11. The bonding pad 12 is integrated with the wafer pad 11, and the 314863 15 200405779 are also electrically connected. As shown in FIG. 7 'the second step of the present invention is to fix the semiconductor element 13 through the fresh material μ. The soldering core of the wafer connected to each circuit device portion 45 is referred to FIG. 7 (A). The semiconductor element i3 is mounted on the wafer through the solder 19. Here, the solder 19 is made of fresh tin or silver (Ag). In this step, because the solder # 19 is in a molten state, by placing the semiconductor element 13 on the upper portion of the solder 19, the solder 19 is affected by the weight of the semiconductor element 13, etc. Spread to ^ busy politics to the surrounding. Here, since the The channel 14 is cut around the area where the semiconductor element 13 is placed, so that the spread solder 19 does not flow out from the wafer pad u. The solder 19 that has reached the channel 14 is The form of flowing into the channel 14 is, therefore, the channel 14 is used as a blocking area to prevent the outflow of fresh tin. Also, an insulating tree pad u can be used. Where the pieces u are mounted on the wafer as shown in FIG. 8, the third step of the present invention is wire bonding of the semiconductor element Η and the intended bonding pad 12. Specifically, the semiconductor element 13 mounted on each circuit device portion The electrode and the intended bonding pad 12 ^ rba11 K 扪 ball interface (ball b〇ndlng) by thermocompression bonding and by wedge bonchng of the supersonic h〇nd \ n〇 \ ^ 仃Collect wire bonding together. g As shown in FIG. 9, the fourth semiconductor-covered semiconductor device 13 of the present invention is co-molded with an insulating resin package and eight fillings in the S partition groove 9 and the groove. As shown in FIG. 9 (A) for a long time from 4 to 14, as shown in FIG. 9 (A), the insulating resin in this step | 6 complete 314863 16 200405779 after the ground semiconductor element 3, a plurality of wafer pads 11 and bonding pads 1 2. The insulating trench 9 and the trench 9 and the trench 4 are filled with an insulating resin 6 and are firmly connected to the trench 9 through a. Then, the wafer pad 11 and the bonding pad 12 are supported by the insulating resin 16. And, in this step, it can be realized by a transfer molding method (injection molding method), or an injection molding method (pouring). In terms of materials, Shuyue said that thermosetting resins such as epoxy resin can be achieved by injection molding, polyimide resin, polyphenylene sulfide (p〇iy

Phenylene sulfide)等熱可塑性樹脂可藉由射出成型法而實 丹有，在本步 H戏射出成型诗 T ’弟9圖（B)所示，各方塊係將電路裝置部收容在^ 共通的成型模具中，而以丨個絕緣性樹脂“對每一方 同進行成型。因此，與f知之轉注成型法等般，將久 裝置部個別進行成型之方法相較， Π屯 脂量的目的。 Τ 了達成減少大量掏 本步驟之特徵為到包覆絕緣性樹脂16為止，Thermoplastic resins such as Phenylene sulfide) can be obtained by injection molding. In this step, the injection molding poem T 'brother 9 is shown in Figure 9 (B). Each block contains the circuit device part in a common molding. In the mold, each of the insulating resins is molded in the same way. Therefore, compared with the method of the injection molding method known by f, etc., the method of individually molding the long device is compared with the purpose of the amount of grease. Τ 了The feature of achieving a reduction in this step is that the insulating resin 16 is covered,

電圖案5丨之導電“則當作支持基板 传V 原本並不需要的支持基板來形成導電圖案，但I::用 中，作為支持基板之導電薄片4G係作為電極材料之Μ明 料。因此，具有在作業上可極力節省構成材 要材 可實現降低成本。 H，、£，且 而且由於分隔溝9形成地比導電薄片的 並未個別地分隔導電薄片4〇作為 、口此 兒圃茶51。因而其特 314863 17 200405779 200405779 徵為作為薄板狀 16進行成型時， 易。 導電薄片40以一體處理，且將絕緣性樹脂 運送到模具、安裝到模具的作業非常地容 +贫明之第 緣性樹脂為止。 北本步驟係以化學方式及/或物理方式去除導電薄片4〇 刀隔作為‘電圖案51。藉由研磨、研削、蝕刻、 田十之金屬蒸發等來實施本步驟。 實驗中將導電薄片40全面濕式_(wetete :二=9露出絕緣性樹脂16。在第9圖(A)中以虛線 係形：：Γ面。其結果係分隔形成導電圖案51。該結果 亦即，埴//案51之背面露出在絕緣性樹脂16之構造。 51的表面 “9之絕緣性樹脂以面和導電圖案 的表面係形成實質上相一致之構造。 再者，進行導電圖案 b 圖所示之最蚁^ ^、 處理，例如獲得第1 需要:露出之導電圖案。，以成為電::， 16露出在背面本二=’將填充在分隔溝9之絕緣性樹脂 出在背面。- 在溝這14之絕緣性樹脂16並未露 置部IV二圖所示’本發明之第6步驟係對每-電” 緣性樹脂16藉由切割加以分隔。 破 本步驟中，以直命f斗 置放方式將方塊42吸附在切割裝置之 以切割刀49沿著各電路裝置…的切割線(: Ο Ά : 0*i'. 314863 】8 200405779 線）切割分隔溝 裝置。 之絶緣性樹脂1 6，而分隔成個別的電路 本步私中，切割刀49係以大致切開絕緣性樹脂1 6之 切削冰度進仃’從切割裝置取出方塊42後，以滾筒製作成 如巧克力塊即可。切㈣，減辨識在前述第i步驟中裝 設之各方塊的^位記號47，將其當作基準進行切割。眾所 週知切割係朝向縱向切割所有的切割線後，9〇度旋轉置放 口再按如檢向切割線7 〇進行切割。 [發明功效] 本舍明可達成如以下所示之效果。 第1，本發明中，以圍繞半導體元件13的方式在接合 墊11周邊部裝設溝道14，由於防止用以固接半導體元件 13之銲材19流出，因此可防止流出之銲材19造成導電圖 案彼此發生短路。 曰第2,由於可藉由溝道14防止銲材19流出，因此可 使晶2銲墊u和接合墊12接近，而可使全體裝置小型化。 第3，於安裝半導體元件丨3之步驟中，裝設在晶片銲 2周适。卩的溝道丨4發揮作為阻止銲材流出之阻止區域 的功能，可防止銲材19流出到外部而造成導電圖案彼此發 生短路。 [圖示簡單說明] 第1圖係說明本發明之電路裝置之俯視圖（Α)，剖視圖 (Β) 〇 第2圖係說明本發明之電路裝置之背面圖（a”剖視圖 314863 19 200405779 (B)。 (B)。 (A)， 圖。 (A) (A) (A) (A) 9 1卜 13 15、 17 第3圖係说明本發明之带 毛路裝置之剖祝圖（A)，俯視圖 第4圖係說明本發明之雷 电略裝置之製造方法的剖 俯視圖（B)。 弟5圖係說明本發明之+ a之電路袭置之製造方法 視圖 的剖視 第6圖係說明本發明之電 兒路裝置之製造方法的剖視圖 ，俯視圖（B)。 」仇口 第7圖係說明本發明之電 也路裝置之製造方法的 ，俯視圖（B)。 第8圖係說明本發明之電路裳置之製造方法 ，俯視圖（B)。 第9圖係說明本發明之電路裳置之製造方法 ，俯視圖（B)。 剖視圖 的剖視圖 的剖視圖 第1 〇圖係本發明之電路爿 笔n 峪破置之製造方法之俯視圖 弟11圖係說明習知之電 口 hH 路破置之剖視圖。 弟12圖係說明習知 笔路裴置之剖視圖。 分隔溝 69 晶片鲜塾 半導體元件 72 金屬細線 外部電極 10、 12、 14、 16 18 10A 電路裝置 12A、12B 接合墊 14A 溝道 絕緣性樹脂 光阻劑 3]4863 20 200405779 19 銲材 40、 60 導電薄片 42 方塊 43 隙縫 44 索引孔 45 電路裝置部 46 框形圖案 47 定位記號 49 切割刀 51 導電圖案 61 封裝型半導體裝置 62 半導體晶片 63 > 73 樹脂層 64 導線端子 65 玻璃環氧基板 66 CSP 67 第1電極 68 第2電極 70 第1背面電極 71 第2背面電極 CC 晶片電容為 CR 晶片電阻 PR 光阻劑 PS 印刷基板 T 電晶體晶片 TH 貫通孔 21 314863The conductive pattern of the electric pattern 5 丨 is regarded as a supporting substrate. V does not originally need a supporting substrate to form a conductive pattern, but I :: In use, the conductive sheet 4G serving as the supporting substrate is used as the M material for the electrode material. Therefore It can reduce the cost of construction materials and materials as much as possible in operation. H ,, £, and, because the separation groove 9 is formed more than the conductive sheet, the conductive sheet 40 is not individually separated as the mouth tea. 51. Therefore, its special feature is 314863 17 200405779 200405779. It is easy to mold as a thin plate 16. The conductive sheet 40 is integrally processed, and the operation of transporting the insulating resin to the mold and installing it into the mold is very good. This step is to chemically and / or physically remove the conductive foil 40 blades as the 'electric pattern 51. This step is performed by grinding, grinding, etching, metal evaporation of the field ten, etc. In the experiment will be The conductive sheet 40 is fully wet-type (wetete: 2 = 9, and the insulating resin 16 is exposed. In FIG. 9 (A), the dotted line is formed in the shape of the: Γ plane. As a result, the conductive pattern 51 is formed separately. As a result, the structure in which the back surface of the case 51 is exposed on the insulating resin 16. The surface of the "9" insulating resin has a substantially uniform structure with the surface and the surface of the conductive pattern. Furthermore, conductive is performed Pattern b shows the most ant ^^ treatment. For example, to obtain the first need: exposed conductive pattern. To become electric ::, 16 exposed on the back. This two = 'will be filled in the insulating resin filled in the separation trench 9. On the back side.-The insulating resin 16 in the trench 14 is not exposed. The second step of the present invention is shown in the second figure. The "sixth step of the present invention is for each-electric" edge resin 16 is separated by cutting. In this step The block 42 is adsorbed to the cutting device by a straight-line f bucket placement method, and the cutting knife 49 is along the cutting line of each circuit device (: Ο Ά: 0 * i '. 314863) 8 200405779 line) cutting the dividing groove device The insulating resin 16 is divided into individual circuits. In this step, the cutting blade 49 is made by cutting the ice of the insulating resin 16 approximately. After removing the block 42 from the cutting device, it is made by a roller. Just like a chocolate bar. Cut ㈣, minus recognition in the i step above The square mark 47 of each square installed in the center is used as a reference for cutting. It is well known that after cutting all cutting lines in the longitudinal direction, rotate the placement opening at 90 degrees and then cut the cutting line according to the direction of the cutting line 70. [Effect of the invention] The present invention can achieve the effects shown below. First, in the present invention, a channel 14 is provided around the bonding pad 11 so as to surround the semiconductor element 13 to prevent the semiconductor from being fixedly connected. The soldering material 19 of the element 13 flows out, so that the conductive material 19 flowing out can be prevented from causing a short circuit between the conductive patterns. Second, since the soldering material 19 can be prevented from flowing out by the channel 14, the bonding pad u and the bonding of the crystal 2 can be made. The proximity of the pad 12 allows miniaturization of the entire device. Third, in the step of mounting the semiconductor element 3, it is appropriate to mount the wafer on the wafer for 2 weeks. The trench 卩 4 functions as a blocking area for preventing the welding material from flowing out, and can prevent the welding material 19 from flowing out to the outside and cause the conductive patterns to short-circuit each other. [Brief description of the diagram] Figure 1 is a plan view (A) and a cross-sectional view (B) of the circuit device of the present invention. Figure 2 is a rear view (a "sectional view of the circuit device of the present invention 314863 19 200405779 (B). (B). (A), Figure. (A) (A) (A) (A) 9 1 bu 13 15, 17, Figure 3 is a cross-sectional view (A) illustrating the device with a hair path of the present invention, Plan view 4 is a cross-sectional plan view (B) illustrating a method for manufacturing a lightning circuit device according to the present invention. Figure 5 is a cross-sectional view illustrating a method for manufacturing a + a circuit arrangement according to the present invention. Section 6 is a view illustrating the present invention. A cross-sectional view of a method of manufacturing an electric circuit device, a plan view (B). "Figure 7 shows a method of manufacturing an electric circuit device of the present invention, a top view (B). Fig. 8 illustrates a circuit of the present invention. Top view (B) of a method for manufacturing a fabric. Figure 9 illustrates a method for manufacturing a fabric of a circuit according to the present invention, top view (B). Sectional view of a cross-sectional view. Figure 10 is a circuit of the present invention. The top view of the manufacturing method of the installation device. The figure 11 is a cross-sectional view illustrating the breakage of the hH road of the conventional electrical port. Figure 12 is a cross-sectional view illustrating the conventional pen circuit. Separation trench 69 Wafer semiconductor element 72 Thin metal wire external electrode 10, 12, 14, 16 18 10A Circuit device 12A, 12B Bonding pad 14A Channel insulation Resin Photoresist 3] 4863 20 200405779 19 Welding material 40, 60 Conductive sheet 42 Block 43 Slot 44 Index hole 45 Circuit device section 46 Frame pattern 47 Positioning mark 49 Cutting knife 51 Conductive pattern 61 Packaged semiconductor device 62 Semiconductor wafer 63 > 73 resin layer 64 wire terminal 65 glass epoxy substrate 66 CSP 67 first electrode 68 second electrode 70 first back electrode 71 second back electrode CC chip capacitance is CR chip resistance PR photoresist PS printed circuit board T transistor Wafer TH Through Hole 21 314863

Claims (1)

200405779 拾、申請專利範圍： 】· ~種電路裝置，其特徵為具有·· 致係形成舆透過銲材安裝之半導體元件大 接合墊，係設置成接近 ^. 乂银迎在刚述晶片銲墊； 溝這，係以®繞前述半導 晶月H 4时相成在前述 刀邊心且可防止前述銲材流出；以及 絕緣性樹脂，将彳φ治、+、 φ ^ Α曰曰片銲墊及前述接合墊之背 面露出，而封裝前 、接σ墊之月 體元件。 ι曰曰片杯塾、前述接合塾及前述半導 2.如申請專利範圍帛i項之 、， 成地比前述晶片銲塾之厚度淺放置其中’所述溝道形 3 ·如申請專利範圍第1項之泰 埴充右儿、+、 、电衣置，其中，前述溝道中 "兄有刖述絕緣性樹脂。 、得I T 4·如申請專利範圍帛i項之電路 骏置係1C晶片。 羞置其中，前述半導體 5·如申請專利範圍第i項之 元件係透過金屬細線而與預前述半導體 連接。 t月的則述導電圖案作電性 6· ^申請專利範圍第^之電路裝置， 銲錫或銀（Ag)膠。 /、 則述銲材係 7.如申請專利範圍第！項之電路 接著劑代替前述銲材。 衣，、中，使用絕緣性 如申晴專利範圍第1 d'4.7 -路裝置，其中，在環繞前述 314863 22 200405779 B曰 片鲜墊之前述溝道之區域中，再形成溝道。 9·如申明專利範圍第8項之電路裝置，其中，在 曰 y力曰4 u 、， 長繞別述 曰日、干 則述溝道之區域中，以格子狀形成、| 冤路衣置之製造方法，其特徵為具有： 準備導電薄片之步驟； f前述導電薄片形成比其厚度淺的分隔溝而形成 構成複數個電路梦晉# s 衣置口卩之日日片ί干墊及接合墊，同時 繞預定固接的丰莫，&处 > 广上 ^ ^ +導體兀件之區域的方式在前述晶片銲 墊形成比前述分隔溝淺的溝道之步驟； 在則述曰曰片銲墊透過銲材而固接半導體元件之步驟； 對前述半導體元件和預期之前述接合塾進行打線 接合之步驟； v以絕緣性樹脂包覆前述半導體元件且填充於前述 /刀隔溝及前述溝道 < 方式共同成型之步驟； 去除前述導電薄片之背面至露出前述絕緣性樹脂 為止之步驟；以及 藉由切割前述絕緣性樹脂之方式而分隔成各電路 裝置之步驟。 U·如申：專利範圍第10•項之電路裝置之製造方法，其 中，則述溝迢係形成地比前述晶片銲墊淺。 12·如申請專利範圍第10項之電路裝置之製造方法，其 中’ 4ίι述鮮材係焊錫或銀（A g)膠。 13_如申請專利範圍第10項之電路裳置之製造方法，其 中，使用絕緣性接著劑代替前述銲材。 S4S. 23 314863200405779 Scope of patent application:】 · ~ Circuit devices, which are characterized by having a large bonding pad for semiconductor components that are mounted through soldering materials and are arranged close to ^. 乂 银 迎 在 just mentioned wafer pads The groove is formed with ® around the semiconducting crystal moon H at 4 o'clock in the center of the knife edge and can prevent the welding material from flowing out; and an insulating resin that welds φφ, +, φ ^ A The back surfaces of the pads and the aforementioned bonding pads are exposed, and before the packaging, the moon body components connected to the σ pads are exposed. ι said tablet cup 前述, the aforementioned bonding 塾 and the aforementioned semiconductor 2. If the scope of the patent application (i), the ground is shallower than the thickness of the aforementioned wafer welding 放置 placed where the said channel shape 3 · as in the scope of the patent application The first item of the battery is the right, +,, and electric clothes, in which the above-mentioned channel " brother has an insulating resin described. ， I T 4 · If the scope of the patent application item 帛 i, the circuit is a 1C chip. Disregarding it, the aforementioned semiconductor 5. The element according to item i of the patent application range is connected to the aforementioned semiconductor through a thin metal wire. The conductive pattern for the month is described as electrically conductive. The circuit device in the scope of the patent application, solder or silver (Ag) glue. / 、 The welding materials are described. 7. If the scope of patent application is the first! The circuit of this item replaces the foregoing solder with a flux. Insulation, use, insulation, such as Shen Qing patent scope No. 1 d'4.7-circuit device, wherein, in the area surrounding the aforementioned channel of the aforementioned 314863 22 200405779 B, a channel is further formed. 9 · As stated in the patent claim No. 8 of the circuit device, in the area of y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, u The manufacturing method is characterized by having the steps of preparing a conductive sheet; f the conductive sheet forms a separation trench which is shallower than its thickness to form a plurality of circuits. Mengjin # s 衣 置 口 卩 日 日 片 Dry pad and bonding The method of forming a trench shallower than the aforementioned separation groove in the aforementioned wafer pad by way of & place > widening the area of the conductor element at the same time around the intended fixed connection. The step of bonding the semiconductor element to the semiconductor element through the soldering material; the step of wire bonding the semiconductor element and the expected bonding pad; v The semiconductor element is covered with an insulating resin and filled in the / knife groove and the foregoing Channel co-forming step; removing the back surface of the conductive sheet until the insulating resin is exposed; and separating the circuit pack by cutting the insulating resin The step. U · Rushen: The method for manufacturing a circuit device according to item 10 of the patent, wherein the trench is formed shallower than the aforementioned wafer pad. 12. The method for manufacturing a circuit device according to item 10 of the scope of application, wherein the fresh material is solder or silver (Ag) glue. 13_ The method for manufacturing a circuit board according to item 10 of the application, wherein an insulating adhesive is used in place of the foregoing soldering material. S4S. 23 314863
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JP4093818B2 (en) 2008-06-04
CN1501490A (en) 2004-06-02

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