TWI222844B - Printed circuit board and its manufacturing method - Google Patents

Printed circuit board and its manufacturing method Download PDF

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Publication number
TWI222844B
TWI222844B TW89110764A TW89110764A TWI222844B TW I222844 B TWI222844 B TW I222844B TW 89110764 A TW89110764 A TW 89110764A TW 89110764 A TW89110764 A TW 89110764A TW I222844 B TWI222844 B TW I222844B
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Taiwan
Prior art keywords
foil
printed circuit
circuit board
forming
board
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TW89110764A
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Chinese (zh)
Inventor
Kinji Saijo
Kazuo Yoshida
Hiroaki Okamoto
Shinji Ohsawa
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Toyo Kohan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

By using a clad technique and adopting a bare chip mount system using an anisotropic conductive adhesive in a connection system of electronic parts, a solder reflow process becomes unnecessary. Thus, there is provided a process for producing a clad plate for printed wiring board, an IC card and a printed wiring substrate, which makes it possible to use an inexpensive material such as PET and can produce the printed wiring board at low cost. Therefore, the printed wiring board forms a clad plate (31) for the printed wiring board, which has a laminated structure, by pressure-bonding a bump forming foil (13) made of a copper foil material to one side face of a circuit forming foil (11) made of the copper foil material through an etching stop layer (12) made of a nickel foil material or a nickel plating, and a resin film (17) such as PET is bonded to the other side face of the clad plate (31) for the printed wiring board.

Description

1222844 曰1222844 said

號 891]D7fU 五、發明說明（1) 的技 本發明係有關可適用於1(:卡（積 板、1C卡及印刷電路基板之製造方法 ）之印刷電路 !用技_避 近年、 小型化且電 密度化乃正 例如IC 可撓性印刷 裝密度高且 佳。 裸晶片 然而近年來 發著。此為 表面上，採 電子組件5 4 連接之可靠 上有必要形 隨著半 子機器 被要求 卡，在 電路板 可對應 安裝方 採用異 如第10 用已含 之方法 性，於 成*** V体I置之咼功能化、多腳（p i J倒輕化、薄型化，半導体裝置之高 小；化、高密度化、尤其被要求薄型化的 之情形。電子組件（IC晶片）之；壯化的 於薄型化之裸晶片（bare chip)安裝衣為以安 式，雖以利用穿線或焊接的方式為主法 向性導電接著劑之裸晶片㈣彳式正；開 圖所示，於具有電路50之印刷電路板51之 有導電粒子52之接著樹脂53，連接並安裝 。因此，在此種裸晶片安裝方式，為提^ 印刷電路板51上或電子組件54之電極部= 物（突起，bump)。 發明欲解決的課題 ^而利用上述的裸晶片安裝方式之電子組件5 4的安 哀’仍有下述應予解決的課題。 亦即向來***物5 5因係予成形於電子組件5 4側，故No. 891] D7fU V. Description of the invention (1) The present invention relates to printed circuits that can be applied to 1 (: cards (manufacturable boards, 1C cards, and printed circuit board manufacturing methods)! Use technology _ avoid recent years, miniaturization And the density is reduced. For example, the IC flexible printed package has high density and good quality. However, bare chips have been issued in recent years. This is the surface, and the use of electronic components 5 4 is necessary for reliable connection. The card can be used on the circuit board according to the method of installation. It can be used in the same way as the tenth. It is functional and multi-pin (pi J is lighter and thinner), and the height of the semiconductor device is high. ; Thin, high-density, especially when thinness is required. Electronic components (IC chips); hardened thin chip bare chip (bare chip) installation clothing is in the safety type, although the use of threading or welding The method is based on a bare wafer of a normal conductive adhesive. The drawing shows that the resin 53 with conductive particles 52 on the printed circuit board 51 with the circuit 50 is connected and installed. Therefore, here A bare chip mounting method, The electrode part on the printed circuit board 51 or the electronic component 54 is a bump (bump). The problem to be solved by the invention ^ The safety of the electronic component 54 using the bare chip mounting method described above still has the following application That is, since the conventional bump 5 5 is formed on the side of the electronic component 5 4,

1222844 五、發明說明（2) 其形成方法係蒸鑛後大多採用電鍍，在降低製造成本方面 係有困難的。 又’如日本特開平10 —：! 7330 5號公報所揭示，在電子 組件5 4之連接上採用焊接法的情形、回流焊接（f 1 soldering)時印刷電路板51因會曝露於高熱中，故使用耐 熱性較低的廉價材料即有困難。 >本發明係欲解決此種課題而完成者，其目的在於提供 採用包層技術、同時於與電子組件間之連接方式上以採用 已，=異向性導電接著劑的裸晶片安裝方式，由於不需要 回流焊接步驟，故可使用PET等的廉價材料，可價廉的製 造出印刷電路板之印刷電路板用包層板，κ卡及衣 基板之製造方法。 解決課題而採的丰恐 申請專 箔材或鑛鎳 箔材而成的 用箔材予以 成***物為 申請專 箔材而成的 材之任一種 刻至成可形 申請專 利範圍第1項之印刷電路板，係以藉由介經鎳 而成的停止蝕刻（etching stop)層，於由鋼 $路形成箔上，對由銅箔材而成的形成***物 冷軋包層而形成的層合構造經予蝕刻至成可形 特徵。 7 1乾圍第2項之印刷電路板，係以藉由將由鋼 形成***物用箔材冷軋包層至由銅箔材或鋁箔 而成的電路形成箔上而形成的層合構造經 成***物為特徵。 利範圍第3項之印刷電路板，係以介經鎳箔材1222844 V. Description of the invention (2) Most of its formation method is electroplating after ore evaporation, which is difficult to reduce the manufacturing cost. Also, as disclosed in Japanese Patent Application Laid-Open No. 10 :: 7330 5, when the soldering method is used for the connection of the electronic component 54, the printed circuit board 51 is exposed to high heat during reflow soldering (f 1 soldering). Therefore, it is difficult to use inexpensive materials with low heat resistance. > The present invention has been completed to solve such a problem, and an object thereof is to provide a bare chip mounting method using a cladding technology and a connection method with an electronic component using an existing anisotropic conductive adhesive, Since a reflow soldering step is not required, inexpensive materials such as PET can be used, and a printed circuit board clad board, a kappa card, and a clothing substrate manufacturing method can be manufactured at low cost. To solve the problem, apply the special foil or mineral nickel foil to apply the foil to form a bump. Any of the materials applied for the special foil is engraved to form 1 of the patent application scope. The printed circuit board is a laminate formed by cold-rolling a cladding layer formed of a copper foil on a foil formed of steel by a stopping stop layer made of nickel through nickel. The structure is pre-etched to form features. 7 1 The printed circuit board of item 2 is made of a laminated structure formed by cold-rolling a foil for forming bumps made of steel onto a circuit forming foil made of copper foil or aluminum foil. The bulge is characteristic. The printed circuit board of item 3 of the profit scope is made of nickel foil

1222844 日 ^M^8911Q764 i、發明說明（3) =鍍，而成的停止蝕刻層，於 ;::Γ上，採用冷乾包層技術壓、著由:ί:1 路形成ί ***物用f “才，形成具有層 Τ :材而成的形成 層板，於前述印刷電路板包層板 ：：路板用冷軋包 膜而成為特徵。 曰极之另側面上接合樹脂薄 或紹以於由銀溶材 II包層技術並屢；= 編之-倒面上，灣 A目女Μ人t 銅泊材而成的形成***物用笤& ^ 成具有層合構造之印刷電路板用包層板，於！才，开v 板包層板之另一側面上拉人 、則述印刷電路 _利範圍第面5上項接二 項或第4項之印刷電路板而成，於前述樹以 具備傳達資訊用凹凸花紋為特徵。 、之表面上 申請專利範圍第6項之印刷電路板之 (1 )介經鎳箔材或鍍鎳而成的停止蝕刻層由::二 而成的形成***物用箔材上予w Α 於甶銅泊材 電路脚，並形成印刷電：：二 =銅編成的 ⑴於前述印刷電路板用包層板之 樹脂薄膜、 乂，白例上貼附 (3 )於前述印刷電路板用包層板之形成***物 之***物形成面上塗布第一光阻（resist)、 /白材側 (4) 對形成前述形成***物用箱材 第 進行選擇餘刻，形成***物、自材'木用第-1虫刻液並 (5) 由前述選擇餘刻後之前述***物去除第一光阻後， 8911〇764-91033TYJP-Ptc 第9頁 1222844 修正 曰 案號8min7w 五、發明說明（4) —— ___ 述電路形成箔上的停止蝕電 布第二光阻、 〜’成面上塗 ^6 )、對形成前述導体電路之箱材，採用第二蝕1222844 日 ^ M ^ 8911Q764 i. Description of the invention (3) = plating to stop the etched layer on; :: Γ, using cold-dried cladding technology to press and direct the formation of: ί: 1 f "It is formed by forming a laminated board with a layer of T: material, which is characterized by the aforementioned cold-rolled cladding of printed circuit board clad board: road board. It is said that a thin resin is bonded to the other side of the electrode In the silver-clad material II cladding technology is repeated; = Knitting-Inverted, Bay A female M person t copper copper material for the formation of bumps 笤 & ^ For the printed circuit board with a laminated structure Cladding board, only before, open the other side of the v board clad board, then the printed circuit _ profit range of the 5th item above the 2nd or 4th printed circuit board, as described above The tree is characterized by a concave-convex pattern for conveying information. The surface of the (1) printed circuit board for which the patent scope of the patent application is applied on the surface is (1) Stop etching layer formed by nickel foil or nickel plating. The foil for forming the bump is provided with w Α on the copper foot of the copper circuit board, and a printed circuit is formed: 2: = copper braided on the aforementioned printed circuit board The resin film and the cladding of the clad board are attached (3) to the above-mentioned bump-forming surface of the clad board for the printed circuit board, and a first photoresist (resist) and a white material side ( 4) Select the remaining time for forming the box material for forming the bump, to form the bump, the first wood -1 insect engraving solution and (5) remove the first light from the bump after the selection After the resistance, 8911〇764-91033TYJP-Ptc Page 9 1222844 Amended case number 8min7w V. Description of the invention (4) —— ___ The photoresist on the circuit forming foil is stopped. The second photoresistor is coated on the surface ^ 6) For the box material forming the aforementioned conductor circuit, a second etching is used

x並形成導体電路、其後去除前述第二光阻、x M )採用異向性導電接著劑並安裝子組件 為特徵。 申請專利範圍第7項之印刷電路板之製造方 i由Λ由，猪材，成的形成***物用驗予以冷：： 刷電路板用包層板、 而成的電料以並形成印 (2 )於前述印刷電路板用包層板 樹脂薄膜、 θ販之電路形成泊側上貼附 (3 )於前述印刷電路板用包層板 之***物形成面上塗布第一光阻、y 用箔材側 (4 )對形成前述形成***物用箔材 進行選擇蝕刻，形成***物、 抹用弟一蝕刻液並 (5)由前述選擇蝕刻後之前述*** 於前述電路形成结上的導体電路^去除苐一光阻後， (㈠對形成前述導体電路之落材塗布第二光阻、 蝕刻並形成導体電路，其後去除木弟一蝕刻液予以 (η採用異向性導電接著劑並’雷二光阻、 為特徵。 文衣電子組件x and forming a conductor circuit, and thereafter removing the aforementioned second photoresistor, x M) using an anisotropic conductive adhesive and installing a sub-assembly. The printed circuit board manufacturer i in the scope of patent application No. 7 is made of Λ, pig wood, and the bumps formed by the test are cold: brush the circuit board with a clad board, and the electrical material to form a printed board ( 2) Attach the resin film of the clad board for the printed circuit board and the circuit forming side of the θ vendor (3) Apply the first photoresist on the raised surface of the clad board for the printed circuit board. The foil side (4) selectively etches the foil for forming the bumps to form bumps, wipes with an etchant, and (5) conducts the conductor circuits on the circuit forming junctions from the bumps after the selective etching. ^ After removing the first photoresist, (㈠ apply a second photoresist to the material forming the aforementioned conductor circuit, etch and form a conductor circuit, and then remove the woody etch solution (η using an anisotropic conductive adhesive and ' Thunder II photoresistor is featured. Wenyi electronic components

修正 曰 8911Q7fid 五、發明說明（5) 至於液：宜為採用硫酸+過氧化氫。又 液或氯化銅液，對二13::、銅箔材之情形採用氯化鐵 情形則採用氫氧化鈉或氫氧：：：採用破酸鐵，銘箱材之 發明㈣所示的—實施形態’並具体的說明本 之構:先參Si?本圖發明軸 銀箔材：銘箔：)由：π° _厚度之銅箔材(亦可採用 成的停+砧亡丨^。 何及具有0· 5〜3 厚度之鍍鎳而 成的$止餘刻層12，載置著由具有1〇〜丨 材而成的***物1 3。此***你·| q尨上 又 / 綱予形成。於***：藉“刻銅 導体晶片U。X，半導体曰子組件之-例的半 路渺忐唁1 1 β少、曾4 本曰曰片1 4係猎由含有經予填充於電 ，/成 >自11及丰ν体兀件丨3之間的導電粒子1 5a之里向性 ¥電接著劑15，使連接至電路形成川 ，、 路形成箔11之導体電路形成部上嗖置 矛面上又於電 内填充著異向性導電接著再1者：，：於f 口16 另一側面内，貼附有10〜100 PET厂路形成泊11之 酉旨）膜17。 _<ΡΕΤ (聚對苯二甲酸乙二 於上述的印刷電路板，係構成著電路 蝕刻層1 2、***物1 3、與具有由包声 y成v自11、知止 刷電路板用包層⑽。層而成的層合構造之印Amendment 8911Q7fid V. Description of the invention (5) As for the liquid: sulfuric acid + hydrogen peroxide should be used. Liquid or copper chloride solution. For the case of 2:13 :, copper foil, use sodium chloride or hydroxide :: use iron-breaking iron, as shown in the invention of box materials— Implementation mode 'and concrete description of the structure of this: first refer to Si? In this figure, the shaft silver foil of the present invention: Ming foil :) from: π ° _ thickness of copper foil (also can be used to stop + anvil die ^^. Ho And nickel-plated layer 12 made of nickel plated with a thickness of 0.5 to 3, on which a bulge 1 made of 10 to 丨 is placed. This bulge you || q 尨 上 又 / 纲Pre-formed. Yu uplift: By "engraved copper conductor wafer U.X, semi-conducting semi-conductor sub-assembly example-1 1 β is less, Zeng 4 is said to be a film 1 4 series is made by containing pre-filled electricity / 成> Since the conductive particles 1 5a between 11 and the ν ν body element 丨 3 inwardly ¥ electric adhesive 15 to connect to the circuit forming channel, the circuit forming foil 11 conductor circuit forming portion On the surface of the spear, anisotropic conductivity is filled in the electricity, and then one of the following is added: On the other side of the f-port 16, a 10 to 100 PET factory road is formed to attach the film 17). _ < ΡΕΤ ( Polyethylene terephthalate on the above-mentioned printed circuit board is composed of a circuit etching layer 1 2, a bump 1 3, and a cladding layer for a printed circuit board having a sound layer y to v from 11, and a brush stopper for the circuit board. Stamp of laminated structure

8911〇764-9l〇33TYJP.ptc 12228448911〇764-9l〇33TYJP.ptc 1222844

案號 891107R4 五、發明說明（6) PET薄膜1 7係以未拉伸薄漠、拉伸 可，惟對使用拉伸薄膜之情形，因可被視作\一種均 歷引起的收縮，故以採用未拉伸薄膜。广後之熱經 • PET薄膜17，其本身係予作成白色薄腹f ，並施加印刷至其表面上，亦可事先查w 1 e卜 貧訊。又、亦可使用pBT等盆他 曰寫者條碼等 又，亦可採用聚碳酸醋、聚酿亞=、系聚專氣膜乙取/阳薄膜。 丙烯等。 祆虱乙烯、耐綸、聚 PET薄膜17及印刷電路板用包層板以 :刻步驟、以提高m薄膜17及印刷用；= 界面的耐溶解性之目的’採用底層塗料】9予以接曰合板二之 且，上述的印刷電路板18係可較 ^。 際’如第8圖…於其PET薄膜17之表面上：=成= 數的突起35而成的資訊傳達用凹凸花紋36。 /成由夕 其次，就上述的印刷電路板1〇之製造方法予以 < 1 >百先、在製造印刷電路板之 (# ^10^50,m) 停止蝕刻層1 2之鍍鎳層2 1，製造鍍鎳銅箔材22。也σ ，、'、 <2 >將鍍鎳銅箔材22捲繞於第9圖所示的包声 裝置之回繞捲軸23上。又將成為***：以 二回繞卿上。由回繞捲轴23,同時回繞; 22及銅箱材24，將其一部分捲繞於韻刻室突：二：Case No. 891107R4 V. Description of the invention (6) PET film 17 is unstretched and stretchable, but the use of stretched film can be regarded as a kind of shrinkage caused by calendar. Use unstretched film. Guanghou's thermal history • The PET film 17 itself is made into a thin white belly f and printed on its surface. It can also be checked in advance. In addition, you can also use pBT and other writer barcodes, etc. Also, you can use polycarbonate, poly brewing sub- =, poly-gas film Yi take / positive film. Acrylic and so on. Tick vinyl, nylon, polyPET film 17 and clad board for printed circuit board: engraving steps to improve m film 17 and printing; = the purpose of the interface's resistance to dissolution 'using primers] 9 Moreover, the printed circuit board 18 described above can be compared. As shown in FIG. 8 on the surface of the PET film 17: a convex-concave pattern 36 for information transmission formed by protrusions 35 of equal number. / Second, next, the above-mentioned manufacturing method of the printed circuit board 10 is given < 1 > Baixian, the (# ^ 10 ^ 50, m) nickel plating layer for stopping the etching of the printed circuit board 12 2 1. The nickel-plated copper foil 22 is manufactured. Also, σ ,, ', < 2 > The nickel-plated copper foil 22 is wound around the winding reel 23 of the sound-absorbing device shown in FIG. Will again become a bulge: Yi Er round the Qing. By rewinding the reel 23, rewinding at the same time; 22 and copper box material 24, winding a part of it around the rhyme chamber protrusion: two:

1222844 曰 修正 〇〇llUib4 年 月 五、發明說明（7) 此時，活性化處理係如本申請人先前於日本特開平 卜224 i 84號公報所揭示，係⑴於! χ〗卜】χ】$ =千 = :: = 2中，(2)以具有接合面之鑛鎳銅荡材 =予其St請之面一下，⑷心 軋，^ ί有利^ ^设於真空槽29内之輕札單位30予以冷 捲取親輪t構造之印刷電路板用包層板材…捲取於 18a裁'Hi如第1圖所示’將印刷電路板用包層板材 -1 9 (東洋、％ w 1 =大小後，如第2圖所示，採用底層塗料 〆/ w股份有限公司製造，Finishers，丁491一 材彳8雷白势上。具体而言，首先於印刷電路板用包層板 m之】Ϊ 1 Ϊ形成箱側及P E T薄膜1 7之對應面上以1㈣〜2 " 塗布底層塗料19後，將塗有底層塗料之包層 涂古广1炎、〇 C溫度加熱30秒，其後於貼附pET薄膜17至 、，I:主料之包層材18&後，通過加壓輥輪（5〜15kg/cm )亚進行層合處理。 <4 >如第3圖所示，塗布第一光阻“於印刷電路板用 已曰板之***物形成箔側的***物形成面上。 < 5 >如第4圖所示，對形成***物形成箔之銅箔材241222844 Amendment 〇〇llUib5. Description of Invention (7) At this time, the activation treatment is as disclosed by the present applicant in Japanese Patent Application Laid-Open No. 224 i 84, which is based on! Χ 〖卜】 χ】 $ = Thousands = :: = 2, in (2) ore nickel-copper slab with a joint surface = give it to St. please, roll it heartily, ^ ί advantageous ^ ^ set in the vacuum tank 29 Unit 30 cold-rolled the clad board for printed circuit boards with a round structure ... rolled at 18a and cut 'Hi as shown in Figure 1'. The clad board for printed circuit boards-1 9 (Toyo,% w 1 = After the size, as shown in Figure 2, using the primer coating 〆 / w Co., Ltd., Finishers, Ding 491 a material 彳 8 white potential. Specifically, first, the cladding board m for printed circuit boards ] Ϊ 1 Ϊ Form the side of the box and the corresponding surface of the PET film 17 with 1㈣ ~ 2 " After coating the undercoat 19, the cladding coated with the undercoat is coated with Gu Guang 1yan and heated at 0 ° C for 30 seconds. After attaching the pET film 17 to 1, I: the cladding material 18 of the main material, the lamination process was performed by a pressure roller (5 to 15 kg / cm). ≪ 4 > As shown in FIG. 3, the first photoresist is applied “on the bump formation surface on the side of the bump formation foil for the printed circuit board. ≪ 5 > As shown in FIG. 4, a foil is formed on the bump formation. Copper Foil 24

89110764-91033TYJP. Ptc _ιι 第13頁89110764-91033TYJP. Ptc _ιι Page 13

J 號 891107fU 年 五、發明說明(8)'" ' ---修毛 採用I虫刻液進行選擇钮刻，形成***物13。 -光：36二广第=示，由選擇蝕刻後的***物13去除第 第於…体電路形成面並塗布 去除Γ二〉光,/336圖所示’蝕刻非導体電路形成面34 ’其後 半導第。7圖所示，採用異向性導電接著劑15並安裝 又’與本發明有關的印 (M λ封]Ρ刷冤路板10，係於銅箔材20 又、 # ^)之一側面上施以成為停止蝕刻声丨2之妒 鎳層21並製造鍍鎳銅箱材2 2， 曰 、又 制谇古、土 a D 士 μ 何Ζ以取代上述的印刷電路板之 :㈣供二：採用底層塗料19貼’τ薄膜17於背面， 後：m22及銅箱材24進行上述的活性化處理 曰已δ又於真空槽29内的輥軋單位3〇，利冷 亦可製造。此•，已設於真空槽29内 以 熱量時，Ρ丨丨PFT键腺1 7 士， 〕』仇乳早位川右具有 浐。 、彳、有熔解的顧慮，故需冷卻輥軋輥 發明之功斂 如上述，藉由採用包層技術 刷電路板之基板的印刷電路板用 又’形成印刷電路板用包層板， 刷電路板包層板之另一側面上，採用 接合技術可價廉的製造出印刷電路板 ’可價廉的製造出成為 包層板。 將樹脂薄膜接合至 包層技術及樹脂薄 印 印 mYear No. J 891107fU 5. Description of the invention (8) '"' --- Trim Use I insect engraving solution to carry out the selection button engraving to form the bulge 13. -Light: 36 Erguang No. = shown, the first and the bulk circuit forming surface are removed by the etched bump 13 and coated and removed The second semi-conductor. As shown in FIG. 7, an anisotropic conductive adhesive 15 is used and installed, and the seal (M λ seal) related to the present invention is applied to one of the side surfaces of the copper foil 20 and # ^. The jealous nickel layer 21 and the nickel-plated copper box 22 were made to stop the etching sound, and the nickel-plated copper box 22 was also replaced with the above-mentioned printed circuit board: The primer film 19 is used to attach the 'τ film 17 on the back surface. After that, the m22 and the copper box 24 are subjected to the above-mentioned activation treatment, and the rolling unit 30 has been δ in the vacuum tank 29, and it can also be manufactured by cold cooling. Therefore, when the heat has been set in the vacuum tank 29, the P 丨 丨 PFT key gland is 17, 』』 Chou milk early position Chuanyou has 浐. There are concerns about melting, so the work of the invention needs to be cooled as described above. By using the clad technology to brush the circuit board, the printed circuit board is used to form the clad board for the printed circuit board, and the circuit board is brushed. On the other side of the cladding board, a printed circuit board can be manufactured inexpensively by using bonding technology. Bonding resin film to cladding technology and resin film printing m

89110764-91033TYJP.ptc 第14頁 122284489110764-91033TYJP.ptc Page 14 1222844

廉的：=:月之1c卡，不僅採用包層技術及樹脂薄膜可價 衣&IC卡，因附加有可用手之觸感判斷的資訊，楹 鬲目人等的便利使用。 』徒 時於ΐΐΐΓί印ΐ電路板之製造方法，採用包層板，同 劑之裸接t式上採用已使用異向性導電接著 PET等價廉的樹" 於成為不需回流焊接，故可使用 曰4 Μ材料，可價廉的製造印刷電路板。Inexpensive: =: Monthly 1c card, not only using cladding technology and resin film valence & IC card, because it can be judged by the touch of the hand, it is convenient for everyone. "Only in the manufacturing method of the printed circuit board, a clad board is used. The bare t-type of the same agent uses an inexpensive tree that has used anisotropic conductivity followed by PET." It does not require reflow soldering, so It can use 4M material and can manufacture printed circuit boards at low cost.

12228441222844

---MM 89110764____ 圖式簡單說明 圖式之簡明 第1圖為與本發明之一實施形態有關的印刷電路板之 製造方法之步驟說明圖。 第2圖為與本發明之一實施形態有關的印刷電路板之 衣^方法之步驟說明圖。 弟3圖為與本發明之 貫施形悲有關的印刷電路板之 製造方法之步驟說明圖。 第4圖為與本發明之一實施形態有關的印刷電路板之 製造方法之步驟說明圖。 第5圖為與本發明之一實施形態有關的印刷電路板之 製造方法之步驟說明圖。 第6圖為與本發明之一實施形態有關的印刷電路板之 製造方法之步驟說明圖。 第7圖為與本發明之一實施形態有關的印刷電路板之 製造方法之步驟說明圖。 第8圖為由與本發明之一實施形態有關的印刷電路板 而得的1C卡之平面圖。 第9圖為可使用於與本發明之一實施形態有關的印刷 電路板之製造方法的印刷電路板用包層板之製造裝置的節 面正面圖。 第1 0 圖為習用的印 刷電路板之正面圖 圖號之說明 10 印刷電路板 11 電路形成箔--- MM 89110764____ Brief description of the drawing Concise drawing The first drawing is an explanatory drawing of the steps of a method for manufacturing a printed circuit board related to an embodiment of the present invention. Fig. 2 is a diagram illustrating the steps of a method for manufacturing a printed circuit board according to an embodiment of the present invention. Figure 3 is a diagram illustrating the steps of a method for manufacturing a printed circuit board related to the conventional embodiment of the present invention. Fig. 4 is a diagram illustrating the steps of a method for manufacturing a printed circuit board according to an embodiment of the present invention. Fig. 5 is a diagram illustrating the steps of a method for manufacturing a printed circuit board according to an embodiment of the present invention. Fig. 6 is an explanatory diagram of steps in a method of manufacturing a printed circuit board according to an embodiment of the present invention. Fig. 7 is a diagram illustrating the steps of a method for manufacturing a printed circuit board according to an embodiment of the present invention. Fig. 8 is a plan view of a 1C card obtained from a printed circuit board according to an embodiment of the present invention. Fig. 9 is a sectional front view of an apparatus for manufacturing a clad board for a printed circuit board that can be used in a method for manufacturing a printed circuit board according to an embodiment of the present invention. Fig. 10 is a front view of a conventional printed circuit board. Explanation of drawing numbers 10 Printed circuit board 11 Circuit forming foil

89110764-91033TOP.ptc 第16頁 1222844 案號89110764_年月日 修正 圖式簡單說明 12 停 止 ik 刻 層 13 隆 起 物 14 半 導 体 晶 片 15 異 向 性 導 電 接 著 15c i 導 電 粒 子 16 開 孔 17 樹 脂 薄 膜（PET) 18 印 刷 佈 線 用 包 層 板 19 底 層 塗 料 20 銅 箔 材 21 鍍 鎳 22 鍍 鎳 銅 箔 材 23 回 繞 捲 軸 24 銅 箔 材 25 回 繞 捲 轴 26 I虫 刻 室 27 >28 滾 動 電 極 30 輥 軋 單 位 31 捲 取 輥 輪 32 第 一 光 阻 33 第 二 光 阻 34 非 導 體 電 路 形 成 面 35 突 起 36 資 訊 傳 達 用 凹 凸 花紋89110764-91033TOP.ptc Page 16 1222844 Case No. 89110764_Year Month and Day Correction Schematic Description 12 Stop ik engraved layer 13 Protrusion 14 Semiconductor wafer 15 Anisotropic conductive 15c i Conductive particles 16 Opening 17 Resin film (PET ) 18 Cladding board for printed wiring 19 Primer 20 Copper foil 21 Nickel plating 22 Nickel-plated copper foil 23 Rewinding reel 24 Copper foil 25 Rewinding reel 26 I Insect engraving chamber 27 > 28 Rolling electrode 30 roller Rolling unit 31 Winding roller 32 First photoresist 33 Second photoresist 34 Non-conductor circuit forming surface 35 Protrusion 36 Concave-convex pattern for information transmission

89110764-91033mP.ptc 第17頁89110764-91033mP.ptc Page 17

Claims (1)

1222844 修正 _ 案號 89110764 申請專利範圍 1. 一種印刷電路板之製造方 (1 )介經鎳箔材或链辞而$ 、仏 ；· 而成的形成***物用箔材上予 曰於由鋼箔材 電路形成箔，並形成印刷電 =^ / 、，5泊材而成的 广〇、 丨W电路板用包層板、 (2 )於前述印刷電路板用包声 樹脂薄膜、 θ板之電路形成泊側上貼附 (3 )於前述印刷電路士田 之***物形成面上塗布第二日阻板之形成***物用箱材側 二對埋形成前述形成***物用箱材，採用第-蝕叫Γ、’ 進仃選擇蝕刻，形成***物、 蚀刻液亚 (5)由前述選擇蝕刻後之前述 :前述電路糊上的停止餘刻層之導体于電弟;^ ’ 布第二光阻、 守1个电俗形成面上塗 (6 )對形成前述導体電路之f|材，採用第二 蝕刻並形成導体電路、其後去除前述第二光阻/液予以 (7、）採用異向性導電接著劑並安裝電子組件 而成。 2 · —種印刷電路板之製造方法，其特徵在於： (1 )於由銅箔材而成的形成***物用箔材上予以冷 層由銀箔材或鋁箔材之任一種而成的電路形成箔並：成印 刷電路板用包層板、 Ι2Λ於前述印刷電路板用包層板之電路形成羯側上貼附 树月曰溥膜、1222844 Amendment _ Case No. 89110764 Scope of patent application 1. A manufacturer of printed circuit board (1) via a nickel foil or a chain of words, $, ·; · The foil used to form the bump is made of steel A foil circuit is used to form a foil, and a printed circuit board is formed from a printed circuit board with a thickness of 5 poise, a cladding board for a circuit board, (2) a sound-insulating resin film for the printed circuit board, and a θ board. Attach (3) the circuit-forming berth side to the above-mentioned printed circuit maker's ridge-forming surface, and apply the second-day resistance plate to form the ridge-forming box material side two pairs to form the ridge-forming box material. -Etching is called Γ, 'into the selective etching to form a bump, the etching solution is sub- (5) from the aforementioned selective etching: the conductor of the stop layer on the aforementioned circuit paste to the electric brother; ^' 布 第二 光(6) The f | material forming the aforementioned conductor circuit is coated with (6) on the surface of the electric circuit, and the second circuit is etched to form the conductor circuit. Thereafter, the aforementioned second photoresist / fluid is removed and (7,) anisotropic is used. A conductive adhesive and an electronic component are mounted. 2 · A method for manufacturing a printed circuit board, characterized in that: (1) a cold layer is formed on a foil for forming bumps made of copper foil, and the circuit is formed of any one of silver foil or aluminum foil; Foil bonding: forming a clad board for a printed circuit board, and attaching a film to the circuit formation side of the clad board for the printed circuit board described above, 六 t^_89a〇764 修正 曰 申請專利範園 〜〜 (3)於前述印刷電路板 之***物形成面上涂 匕曰板之形成***物用箔材側 (λ \ 4kl τγ> ' 弟 光 1¾、 )子形成前述形成***物 進行選擇勤^]，形成***物、力材，私用第一韻刻液並 前述選擇钱刻後之前述***物去除第-光阻後 U二二成箔上的導体電路形成面上塗布第二光阻 (6 )對形成前述導体電路之箔材，接 先阻、 蝕刻並形成導体電路，其後去除前述第—光阻Xl ’夜予以 (7 )採用異向性導電接著劑並安萝一、> 阻、 而成。 Μ子組件Six t ^ _89a〇764 Amendment to apply for a patent application ~~ (3) Apply the foil side for forming the bump on the bump formation surface of the aforementioned printed circuit board (λ \ 4kl τγ > 'Diguang 1¾ ,) The formation of the above-mentioned formation of the bulge for selection ^], the formation of the bulge, the strength material, the private use of the first rhyme engraving solution and the aforementioned selection of the engraved material after the first engraving removes the first and second photoresist on the foil A second photoresist (6) is coated on the conductor circuit forming surface of the conductor circuit, and the foil material forming the aforementioned conductor circuit is first blocked, etched, and a conductor circuit is formed, and then the aforementioned first photoresist Xl is removed (7). Anisotropic conductive adhesives are made of anisocyanate. M subassembly 89110764-91033TYJP.ptc89110764-91033TYJP.ptc
TW89110764A 1999-06-03 2000-06-02 Printed circuit board and its manufacturing method TWI222844B (en)

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JP2001196381A (en) * 2000-01-12 2001-07-19 Toyo Kohan Co Ltd Semiconductor device, metallic laminated board used for formation of circuit on semiconductor, and method for forming circuit
WO2003101163A1 (en) * 2002-05-27 2003-12-04 North Corporation Wiring substrate, method for producing the same, and semiconductor chip inspection equipment utilizing it
EP1715445A4 (en) * 2004-02-06 2016-08-31 Hitachi Chemical Co Ltd Electronic device
JP4713305B2 (en) * 2005-11-08 2011-06-29 株式会社マルチ Printed wiring board with resistance circuit and manufacturing method thereof
KR100756374B1 (en) * 2006-08-21 2007-09-10 삼성전기주식회사 Printed circuit board and method of manufacturing thereof
JP4907286B2 (en) * 2006-09-29 2012-03-28 東洋アルミニウム株式会社 Circuit structure and manufacturing method thereof
JP5429890B2 (en) * 2008-12-10 2014-02-26 国立大学法人九州工業大学 WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD
JP6543887B2 (en) * 2014-02-24 2019-07-17 日立化成株式会社 Bumped wiring board and method of manufacturing the same

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JPH05291744A (en) * 1992-04-10 1993-11-05 Hitachi Chem Co Ltd Manufacture of multilayer interconnection board and insulating board with multilayer metal layer
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CN102054711A (en) * 2009-10-30 2011-05-11 三星电机株式会社 Method of manufacturing printed circuit board having bump
US8986555B2 (en) 2009-10-30 2015-03-24 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing printed circuit board having bump

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