TW515142B - Frequency divider - Google Patents
Frequency divider Download PDFInfo
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- TW515142B TW515142B TW088104025A TW88104025A TW515142B TW 515142 B TW515142 B TW 515142B TW 088104025 A TW088104025 A TW 088104025A TW 88104025 A TW88104025 A TW 88104025A TW 515142 B TW515142 B TW 515142B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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Abstract
Description
關於一 分割成 同步資 裝置。 由封包 校正石,| 生封包 封包時 述位於 輸裝置 言，封 考時脈 所需之 問題傳輸裝置需包 為前述傳輸裝置包 Loop)電路，此傳 種除頻器用 為所欲產生 料傳送裝置 封包傳送裝 協助傳送資 與傳送資料 之CPU。 需依循由前 傳輸側之裝 。傳輸敦置 包產生裝置 。但在習知 傳輸時脈經 五、發明說明（1) 本發明係有 別是將時脈頻率 在一般起止 包產生（packet) 協定定義，並藉 封包中包含誤差 產生裝置包括產 在傳輸此類 定頻率時脈。前 裝置下一級之傳 送出去。一般而 振盪器產生一參 ’即是傳輸裝置 〇 為解決上述 輪時脈。此狀況 ’Phase Locked 生。 以分割時脈之頻率， 之時脈頻率。 ' 中，傳輸側裝置包含封 置所產生之封包由傳輪 料至接收側裝置。前述 之目的位址。一般封包 述傳輸協定所指定之特 置包括在前述封包產生 利用傳輸時脈將封包傳 中時脈產生器利用石英 技術中遭遇到一個問題 常與參考時脈無法匹配 含一振盪電路以產生傳 括一PPL(相位鎖定迴路 輸時脈由參考時脈產 楂认例如，1RDA(Infrared Data Association)的紅外線 ，=標準提供兩種傳輸模式：第—種有4 Mbps的傳輸速率 二第二種有1. 152 Mbps的傳輸速率。兩種傳輸速度可簡單 地用兩種振盪器實現，然而需要額外的成本以及更多裝置 面積，此比單一振盪器增加兩倍的製造成本。再者亦無法 以較經濟的方法取得丨·丨52 Mbps的振盪器。既使可以取得About one split into sync devices. According to the packet correction stone, when the packet is generated, the description is located in the transmission device. The problem required to test the clock is the transmission device package (Loop) circuit. This seeding frequency divider is used to generate the material transmission device. The packet transmission device assists the CPU in transmitting data and data. Follow the installation on the front transmission side. Transmission Hold Packet Generator. However, in the transmission of the clock meridians, the description of the invention (1) The present invention is different from the definition of the clock frequency in the general start and stop packet agreement (packet) agreement definition, and by the packet contains the error generation device, including the production of such transmission Constant frequency clock. The previous device transmits the next level. Generally, the oscillator generates a parameter 'that is the transmission device'. In order to solve the above-mentioned clock. This condition is' Phase Locked. By dividing the frequency of the clock, the frequency of the clock. In the transmission side device, the packet generated by the encapsulation is transferred from the transfer material to the reception side device. The aforementioned destination address. The special features specified in the general packet transmission protocol include the aforementioned packet generation. The transmission clock is used to transmit the packet to the clock generator. The use of quartz technology encountered a problem. It often failed to match the reference clock and contained an oscillator circuit to generate transmission. A PPL (Phase-locked loop clock input is recognized by the reference clock. For example, 1RDA (Infrared Data Association) infrared, = standard provides two transmission modes: the first type has a transmission rate of 4 Mbps, the second type has 1 152 Mbps transmission rate. Two transmission speeds can be easily achieved with two oscillators, but they require additional costs and more device area, which doubles the manufacturing cost of a single oscillator. Economical way to get a 52 Mbps oscillator. Even if it is available
515142 五、發明說明（2) 亦因其量少而價位偏高。此外，振盪係利用線圈與電容間 之諸振（resonance)，以確定一預設振遭頻率，但需要藉 助電路設計與頻率調整的方法防止頻率隨溫度或電源供應 電壓變化。 為利用一振盪器提供適合時脈對應兩種傳輸速率，至 少必須取得兩種傳輸速率所需時脈之公倍數，亦即4. 6 0 8 GHz。將此頻率除以4〇〇〇可得1.1 52 MHz，除以11 52即可得 4 MHz 〇515142 V. Description of the invention (2) The price is also high due to its small quantity. In addition, the oscillation system uses the resonance between the coil and the capacitor to determine a preset vibration frequency. However, it is necessary to use circuit design and frequency adjustment methods to prevent the frequency from changing with temperature or power supply voltage. In order to use an oscillator to provide a suitable clock corresponding to two transmission rates, it is necessary to obtain at least a common multiple of the clocks required for the two transmission rates, that is, 4. 6 8 GHz. Divide this frequency by 400 to get 1.1 52 MHz, and divide by 11 52 to get 4 MHz.
然而，因為此振盪頻率相當高，欲在一半導體積體電 路中佈局實現時，需要兩個製造步驟完成數個1〇s MHz以 及數個GHz，相對地增加製造成本。 再者，另一個問題是因為許多被採用之頻率相當高， 流經除頻電路之電流增加。既使利用PPL取代除頻電路亦 會發生同樣的問題。 另一種解決的方法是利用例如48 MHz的振盪速率處理 此兩種傳輸速率。假如此頻率除以1 2可以精確地得到4mhzHowever, because this oscillating frequency is quite high, two layout steps are needed to complete several 10s MHz and several GHz when implementing layout in a semiconductor integrated circuit, which relatively increases the manufacturing cost. Furthermore, another problem is that because many of the adopted frequencies are quite high, the current flowing through the frequency division circuit increases. The same problem occurs even if PPL is used instead of the frequency division circuit. Another solution is to handle these two transmission rates with an oscillation rate of, for example, 48 MHz. If this frequency is divided by 1 2 you can get 4mhz accurately
，但假若除以41得1.170 MHz，再除以42得1.1 40 MHz。1 140 MHz與1·152 MHz之間存在1%的誤差，在短的封包長度 條件下並無大礙。但是在傳送長的封包時，資料接近ς ς ，例如在第100位元時，與預設時間間隔大約會相差}個時 脈’使得所接收的資料無法在接收端再生。 因此，本發明之一目的 少因增加製程所產生之成本 率之時脈。 在於提供一種除頻器，可減 並利用任意時脈產生欲得頻, But if you divide it by 41 to get 1.170 MHz, then divide by 42 to get 1.1 40 MHz. There is a 1% error between 1 140 MHz and 1.152 MHz, which is not a big deal with short packet lengths. However, when transmitting a long packet, the data is close to ς, for example, at the 100th bit, it is about} clocks away from the preset time interval, so that the received data cannot be reproduced at the receiving end. Therefore, an object of the present invention is to reduce the timing of the cost rate caused by increasing the manufacturing process. The purpose is to provide a frequency divider, which can reduce and use any clock to generate the desired frequency.
第5頁 515142 五、發明說明（3) 為達上述目 頻裝置，依據一 脈；一轉換裝置 生時輪出來自該 且當代表一第二 除頻裝置 裝置，用 號，且根 換信號輪 本發 該輸入時 時脈之一 生該第二 之該第 以產生 據該轉 出至該 明之第 脈之頻 除頻比 時脈。 本發明之第 的’具 輸入日寺 ’當代 除頻裝 狀態之 一時脈 代表該 換裴置 轉換裝 一特徵 率以產 所得之 本發明 脈用以 表一第 置之該 〜輸出 作為一 第一狀 之該輸 置中。 為在上 生該第 一差值 特徵之除頻器包括一除 生:第一時脈與一第二時 狀恶之一輪入轉換信號發 弟一時脈作為一輸出時脈， 轉換^號發生時輪出來自該 ，出時脈；以及一轉換控制 恶或該第二狀態之該轉換信 出時脈頻率將所產生之該轉 述第一特徵中該除頻裝置除 一時脈，並利用產生該第一 除該輸入時脈之頻率，以產 包括：一 時，輸出 較裝置， 一計數器 代表該偵 本發 包括：一 裝置，預 計數器之 表該偵測 第一計 一信號 預設一 之一計 測結果 明之第 第二計 設一第 一計數 三特徵為 數器，用 表示溢位 第一預設 數值與該 作為該第 四特徵為 數器，用 二預設值 值與該第 結果作為該第一 在上述第 以在每次 作為該第 值用以輸 第一預設 二時脈。 在上述第 以計數該 用以輸出 二預設值 時脈；以 一特徵中該除頻裝置還 計數該輸入時脈並溢位 一時脈；以及一第一比 出，在每次偵測得該第 值相同時，輸出一信號 一特徵中該除頻裝置還 輸入時脈；一第二比較 ，在每次偵測得該第二 相同時，輸出一信號代 及一第三比較裝置，預Page 5 515142 V. Description of the invention (3) In order to reach the above-mentioned frequency-frequency device, according to a pulse; when a conversion device is born, it comes from this and when it represents a second frequency-reduction device, use the number, and change the signal wheel. One of the input clocks of this hair generates the second clock of the second clock to generate a clock of the frequency division ratio of the clock that is transferred out to the clock of the clock. One of the clocks of the present state of the "re-input temple" of the present invention is the frequency-removing device, which represents the characteristic of the replacement device. The pulse of the present invention is used to display the first output of the ~~ output as a first. The state of the loser. In order to generate the first difference feature, the frequency divider includes a divider: one of the first clock and the second clock is a round-robin conversion signal that sends a clock as an output clock. When the transition ^ occurs The rotation is from the clock, and the clock signal is switched to control the evil or the second state. The clock frequency of the conversion is to divide the clock generated by the frequency division device in the first feature of the paraphrase, and use it to generate the clock. Once the frequency of the input clock is divided, the output includes: one time, the output compares with a device, and a counter represents the detection. The device includes: a device, a table of the pre-counter, the detection of the first count, a signal, a preset one, and a measurement result. The second plan of the Ming Dynasty has a first count and three features as a counter, a first preset value indicating the overflow and the fourth feature as a counter, and a second preset value and the second result as the first on The above-mentioned first time is used as the first value every time to input the first preset second clock. In the first step, the clock is used to output two preset clocks; in a feature, the frequency dividing device also counts the input clock and overflows a clock; and a first comparison, the signal is obtained every time the detection is performed. When the first values are the same, the frequency-removing device also outputs a signal and the clock is input; a second comparison, each time the second is detected, a signal generation and a third comparison device are output.
第6頁 515142 五、發明說明（4) ό又一第二預設值用以輸出，在每次偵測得該第二計數器之 一計數值與該第三預設值相同時，輸出一信號代表該偵测 結果作為該第二時脈。 m本發明之第五特徵為在上述第一特徵中該轉換控制裝 ，還包括· 一第二計數器，用以計數該輸出時脈；以及一 第四比較裝置’預設一第四預設值，不論該第三計數器之 計數值與該第四預設值是否相同，產生代表該第一狀態或 該第二狀態之該轉換信號。 ^ =明之第，、特徵為在上述第一特徵中該轉換控制裝 置還包括：-第四計數器，用以計數該輸出時脈；_第五 比較裝置，預設-第五預設值，不論該第 值與該第五預設值是否相同my ^ 丁致:之片數 f狀態之該轉換信號；以及一第六比較裝：:;Page 6 515142 V. Description of the invention (4) ό Another second preset value is used for outputting, and a signal is output every time when a count value of the second counter is the same as the third preset value Representing the detection result as the second clock. The fifth feature of the present invention is the conversion control device in the first feature described above, further comprising: a second counter for counting the output clock; and a fourth comparison device 'preset a fourth preset value Regardless of whether the count value of the third counter is the same as the fourth preset value, the conversion signal representing the first state or the second state is generated. ^ = The first, characterized in that in the above-mentioned first feature, the conversion control device further includes:-a fourth counter for counting the output clock;-a fifth comparison device, a preset-a fifth preset value, regardless of Whether the first value is the same as the fifth preset value my ^ 丁 致: the conversion signal of the number of pieces f state; and a sixth comparison device ::;
與該第五預設值相同時，"(二V ^讓本發明之上述和其他目的、特徵 細說明如；“幸又佳貫施例，並配合所附圖式，作詳 圖示之簡單說明： Κίϊΐΐι發：第一實施例中除頻器之架構圖； 形圖圖除頻器中產生比較信號狀態下之波 第3圖係顯示第i圖除頻器中除頻狀態 第4圖係顯示本發明第二 之波形圖， 貝犯椚T陈頻斋之架構圖；When the value is the same as the fifth preset value, " (二 V ^ Let the above and other objects and features of the present invention be described in detail; Brief description: Κίϊΐΐι hair: the structure diagram of the frequency divider in the first embodiment; the figure diagram shows the wave in the state of the comparison signal generated in the frequency divider. The third diagram shows the frequency division state in the frequency divider in the i-th diagram. It is the second waveform diagram of the present invention.
515142 五、發明說明（5) ----- 第5圖係顯示第4圖除頻器中產生比較信號狀熊下 形圖； 〜 氣 第6圖所示為；顯示本發明第三實施例中除頻哭之 構圖 、抑永 第7圖所示為第6圖除頻器中產生比較信號狀能下之 形圖； 〜 第8圖係顯示顯示本發明第四實施例中除頻器之架構 第9圖所示為第8圖除頻器中產生比較信號狀態下之 形圖。 、彳 符號說明： 卜除頻電路；2〜選取器；2Α、2Β〜端點；3C、13、22 、3 2〜比較；3Β、1 2、2 1、3卜比較器；3 A、11〜計數器； S1〜參考時脈；S2、S3〜除頻信號；S4〜除頻時脈；％、su 〜計數值；S6、S12、S21、S3卜比較值；S7〜比較信號； 〇Fl〜溢位；pi、P2、P3〜脈衝。 〇儿’ 實施例： ，1圖係顯不本發明第—實施例中除頻器之架構圖。 形圖係顯示幻圖除頻器中產生比較信號狀態下之波 在第I’m由圖係顯示第1圖除頻器中除頻狀態下之波形圖。 碩線s5丄’二箭封頭線S2、S3為單-信號線，而粗空心箭 S6思為數個信號線。 装置（夫員可作為例如傳輸封包之傳輸裝置，在資料傳輪 I、未不於圖中）舾楗如” #貝T卞丨哥％ 根據起始同步化原則以一特定傳輸時 、2Β〜端點；3C、13、22 •器；3Α、11〜計數器；515142 V. Description of the invention (5) ----- Fig. 5 shows a bear-shaped picture of the comparison signal generated in the frequency divider of Fig. 4; ~ Fig. 6 shows it; shows the third embodiment of the present invention The composition of the middle frequency elimination cry, YI Yong Figure 7 shows the shape of the comparison signal generated in the frequency divider in Figure 6; ~ Figure 8 shows the frequency divider in the fourth embodiment of the present invention Figure 9 of the architecture shows the shape of the comparison signal generated in the frequency divider of Figure 8. Explanation of 彳 and 彳 symbols: Dividing circuit; 2 ~ selector; 2A, 2B ~ endpoint; 3C, 13, 22, 3 2 ~ comparison; 3B, 1 2, 2 1, 3, 3 comparator; 3 A, 11 ~ Counter; S1 ~ Reference clock; S2, S3 ~ Divided signal; S4 ~ Divided clock;%, su ~ Count value; S6, S12, S21, S3; comparison value; S7 ~ comparison signal; 〇Fl ~ Overflow; pi, P2, P3 ~ pulse. 〇 儿 ’Embodiment: FIG. 1 is a structural diagram showing a frequency divider in the first embodiment of the present invention. The figure shows the wave in the state where the comparison signal is generated in the magic picture frequency divider. At the I'm, the picture shows the wave form in the frequency divided state in the frequency divider of the first picture. The master line s5 丄 'two arrows head lines S2 and S3 are single-signal lines, and the thick hollow arrow S6 is considered as several signal lines. Device (the husband can be used as a transmission device for transmitting packets, for example, in the data transmission wheel I, not shown in the figure), such as "# 贝 T 卞 丨 brother% According to the starting synchronization principle in a specific transmission, 2B ~ endpoint ; 3C, 13, 22 • device; 3Α, 11 ~ counter;
五、發明說明（6) 傳輸封包。 士口第1圖所不，參考時脈s j作為輸入時脈並 =二戈稱分頻)。參考時脈嶋 者护脱以々邮方人 （禾於圖中）。除頻電路1以參 考捋脈31之頻率除以預定除頻比（frequency divisiQn 至』。:心之：’產生除頻信號S2，並將除頻信號以傳 之ϊί;以二入端2A。再者，除頻電路1以參考時脈S1 項率除乂預疋除頻比（frequency divisi〇n 至選之正’產生除頻信號S3，並將除頻信號以傳 主選取之一輸入端2β。 ▼ 根據來自比較器3Β之比較信號S7，選取哭2在 ;3二除=:;ί2入單點3B之除“ 人^ 值馬U則選取器2輸出除頻信號S2作糸 除頻時脈S4。…，假若比較信鎖之值為】取為 器2輸出除頻仏號83作為除頻時脈S4。所產生除頻 S4乃作為前述傳輸裝置之傳輸時脈。 之除^脈 。。計數器3Α，連接比較器3Β與選取器2，為一m_a 數器用以計算自選取器2輸出之除頻s : 入-計數腿作為計數⑽之計算結果輪 —計數器，其輸出作為計數值 除頻”S4結果之計數值S5剛好為η時計數器 ： t(〇 = rfl〇wed)。藉此，計數器3丸清除 / 時脈S4之計算起始值為〇。 ι除頻 五、發明說明（7) S1之之一比較3C可送出作為除分參考時脈 <比車X值S6至比較器3B中。比較值％為比較3C中一 ’其值必須小於最大計數值m-Ι。 、 特別，if3B根據比較3c中之比較值s6產生比較信傾。 此」疋第2圖所示之比較器3B會對計數值S5與S6進行相互 之值"〇假:f、\數值S5小於S6，比較器38會產生比較信號S7 〇以視為第一狀態。假若計數值S5大於S6 补會產生士較信號S7之值”i”以視為第二狀態。 季乂°° 值Sfi ^ ^ s 3B產生比較信號S7 ’並利用改變比較3C之比較 的方式改變第一與第二狀態之時間間隔。 產生ΞΙ?詳述第一實施例之操作。如第3圖所示，時脈 相M I i麥考時脈81，其時脈接著輸入除頻電路1中。 兩，除頻電路1產生除頻信號S2與S3，並將 3A為η ·韵，選，1582之端點2A與2B。此時，假設計數器 率Κ以夂二，數，’、亚假設除頻信號S2由參考時脈S1之頻 〇1 ^ 而得，並假設除頻信號S2由相同的參考時脈 '員率除以4(D2)而得。除頻電路丨利用計數參考時脈S1 n 脈衝的方式產生除頻信號S2，亦即當計數值為'· 2 守多考時脈S1超過一週期之值為"Γ，，並清除計數值。 衝的二，=丄除頻電路1利用計數參考時脈S1並產生一脈 晰ςι i式生除頻信號S3，亦即當計數值為"4" a夺參考時 脈超過一週期之值為"丨"，並清除計數值。 号 輸入ϋ t *較器⑽輸入比較信號之"〇Π值，意為前述 ,、取益2之第一狀態。根據比較信號87，選取器2輸出5. Description of the invention (6) Transmission packet. As shown in Figure 1 of Shikou, the reference clock s j is used as the input clock and the frequency is divided into two. With reference to the clock, those who take care of them will post the people (he in the picture). The frequency division circuit 1 divides the frequency of the reference pulse 31 by a predetermined frequency division ratio (frequency divisiQn to) .: The heart: 'Generates the frequency division signal S2, and transmits the frequency division signal to the terminal 2A. Furthermore, the frequency division circuit 1 divides the pre-frequency division ratio (frequency divisi0n to the selected positive frequency) by using the reference clock S1 term rate to generate the frequency division signal S3, and selects one of the frequency division signals as the input terminal of the host. 2β. ▼ According to the comparison signal S7 from the comparator 3B, select Cry 2 in; 3 Divide = :; ί 2 enters the single point 3B. The person ^ value horse U, then the selector 2 outputs the frequency division signal S2 for frequency division. Clock S4 ...., if the value of the comparison lock is [taken], the output frequency divider number 83 is output by the device 2 as the frequency cut-off clock S4. The frequency cut-off S4 generated is used as the transmission clock of the aforementioned transmission device. The counter 3A is connected to the comparator 3B and the selector 2. It is a m_a counter used to calculate the frequency division s output from the selector 2. The input-counter leg is used as the counting result of the counting wheel-counter, and its output is used as the count value. When the count value S5 of the frequency division S4 result is just η, the counter: t (〇 = rfl〇wed). With this, the counter 3 pills The calculated starting value of division / clock S4 is 0. ι Dividing frequency V. Invention description (7) One of S1 compares 3C and can be sent as a division reference clock < compares vehicle X value S6 to comparator 3B. The comparison value% is 1 in comparison 3C, and its value must be less than the maximum count value m-1. In particular, if3B generates a comparative confidence based on the comparison value s6 in comparison 3c. Therefore, the comparator 3B shown in FIG. 2 will Mutual value of the count values S5 and S6 " False: f, \ value S5 is less than S6, the comparator 38 will generate a comparison signal S7 〇 as the first state. If the count value S5 is greater than S6, it will generate a comparison The value "i" of the signal S7 is regarded as the second state. The value of the season S °° Sfi ^ ^ s 3B generates a comparison signal S7 'and changes the time interval between the first and second states by changing the comparison of the comparison 3C. Generate ΞΙ? Describes the operation of the first embodiment in detail. As shown in FIG. 3, the clock phase MI i McCaw clock 81, and the clock is then input to the frequency division circuit 1. Two, the frequency division circuit 1 generates a frequency division signal S2 and S3, and 3A is η · rhyme, choose, the endpoints 2A and 2B of 1582. At this time, suppose the counter rate K is counted by two, ', The hypothetical frequency-divided signal S2 is obtained from the frequency 001 of the reference clock S1, and it is assumed that the frequency-divided signal S2 is obtained by dividing the member rate of the same reference clock by 4 (D2). The frequency-division circuit 丨 uses the counting reference The clock S1 n pulse mode generates a frequency division signal S2, that is, when the count value is' · 2, the value of the clock S1 exceeding one period is " Γ, and the count value is cleared. The frequency division circuit 1 counts the reference clock S1 and generates a pulse-clear i-frequency division signal S3, that is, when the count value is " 4 " a value that exceeds the reference clock period is " 丨 " And clear the count value. No. Input ϋ t * Comparison ⑽ The value of the input comparison signal " 〇Π, which means the first state of the above, and benefit 2. Based on the comparison signal 87, the selector 2 outputs
：)丄：）丄42 五、發明說明（8) t = L #uS2作為除頻時脈S4。計數器3A計算除頻時脈S4， 享夯2為計數結果之計數值85輸入比較器^中。比較3(：中 中。奴蛇成4比較值S6，且比較3C輸入比較值S6至比較器3B S5小2車父器3B比較計數器3A之計數值以與％。假若計數值 义、^S6 ’則計數器3B產生比較信號S7之值為"〇，，，意為 剛述弟=狀態，並將其輸入選取器2中。 Γ圖所示，在時_時計數器3八清除其計數值， 除，二。因比較器”之輸出為’'ο"，選取器輸出 除頻k戒S2作為時脈信號S4。 ❿ 亦變t,"!間W’當參考時脈S1變為”1，'日夺，除頻信號S2 信號S2變為:〇 :=當f考時脈S1變為，Τ'時，除頻 至丨丨j ”。 ” 田在除頻4吕號s 2邊緣時計數器3 Α計數 ，^:^”時在當/^考時脈^變為^”時’除頻信㈣:) 丄 :) 丄 42 V. Description of the invention (8) t = L # uS2 is used as the frequency division clock S4. The counter 3A calculates the frequency-divided clock S4, and the share 2 is the count value 85 of the counting result and is input into the comparator ^. Comparison 3 (: Medium.) The slave snake becomes 4 comparison value S6, and the comparison 3C inputs the comparison value S6 to the comparator 3B S5. The small car parent device 3B compares the count value of the counter 3A with the%. 'Then the counter 3B generates a comparison signal S7 with a value of " 〇 ,, which means that the state = state, and enters it into the selector 2. As shown in the figure, the counter 3 clears its count value at time_time , Divide, two. Because the output of the comparator "is" ο ", the selector outputs the division frequency k or S2 as the clock signal S4. 变 Also changes to t, "! W when the reference clock S1 becomes" 1, 'Day wins, the frequency division signal S2 signal S2 becomes: 〇: = when f test clock S1 becomes, T', frequency division to 丨 丨 j "." Tian in the frequency division 4 Lu s 2 edge Hour counter 3 Α counts, ^: ^ "when / ^ 考 时钟 ^ becomes ^" 'Divided frequency signal ㈣
除頻信號S2變為”。"二2二：f考時脈S1變為T時， 計數增加至”2”。 田在除頻偽號S2邊緣時計數器3A 在時間t5至t7重複相同的操作。The frequency-dividing signal S2 becomes "." 22: When the clock S1 becomes T, the count increases to "2". When the frequency-reduction pseudo-sign S2 is on the edge, the counter 3A repeats the same from time t5 to t7. operating.
在時間18時，當舛叙w。A 祐初、風L Λ 冲數^3Α之計數值S5增加至丨丨4” 0士 並超過比較值S6，亦即3時，比 寸， 之值為” Γ，，意為前沭笛一 u At孝3β &產生比較信號S7 #搪μ 〜、 第一狀態，並將其輸入選取哭9 + 根據比較信號S7，選取哭9 ^ ^ ^ 、调八&取為2中。 S4。 Μ輸出除龍觸作為除頻時脈 在時間11 6時，當晗冲5 „ 士〆 頻％廳4之計數值S5發生溢位（ 第11頁 515142 五、發明說明（9) ___ overflowed)，計數器3A 清除 "^ 頻時脈S4開始計數。藉此，計數值= ，思為W述之第一狀態。 心值马〇 ’ ，著’根據來自比較器3Β之比較信號S7 一狀恶下輸出除頻信ES2，以及在 =地在第 號S3。 汉隹弟一狀恶下輸出除頻信 生，2在第除f ?脈“在第一狀態下伴隨除頻信號s2而產 y ^ # ΐ第—狀悲下伴隨除頻信號s3而產生，其中除頻日# ==)用除頻比(rat 10)(此後稱為除頻值)除中參除頻時 脈S1之頻率而取得一頻率，記為方程式（丨）： 才 ^«ii=CLKl XCC0P1/C0ND+CLK2 X(1-(C0N1)) (n 在方程式（1)中，"CLK1”為除頻信號“之 "CLK2"為除頻信號S3之除頻值。 ”八 _數計數器3八之溢位值。當計數器3APm_adi^ ΐί; 值變為”m” °"C〇P1”為比較㈣。當比 作為起始值，則"C〇Pl"之值會成為” a+1”。 J σ § e又疋3丨’作為比較值S6，則丨丨C0Pr丨之值為丨丨4" Γ 之值為2 ，且除頻信號S3之頻率可得自將At 18 o'clock, when narrating w. A Youchu, wind L Λ The number of shocks ^ 3A count value S5 increases to 丨 丨 4 ”0 ± 0 and exceeds the comparison value S6, that is, when 3, the ratio is“ Γ ”, which means the former flute u At 3 3β & generates a comparison signal S7 # μμ ~, the first state, and inputs it to select Cry 9 + according to the comparison signal S7, select Cry 9 ^ ^ ^, adjust eight &2; S4. Μ outputs the dragon's touch as the frequency-removing clock at time 116, when the counter value S5 of 晗 5 晗 士 〆 %% hall 4 overflows (page 515142 V. Description of the invention (9) ___ overflowed), The counter 3A clears and starts counting at the frequency clock S4. With this, the count value =, which is considered as the first state described in W. The heart value is equal to 0, and the 'according to the comparison signal S7 from the comparator 3B is bad. Output frequency division signal ES2, and ground = No. S3. Han Handi output frequency division signal, 2 in the first division f? Pulse "in the first state accompanied by the frequency division signal s2 to produce y ^ # ΐ 第 — # 3 is generated with the frequency division signal s3, where the frequency division day # ==) divides the frequency of the intermediate reference frequency division clock S1 by the frequency division ratio (rat 10) (hereinafter referred to as the frequency division value) and Obtain a frequency and record it as equation (丨): Only ^ «ii = CLKl XCC0P1 / C0ND + CLK2 X (1- (C0N1)) (n In equation (1), " CLK1" is the frequency division signal " ; CLK2 " is the frequency division value of the frequency division signal S3. "Eight_counter 3 overflow value of the counter. When the counter 3APm_adi ^ ΐί; the value becomes" m "° " C0P1" is a comparison value. When the ratio Make The initial value, then the value of "C0Pl" will become "a + 1". J σ § e again 疋 3 丨 'as the comparison value S6, then the value of 丨 丨 C0Pr 丨 丨 丨 4 " Γ Is 2 and the frequency of the divided signal S3 can be obtained from
° -CONI 3C% ，_再者，因在第I圖中’比較值S6設定為比較 運算而得。之值為4 。第3圖之實例係根據方程式⑴° -CONI 3C%, _ Furthermore, it is obtained by setting 'comparison value S6' as the comparison operation in the first figure. The value is 4. The example in Figure 3 is based on the equation ⑴
515142 五、發明說明（ίο) 除頻值=2 X4/6 + 4 Χ(1-4/6) =16/6 例如，利用48MHz參考時脈S1除以41產生除頻信號， 並同樣除以42產生除頻信號S3，假設計數器3A為3m-adic 計數器，並設定比較值S6為” 〇”。 . UODDb 除頻值= 41x1/3+ 4 2x(1-1/3) … 利用除頻值除48MHz，除頻時脈S4之平均頻率如下 平均頻率= 48/41· 66666 =1. 152000 再者，如上所述，可對48MHz除以已知除頻器所提供 之值12而產生4MHz。所以兩傳輸速度可以依照、同°一參考、日士 脈而產生。 ' 根據本發明之實施例，除頻時脈S4之頻率可依 =比較3C中之比較值S6而改變，故可確信所需頻 ς夫 =脈S1之頻率進行除頻而產生。再者，參考時脈S1之頻 率可加以改變，利用一般商用石英振盪器產生參考時脈W 所以可以避免增加資料轉換裝置的成本。 參考時⑽之頻率可被改變，亦可供作其他 此值得注意的是除頻信號S2⑺之 數，但兩者間的差值最好小一些。 I為任思正 J除頻值差異很大’當選取器2中俨號；轉；、心虎S2、S3 ^頰信號S2、S3之除頻值差異相當°大'、·二轉^士亚輸出時， $化所造成之負面影響會增加。；广脈S4之週期 表好是相近之整數值。如果欲氏、幻之除頻值 動）（jitter)，除頻作沪S2上述負面影響效應（擾 傾S3間之頻率差異需減小。 515142 五、發明說明（11) 相反地，所提供此類擾動可多一些或少一些，除頻信 號S2、S3間之頻率差異亦可多一些或少一些，而產生除頻 信號S2、S3之除頻器級數也可降低。 計數器3A之最大計數值” m，，則小於傳送資料之一個封 ^長度。所提供最大計數值” m，，大於此封包長度，在選取 為2改％岫’除頻時脈S4與原始存在時脈之間之誤差會增 加，使得在接收端發生錯誤調變（m〇dulated)資料之機率 增加。所以，最大計數值” m’’最好等於或小於封包長度 一车〇 ^第一日守貫施例中’雖然計數值超過比較器3B之比較 值S6時，比較信號S6被描述成為第二狀態，連帶是計數器 ίS6或更大之值。再者，_然所述之除頻信號S2、 ，考時脈在一個週期中為”1"，且藉以清除計數值 ，棱供加強邊緣作為時脈，產生5〇 %之脈衝。 此二卜’計數器3A之最大計數值"m"與比較值s6可加以 固疋:或可自CPU中對其設定加以改變。 塊圖第4-1 ί本發明第二實施例中所採用除頻器之架構區 波^圖弟β係顯不第4圖除頻器中產生比較信號狀態下之 ，比圖與V此除頻器包括一選取器2 ’計數器3Α與11 之—气:哭u、 u以及比較3C與1 3，其中取代除頻電路1 =數^11，比較器12與比較13。 所不相同標號代表相同功能之元件。 ，、弟1圖 第4圖中11十數器11為一 n-adic計數器用以計算參515142 V. Description of the invention (ίο) Divided frequency value = 2 X4 / 6 + 4 χ (1-4 / 6) = 16/6 For example, a 48MHz reference clock S1 is divided by 41 to generate a divided frequency signal, which is also divided by 42 generates a frequency division signal S3, assuming that the counter 3A is a 3m-adic counter, and the comparison value S6 is set to "0". . UODDb frequency division value = 41x1 / 3 + 4 2x (1-1 / 3)… Use the frequency division value to divide 48MHz, the average frequency of frequency division clock S4 is as follows: average frequency = 48/41 · 66666 = 1. 152000 again As mentioned above, 4MHz can be generated by dividing 48MHz by the value 12 provided by the known divider. Therefore, the two transmission speeds can be generated according to the same reference and the Japanese pulse. According to the embodiment of the present invention, the frequency of the frequency-removed clock S4 can be changed according to the comparison value S6 in the comparison 3C, so it can be ascertained that the required frequency is generated by dividing the frequency of the pulse S1. In addition, the frequency of the reference clock S1 can be changed, and the reference clock W is generated by a general commercial quartz oscillator, so that the cost of the data conversion device can be avoided. The frequency of the reference time chirp can be changed or used for other purposes. It is worth noting that the frequency division signal S2⑺ is the number, but the difference between the two is preferably smaller. I is Ren Sizheng J ’s frequency division value is very different. 'When picker 2; ；;, heart tiger S2, S3 ^ Cheek signal S2, S3 is quite different in frequency division value', · two revolutions ^ Shiya output As time goes on, the negative impact of $ lization will increase. ; The periodic table of Guangmai S4 seems to have similar integer values. If you want to change the frequency of jitter and jitter, the above-mentioned negative impact effect of frequency division operation S2 (frequency difference between disturbances S3 should be reduced. 515142 V. Description of the invention (11) Conversely, provided this The type of disturbance can be more or less, and the frequency difference between the frequency division signals S2 and S3 can also be more or less, and the number of frequency divider stages that generate the frequency division signals S2 and S3 can also be reduced. The maximum count of the counter 3A The value “m” is less than a packet length of the transmitted data. The maximum count value “m” is greater than the length of this packet. When the value is selected, it is 2%. The frequency division clock S4 and the original existence clock are selected. The error will increase, which will increase the chance of erroneous modulated data at the receiving end. Therefore, the maximum count value "m" is preferably equal to or less than the packet length. 'Although the count value exceeds the comparison value S6 of the comparator 3B, the comparison signal S6 is described as the second state, and the value is the counter S6 or greater. Furthermore, the frequency-dividing signal S2 described above, The pulse is "1" in one cycle, and borrows The count value is cleared, and the edge is used to strengthen the edge as a clock to generate a 50% pulse. The maximum count value of the counter 3A " m " and the comparison value s6 can be fixed: or it can be set from the CPU Figure 4-1 of the block diagram: The structure of the frequency divider used in the second embodiment of the present invention is shown in Figure ^. Figure β shows that the comparison signal in the frequency divider in Figure 4 is compared with the figure and V This frequency divider includes a selector 2 'counters 3A and 11-Qi: cry u, u and compare 3C and 1 3, which replaces the frequency divider circuit 1 = number ^ 11, comparator 12 and compare 13. The same reference numerals represent components with the same function. The figure 11 in figure 4 and figure 11 in figure 11 is an n-adic counter used to calculate the parameter.
第14頁 515142Page 515142
五、發明說明（12) 考時脈並輸出"0”至"n-P作為計數值。 值s 11作為計數結果至比較器丨2中。因 ^别入一計數 計數器，預先設定"n-1丨丨於計數器n中。告二^^n-adlc 計數值S11與前述設定值一致時，計數器心之 且於下一個時脈時產生溢位。此時， 义 SU，並從一起始狀態開始計數此參考時脈广除計數值 計數值S11在第5(a)圖中以一方波形式 於第5⑻圖中。特別是計數值S11隨時間 ㊁化们则與比較細一料，產生“二 下一個參考柃脈S1輸入時計數值S11清除成為，，〇π。 計數器利用輸出自選取器2之除頻時脈之一脈衝作為 一清除信號。特別是當除頻時脈S4之脈衝被輸入至計數器 11之一端點CLR時，計數器11會被清除至一初始狀態。當 前述溢位與清除動作發生時’計數器產生脈衝°，並^輸入"脈 衝至選取器2之端點2Α作為除頻信號S13。將比較13輸入一 比較值S1 2以產生除頻信號S1 4。比較值係預先設定於比較 13 中。 、V. Explanation of the invention (12) Test the clock and output "0" to "nP" as the count value. The value s 11 is the count result to the comparator 丨 2. Because ^ is not entered into a count counter, it is set in advance "n" -1 丨 in counter n. ^^ n-adlc When the count value S11 is consistent with the aforementioned set value, the counter will generate an overflow at the next clock. At this time, SU is defined and starts from one. The state starts to count. This reference clock divides the count value. The count value S11 is shown in Figure 5 (a) as a square wave in Figure 5. In particular, the count value S11 is reduced with time. "When the next reference pulse S1 is input, the count value S11 is cleared to become, π. The counter uses a pulse output from the frequency-divided clock from the selector 2 as a clear signal. In particular, when the pulse of the frequency division clock S4 is input to one of the endpoints CLR of the counter 11, the counter 11 is cleared to an initial state. When the aforementioned overflow and clear actions occur, the counter generates pulses and inputs the "pulse" to the terminal 2A of the selector 2 as the frequency division signal S13. The comparison 13 is input to a comparison value S1 2 to generate a frequency-divided signal S1 4. The comparison value is set in comparison 13 in advance. ,
比較器1 2根據來自計數器11之計數值§丨1以及來自比 較1 3之比較值S1 2而產生一比較信號。特別是比較器丨3比 較計數值S11以及比較值S1 2，假使計數值s 11小於比較值 S12，則產生比較信號值”0”。假入計數值su與比較值S12 一致，比較器1 2便產生一比較信號脈衝。比較器1 2改變時 序並對應比較1 3之比較值S1 2而產生比較信號脈衝。比較 器1 2輸入比較信號，接著產生除頻信號s 1 4至選取器2之端The comparator 12 generates a comparison signal based on the count value §1 from the counter 11 and the comparison value S1 2 from the comparison 13. In particular, the comparator 3 compares the count value S11 and the comparison value S1 2. If the count value s 11 is smaller than the comparison value S12, a comparison signal value “0” is generated. The fake count value su coincides with the comparison value S12, and the comparator 12 generates a comparison signal pulse. The comparator 12 changes the timing and generates a comparison signal pulse corresponding to the comparison value S1 2 of the comparison 13. The comparator 1 2 inputs a comparison signal, and then generates a frequency division signal s 1 4 to the end of the selector 2
第15頁 515142 五、發明說明（13) 點2B中 以下將描述第二實施例之操作情形。當時脈產生器（ 未示於圖中1產生參考時脈S1時，將參考時脈§1輸入計數 器11中。如第5A圖所示，計數器丨丨計算參考時脈S1，假若 發生溢位0F1，產生一脈衝P1。比較13之比較值si2預先設 定，並輸入比較值1 2至比較器1 2中。 比較器1 2比較計數器丨丨之計數值311與比較丨3之比較 值S12。假入計數值S11小於比較值S12，比較器12產生比 較信號π Οπ。Page 15 515142 V. Description of the invention (13) Point 2B The operation of the second embodiment will be described below. Clock generator (not shown in Figure 1 when generating reference clock S1, input reference clock §1 into counter 11. As shown in Figure 5A, the counter calculates reference clock S1, if an overflow occurs 0F1 A pulse P1 is generated. The comparison value si2 of the comparison 13 is set in advance, and the comparison value 12 is input to the comparator 12 2. The comparator 12 compares the counter value 311 of the counter 丨 and the comparison value S12 of the comparison 丨 3. False The input count value S11 is smaller than the comparison value S12, and the comparator 12 generates a comparison signal π Οπ.
接著’增加計數值S11增加，假如計數值s丨1與比較值 S1 2相同時’比較器1 2產生比較信號脈衝。比較器丨2輸入 比較信號至選取器2中作為除頻信號31 4。所產生之脈衝為 第5(a)圖所示之脈衝P2。 相反地，比較器3B輸入比較信號S7之值為” 〇，，，亦即 選取器2成為前述第一狀態。選取器2輸出來自計數器丨丨之 除頻h號S1 3作為以比較信號s 7為基礎之除頻信號s 4。 隨後’計數器11產生因計數參考時脈S1造成溢位F1之 前脈衝P1。包含脈衝P1之除頻信號S1 3由選取器2輸出作為 除頻時脈S4。Next, "the count value S11 is incremented. If the count value s 丨 1 is the same as the comparison value S1 2", the comparator 12 generates a comparison signal pulse. The comparator 丨 2 inputs the comparison signal into the selector 2 as a frequency division signal 31 4. The generated pulse is the pulse P2 shown in Fig. 5 (a). Conversely, the value of the comparison signal S7 input by the comparator 3B is "0", that is, the selector 2 becomes the aforementioned first state. The selector 2 outputs the frequency division number h S1 3 from the counter 丨 as the comparison signal s 7 Based on the frequency-dividing signal s 4. Subsequently, the counter 11 generates the pulse P1 before the overflow F1 due to the counting reference clock S1. The frequency-dividing signal S1 3 including the pulse P1 is output by the selector 2 as the frequency-dividing clock S4.
計數器3A之計數值S5接著會增加，假若計數值S5超過 比較值S6，比較器3B產生比較信號S7之值為π1”，意指前 述第一狀態’並將其輸入選取器2。選取器2輸出除頻信號 S1 4作為以比較信號S7為基礎之除頻時脈S4。 相反地，比較13之比較值S12為預先設定且比較13輸The count value S5 of the counter 3A will then increase. If the count value S5 exceeds the comparison value S6, the comparator 3B generates the value of the comparison signal S7 as π1 ", which means the aforementioned first state and enters it into the selector 2. The selector 2 The frequency division signal S1 4 is output as the frequency division clock S4 based on the comparison signal S7. In contrast, the comparison value S12 of the comparison 13 is set in advance and the comparison 13 is output.
第16頁 515142 五、發明說明（14) 入比較值S1 2至比較器1 2中。比較器1 2比較計數器1 1之計 數值S1 1與比較1 3之比較值S1 2。假若計數值S1 1小於比較 值S1 2，則比較器1 2產生比較信號之值為ff (Γ。 接著，計數值S11增加，且當計數值S11與比較值s 1 2 相符合時，比較器12產生比較信號如第5(a)圖所示一脈衝 p2，，並將此比較信號輸入輸入選取器2作為除頻信號S1 4 。每當計數值SI 1與比較值S12相符時，比較器12便會產生 脈衝P2。包括脈衝P2之除頻信號S1 4由選取器2被輸出作為 除頻時脈S4。同時，計數器丨丨因脈衝P2清除至起始狀態。 接著，，據來自比較器3B之比較信號S7重複輸出代表^述 ，一狀態之除頻信號S1 3以及代表前述第二狀態之除頻信 號S14，以產生除頻時脈§4。 藉此，將參考時脈S1除以依據下式（2)所得一除頻值 可得除頻時脈S4。 除頻值=(c〇P1 xCON2+COP2 x(c〇N1_c〇pi))/c〇Ni (2) 在2學式（2)中，"C0N2”為清除計數器u之值。當計 一^rdlc計數器時，，，C0N2，，之值變為°"C0P2 馬比較值S1 2。 在第二實施例中，炎去 較3C中之比較值S6而加；時脈可根據設定於比 之比較值S12改變時序而產因為可依據設定於比較13 脈S1之頻率甚至可根據比1頻/吕㈣4之脈衝，參考時 因為參數（可改變）增加，盥每瓮 改變欲得之除頻值。 ，、第一貝把例相較下可更便利於Page 16 515142 V. Description of the invention (14) Enter the comparison value S1 2 to the comparator 12. The comparator 1 2 compares the counter S 1 with the value S 1 1 and the comparison value S 1 2 with the comparison 1 3. If the count value S1 1 is smaller than the comparison value S1 2, the value of the comparison signal generated by the comparator 12 is ff (Γ.) Then, the count value S11 increases, and when the count value S11 matches the comparison value s 1 2, the comparator 12 generates a comparison signal as a pulse p2 as shown in FIG. 5 (a), and inputs the comparison signal into the selector 2 as the frequency division signal S1 4. When the count value SI 1 matches the comparison value S12, the comparator The pulse P2 will be generated at 12. The frequency-dividing signal S1 4 including the pulse P2 is output by the selector 2 as the frequency-dividing clock S4. At the same time, the counter is cleared to the initial state by the pulse P2. Then, according to the data from the comparator The comparison signal S7 of 3B repeatedly outputs a representative signal, a frequency-dividing signal S1 3 in one state, and a frequency-dividing signal S14 representing the aforementioned second state to generate a frequency-divided clock §4. Thus, the reference clock S1 is divided by The frequency division clock S4 can be obtained according to a frequency division value obtained by the following formula (2). The frequency division value = (c0P1 xCON2 + COP2 x (c〇N1_c〇pi)) / c〇Ni (2) (2), "C0N2" is the value of clear counter u. When counting a ^ rdlc counter, the value of C0N2, becomes ° " C0P2 Comparison value S1 2. In the second embodiment, the inflammation value is added to the comparison value S6 in 3C; the clock can be changed according to the comparison value S12 set at the ratio and the timing can be generated because it can be compared to the frequency of 13 pulse S1. It can even be based on the pulses of the frequency of 1/4. When the reference is increased, the parameter can be changed, and the frequency of the division can be changed each time. It is more convenient to compare the first case.
第17頁 515142 五、發明說明（15) 弟6圖所示為；顯示本發明第三實施例中除頻器之架 構圖。第7圖所示為第6圖除頻器中產生比較信號狀態下之 波形圖。 第6圖所示之除頻器包括一選取器2，計數器3A與丨i， 比較器3B、1 2、21，以及比較3C、1 3、與22。 本實施例與第4圖所示之除頻器不同在於額外提供比 較器2 1與比較2 2。第6圖所示之標號與第1圖與第4圖所示 之7G件標號相同。 如第6圖所示，比較22輸入比較值S2 1以產生除頻信號Page 17 515142 V. Description of the invention (15) Figure 6 shows the structure of the frequency divider in the third embodiment of the present invention. Fig. 7 is a waveform diagram in a state where a comparison signal is generated in the frequency divider of Fig. 6. The frequency divider shown in FIG. 6 includes a selector 2, counters 3A and i, comparators 3B, 1, 2, 21, and comparisons 3C, 1, 3, and 22. This embodiment differs from the frequency divider shown in FIG. 4 in that a comparator 2 1 and a comparison 2 2 are additionally provided. The reference numerals shown in FIG. 6 are the same as those of the 7G elements shown in FIGS. 1 and 4. As shown in Fig. 6, the comparison 22 inputs the comparison value S2 1 to generate a frequency division signal
S22至比較器21中。比較值S2i為一預先設定於比較22之預 設值。 比較器21根據來自計數器^之計數值311與來自比較 22之比較值821以產生比較信號。 ，，特別是比較器21會對計數值S11與比較值S2i加以比較 ’饭，如計數值S1 1小於比較值S2 1，比較器2 1產生比較信號 ^ ° 。假如計數值S11比較值S1 2，比較器2 1產生比較信 號之值〇 。假如計數值S11與比較值S 2 1相符時，比較器 2 1產生 比較信號脈衝。比較器2 1接著根據比較2 2之比較 值S21改變時序以產生脈衝。 比較器2 1輸入比較信號至選取器2之端點2 A。 以下將詳述本發明中第三實施例之操作情形。 t脈產生器（未不於圖中）產生參考時脈S1，並輸入至 =數器11中。計數器11計算參考時脈S1，並輸入計數值至 第7圖所示之比較器1 2、21中。比較器1 2產生除頻信號s 1 4S22 to the comparator 21. The comparison value S2i is a preset value previously set in the comparison 22. The comparator 21 generates a comparison signal based on the count value 311 from the counter ^ and the comparison value 821 from the comparison 22. In particular, the comparator 21 compares the count value S11 with the comparison value S2i. If the count value S1 1 is smaller than the comparison value S2 1, the comparator 21 generates a comparison signal ^ °. If the count value S11 is compared with the value S1 2, the comparator 21 generates a value of the comparison signal 0. If the count value S11 matches the comparison value S 2 1, the comparator 2 1 generates a comparison signal pulse. The comparator 21 then changes the timing based on the comparison value S21 of the comparison 2 2 to generate a pulse. Comparator 2 1 inputs a comparison signal to terminal 2 A of selector 2. The operation of the third embodiment of the present invention will be described in detail below. The t-pulse generator (not shown in the figure) generates the reference clock S1 and inputs it to the counter 11. The counter 11 calculates the reference clock S1 and inputs the count value to the comparators 1 2 and 21 shown in FIG. 7. Comparator 1 2 generates a divided signal s 1 4
第18頁 515142 五、發明說明（16) ，同時比較13採用計數值S11。 比較22中預先設定比較值S21，比較22輸入比較值S2l 至比較器2 1中。比較器2 2比較計數器11之計數值§ π與比 較2 2之比較值S 2 1。假如計數值S1 1小於比較值s 2 1，比較 器21會產生比較信號值π 0"。 接著，計數器3 Α之計數值S11增加，假如計數值s 11與 比較值S 2 1相同時，比較器2 1會產生一比較信號脈衝。比 較器2 1輸入此比較信號至選取器2之端點2 A，作為除頻信 號S22。接著便產生如第7圖所示之脈衝P3。 相反地，比較器3 B輸入比較信號S 7之值，，〇，’至選取器2 W 中，亦即前述第一狀態。 選取器根據比較信號S 7輸出比較器2 1之除頻信號2 2作 為除頻時脈S4。 如前所述，比較器21比較計數值SI 1與比較值S21。每 當計數值SI 1與比較值S21相同時，比較器21會產生必7圖 所示脈衝P3之比較信號。同時，計數器丨丨根據此脈衝p3被 清除成初始狀態。 接著’假如計數器3A之計數值S5超過比較值S6，亦即 S5>S6，比較器3B會產生比較信號值”丨”至選取器2，亦即 表示其為前述第二狀態。 f 利用此比較信號S 7，選取器2輸出來自比較器1 2之除 頻信號S14作為除頻時脈S4。 然後’在本發明中會根據來自比較器3B之比較信號S7 ’重複地輸出‘述第一狀態之除頻信號822以及前述第二Page 18 515142 V. Description of the invention (16), while comparing 13 with the count value S11. The comparison value S21 is set in the comparison 22 in advance, and the comparison value S2l is input to the comparator 21 in the comparison 22. The comparator 2 2 compares the count value § π of the counter 11 with the comparison value S 2 1 of the comparison 2 2. If the count value S1 1 is smaller than the comparison value s 2 1, the comparator 21 will generate a comparison signal value π 0 ". Next, the count value S11 of the counter 3 A increases. If the count value s 11 is the same as the comparison value S 2 1, the comparator 21 will generate a comparison signal pulse. The comparator 2 1 inputs this comparison signal to the terminal 2 A of the selector 2 as the frequency division signal S22. Then, a pulse P3 as shown in FIG. 7 is generated. In contrast, the comparator 3 B inputs the value of the comparison signal S 7 ,, 0, 'into the selector 2 W, that is, the aforementioned first state. The selector outputs the divided signal 2 2 of the comparator 21 according to the comparison signal S 7 as the divided clock S4. As described above, the comparator 21 compares the count value SI 1 with the comparison value S21. Whenever the count value SI 1 is the same as the comparison value S21, the comparator 21 generates a comparison signal of the pulse P3 shown in FIG. 7. At the same time, the counter is cleared to the initial state according to this pulse p3. Then "if the count value S5 of the counter 3A exceeds the comparison value S6, that is, S5 > S6, the comparator 3B will generate a comparison signal value" 丨 "to the selector 2, which means that it is the aforementioned second state. f Using this comparison signal S7, the selector 2 outputs the frequency-divided signal S14 from the comparator 12 as the frequency-divided clock S4. Then, in the present invention, based on the comparison signal S7 from the comparator 3B, the frequency division signal 822 of the first state and the second signal of the second state are repeatedly output.
第19頁 515142 五、發明說明（17) 狀悲之除頻信號S1 4，以產生除頻時脈g 4。 藉此，將參考時脈S1除以依據下式（3)所得一除頻值 可得除頻時脈S4。因參數數目增加，其較第二實施例 於改變欲得之除頻值。 、 货 除頻值=(COPC XCOP3 + COP2 X(C0N1-C0P1))/C0N1 (3、 在第（3)式中n C0P3"係比較值S21。 在本實施例中，參考頻率S1之時脈可根據設定於比較 3C中之比較值S6與S12而加以改變。因為可依據設定於比 較22之比較值S21改變時序而產生除頻信號S22之脈衝，夂 考時脈si之頻率甚至可根據比較值S2i而改變。 / 第8圖係顯示顯示本發明第四實施例中除頻器之架構 圖；以及第9圖所示為第8圖除頻器中產生比較'信號狀態 之波形圖。 如第8圖所示，此除頻器包括一選取器2、計數器以與 11、比較器3B、12、21 與31、比較3C、13、22 與32。第8 圖中與第1、4、6圖中相同標記係指功能相同之元件。在 本實施例中較第6圖所示裝置更額外提供比較器“盘比較 32。此外，在本實施例中，計數器3人之連接部分被改變， 使得計數值S5由計數器3A輸入至比較器31中。 比較32輸入比較值S31以產生一清除信號S33至比 31° 比較器31依據計數器3A之計數值S5與比較32之比較值 S 3 1而產生比較信號。 特別是比較器31比較計數值S5與比較值S31，假如計Page 19 515142 V. Description of the invention (17) The truncated frequency division signal S1 4 is generated to generate the frequency division clock g 4. Thereby, the reference clock S1 is divided by a frequency division value obtained according to the following formula (3) to obtain the frequency division clock S4. As the number of parameters increases, it is different from the second embodiment in changing the desired division value. 、 Divide the frequency value = (COPC XCOP3 + COP2 X (C0N1-C0P1)) / C0N1 (3, In the formula (3) n C0P3 " is the comparison value S21. In this embodiment, the clock of the reference frequency S1 It can be changed according to the comparison values S6 and S12 set in the comparison 3C. Because the timing can be changed according to the comparison value S21 set in the comparison 22 to generate the pulse of the frequency division signal S22, the frequency of the clock si can be even compared according to the comparison. The value S2i is changed. / FIG. 8 is a diagram showing the architecture of the frequency divider in the fourth embodiment of the present invention; and FIG. 9 is a waveform diagram showing a comparison signal state in the frequency divider in FIG. 8. As shown in Fig. 8, this divider includes a selector 2, a counter to and 11, a comparator 3B, 12, 21 and 31, and a comparison 3C, 13, 22, and 32. In Fig. 8 and 1, 4, The same reference numerals in Fig. 6 refer to components having the same function. In this embodiment, a comparator "disc comparison 32" is provided in addition to the device shown in Fig. 6. In addition, in this embodiment, the connection part of the counter 3 is changed. , So that the count value S5 is input from the counter 3A to the comparator 31. The comparison 32 inputs the comparison value S31 to generate a clear value. Signal S33 to the comparator 31 than 31 ° according to the count value of the counter 3A S5 Comparative Comparative 32 S 3 1 value to generate a comparison signal, especially a comparator 31 compares the count value with the comparison value S5 S31, if the count
五、發明說明（18) 數值S5小於比較值S31，比較器31會產生比較信號值”〇"。 再者，假如計數值S5與比較值S31相符，比較器“會產生 一比較信號脈衝。接著比較器31根據比較32之比較值S31 改變時序以產生比較信號脈衝。比較器31輸入所產生之比 較信號至計數器3A之端點CLR作為一清除信號333。 以下將詳述本實施例之操作情形，請參照第9圖。 將時脈產生器（未示於圖中）之參考時脈S1輸入至計數 ，11。計數器11計算參考時脈S1，並入計數值su至比較 器12、21中，如第9圖所示。比較器12產生除頻信號SH， 同時比較13採用計數值SI 1。 相反地，比較器3 B輸入比較信號s 7值” 〇，，至選取器2， 亦即代表前述第一狀態。依據此比較信號S7，選取器2輸 出比較器21之除頻信號S22作為除頻時脈S4。 藉此，計數器3A可計算出除頻信號s22。 接著’計數器3A之計數值S5增加，且當計數值S5超過 比較值S6時，計數器3B會產生比較信號s7值，1 Γ，至選取器 2 ’亦即代表前述第二狀態。根據比較信號37，選取器2輸 出來自比較器1 2之除頻信號S1 4作為除頻時脈S4。計數器 3 A计异所產生除頻時脈S4之脈衝數。比較器3丨比較比較3 2 之比較值S 31與計數器3 A之計數值S 5。當計數值S 5與比較❿ 值S31相符後，比較器會產生清除信號33。 藉此，前述第二狀態之時間間隔可依據比較值S3 1而 改變’因此前述第二狀態中脈衝P2之峰值（peaks)數可予 以調整。所以，利用下列第（4 )式所得之除頻值除猜考時V. Description of the invention (18) When the value S5 is smaller than the comparison value S31, the comparator 31 will generate a comparison signal value "0". Furthermore, if the count value S5 matches the comparison value S31, the comparator "will generate a comparison signal pulse. The comparator 31 then changes the timing according to the comparison value S31 of the comparison 32 to generate a comparison signal pulse. The comparator 31 inputs the generated comparison signal to the terminal CLR of the counter 3A as a clear signal 333. The operation of this embodiment will be described in detail below, please refer to FIG. 9. Input the reference clock S1 of the clock generator (not shown in the figure) to the count, 11. The counter 11 calculates the reference clock S1 and incorporates the count value su into the comparators 12, 21 as shown in FIG. The comparator 12 generates a frequency-divided signal SH, and the comparison 13 uses a count value SI 1. Conversely, the comparator 3 B inputs the value of the comparison signal s 7 ″, to the selector 2, which represents the aforementioned first state. Based on the comparison signal S7, the selector 2 outputs the frequency division signal S22 of the comparator 21 as a division. The frequency clock S4. In this way, the counter 3A can calculate the frequency division signal s22. Then the counter value S5 of the counter 3A increases, and when the count value S5 exceeds the comparison value S6, the counter 3B will generate a comparison signal s7 value, 1 Γ To the selector 2 ', which represents the aforementioned second state. According to the comparison signal 37, the selector 2 outputs the frequency division signal S1 4 from the comparator 12 as the frequency division clock S4. The counter 3 A calculates the frequency division The number of pulses of the clock S4. Comparator 3 丨 compares the comparison value S 31 of comparison 3 2 with the count value S 5 of counter 3 A. When the count value S 5 matches the comparison value S31, the comparator will generate a clear signal 33 With this, the time interval of the aforementioned second state can be changed according to the comparison value S3 1 '. Therefore, the number of peaks of the pulse P2 in the aforementioned second state can be adjusted. Therefore, the division obtained by the following formula (4) is used Frequency
515142 五、發明說明（19) 脈si之頻率而得除頻時脈S4之頻率。 除頻值=(COPl XC0P3 + C0P2 X(C0P4-C0P1) )/C0P4 (4) 在第（4)式中，”C0P4”係為比較值S3i。 π ^本貫施例中’參考頻率以之時脈可根據設定於比較 =秘13、22中之比較值％與812與s2i而加以改變。因為可 Γ; ϊ设：於比較3 2之比較值s 31改變前述第二狀態之時間 整除頻時脈S4之頻率，參考時脈si之頻率甚至 值可較第二〜^ 冉者因參數數目增加，除頻 罕乂弟一貝施例更便於實現。 雖然本發明第一、第二、筮二與 揭露如上，缺1 一弟二貝苑例已以較佳實施例 ， 上 ^其亚非用以限定本發明，任何孰習士杜溢i =脫離本發明之精神和範圍β者 =本發明之保護範圍當更潤飾， 為準。 τ明寻利耗圍所界定者 例如’參考時脈S1可利用商用舍座 σ 生器加以產；i $ α κ應振盈器作Λ日卑hi?太 考時脈。 所知用之時脈亦可作為參 一如上所述，利用一輸入時脈可一 一日守脈與一筮一士 屋生具不同頻盘々 A. 供一輪出、日士 r —守a，且可接著改變第一盥第一、 第 之時脈。 頻率可成為所欲取得 根據本發明，輸入 于 之方式改變所欲& ml 頻率可利用調整每-— 义丨紙取侍之時脈。 i 设定值515142 V. Description of the invention (19) The frequency of the pulse si is obtained by dividing the frequency of the clock S4. Dividing value = (COPl XC0P3 + C0P2 X (C0P4-C0P1)) / C0P4 (4) In the formula (4), "C0P4" is the comparison value S3i. The clock of the reference frequency in π ^ in this embodiment can be changed according to the comparison value% and 812 and s2i set in the comparison = sec. 13, 22. Because it can be Γ; set: the comparison value s 31 in the comparison 3 2 changes the frequency of the clock S4 in the time of the second state, the frequency of the reference clock si can be even higher than the second ~ ^, depending on the number of parameters Addition, the addition of the frequency of the uncle brother-bei example is more convenient to implement. Although the first, the second, the second and the disclosure of the present invention are as above, the example of the first and the second is the preferred embodiment, and its Asia and Africa are used to limit the present invention. The spirit and scope of the present invention β = the protection scope of the present invention should be more polished, whichever is prevailing. τ is defined by the profit-seeking and profit-consuming area. For example, ’reference clock S1 can be produced by the commercial building σ generator; i $ α κ should be used as a Λ sunbeam hi? Known clock can also be used as a reference, as described above, using an input clock can keep the clock a day with a different frequency board 筮 A. For a round out, the Japanese R-Shou a , And then change the first and first clock. Frequency can be obtained as desired According to the present invention, the input mode changes the desired & ml frequency can be adjusted by using the timing of each paper. i set value
第22頁Page 22
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10070527A JPH11274917A (en) | 1998-03-19 | 1998-03-19 | Frequency divider |
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| Publication Number | Publication Date |
|---|---|
| TW515142B true TW515142B (en) | 2002-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW088104025A TW515142B (en) | 1998-03-19 | 1999-03-16 | Frequency divider |
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| JP (1) | JPH11274917A (en) |
| KR (1) | KR100342125B1 (en) |
| CN (1) | CN1235408A (en) |
| DE (1) | DE19911945A1 (en) |
| TW (1) | TW515142B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7379723B2 (en) | 2004-07-29 | 2008-05-27 | Silicon Laboratories Inc. | Local oscillator and mixer for transceiver |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3870942B2 (en) * | 2003-10-20 | 2007-01-24 | ソニー株式会社 | Data transmission system and data transmission apparatus |
| DE102004006398B4 (en) | 2004-02-10 | 2006-06-08 | Atmel Germany Gmbh | Method and device for synchronizing a functional unit to a predetermined clock frequency |
| JP4734510B2 (en) * | 2004-03-11 | 2011-07-27 | エスティー‐エリクソン、ソシエテ、アノニム | Divider |
| CN102412836B (en) * | 2011-09-30 | 2013-03-27 | 杭州电子科技大学 | Dual programmable subtraction frequency divider |
| CN110545100A (en) * | 2019-09-29 | 2019-12-06 | 曹怡珺 | Low-power-consumption traveling wave frequency division circuit |
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| JPH03222514A (en) * | 1990-01-26 | 1991-10-01 | Kanzaki Paper Mfg Co Ltd | Pulse signal generating circuit |
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1999
- 1999-03-16 TW TW088104025A patent/TW515142B/en not_active IP Right Cessation
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7379723B2 (en) | 2004-07-29 | 2008-05-27 | Silicon Laboratories Inc. | Local oscillator and mixer for transceiver |
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| JPH11274917A (en) | 1999-10-08 |
| DE19911945A1 (en) | 1999-09-30 |
| KR100342125B1 (en) | 2002-06-26 |
| CN1235408A (en) | 1999-11-17 |
| KR19990078065A (en) | 1999-10-25 |
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