CN1235408A - Frequency divider - Google Patents
Frequency divider Download PDFInfo
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- CN1235408A CN1235408A CN99103070A CN99103070A CN1235408A CN 1235408 A CN1235408 A CN 1235408A CN 99103070 A CN99103070 A CN 99103070A CN 99103070 A CN99103070 A CN 99103070A CN 1235408 A CN1235408 A CN 1235408A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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Abstract
The frequency divider circuit of a frequency divider device generates one frequency division signal and the other frequency division signal based on a reference clock. A selector outputs one frequency division signal from the frequency divider circuit as a frequency division clock when a comparison signal indicates a 1st state, and outputs the other frequency division signal from the frequency divider circuit as a frequency division clock when the comparison signal indicates a 2nd state. A changeover control means generates the changeover signal, that denotes the 1st state or the 2nd state based on frequency of the frequency division clock from the selector.
Description
The present invention relates to distribute the frequency divider of clock frequency, more particularly, relate to by clock frequency is carried out frequency division, to produce the frequency divider of the satisfactory clock of frequency.
Usually, in start-stop (start-stop) synchrodata transmitting apparatus, the equipment of transmitting terminal comprises a grouping generation device.Packet transmission device produces the grouping of being determined by communication protocol, and by means of the equipment sending data of grouping to receiving terminal.By producing above-mentioned grouping to transmitting data markers error correcting code and destination-address.The grouping generation device comprises CPU (central processing unit) usually, produces grouping with it.
When sending the grouping that is produced, need follow of the clock transmission grouping of its frequency by above-mentioned communication protocol regulation.For this reason, the said apparatus that is positioned at transmitting terminal is included in the dispensing device of the back level of above-mentioned grouping generation device.Dispensing device sends grouping with tranmitting data register.Usually, the clock generator in the grouping generation device utilizes a quartz (controlled) oscillator to produce a reference clock.But prior art has a difficulty, is exactly the desired tranmitting data register of above-mentioned dispensing device, often and the said reference clock inconsistent.
In order to solve this difficulty, dispensing device comprises an oscillating circuit that is used for producing tranmitting data register.A kind of situation is to use a PLL (phase-locked loop) circuit in above-mentioned dispensing device, utilizes it to produce tranmitting data register from reference clock.
For example, the infrared communication standard of IPDA (Infrared Data Association) provides dual mode: the communication speed of first kind of mode is 4Mbps, and the communication speed of the second way is 1.152Mbps.For simple these two kinds of communication speeds of handling, simple method is to use two oscillators, still, its needed part cost usefulness, position that oscillator is shared and debugging cost are the twices of these required expenses of single oscillator or more.Also have, the quartz (controlled) oscillator of having bought characteristic frequency and be 1.152Mbps from commodity also is difficult.Promptly enable to have bought, price also is expensive, because its output seldom.Have, vibration is to utilize the resonance that produces between coil and the capacitor again, and desired frequency of oscillation should guarantee to obtain, but will prevent because the frequency change that the variation of temperature and supply voltage causes need be carried out circuit design and frequency and be debugged.
Use an oscillator and clock corresponding to two kinds of send modes is provided, can prepare a clock, frequency is the least common multiple of two kinds of transmission speeds, be that frequency is the clock of 4.608GHz, this clock that is provided is made 4000 frequency divisions, can obtain the 1.152MHz clock, further, the 4.608GHz clock that is provided is made 1152 frequency divisions, can obtain the 4MHz clock.
But this frequency of oscillation is very high, will realize such frequency on a semiconductor integrated circuit, needs the manufacturing process of tens MHz and two steps of manufacturing process of several GHz, and this just makes manufacturing expense increase.
Also have, another problem can occur,, increase through the frequency dividing circuit consumed current because the frequency of using is many and high.Promptly use the PLL circuit to replace frequency dividing circuit, also same problem can take place.
Another kind method can be like this: tackle two kinds of communication speeds with for example frequency of oscillation of 48MHz.If this frequency is made 12 frequency divisions, can obtain accurate 4MHz clock, if it is made 41 frequency divisions, can produce the 1.170MHz clock.Further, if it is made 42 frequency divisions, can produce the 1.140MHz clock.Use 1.142MHz, nearly 1% error with respect to 1.152MHz, if block length is shorter, this does not have any problem.But when transmitting a long grouping, the data (for example the 100th byte data) near maximal end point can postpone an about clock than preset time.Therefore, the device of receiving terminal fails to produce correct data.
The present invention can solve the problems referred to above of prior art, and its objective is provides a kind of frequency divider, this frequency divider can avoid expense to rise, and manufacturing process increases, and the clock that can have satisfactory frequency from clock generating arbitrarily.
For achieving the above object, a kind of frequency divider according to a first aspect of the invention is characterized in that comprising: frequency divider is used for producing first clock and second clock according to input clock; Conversion equipment, its effect are when the input switching signal is indicated first state, to export first clock as the output clock from above-mentioned frequency divider, and when above-mentioned switching signal is indicated second state, export second clock as the output clock from above-mentioned frequency divider; And conversion control device, its effect is, produces the above-mentioned switching signal of above-mentioned first state of indication or above-mentioned second state, and according to the frequency from the output clock of above-mentioned conversion equipment, the switching signal that produces outputed to above-mentioned conversion equipment.
According to a second aspect of the invention, frequency divider according to first aspect is characterised in that: above-mentioned frequency divider carries out frequency division to above-mentioned input clock, produce above-mentioned first clock, and with the different numerical value of frequency division ratio that produces above-mentioned first clock, above-mentioned input clock is carried out frequency division, produce above-mentioned second clock.
According to a third aspect of the invention we, a kind of frequency divider according to above-mentioned first aspect is characterized in that further comprising: first counter, its effect is, when above-mentioned input clock is counted and overflows, export the signal that indication is overflowed, as above-mentioned first clock; With first comparison means, wherein set in advance first set point, its effect is, when the count value that detects above-mentioned first counter meets above-mentioned first set point, exports the signal of an indication testing result, as above-mentioned second clock.
According to a forth aspect of the invention, a kind of frequency divider according to above-mentioned first aspect is characterized in that further comprising: second counter is used for above-mentioned input clock counting; Second comparator device wherein sets in advance second set point, and its effect is, whenever detecting above-mentioned second count value when meeting above-mentioned second set point, exports the signal of an indication testing result, as above-mentioned first clock; With the 3rd comparison means, wherein set in advance the 3rd set point, its effect is, when the count value that detects above-mentioned second counter meets above-mentioned the 3rd set point, exports the signal of an indication testing result, as above-mentioned second clock.
According to a fifth aspect of the invention, the frequency divider according to above-mentioned first aspect is characterized in that: above-mentioned conversion control device further comprises: the 3rd counter is used for above-mentioned output clock count; With the 4th comparison means, wherein set in advance the 4th set point, its effect is, whether meets above-mentioned the 4th set point according to the count value of above-mentioned the 3rd counter, produces the above-mentioned switching signal of above-mentioned first state of indication or above-mentioned second state.
According to a sixth aspect of the invention, the frequency divider according to above-mentioned first aspect is characterized in that: above-mentioned conversion control device further comprises: four-counter is used for above-mentioned output clock count; The 5th comparison means wherein presets the 5th set point in advance, and its effect is, whether meets above-mentioned the 5th set point according to the count value of above-mentioned four-counter, produces the above-mentioned switching signal of above-mentioned first state of indication or above-mentioned second state; With the 6th comparison means, wherein set in advance the 6th set point, its work is, when the count value of above-mentioned four-counter meets above-mentioned the 5th set point, makes above-mentioned four-counter zero clearing.
Above-mentioned and other purposes, advantage and characteristics of the present invention, by description below in conjunction with accompanying drawing, will be more obvious.Wherein:
Fig. 1 is the structure calcspar of the frequency divider of expression first preferred embodiment of the present invention;
Fig. 2 is a waveform, and expression is produced the state of comparison signal by the frequency divider of Fig. 1;
Fig. 3 is an oscillogram, the state during the frequency divider frequency division of presentation graphs 1;
Fig. 4 is the structure calcspar of the frequency divider of expression second preferred embodiment of the present invention;
Fig. 5 is a waveform, and expression is by the state of the classification device generation frequently comparison signal of Fig. 4;
Fig. 6 is the structure calcspar of the frequency divider of expression the 3rd preferred embodiment of the present invention;
Fig. 7 is a waveform, and expression is by the state of the classification device generation frequently comparison signal of Fig. 6;
Fig. 8 is the structure calcspar of the frequency divider of expression the 4th preferred embodiment of the present invention;
Fig. 9 is a waveform, and expression is by the state of the classification device generation frequently comparison signal of Fig. 8.
Preferred embodiments more of the present invention are described below with reference to the accompanying drawings in more detail.
Fig. 1 is the structure calcspar of the frequency divider of simple expression first preferred embodiment of the present invention;
Fig. 2 is a waveform, the state when the expression frequency divider produces comparison signal; Fig. 3 also is an oscillogram, the state during expression frequency divider frequency division.In Fig. 1, thin holding wire S2, S3 represents the individual signals line, thick holding wire S5, S6 then represents one group of a plurality of holding wire.
Frequency divider can be used in the dispensing device, is used in the data transmitting equipment (not shown) with specific tranmitting data register and synchronous the carrying out of starting (start-step).
As shown in Figure 1, a reference clock S1 is applied to divider circuit 1 as input clock, there by frequency division.Reference clock S1 is that the vibration by the clock generator (not shown) of the said equipment that is arranged in transmitting terminal obtains.Divider circuit 1 carries out D1 (integer) frequency division by predefined frequency dividing ratio to reference clock S1, produces fractional frequency signal S2, and fractional frequency signal S2 is delivered to an input terminal 2A of selector 2.In addition, divider circuit 1 carries out D2 (integer) frequency division by predefined frequency dividing ratio to reference clock S1, produces fractional frequency signal S3, and fractional frequency signal S3 is delivered to another input terminal 2B of selector 2.
The function of selector 2 is according to the comparison signal S7 from comparator 3B, between the fractional frequency signal S3 of fractional frequency signal S2 that is input into terminal 2A and lead-out terminal 2B, carries out conversion operations.More particularly, selector 2 is used as switching signal with comparison signal S7.If comparison signal S7 is " 0 " value, so, selector 2 will be input into the fractional frequency signal S2 output of terminal 2A, as frequency-dividing clock S4.On the contrary, if comparison signal S7 is " 1 ", selector 2 just will be input into the fractional frequency signal S3 output of terminal 2B, as frequency-dividing clock S4.The frequency-dividing clock S4 of Chan Shenging like this is as the above-mentioned tranmitting data register of above-mentioned dispensing device.
Being connected to the counter 3A of comparator 3B and selector 2, is a m-full scale (m-adic) counter, and the frequency-dividing clock S4 from selector 2 outputs is counted.Counter 3A is to the count value S5 of comparator 3B output count results.Because counter 3A is a m-full scale counter, so the count value S5 of its output is that " 0 " is to " m-1 ".When the count value S5 that frequency-dividing clock S4 is counted was consistent with " m-1 ", counter 3A overflowed.Therefore, counter 3A removes count value S5, begins frequency-dividing clock S4 is counted from initial value " 0 ".
The comparing section 3C that is connected with comparator 3B carries a comparison value S6 who is used for the frequency division reference clock to comparator 3B.Comparison value S6 is the set point of in advance comparing section 3C being set, and this value must be less than maximum count value " m-1 ".
Below, narrate the operation of first embodiment.As shown in Figure 3, clock generator produces reference clock S1, and this clock is input to divider circuit 1 successively.According to reference clock S1, divider circuit 1 produces fractional frequency signal S2 and S3, these fractional frequency signals S2 and the S3 that are produced, and terminal 2A and the 2B from them is input to selector 2 respectively.Now, counter 2A supposition is a 6-full scale counter, and fractional frequency signal S2 supposition is that 2 (D1) frequency divisions of reference clock S1 are obtained, and fractional frequency signal S3 gets 4 (D2) frequency divisions of reference clock S1.Divider circuit 1 is by obtaining fractional frequency signal S2 to reference clock S1 counting and generation pulse, and here, when count value was " 2 ", the reference clock S1 in the one-period was " 1 ", and removed count value.
Similarly, divider circuit 1 is by to reference clock S1 counting and produce pulse and obtain fractional frequency signal S3, and here, when count value was " 4 ", the reference clock S1 in the one-period was " 1, and remove count value.
In addition, the comparator 3B value that will indicate first state is input into selector 2 for the comparison signal S7 of " 0 ".According to comparison signal S7, selector 2 output frequency division signals 2 are as frequency-dividing clock S4.Counter 3A counts frequency-dividing clock S4, and the count value S5 of count results is transported to comparator 3B.Comparator 3B compares mutually count value S5 and the comparison value S6 from counter 3A.If count value S5 is less than comparison value S6, so, the value that comparator 3B produces above-mentioned first state of indication is the comparison signal S7 of " 0 ", and it is transported to selector 2.
As shown in Figure 3, at moment t0, the count value of counter 3A is eliminated, and its output becomes " 0 ".Because comparison signal S7 is " 0 ", selector 2 output frequency division signal S2 are as clock signal S4.
At moment t1, reference clock S1 becomes " 1 ", and fractional frequency signal S2 also becomes " 1 ".At moment t2, reference clock becomes " 1 ", and fractional frequency signal S2 becomes " 0 ", and at the pulse trailing edge edge, counter 3A counting is upgraded to " 1 ".
At moment t3, when reference clock S1 becomes " 1 ", fractional frequency signal S2, S3 also become " 1 ".At moment t4, reference clock S1 becomes " 1 ", and fractional frequency signal S2 becomes " 0 ", and at the pulse trailing edge edge of fractional frequency signal S2, counter 3A counting is upgraded to " 2 ".
At moment t5 to t7, repeat same operation.
At moment t8, the count value S5 of counter 3A is increased to " 4 ", surpasses comparison value S6, and just " 3 ", comparator 3B just produces the comparison signal S7 of the value of above-mentioned second state of indication for " 1 ", and is transported to selector 2.According to comparison signal S7, selector 2 output frequency division signal S3 are as frequency-dividing clock S4.
At moment t16, the count value S5 of frequency-dividing clock S4 overflows, and counter 3A removes count value S5 becomes " 0 ", and begins frequency-dividing clock S4 is counted from initial condition.Therefore, count value S5 becomes " 3 " less than comparison value S6, and the value that comparator 3B produces indication first state is the comparison signal S7 of " 0 ".
After this, according to comparison signal S7, repeatedly at the first state output frequency division signal S2, at the second state output frequency division signal S3 from comparator 3B.
Therefore, at first state fractional frequency signal S2, produce frequency-dividing clock S4 at second state with fractional frequency signal S3, this clock S4 is by getting the available formula of frequency dividing ratio (hereinafter referred to as frequency division value) (1) expression to reference clock S1 frequency division:
Frequency division value=CLK1 (COP1/CON1)+CLK2 (1-(COP1/CON1)) ... (1)
In formula (1), " CLK1 " is the frequency division value of fractional frequency signal S2, and " CLK2 " is the frequency division value of fractional frequency signal S3.
" CON1 " is the overflow value of counter 3A.When counter 3A was m-1 full scale counter, " CLK1 " became value " m "." COP1 " is comparison value S6.When setting comparison value S6 is " a " and when being initial value with " 0 ", and " COP1 " becomes value " a+1 ".For example, when " 3 " were set to comparison value S6, " COP1 " was " 4 ".
Under the situation of Fig. 3, because fractional frequency signal S2 is by obtaining with 2 frequency division reference clock S1, the value of " CLK1 " is 2, by with 4 frequency division reference clock S1 acquisition fractional frequency signal S3.Because counter 3A is a 6-full scale counter, the value of " CON1 " is " 6 ".In addition, because under the situation of Fig. 3, for rating unit 3C, " 3 " are set to comparison value, " COP1 " becomes numerical value " 4 ".On the basis of these values, the frequency division value under Fig. 3 situation can obtain with formula (1), and is as follows:
Frequency division value=2 * 4/6+4 (1-4/6)=16/6
For example, fractional frequency signal S2 gets with 41 frequency division 48MHz reference clocks, and fractional frequency signal S3 is got by the same reference clock S1 of 42 frequency divisions, and supposes that counter 3A is a 3-full scale counter, supposes that again comparison value S6 is " 0 ".
Frequency dividing ratio=41 * 1/3+42 (1-1/3)=41.66666
When 48MHz pressed frequency division value by frequency division, the average frequency of frequency-dividing clock S4 was as follows:
Average frequency=48/41.66666=1.152000
Have again, as previously mentioned,, can utilize the frequency divider of knowing, 48MHz is made 12 frequency divisions and gets for producing the frequency of 4MHz.Therefore, can be according to a reference clock, and easily obtain two kinds of transmission speeds.
According to present embodiment, the frequency of frequency-dividing clock S4 can change by the comparison value S6 that is arranged among the comparing section 3C, therefore, can use the method to reference clock S1 frequency division to obtain desired frequency.Also have, the frequency of reference clock S1 can be changed, and can utilize the commodity quartz (controlled) oscillator to produce reference clock S1.Therefore, can avoid the data transmitting equipment expense to rise.
Furtherly, because the frequency of reference clock S1 is variable, thus also can utilize the used clock of other circuit, as reference clock S1.
Here be noted that fractional frequency signal S2, the used frequency division value of S3 can be got arbitrary integer, still, the difference between these two frequency division values with smaller for well.If fractional frequency signal S2, the frequency division value of S3 are significantly different, when these signals were changed in selector 2 and exported therefrom, the unfavorable property that the variation in frequency-dividing clock S4 cycle is promptly fluctuateed had just increased.Fractional frequency signal S2, the integer that the frequency division value of S3 is preferably adjacent.Fractional frequency signal S2, the difference on the frequency between the S3 wish and can reduce very much, because do like this fluctuation are reduced.
More or less allow such fluctuation conversely speaking,, fractional frequency signal S2 allows some differences between the frequency of S3, produces fractional frequency signal S2, and the progression of the frequency divider of S3 just can reduce.
The maximum count value of counter 3A " m " is also wished can be less than the block length that sends data.The maximum count value that is provided " m " is if greater than block length, and frequency-dividing clock S4 before selector 2 is about to conversion and the error between the unborn clock can increase, so that the mistake modulation of data may take place at receiving terminal.Therefore, Zui Da count value " m " preferably divide into groups half or littler.
In this first embodiment, though as count value S5 during above the comparison value S6 among the comparator 3B, described comparison signal S6 becomes second state, if count value S5 becomes comparison value S6 or bigger, comparison signal S6 just becomes second state.Also have, although cross fractional frequency signal S2, S3 is the pulse that reference clock S1 produces when being " 1 " in one-period, and count value is eliminated at this moment, as long as the rising edge is used as clock, just can produce the pulse of duty factor 50%.
Say that further the maximum count value of counter 3A " m " and comparison value S6 can be fixed, perhaps from the setting of CPU change to them.
Fig. 4 is a block schematic diagram, the structure of expression second embodiment of the present invention frequency divider, and Fig. 5 is the oscillogram of the frequency divider of key diagram 4 when producing comparison signal.
In Fig. 4, shown frequency divider comprises: selector 2, counter 3A and 11, comparator 3B and 12 and comparing section 3C and 13, and, replace frequency dividing circuit 1, usefulness be counter 11, comparator 12 and comparing section 3C.In the drawings, with structure member identical among Fig. 1, be marked with Fig. 1 in identical label, and omit description of them.
In Fig. 4, counter 11 is n-full scale counters, be used for to reference clock S1 counting, and the count value of output " 0 " to " n-1 ".Counter 11 is transported to comparator 12 with the count value S11 of count results.Because counter 11 is n-full scale counters, so in counter 11, set a design load " n-1 " in advance.When the count value S11 of reference clock S1 and above-mentioned design load meet, pulse of counter 11 outputs, and counter 11 overflows when next clock arrives.So counter 11 is removed count value S11, begins reference clock S1 is counted from initial condition.
Count value S11 shows as sawtooth waveforms in Fig. 5 A, and further expression and expansion in Fig. 5 b.More particularly, As time goes on count value 11 changes with step-by-step system, and when count value S11 and comparison value S12 met, pulse P1 was produced.In case when next reference clock S1 imported, count value S11 was eliminated and is " 0 ".
The operation of second embodiment of the invention will be described below.When clock generator (not shown) produced reference clock S1, this reference clock S1 was input into counter 11.If shown in the 5A, 11 pairs of reference clock S1 countings of counter take place if overflow OF1, just produce the pulse P1 that the back will illustrate.Comparison value S12 sets in advance in comparing section 13, and comparing section 13 is input into comparator 12 with comparison value 12.
12 pairs of comparators compare from the count value S11 of counter 11 with from the comparison value S12 of comparing section 13.If count value S11 is less than comparison value S12, comparator 12 just produces the comparison signal of " 0 ".
After this, count value S11 increases, if count value S11 and comparison value S12 meet, 12 of comparators produce the comparison signal pulse.Comparator 12 is input into selector 2 with comparison signal, as fractional frequency signal S14.The pulse that is produced is the pulse P2 shown in Fig. 5 A, will illustrate below.
On the other hand, the comparator 3B value that will indicate above-mentioned first state is input into selector 2 for the comparison signal S7 of " 0 ".Selector 2 will be from the fractional frequency signal S13 output of counter 11, as fractional frequency signal S4 according to comparison signal S7.
About this point, 11 pairs in counter by the countings of reference clock S1 rise produce each overflow and produce pulse P1.The fractional frequency signal S13 that comprises pulse P1 is from selector 2 outputs, as frequency-dividing clock S4.
After this count value S5 of counter 3A is increased, if count value S5 surpasses comparison value S6, comparator 3B then produces the comparison signal S7 of the value of above-mentioned second state of indication for " 1 ", and it is input into selector 2.Selector 2 is according to comparison signal S7 output frequency division signal S14, as frequency-dividing clock S4.
On the other hand, comparing section 13 is provided with comparison value S12 in advance, and comparing section 13 is input into comparator 12 with comparison value S12.12 pairs of comparators compare from the count value S11 of counter 11 with from the comparison value S12 of comparing section 13.If count value S11 is less than comparison value S12, then generation value of comparator is the comparison signal of " 0 ".
After this, count value S11 increases, when count value S11 meets comparison value S12, and the such comparison signal of pulse P2 that comparator 12 produces shown in Fig. 5 (a), and the comparison signal that is produced is input into selector 2, as fractional frequency signal S14.Comparator 12 all produces pulse P2 when count value S11 and comparison value S12 meet each time.The fractional frequency signal S14 that comprises pulse P2 is from selector 2 outputs, as frequency-dividing clock S4.Simultaneously, counter 12 usefulness pulse P2 remove, the initial condition that enters it.After this, according to the comparison signal S7 from comparator 3B, at the above-mentioned first state output frequency division signal S13, at the above-mentioned second state output frequency division signal S14, produce frequency-dividing clock S4 thus, this process repeats.
Therefore, the frequency of frequency-dividing clock S4, by can obtaining reference clock S1 frequency division, its frequency division value is represented by following formula (2):
Frequency division value=(COP1CON2+COP2 (CON1-COP1))/CON1 ... (2)
In formula (2), " CON2 " is the value when removing counter 11.When counter 3A was m-full scale counter, " CON2 " became value " m "." COP2 " is comparison value S12.
According to this second embodiment, the frequency of reference clock S1 can be changed into desired frequency according to the comparison value S6 that is arranged among the comparing section 3C.Because according to the comparison value S12 that is arranged in the comparing section 13, can change regularly, with the pulse of generation fractional frequency signal 14, so, even according to comparison value S12, reference clock S1 also can change into desired frequency.
Owing to increased parameter (variable), can change frequency division value more easily than first embodiment is desirable value.
Fig. 6 is a calcspar, the structure of schematic illustration third embodiment of the present invention frequency divider; Fig. 7 is the oscillogram that the frequency divider of key diagram 6 produces comparison signal.
As shown in Figure 6, frequency divider comprises: selector 2, counter 3A and 11, comparator 3B, 12 and 21, comparing section 3C, 13 and 22.
The difference of the frequency divider of present embodiment and Fig. 4 is, has increased comparator 21 and comparing section 22 on the frequency divider of Fig. 4.With with Fig. 6 in identical label list diagrammatic sketch 1 structure member identical with Fig. 4.
As shown in Figure 6, comparing section 22 is used for producing the fractional frequency signal S22 that the back will be illustrated with comparison value S21 input comparator 21.Comparison value S21 is set in the comparing section 22 as set point.
More particularly, comparator 21 is count value S11 and comparison value S21 relatively, if count value S11 less than comparison value S21, the comparison signal that 21 generation values of comparator are " 0 ".If count value S11 meets comparison value S21,21 of comparators produce the comparison signal pulse.Therefore, comparator 21 responses are from the comparison signal 21 of comparing section 22, and regularly alternately conversion produces pulse.
Below, with reference to figure 6 and Fig. 7 the originally operation of the 3rd embodiment is described.
The clock generator (not shown) produces reference clock S1, and reference clock S1 is imported into counter 11.11 pairs of reference clocks of counter are counted, and count value is input to comparator shown in Figure 6 12 and 21.Comparator 12 utilizes count value S11, produces fractional frequency signal S14 with comparing section 13.
Comparison value S21 is set in comparing section 22 in advance, and comparing section 22 is transported to comparator 21 with comparison value S21.21 pairs of comparators compare from the count value S11 of counter 11 with from the comparison value S21 of comparing section 22.If count value S11 is less than comparison value S21, the comparison signal that 21 generation values of comparator are " 0 ".
After this, the count value S11 of counter 11 increases, if count value S11 meets comparison value S21,21 of comparators produce the comparison signal pulse.Comparator 21 is input to the terminal 2A of selector 2 with comparison signal, as fractional frequency signal S22.Consequent pulse is the pulse P3 shown in Fig. 7, and the back also will illustrate.
On the other hand, the comparator 3B value that will indicate above-mentioned first state is input to selector 2 for the comparison signal S7 of " 0 ".
As previously described, 21 couples of count value S11 of comparator and comparison value S21 compare.Count value S11 meets comparison value S21 each time, and comparator 21 produces the comparison signal of pulse P3 as shown in Figure 7.Simultaneously, with pulse P3 counter 11 is removed.Enter initial condition.
After this, if the count value S5 of counter 3A surpasses comparison value S6, i.e. S5＞S6, comparator 3B then produces the comparison signal of the value of above-mentioned second state of indication for " 1 ", and it is outputed to selector 2.
Utilize comparison signal S7, selector 2 will be from the fractional frequency signal S14 output of comparator 12, as frequency-dividing clock S4.
Again backward, in the present embodiment, repeatedly,,, produce frequency-dividing clock S4 like this with the above-mentioned second state output frequency division signal S14 with the above-mentioned first state output frequency division signal S22 according to comparison signal S7 from comparator 3B.
Therefore, the frequency of frequency-dividing clock S4 can get by the frequency division of reference clock S1, and its frequency division value is represented by formula (3).Because the quantity of parameter increases, thus frequency division value is changed into desirable value, just more convenient than second embodiment.
Frequency division value=(COP1COP3+COP2 (CON1-COP1))/CON1 ... (3)
Here, in formula (3), " COP3 " is comparison value S21.
According to present embodiment, the frequency of reference clock S1 can change by comparison value S6 and the S12 that is arranged in comparing section 3C and the comparing section 13.Because the generation time limit of the pulse of fractional frequency signal S22 can change by the comparison value S21 that is arranged on comparing section 22, so, even utilize comparison value S21, can with the frequency shift of reference clock S21 desirable frequency also.
Fig. 8 is a calcspar, simply represents the structure of the 4th embodiment frequency divider of the present invention, and Fig. 9 is the oscillogram that the expression frequency divider produces comparison signal.
As shown in Figure 8, frequency divider comprises: selector 2, counter 3A and 11, comparator 3B, 12,21 and 31, comparing section 3C, 13,22 and 32.Among Fig. 8 with Fig. 1,4, with 6 in identical structure member, be marked with identical label.In the present embodiment, comparator 31 and comparing section 32 have been increased than the fraction frequency device parts among Fig. 6.Also have, in the present embodiment, the connection of counter 3A changes to some extent, and the count value S5 that exports from counter 3A is transported to comparator 31.
Comparator 32 is input into comparator 31 with comparison value S31, the clear signal S33 that will illustrate below producing.
Comparator 31 produces comparison signal according to from the count value S5 of counter 3A with from the comparison value S31 of comparing section 32.
More particularly, 31 couples of count value S5 of comparator and comparison value S31 compare, if count value S5 less than comparison value S31, the comparison signal that 31 generation values of comparator are " 0 ".If count value S5 meets comparison value S31,31 of comparators produce the comparison signal pulse.Therefore, comparator 31 response comparison value S31 change the conversion time limit, thereby produce the comparison signal pulse.Comparator 31 is delivered to the CLR terminal of counter 3A with the comparison signal that is produced, as clear signal S33.
Below, will the operation of present embodiment be described with reference to figure 9.
The reference clock S1 that is produced by the clock generator (not shown) is transported to counter 11.11 couples of reference clock S1 of counter count, and count value S11 is transported to comparator 12,21, as shown in Figure 9.Comparator 12 utilizes counter S11, with comparing section 13, produces fractional frequency signal S14.Have, comparator 21 utilizes count value S11 again, with comparing section 13, produces fractional frequency signal S22.
On the other hand, the comparator 3B value that will indicate above-mentioned first state is transported to selector 2 for the comparison signal S7 of " 0 ".According to comparison signal S7, selector 2 will be from the fractional frequency signal S22 output of comparator 21, as frequency-dividing clock S4.
Thus, counter 3A counts fractional frequency signal S22.
After this, the count value S5 of counter 3A increases, and when count value S5 surpassed comparison value S6, the value that comparator 3B produces above-mentioned second state of indication was the comparison signal S7 of " 1 ", and it is transported to selector 2.According to comparison signal S7, selector 2 will be from the fractional frequency signal S14 output of comparator 12, as frequency-dividing clock S4.Counter 3A is the frequency-dividing clock S4 counting to being produced therefore.31 pairs of comparators compare from the comparison value S31 of comparing section 32 with from the count value S5 of counter 3A, and after count value S5 met comparison value S31, comparator 31 produced clear signals 33.
Therefore, response comparison value S31, the spacing of above-mentioned second state can change, and the number of the pulse P2 of above-mentioned second state also just can be adjusted.Like this, frequency-dividing clock S4 can be got by reference clock S1 frequency division, and its frequency division value is represented with following formula (4).
Frequency division value=(COPCOP3+COP2 (COP4-COP1))/COP4 ... (4)
In formula (4), " COP4 " is comparison value S31.
According to present embodiment, the frequency of reference clock S1 can be by being arranged on comparing section 3C, the comparison value S6 in 13 and 22, and S12 and 21 is changed and is desired frequency.Because the frequency of frequency-dividing clock S4, be to adjust, and the spacing of above-mentioned second state depend on the comparison value 31 that is arranged in the comparing section 32 by the spacing that changes above-mentioned second state, so, the frequency of reference clock S1 even can pass through comparison value S31 is changed into desired frequency.Have again, because the number of parameter increases, so frequency division value is adjusted to desired value than the 3rd embodiment is easier.
Of the present invention the first, the second, though third and fourth preferred embodiment illustrated in greater detail, concrete structure of the present invention is not limited to these, and under the situation that does not depart from requirement of the present invention, any change of design of the present invention all can realize.
For example, reference clock S1 can be produced by the clock generator that the commodity quartz (controlled) oscillator is done.Have, the clock that is used in other circuit can be used as reference clock S1 again.
According to above-mentioned the present invention, with an input clock, can produce first clock and second clock with different frequency, then, first clock and second clock be conversion alternately, and an output clock is provided.Therefore, the frequency of input clock can be transformed to desired frequency.
According to the present invention, the frequency of input clock can be transformed to desired frequency by adjusting each set point.
Therefore obviously as seen, the present invention does not limit to the foregoing description, but under the situation that does not depart from scope and spirit of the present invention, can modifications and variations.
At last, the present invention requires the priority at the Japanese patent application No.Hi10-070527 of application on March 19th, 1998.
Claims (6)
1. frequency divider is characterized in that comprising:
Frequency divider is used for producing first clock and second clock according to input clock;
Conversion equipment, its effect are when the input switching signal is indicated first state, to export first clock as the output clock from described frequency divider, and when described switching signal is indicated second state, export second clock as the output clock from described frequency divider; With
Conversion control device, its effect be, produces the described switching signal of described first state of indication or described second state, and according to the frequency from the output clock of described conversion equipment, the switching signal that produces is outputed to described conversion equipment.
2. frequency divider according to claim 1, it is characterized in that: described frequency divider carries out frequency division to described input clock, produces described first clock, and with the different numerical value of frequency division ratio that produces described first clock, described input clock is carried out frequency division, produce described second clock.
3. frequency divider according to claim 1 is characterized in that described frequency divider further comprises:
First counter when described input clock is counted and overflows, is exported the signal that indication is overflowed, as described first clock; With
First comparison means wherein sets in advance first set point, and its effect is, when the count value that detects described first counter meets described first set point, exports the signal of an indication testing result, as described second clock.
4. frequency divider according to claim 1 is characterized in that further comprising:
Second counter is used for described input clock counting;
Second comparator device wherein sets in advance second set point, and its effect is, whenever detecting described second count value when meeting described second set point, exports the signal of an indication testing result, as described first clock; With
The 3rd comparison means wherein sets in advance the 3rd set point, and its effect is, when the count value that detects described second counter meets described the 3rd set point, exports the signal of an indication testing result, as described second clock.
5. frequency divider according to claim 1 is characterized in that described conversion control device further comprises:
The 3rd counter is used for described output clock count; With
The 4th comparison means wherein sets in advance the 4th set point, and its effect is, whether meets described the 4th set point according to the count value of described the 3rd counter, produces the described switching signal of described first state of indication or described second state.
6. frequency divider according to claim 1 is characterized in that described conversion control device further comprises:
Four-counter is used for described output clock count;
The 5th comparison means wherein presets the 5th set point in advance, and its effect is, whether meets described the 5th set point according to the count value of described four-counter, produces the described switching signal of described first state of indication or described second state; With
The 6th comparison means when the count value of described four-counter meets described the 5th set point, makes described four-counter zero clearing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10070527A JPH11274917A (en) | 1998-03-19 | 1998-03-19 | Frequency divider |
| JP070527/1998 | 1998-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1235408A true CN1235408A (en) | 1999-11-17 |
Family
ID=13434103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99103070A Pending CN1235408A (en) | 1998-03-19 | 1999-03-19 | Frequency divider |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH11274917A (en) |
| KR (1) | KR100342125B1 (en) |
| CN (1) | CN1235408A (en) |
| DE (1) | DE19911945A1 (en) |
| TW (1) | TW515142B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930780B (en) * | 2004-03-11 | 2010-06-02 | Nxp股份有限公司 | Frequency divider |
| CN110545100A (en) * | 2019-09-29 | 2019-12-06 | 曹怡珺 | Low-power-consumption traveling wave frequency division circuit |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3870942B2 (en) * | 2003-10-20 | 2007-01-24 | ソニー株式会社 | Data transmission system and data transmission apparatus |
| DE102004006398B4 (en) | 2004-02-10 | 2006-06-08 | Atmel Germany Gmbh | Method and device for synchronizing a functional unit to a predetermined clock frequency |
| US7379723B2 (en) | 2004-07-29 | 2008-05-27 | Silicon Laboratories Inc. | Local oscillator and mixer for transceiver |
| CN102412836B (en) * | 2011-09-30 | 2013-03-27 | 杭州电子科技大学 | Dual programmable subtraction frequency divider |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222514A (en) * | 1990-01-26 | 1991-10-01 | Kanzaki Paper Mfg Co Ltd | Pulse signal generating circuit |
-
1998
- 1998-03-19 JP JP10070527A patent/JPH11274917A/en active Pending
-
1999
- 1999-03-16 TW TW088104025A patent/TW515142B/en not_active IP Right Cessation
- 1999-03-17 DE DE19911945A patent/DE19911945A1/en not_active Ceased
- 1999-03-19 CN CN99103070A patent/CN1235408A/en active Pending
- 1999-03-19 KR KR1019990009344A patent/KR100342125B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930780B (en) * | 2004-03-11 | 2010-06-02 | Nxp股份有限公司 | Frequency divider |
| CN110545100A (en) * | 2019-09-29 | 2019-12-06 | 曹怡珺 | Low-power-consumption traveling wave frequency division circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW515142B (en) | 2002-12-21 |
| KR100342125B1 (en) | 2002-06-26 |
| KR19990078065A (en) | 1999-10-25 |
| JPH11274917A (en) | 1999-10-08 |
| DE19911945A1 (en) | 1999-09-30 |
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