WO2011050693A1 - Locking system and method thereof - Google Patents
Locking system and method thereof Download PDFInfo
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- WO2011050693A1 WO2011050693A1 PCT/CN2010/078003 CN2010078003W WO2011050693A1 WO 2011050693 A1 WO2011050693 A1 WO 2011050693A1 CN 2010078003 W CN2010078003 W CN 2010078003W WO 2011050693 A1 WO2011050693 A1 WO 2011050693A1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Definitions
- the present invention relates to the fields of communication, navigation, and spectrum measurement, and more particularly to a locking system and method.
- the locking accuracy of the phase-locked loop must be high enough.
- the higher the phase-locking accuracy the frequency difference between the locked source and the standard source. The smaller, the easier it is to achieve synchronization between systems.
- the phase-locked loop must be able to achieve fast locking.
- the faster the phase-locked loop locks the faster the locked source can be locked with the standard source.
- the tracking is locked by the source to achieve synchronization.
- the phase-locked loop circuit can improve the short-term stability of the local source output frequency, and the frequency output accuracy, especially the long-term stability improvement is particularly obvious.
- the phase-locked loop can maintain a good short-term stability of the local constant temperature crystal oscillator, and since the local constant temperature crystal oscillator is kept in sync with the atomic clock in the navigation system, the long-term stability of the local constant temperature crystal oscillator can be Basically maintain the level of the atomic clock in the navigation system. This maintains good short-term stability of the oven controlled crystal oscillator, and the constant temperature crystal oscillator achieves better long-term stability close to the atomic clock level due to locking. Due to the locking with the atomic clock, its short-term stability can also be improved to some extent.
- phase-locked loops use a frequency divider to sum and signal the complex frequency conversion line. The road is transformed into the same lower frequency signal and then phase-detected.
- the principle is shown in Figure 1.
- phase-locked loops are mainly divided into two types: analog phase-locked loops and digital phase-locked loops.
- the analog phase-locked loop is the earliest phase-locked loop that has been widely used.
- the analog phase-locked loop has the characteristics of high phase-locking precision.
- the low-pass filter and voltage-controlled oscillator of the analog phase-locked loop circuit are analog circuits, which have the disadvantages of charge drift, aging of components, and unstable parameters.
- the analog phase-locked loop was widely used in various fields due to its high phase-locking accuracy.
- digital circuits are developing at a high speed, and digital circuits are being used in more and more fields. It can be said that digital circuits are almost ubiquitous.
- the use of an analog phase-locked loop to lock some digital signals requires corresponding digital conversion processing of the analog circuit, which increases the complexity of the phase-locked loop circuit. Therefore, the application of the analog phase-locked loop in some digital circuits is affected. limit.
- the digital phase-locked loop can be directly applied to modern digital circuits without first embedding the digital signal and then using the analog phase-locked loop to lock, but the traditional digital phase-locked loop also has the following problems:
- the lock time is long.
- the traditional digital phase-locked loop is used to divide the frequency first, and then the signal with the phase error passing through the filter is used to control the constant temperature crystal oscillator. It can be seen from the loop formula of the phase-locked loop that the phase-locked process of the traditional phase-locked loop is an oscillation convergence process, and the locking time is relatively long due to the repeated process of convergence.
- phase-locking accuracy is relatively high.
- DDS Direct Digital Synthesizer
- the phase-locking accuracy is affected by the DDS resolution, so the phase-locking accuracy is not high enough.
- phase-locked loops are increasingly used in applications such as SDH (Synchronous Digital Hierarchy) communication, navigation and high-precision measurement.
- SDH Serial Digital Hierarchy
- SDH communication which requires fast local source frequency output and consistent with standard source frequency output, it not only requires fast locking of local source and standard source, but also requires high precision and fast locking.
- the invention provides a locking system and method, which greatly increases the locking speed of the phase lock, and the lock The phase accuracy is also significantly improved.
- the present invention discloses a locking system including a digital phase detecting and converting unit, a digital loop filtering unit and a digital voltage controlled oscillating unit which are sequentially connected, wherein:
- the digital phase detector and conversion unit is configured to input a divided standard external source input signal and a feedback output signal F of the local oven controlled crystal oscillator.
- a phase discrimination and conversion process is performed to generate a clock signal elk and to represent the signal and signal F.
- a signal sign of a frequency relationship between the numbers; the digital loop filtering unit is configured to filter the signal elk and the signal sign to generate a signal F.
- the frequency of the signal is less than the frequency of the signal and is used to represent the signal F. a signal having a frequency greater than the frequency of the signal lag;
- the digital voltage-controlled oscillating unit is configured to perform a voltage-controlled oscillating process on the signal ahead and the signal lag generated after the filtering process to achieve locking of the signal F 0 and the signal Fi.
- the digital phase discrimination and conversion unit may include a digital phase detector and a conversion module, wherein: the digital phase detector may be configured to perform phase discrimination processing on the signal Fi and the signal F 0 to generate the signal Fi and the signal F.
- the pulse signal error of the phase relationship between the two; the conversion module can be configured to calculate the monthly value of the pulse signal error according to the count signal count, and generate the representation signal ⁇ and the signal.
- the signal sign between the frequency relationship and the signal equ nequ indicating whether the adjacent pulse widths are equal, and then processing the signal equ nequ with the signal to generate the clock signal elk; the counting signal count can be realized by the time interval calculation method
- the signal sign can represent the signal and the signal F by the magnitude relationship of the adjacent pulse widths in the pulse signal error. The relationship between frequency and size.
- the digital voltage controlled oscillating unit may include a digital to analog (DA) converter and a digital voltage controlled oscillator; the DA converter may be configured to receive signals ahead and lag output by the digital loop filtering unit, and control the DA by using the received signal The converter performs digital-to-analog conversion and then transmits it to the digital voltage-controlled oscillator.
- the digital voltage-controlled oscillator can be set to perform voltage-controlled oscillation processing on the signal transmitted by the DA converter.
- the digital voltage controlled oscillating unit may include a pulse width modulation (PWM) module and a digital voltage controlled oscillator;
- PWM pulse width modulation
- the PWM module may be configured to: generate a PWM wave with a constant period and a high pulse width, and utilize a digital ring The signals ahead and lag output by the path filtering unit pulse-modulate the PWM wave pair, and transmit the pulse width modulated signal to the digital voltage controlled oscillator;
- the digital voltage controlled oscillator can be set to perform signal transmission on the PWM module Voltage controlled oscillation processing.
- PWM module can be locked by The processor of the field programmable gate array or programmable logic device in the system is implemented by timing setting.
- the invention also discloses a locking method, comprising:
- the locking system first inputs the divided external standard source input signal and the feedback output signal F of the local oven-controlled crystal oscillator. Phase discrimination and conversion processing is performed to generate a clock signal elk and to represent the signal and signal F.
- the signal sign between the frequency magnitude relationship is filtered, and the signal elk and the signal sign are filtered, and the signal generated by the filtering process is used to represent the signal F.
- the frequency of the signal is less than the frequency of the signal and is used to represent the signal F.
- the signal lag having a frequency greater than the frequency of the signal is subjected to voltage-controlled oscillation processing to realize the signal F. Locked with the signal.
- the locking system will pass the divided signal and signal F.
- Phase discrimination and conversion processing is performed to generate a clock signal elk and to represent the signal and signal F.
- the relationship between the frequency magnitude of the signal sign can include: locking the system pair signal and signal F.
- the phase discrimination process is first performed to generate a signal and a signal F.
- the pulse signal error between the phase relationships is calculated according to the count signal count, and the representation signal ⁇ and the signal are generated.
- the locking system can use the signals generated by the filtering process to control the digital-to-analog conversion and then perform the voltage-controlled oscillation processing.
- the locking system may perform pulse width modulation on the pulse width modulation (PWM) wave using the signals ahead and lag generated after the filtering process, and then perform voltage controlled oscillation processing.
- PWM pulse width modulation
- the PWM wave can be a PWM wave with adjustable period and high pulse width adjustable by the timer of the field programmable gate array or programmable logic device in the locking system.
- the technical solution of the invention avoids the oscillation convergence process of the traditional phase-locked loop during the locking process, so that fast and high-precision locking can be realized.
- the technical solution of the present invention reduces the circuit area and reduces the circuit cost.
- Figure 1 is a schematic diagram of the principle of a conventional phase-locked loop
- Embodiment 2 is a schematic diagram of the principle of the phase locked loop proposed in Embodiment 1;
- FIG. 3 is a schematic block diagram showing the connection of a DA converter and a CPLD in Embodiment 1;
- Embodiment 4 is a schematic diagram of an interface of a digital phase difference detector in Embodiment 1;
- Embodiment 5 is a simulation waveform diagram of an output signal of the digital phase difference detector in Embodiment 1;
- FIG. 6 is a partial circuit diagram of a conversion module in the digital phase discrimination and conversion unit in Embodiment 1;
- FIG. 7 is a simulation waveform diagram of an output signal of the digital phase discrimination and conversion unit in Embodiment 1;
- FIG. 8 is a principle of DLF in Embodiment 1. Schematic diagram
- Figure 9 is a simulation waveform diagram of the output signal of the DLF shown in Figure 8.
- Figure 10 is a schematic diagram showing the principle of the DCO in the first embodiment.
- a digital phase-locked loop can be realized by using a digital phase-detecting and converting unit, a digital loop filtering unit and a digital voltage-controlled oscillating unit, thereby realizing fast locking, wherein the digital phase-detecting and converting unit can Directly determine the relationship between the frequency of the local output signal and the nominal frequency, avoid the oscillation convergence process of the traditional phase-locked loop during the locking process, and the digital circuit in the digital phase-detection and conversion unit can be integrated into the FPGA (on-site Programming gate arrays) or CPLDs (complex programmable logic devices).
- FPGA on-site Programming gate arrays
- CPLDs complex programmable logic devices
- the digital voltage-controlled oscillating unit can first perform digital-to-analog conversion on the digital signal through a DA (digital-to-analog converter) or a pulse width modulation (PWM) module, and then perform voltage-controlled oscillation processing.
- DA digital-to-analog converter
- PWM pulse width modulation
- a fast high-precision locking system comprising at least a digital phase-detecting and converting unit, a digital loop filtering unit and a digital voltage-controlled oscillating unit.
- the digital phase detecting and converting unit is configured to perform phase discrimination and conversion processing on the frequency-divided external standard source input signal and the frequency-divided local constant temperature crystal oscillator feedback output signal F 0 to generate a clock signal elk and to represent Signal and signal F. Signal sign between frequency and size relationships;
- the digital phase discrimination and conversion unit may further include a digital phase difference detector (DPD) and a conversion module;
- DPD digital phase difference detector
- the DPD can phase-detect the input signals Fi and F 0 to display the phase relationship between the signal and the signal F 0 , that is, the signal F. Whether the phase is lagging or leading with respect to the phase of the signal, and the time of lag or lead, as shown in Fig. 5, specifically, the signal F. And respectively connected to the clr and set ports of the digital phase detector shown in Figure 4, the output signal is the pulse width error signal error of the two input signals, the signal error represents the signal and the signal F. The phase relationship between them.
- the conversion module can logically judge the output signal of the DPD to obtain the two input signals F of the phase locked loop.
- the frequency relationship between and. The module can use the error signal generated by the DPD and the count signal count generated by the TDC (time interval calculation mode) to output a signal equ_nequ representing whether the adjacent pulse widths are equal and a signal sign of two adjacent pulse width relationships (ie, A signal indicating the magnitude relationship between the signal and the signal F.).
- the equ_nequ sum can be used to control the clock signal of the DLF through the AND gate.
- the elk, elk signal is the input clock signal of the random ⁇ filter.
- the elk signal counts up and down in response to the internal signal of the random chirp filter according to the sign signal when equ_nequ is not 0 (when the two input signal frequencies of the locking system are not equal);
- Figure 6 shows That is, a circuit diagram for generating a signal sign and a signal equ_nequ in the conversion module, thereby comparing the pulse widths of adjacent errors to generate a signal sign.
- a high-speed clock is used to count the error signal generated by the DPD. The wider the error signal (ie, the larger the pulse width), the larger the count value will be.
- the smaller the error signal ie, the larger the pulse width
- the count signal count that is, the pulse width count value of the error signal
- TDC Time Interval Calculation
- the digital loop filter unit can be implemented by a digital loop filter (DLF), which mainly filters the signals output by the digital phase detector and the conversion unit, that is, removes some accidental factors to achieve the purpose of digital filtering, that is, the digital loop filter unit.
- DPF digital loop filter
- the control loop filter operates when the two frequency signals are not equal, thereby generating a control digital voltage controlled oscillation unit Signals head and lag;
- the DLF uses a random chirp filter, and its structure is as shown in FIG. 8. It includes an up or down counter (U/D_CNT) and a comparator (CMP), and the clock signal is used by the phase detector unit.
- the output elk, the direction of adding or subtracting the count is determined by the output sign of the trigger type phase detector. When the sign is high, the counter is added and accumulated, and vice versa.
- the counter initial value d[3:0] is loaded by the comparator. When the counter output q[3..0] reaches m+k or mk, the comparator generates the load signal Id (active low) and loads m to the counter.
- the random chirp filter plays an important role in the loop, and it can filter out the edge detection pulse and the leading lag pulse caused by the glitch generated in the transmission.
- the larger the value of k is selected the better the filtering effect is, but the locking speed of the whole loop is reduced. Therefore, a suitable k value should be selected, which is neither too large nor too small, and needs to be verified by experiments. to make sure.
- the digital voltage controlled oscillating unit is arranged to logically process the signal ahead and signal lag generated after the filtering process to implement the signal F.
- the digital voltage controlled oscillation unit may further include a digital to analog (DA) converter and a digital voltage controlled oscillator (DCO), as shown in FIG. 10;
- DA digital to analog
- DCO digital voltage controlled oscillator
- the digital-to-analog (DA) converter mainly processes the increase and decrease signals outputted by the digital loop filter unit, and the increase/decrease signal can control the voltage output signal of the DA converter to be correspondingly increased or decreased, that is, when the head When the signal is valid, F is indicated. Less than .
- the phase controller changes the input value of the DA converter by increasing the value of int_d, and the voltage of the DA converter is also increased accordingly, thereby reducing the output frequency of the constant temperature crystal oscillator and adjusting F.
- the lag signal and the response clock signal are valid, the DA converter input value is decreased;
- the DA converter selected in this embodiment is the AD9777, which is a high-speed digital-to-analog converter with a conversion rate of up to 400 MSPS, which has many advantages such as high speed and low power consumption.
- Figure 3 shows the circuit principle of the interface between the AD9777 and the CPLD.
- the DLF unit of the EPM240T100C5 outputs the conversion control signals ahead and lag required by the AD9777.
- the AD9777 increases or decreases the output voltage of the DA converter according to the control signal.
- the DA conversion time is controlled by the clock CLK, and the CLK uses the TDC (time between Separate counting)
- the high-speed sampling clock that counts the error signal, the clock CLK frequency is chosen to be 10MHz. In this system, the clock CLK controls the conversion speed of the DA converter.
- an operational amplifier can be connected after the DA converter.
- the op amp ensures that the output voltage of the DA converter is converted to the voltage control range required for the digital voltage controlled oscillator.
- the digital voltage controlled oscillator mainly performs voltage controlled oscillation processing on the voltage output of the DA converter, so that the increase or decrease of the voltage output of the DA converter reflects that the crystal oscillator becomes the increase and decrease of the output frequency of the constant temperature crystal oscillator.
- the constant temperature crystal oscillator can finally reach the lock with the standard frequency source;
- the local output frequency is expressed as F.
- the nominal frequency is expressed as .
- the digital phase discrimination and conversion unit compares the two input signals with F. a rising edge, obtaining a lead or lag signal sign and a pulse control signal elk for the digital loop filtering unit; the digital loop filtering unit smoothing the error signal by using the sign and elk signals, and generating a control in the digital voltage controlled oscillating unit
- the input of the DA converter adds the signal ahead and the input reduced signal lag; thereby increasing or decreasing the input of the DA converter to control the increase or decrease of the DCO voltage control terminal voltage signal to increase or decrease F.
- the purpose of the frequency Feedback adjustments throughout the loop can ultimately reach Fi and . locking.
- the digital voltage-controlled oscillating unit includes a PWM module, and the PWM wave is used to implement the function realized by the DA converter in Embodiment 1.
- the PWM module can be implemented by using a built-in processor core of the FPGA (or CPLD) of the locking system, even if the processor core built in the FPGA (or CPLD) outputs a period constant and the high-level pulse width is adjustable by timing action ( That is, the high-frequency duty cycle is adjustable) of the PWM wave.
- the built-in processor core of the FPGA (or CPLD) receives the increase and decrease signals output from the digital loop filter unit, and accordingly increases and decreases the high-level width of the PWM wave according to the increase and decrease signal (ie, correspondingly increases according to the increase and decrease signals).
- the PWM wave output by the FPGA is passed through the RC low-pass filter and then connected to the voltage-controlled input terminal of the digital voltage-controlled oscillator, and the PWM pulse high-level pulse width is changed.
- the output voltage of the low-pass filter can be changed, and the digital voltage-controlled oscillation unit
- the voltage control terminal also changes accordingly, achieving the purpose of changing the constant temperature crystal oscillator, so that the frequency output of the constant temperature crystal oscillator and the standard source are finally locked.
- implementation case 2 to implement the locking system can reduce the volume occupied by the system and save relatively expensive high-precision DA converters. Since the implementation case 2 utilizes the embedded core in the FPGA, the phase detector, the digital loop filter, and the PWM wave logic circuit in the phase-locked loop can be fully integrated into the FPGA, thereby saving system peripheral circuits. Complexity, reducing circuit area, but also achieving cost reduction.
- the technical solution of the present invention improves the phase difference detector, and the improved phase detector can directly judge the frequency relationship between the two input signals, thereby avoiding the traditional phase-locked loop in the locking process.
- the oscillation convergence process allows for fast locking.
- the high-precision DA converter is connected to the constant temperature crystal oscillator, and high-precision locking can be realized;
- the configuration processor in the FPGA is used to output the PWM wave, and then the PWM wave is made.
- the low-pass filter the low-pass filter output voltage is applied to the input of the constant-temperature crystal oscillator to achieve high-precision locking.
- the technical solution of the present invention avoids the oscillation convergence process of the traditional phase-locked loop during the locking process, so that fast and high-precision locking can be realized.
- the technical solution of the present invention reduces the circuit area and reduces the circuit cost.
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Abstract
A locking method and system thereof are provided by the present invention, wherein the method includes the following steps: first, the locking system performs phase discrimination and conversion processing for a frequency-divided external standard source input signal Fi and a frequency-divided local oven controlled crystal oscillator feedback output signal F0, to generate a clock signal clk and a signal sign which is used to denote the frequency relationship between the signal Fi and the signal F0, second, performs the filtering processing for the signal clk and sign, and then, performs the voltage controlled oscillation processing for a signal ahead and lag to implement the locking for the signal F0 and Fi, wherein, the signal ahead and lag are generated after the filtering processing, the signal ahead is used to denote the frequency of the signal F0 is lower than that of the signal Fi, and the signal lag is used to denote the frequency of the signal F0 is higher than that of the signal Fi. The present invention can implement the fast and high precision locking, reduce the circuit area, and save the circuit cost.
Description
一种锁定***及方法 Locking system and method
技术领域 Technical field
本发明涉及通信、 导航和频谱测量等领域, 尤其涉及一种锁定***及方 法。 The present invention relates to the fields of communication, navigation, and spectrum measurement, and more particularly to a locking system and method.
背景技术 Background technique
随着电子技术的飞速发展, 通信、 导航、 航天、 测控、 高精密测量和移 动电话等领域对频率源的短期稳定度、 长期稳定度和老化率等一些指标的要 求越来越高。 现代通信技术快速发展的今天, 各种通信***对时间频率的同 步要求也越来越高。 现在很多高稳定度、 高准确度和良好老化率的频率输出 都利用高精密的锁相环实现, 利用高精密锁相环可以实现本地输出频率和标 称频率的快速高精度锁定, 锁相可以使一个频率指标相对于标准源较低的本 地源的各项频率指标得到明显的改善。 锁相环的锁定快慢及其精度是我们衡 量锁相环指标的基础: 首先锁相环的锁定精度必须足够高, 锁相精度越高, 被锁源与标准源之间频率锁定时的频率差异越小, 越容易实现***之间的同 步。 其次锁相环必须可以实现快速锁定, 锁相环锁定速度越快, 被锁源就可 以和标准源越快的实现锁定, 越快的实现通信***频率源之间的频率同步, 就可以越快的跟踪被锁源来实现同步。 With the rapid development of electronic technology, the requirements for short-term stability, long-term stability and aging rate of frequency sources are increasing in the fields of communication, navigation, aerospace, measurement and control, high-precision measurement and mobile phones. Today, with the rapid development of modern communication technologies, the synchronization requirements of various communication systems for time and frequency are also increasing. Now many high-stability, high-accuracy and good-aging frequency outputs are realized with high-precision phase-locked loops. High-precision phase-locked loops enable fast and high-precision locking of local output frequencies and nominal frequencies. A frequency index is significantly improved relative to the frequency indicators of the local source with a lower standard source. The locking speed of the phase-locked loop and its accuracy are the basis of our measurement of the phase-locked loop index. First, the locking accuracy of the phase-locked loop must be high enough. The higher the phase-locking accuracy, the frequency difference between the locked source and the standard source. The smaller, the easier it is to achieve synchronization between systems. Secondly, the phase-locked loop must be able to achieve fast locking. The faster the phase-locked loop locks, the faster the locked source can be locked with the standard source. The faster the frequency synchronization between the communication system frequency sources, the faster. The tracking is locked by the source to achieve synchronization.
锁相环电路可以改善本地源输出频率的短期稳定度, 频率输出精度, 特 别是其长期稳定度的改善尤其明显。 在导航等领域, 锁相环可以使本地的恒 温晶体振荡器保持良好的短期稳定度, 而且由于本地恒温晶体振荡器时刻与 导航***中原子钟保持同步, 所以本地恒温晶体振荡器的长期稳定度可以基 本保持在导航***中原子钟的水平。 这样既可以保持恒温晶体振荡器的良好 短期稳定度, 而且恒温晶体振荡器由于锁定可以获得更好的接近于原子钟水 平的长期稳定度。 由于与原子钟的锁定, 所以其短期稳定度也可以得到一定 程度的改善。 The phase-locked loop circuit can improve the short-term stability of the local source output frequency, and the frequency output accuracy, especially the long-term stability improvement is particularly obvious. In the field of navigation, the phase-locked loop can maintain a good short-term stability of the local constant temperature crystal oscillator, and since the local constant temperature crystal oscillator is kept in sync with the atomic clock in the navigation system, the long-term stability of the local constant temperature crystal oscillator can be Basically maintain the level of the atomic clock in the navigation system. This maintains good short-term stability of the oven controlled crystal oscillator, and the constant temperature crystal oscillator achieves better long-term stability close to the atomic clock level due to locking. Due to the locking with the atomic clock, its short-term stability can also be improved to some extent.
传统的 PLL (锁相环)都是用分频器将 和 ,信号经复杂的频率变换线
路, 变换成相同的较低频信号后再进行鉴相, 其原理如图 1所示。 目前锁相环主要分为两种: 模拟锁相环和数字锁相环, 模拟锁相环是最 早获得广泛应用的锁相环, 模拟锁相环具有锁相精度高的特点。 模拟锁相环 电路的低通滤波器和压控振荡器都是模拟电路, 存在电荷漂移、 元器件易老 化、 参数不稳定等缺点。 Traditional PLLs (phase-locked loops) use a frequency divider to sum and signal the complex frequency conversion line. The road is transformed into the same lower frequency signal and then phase-detected. The principle is shown in Figure 1. At present, phase-locked loops are mainly divided into two types: analog phase-locked loops and digital phase-locked loops. The analog phase-locked loop is the earliest phase-locked loop that has been widely used. The analog phase-locked loop has the characteristics of high phase-locking precision. The low-pass filter and voltage-controlled oscillator of the analog phase-locked loop circuit are analog circuits, which have the disadvantages of charge drift, aging of components, and unstable parameters.
在数字锁相环未出现之前, 模拟锁相环由于其高的锁相精度被广泛应用 于各个领域。 现在数字电路高速发展, 越来越多的领域都在使用数字化电路, 可以说数字电路几乎无处不在。 在一些数字电路中立用模拟锁相环锁定一些 数字信号需要对模拟电路进行相应数字变换处理, 这样会增加锁相环电路的 复杂度, 所以模拟锁相环在一些数字电路中的应用便受到了限制。 Before the digital phase-locked loop did not appear, the analog phase-locked loop was widely used in various fields due to its high phase-locking accuracy. Nowadays, digital circuits are developing at a high speed, and digital circuits are being used in more and more fields. It can be said that digital circuits are almost ubiquitous. In some digital circuits, the use of an analog phase-locked loop to lock some digital signals requires corresponding digital conversion processing of the analog circuit, which increases the complexity of the phase-locked loop circuit. Therefore, the application of the analog phase-locked loop in some digital circuits is affected. limit.
数字锁相环则可以直接应用在现代的数字电路中, 不用先将数字信号模 拟化后再利用模拟锁相环来锁定, 但是传统的数字锁相环也存在如下一些问 题: The digital phase-locked loop can be directly applied to modern digital circuits without first embedding the digital signal and then using the analog phase-locked loop to lock, but the traditional digital phase-locked loop also has the following problems:
1.锁定时间长, 传统数字锁相环是釆用先分频, 然后利用相位误差经过 滤波器后的信号来控制恒温晶体振荡器的。 从锁相环的环路公式可以看出, 传统锁相环的锁相过程是一个振荡收敛过程, 由于存在收敛的反复过程, 所 以锁定时间比较长。 1. The lock time is long. The traditional digital phase-locked loop is used to divide the frequency first, and then the signal with the phase error passing through the filter is used to control the constant temperature crystal oscillator. It can be seen from the loop formula of the phase-locked loop that the phase-locked process of the traditional phase-locked loop is an oscillation convergence process, and the locking time is relatively long due to the repeated process of convergence.
2.锁相精度相对不够高, 对于利用 DDS ( Direct Digital Synthesizer, 数字 频率合成器)等实现的全数字锁相环, 其锁相精度受到 DDS分辨率的影响, 因此锁相精度不够高。 2. The phase-locking accuracy is relatively high. For the all-digital phase-locked loop realized by DDS (Direct Digital Synthesizer), the phase-locking accuracy is affected by the DDS resolution, so the phase-locking accuracy is not high enough.
综上所述, 锁相环越来越广泛的应用于像 SDH ( Synchronous Digital Hierarchy, 同步数字体系)通讯,导航和高精度测量等领域。特别是在像 SDH 通讯等需要本地源频率输出快速的与标准源频率输出保持一致的高精密通信 领域, 其不仅要求可以实现本地源和标准源快速锁定, 而且要求可以实现高 精密快速的锁定。 In summary, phase-locked loops are increasingly used in applications such as SDH (Synchronous Digital Hierarchy) communication, navigation and high-precision measurement. Especially in the field of high-precision communication, such as SDH communication, which requires fast local source frequency output and consistent with standard source frequency output, it not only requires fast locking of local source and standard source, but also requires high precision and fast locking.
发明内容 Summary of the invention
本发明提供一种锁定***及方法, 使锁相的锁定速度大幅提高, 而且锁
相精度也明显提高。 The invention provides a locking system and method, which greatly increases the locking speed of the phase lock, and the lock The phase accuracy is also significantly improved.
为了解决上述问题, 本发明公开了一种锁定***, 包括依次连接的数字 鉴相及转换单元、 数字环路滤波单元以及数字压控振荡单元, 其中: In order to solve the above problems, the present invention discloses a locking system including a digital phase detecting and converting unit, a digital loop filtering unit and a digital voltage controlled oscillating unit which are sequentially connected, wherein:
所述数字鉴相及转换单元设置成将经过分频的外部标准源输入信号 和 本地的恒温晶体振荡器的反馈输出信号 F。进行鉴相及转换处理, 以生成时钟 信号 elk以及用于表示所述信号 和信号 F。之间的频率大小关系的信号 sign; 所述数字环路滤波单元设置成将所述信号 elk和信号 sign进行滤波处理, 生成用于表示信号 F。的频率小于信号 的频率的信号 ahead和用于表示信号 F。的频率大于信号 的频率的信号 lag; The digital phase detector and conversion unit is configured to input a divided standard external source input signal and a feedback output signal F of the local oven controlled crystal oscillator. A phase discrimination and conversion process is performed to generate a clock signal elk and to represent the signal and signal F. A signal sign of a frequency relationship between the numbers; the digital loop filtering unit is configured to filter the signal elk and the signal sign to generate a signal F. The frequency of the signal is less than the frequency of the signal and is used to represent the signal F. a signal having a frequency greater than the frequency of the signal lag;
所述数字压控振荡单元设置成将滤波处理后生成的信号 ahead和信号 lag 进行压控振荡处理, 以实现所述信号 F0与所述信号 Fi的锁定。 The digital voltage-controlled oscillating unit is configured to perform a voltage-controlled oscillating process on the signal ahead and the signal lag generated after the filtering process to achieve locking of the signal F 0 and the signal Fi.
数字鉴相及转换单元可包括数字参差鉴相器和转换模块, 其中: 数字参 差鉴相器可设置成对信号 Fi和信号 F0进行鉴相处理 , 生成用于表示信号 Fi和 信号 F。之间的相位关系的脉冲信号 error; 转换模块可设置成根据计数信号 count计算脉冲信号 error的月永覔, 生成表示信号^和信号 。之间的频率大小 关系的信号 sign, 以及表示相邻脉宽是否相等的信号 equ nequ, 再将信号 equ nequ与信号 进行与处理, 生成时钟信号 elk; 计数信号 count可以釆用时间 间隔计算方式实现,信号 sign可以通过脉冲信号 error中相邻脉宽的大小关系 以表示信号 和信号 F。之间的频率大小关系。 The digital phase discrimination and conversion unit may include a digital phase detector and a conversion module, wherein: the digital phase detector may be configured to perform phase discrimination processing on the signal Fi and the signal F 0 to generate the signal Fi and the signal F. The pulse signal error of the phase relationship between the two; the conversion module can be configured to calculate the monthly value of the pulse signal error according to the count signal count, and generate the representation signal ^ and the signal. The signal sign between the frequency relationship and the signal equ nequ indicating whether the adjacent pulse widths are equal, and then processing the signal equ nequ with the signal to generate the clock signal elk; the counting signal count can be realized by the time interval calculation method The signal sign can represent the signal and the signal F by the magnitude relationship of the adjacent pulse widths in the pulse signal error. The relationship between frequency and size.
数字压控振荡单元可包括数模(DA )转换器和数字压控振荡器; 该 DA 转换器可设置成接收数字环路滤波单元输出的信号 ahead和 lag, 利用所接收 的信号控制所述 DA转换器进行数模转换后传送给数字压控振荡器; 数字压 控振荡器可设置成对 DA转换器传送的信号进行压控振荡处理。 The digital voltage controlled oscillating unit may include a digital to analog (DA) converter and a digital voltage controlled oscillator; the DA converter may be configured to receive signals ahead and lag output by the digital loop filtering unit, and control the DA by using the received signal The converter performs digital-to-analog conversion and then transmits it to the digital voltage-controlled oscillator. The digital voltage-controlled oscillator can be set to perform voltage-controlled oscillation processing on the signal transmitted by the DA converter.
或者, 数字压控振荡单元可包括脉冲宽度调制(PWM )模块和数字压控 振荡器;该 PWM模块可设置成:生成周期不变且高电平脉宽可调的 PWM波, 并利用数字环路滤波单元输出的信号 ahead和 lag来对 PWM波对进行脉冲宽 度调制, 并将脉冲宽度调制后的信号传送给数字压控振荡器; 数字压控振荡 器可设置成对 PWM模块传送的信号进行压控振荡处理。 PWM模块可以由锁
定***内现场可编程门阵列或者可编程逻辑器件的处理器经过定时设置实 现。 Alternatively, the digital voltage controlled oscillating unit may include a pulse width modulation (PWM) module and a digital voltage controlled oscillator; the PWM module may be configured to: generate a PWM wave with a constant period and a high pulse width, and utilize a digital ring The signals ahead and lag output by the path filtering unit pulse-modulate the PWM wave pair, and transmit the pulse width modulated signal to the digital voltage controlled oscillator; the digital voltage controlled oscillator can be set to perform signal transmission on the PWM module Voltage controlled oscillation processing. PWM module can be locked by The processor of the field programmable gate array or programmable logic device in the system is implemented by timing setting.
本发明还公开了一种锁定方法, 包括: The invention also discloses a locking method, comprising:
锁定***先将经过分频的外部标准源输入信号 和本地的恒温晶体振荡 器的反馈输出信号 F。进行鉴相及转换处理,以生成时钟信号 elk以及用于表示 所述信号 和信号 F。之间的频率大小关系的信号 sign,再将所述信号 elk和信 号 sign进行滤波处理, 并将滤波处理后生成的用于表示信号 F。的频率小于信 号 的频率的信号 ahead和用于表示信号 F。的频率大于信号 的频率的信号 lag进行压控振荡处理, 以实现所述信号 F。与所述信号 的锁定。 The locking system first inputs the divided external standard source input signal and the feedback output signal F of the local oven-controlled crystal oscillator. Phase discrimination and conversion processing is performed to generate a clock signal elk and to represent the signal and signal F. The signal sign between the frequency magnitude relationship is filtered, and the signal elk and the signal sign are filtered, and the signal generated by the filtering process is used to represent the signal F. The frequency of the signal is less than the frequency of the signal and is used to represent the signal F. The signal lag having a frequency greater than the frequency of the signal is subjected to voltage-controlled oscillation processing to realize the signal F. Locked with the signal.
上述方法中, 锁定***将经过分频的信号 和信号 F。进行鉴相及转换处 理,以生成时钟信号 elk以及用于表示信号 和信号 F。之间的频率大小关系的 信号 sign的步骤可包括: 锁定***对信号 和信号 F。先进行鉴相处理, 生成 用于表示信号 和信号 F。之间的相位关系的脉冲信号 error, 再根据计数信号 count计算脉冲信号 error的月永覔, 生成表示信号^和信号 。之间的频率大小 关系的信号 sign, 以及表示相邻脉宽是否相等的信号 equ nequ, 再将信号 equ nequ与信号 进行与处理, 生成时钟信号 elk; 其中计数信号 count可以釆用 时间间隔计算方式实现,信号 sign可以通过脉冲信号 error中相邻脉宽的大小 关系以表示信号 和信号 F。之间的频率大小关系。 In the above method, the locking system will pass the divided signal and signal F. Phase discrimination and conversion processing is performed to generate a clock signal elk and to represent the signal and signal F. The relationship between the frequency magnitude of the signal sign can include: locking the system pair signal and signal F. The phase discrimination process is first performed to generate a signal and a signal F. The pulse signal error between the phase relationships is calculated according to the count signal count, and the representation signal ^ and the signal are generated. The signal sign between the frequency relationship and the signal equ nequ indicating whether the adjacent pulse widths are equal, and then processing the signal equ nequ with the signal to generate a clock signal elk; wherein the counting signal count can be calculated by using the time interval Implementation, the signal sign can represent the signal and the signal F by the magnitude relationship of adjacent pulse widths in the pulse signal error. The relationship between frequency and size.
锁定***可以利用滤波处理后生成的信号 ahead和 lag控制数模转换后再 进行压控振荡处理。 The locking system can use the signals generated by the filtering process to control the digital-to-analog conversion and then perform the voltage-controlled oscillation processing.
或者,锁定***可以利用滤波处理后生成的信号 ahead和 lag对脉冲宽度 调制 (PWM ) 波进行脉冲宽度调制后再进行压控振荡处理。 PWM波可以为 锁定***内现场可编程门阵列或者可编程逻辑器件的处理器经过定时设置生 成的周期不变、 高电平脉宽可调的 PWM波。 Alternatively, the locking system may perform pulse width modulation on the pulse width modulation (PWM) wave using the signals ahead and lag generated after the filtering process, and then perform voltage controlled oscillation processing. The PWM wave can be a PWM wave with adjustable period and high pulse width adjustable by the timer of the field programmable gate array or programmable logic device in the locking system.
本发明技术方案避免了传统锁相环在锁定过程中的振荡收敛过程, 从而 可以实现快速高精度的锁定。 另外, 本发明技术方案减小了电路面积, 降低 了电路成本。
附图概述 The technical solution of the invention avoids the oscillation convergence process of the traditional phase-locked loop during the locking process, so that fast and high-precision locking can be realized. In addition, the technical solution of the present invention reduces the circuit area and reduces the circuit cost. BRIEF abstract
图 1为传统锁相环的原理示意图; Figure 1 is a schematic diagram of the principle of a conventional phase-locked loop;
图 2为实施例 1提出的锁相环的原理示意图; 2 is a schematic diagram of the principle of the phase locked loop proposed in Embodiment 1;
图 3为实施例 1中 DA转换器和 CPLD连接的原理方框图; 3 is a schematic block diagram showing the connection of a DA converter and a CPLD in Embodiment 1;
图 4 为实施例 1中数字参差鉴相器的接口示意图; 4 is a schematic diagram of an interface of a digital phase difference detector in Embodiment 1;
图 5 为实施例 1中数字参差鉴相器输出信号的仿真波形图; 5 is a simulation waveform diagram of an output signal of the digital phase difference detector in Embodiment 1;
图 6 为实施例 1中数字鉴相及转换单元中转换模块的部分电路图; 图 7为实施例 1中数字鉴相及转换单元输出信号的仿真波形图; 图 8为实施例 1中 DLF的原理示意图; 6 is a partial circuit diagram of a conversion module in the digital phase discrimination and conversion unit in Embodiment 1; FIG. 7 is a simulation waveform diagram of an output signal of the digital phase discrimination and conversion unit in Embodiment 1; FIG. 8 is a principle of DLF in Embodiment 1. Schematic diagram
图 9为图 8所示 DLF的输出信号的仿真波形图; Figure 9 is a simulation waveform diagram of the output signal of the DLF shown in Figure 8;
图 10为实施例 1中 DCO的原理示意图。 Figure 10 is a schematic diagram showing the principle of the DCO in the first embodiment.
本发明的较佳实施方式 Preferred embodiment of the invention
本发明的主要构思是, 可以釆用数字鉴相及转换单元、 数字环路滤波单 元以及数字压控振荡单元实现全数字化锁相环, 从而实现快速的锁定, 其中, 数字鉴相及转换单元可以直接判断出本地输出信号的频率与标称频率的大小 关系, 避免传统锁相环在锁定过程中的振荡收敛过程, 并且数字鉴相及转换 单元中改进的数字电路, 可以集成到 FPGA (现场可编程门阵列 )或者 CPLD (复杂可编程逻辑器件) 中。 另外, 为了实现高精度的锁相环, 数字压控振 荡单元可以先通过 DA (数模转换器)或者脉冲宽度调制 ( PWM )模块对数 字信号进行数模转换, 再进行压控振荡处理。 The main idea of the present invention is that a digital phase-locked loop can be realized by using a digital phase-detecting and converting unit, a digital loop filtering unit and a digital voltage-controlled oscillating unit, thereby realizing fast locking, wherein the digital phase-detecting and converting unit can Directly determine the relationship between the frequency of the local output signal and the nominal frequency, avoid the oscillation convergence process of the traditional phase-locked loop during the locking process, and the digital circuit in the digital phase-detection and conversion unit can be integrated into the FPGA (on-site Programming gate arrays) or CPLDs (complex programmable logic devices). In addition, in order to realize a high-precision phase-locked loop, the digital voltage-controlled oscillating unit can first perform digital-to-analog conversion on the digital signal through a DA (digital-to-analog converter) or a pulse width modulation (PWM) module, and then perform voltage-controlled oscillation processing.
下面结合附图及具体实施例对本发明技术方案进行详细说明。 The technical solutions of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments.
实施例 1 Example 1
一种快速高精密锁定***, 其结构如图 2所示, 至少包括依次连接的数 字鉴相及转换单元、 数字环路滤波单元以及数字压控振荡单元。 A fast high-precision locking system, the structure of which is shown in Figure 2, comprising at least a digital phase-detecting and converting unit, a digital loop filtering unit and a digital voltage-controlled oscillating unit.
下面介绍各部分的具体功能。
数字鉴相及转换单元设置成将经过分频的外部标准源输入信号 和经过 分频的本地恒温晶体振荡器的反馈输出信号 F0进行鉴相及转换处理, 以生成 时钟信号 elk以及用于表示信号 和信号 F。之间的频率大小关系的信号 sign; The specific functions of each part are described below. The digital phase detecting and converting unit is configured to perform phase discrimination and conversion processing on the frequency-divided external standard source input signal and the frequency-divided local constant temperature crystal oscillator feedback output signal F 0 to generate a clock signal elk and to represent Signal and signal F. Signal sign between frequency and size relationships;
在本实施例中, 数字鉴相及转换单元进一步可以包括数字参差鉴相器 ( DPD )和转换模块; In this embodiment, the digital phase discrimination and conversion unit may further include a digital phase difference detector (DPD) and a conversion module;
其中 , DPD可以对输入信号 Fi和 F0进行鉴相,以显示出信号 和信号 F0之 间的相位关系, 即信号 F。的相位相对于信号 的相位是滞后还是超前, 以及 滞后或者超前的时间, 如图 5所示, 具体地, 将信号 F。和 分别接到如图 4 所示的数字参差鉴相器的 clr和 set端口, 其输出信号为两输入信号的脉宽误 差信号 error, 该信号 error即表示信号 和信号 F。之间的相位关系。 Wherein, the DPD can phase-detect the input signals Fi and F 0 to display the phase relationship between the signal and the signal F 0 , that is, the signal F. Whether the phase is lagging or leading with respect to the phase of the signal, and the time of lag or lead, as shown in Fig. 5, specifically, the signal F. And respectively connected to the clr and set ports of the digital phase detector shown in Figure 4, the output signal is the pulse width error signal error of the two input signals, the signal error represents the signal and the signal F. The phase relationship between them.
转换模块可以对 DPD的输出信号进行逻辑判断,以得到锁相环的两输入 信号 F。和 的频率大小关系。 该模块可以利用 DPD产生的 error信号和 TDC (时间间隔计算方式)产生的计数信号 count输出代表相邻脉宽是否相等的信 号 equ— nequ和两相邻脉宽大小关系的信号 sign (即用于表示所述信号 和信 号 F。之间的频率大小关系的信号) 。 equ— nequ和 通过与门便可以得到控制 DLF的时钟信号 elk, elk信号就是随机徘徊滤波器的输入时钟信号。 这样 elk 信号就在 equ— nequ不为 0(锁定***两输入信号频率不等时)的时候根据 sign 信号来对随机徘徊滤波器的内部计数单元进行响应的加减计数; 其中, 图 6 所示即为转换模块中用于生成信号 sign和信号 equ— nequ的电路示意图,从而 对相邻的 error 的脉宽进行比较而生成信号 sign。 在这里用一个高速时钟对 DPD产生的 error信号进行釆样计数, 越宽的 error信号 (即脉宽越大)将会 得到越大的计数值, 相反, 越小的 error信号(即脉宽越小)将会得到越小的 计数值, 如图 5所示, 而计数信号 count (即 error信号的脉宽计数值 ) 可以 釆用 TDC (时间间隔计算)方式实现。 本实施例中, 图 6所示电路的输出信 号的仿真波形如图 7所示。 The conversion module can logically judge the output signal of the DPD to obtain the two input signals F of the phase locked loop. The frequency relationship between and. The module can use the error signal generated by the DPD and the count signal count generated by the TDC (time interval calculation mode) to output a signal equ_nequ representing whether the adjacent pulse widths are equal and a signal sign of two adjacent pulse width relationships (ie, A signal indicating the magnitude relationship between the signal and the signal F.). The equ_nequ sum can be used to control the clock signal of the DLF through the AND gate. The elk, elk signal is the input clock signal of the random 徘徊 filter. Thus, the elk signal counts up and down in response to the internal signal of the random chirp filter according to the sign signal when equ_nequ is not 0 (when the two input signal frequencies of the locking system are not equal); wherein, Figure 6 shows That is, a circuit diagram for generating a signal sign and a signal equ_nequ in the conversion module, thereby comparing the pulse widths of adjacent errors to generate a signal sign. Here, a high-speed clock is used to count the error signal generated by the DPD. The wider the error signal (ie, the larger the pulse width), the larger the count value will be. On the contrary, the smaller the error signal (ie, the larger the pulse width) Small) will get the smaller count value, as shown in Figure 5, and the count signal count (that is, the pulse width count value of the error signal) can be implemented by TDC (Time Interval Calculation). In this embodiment, the simulation waveform of the output signal of the circuit shown in Fig. 6 is as shown in Fig. 7.
数字环路滤波单元可由数字环路滤波器 (DLF ) 实现, 主要对数字鉴相 及转换单元输出的信号进行过滤处理, 即去除一些偶然因素, 以达到数字滤 波的目的,即数字环路滤波单元根据时钟信号 elk可以实现在 和 F。两频率信 号不相等的时候控制环路滤波器进行工作, 进而产生控制数字压控振荡单元
的信号 ahead和 lag; The digital loop filter unit can be implemented by a digital loop filter (DLF), which mainly filters the signals output by the digital phase detector and the conversion unit, that is, removes some accidental factors to achieve the purpose of digital filtering, that is, the digital loop filter unit. According to the clock signal elk can be achieved in and F. The control loop filter operates when the two frequency signals are not equal, thereby generating a control digital voltage controlled oscillation unit Signals head and lag;
在本实施例中, DLF釆用随机徘徊滤波器, 其结构如图 8所示, 包括加 或减计数器(U/D— CNT ) 以及比较器(CMP ) , 时钟信号釆用鉴相器单元的 输出 elk,加或减计数方向由触发型鉴相器的输出 sign决定, 当 sign为高电平 时,计数器釆用加累加,反之,则减累加。计数器初始值 d[3:0]由比较器装载, 当计数器输出 q[3..0]达到 m+k或者 m-k时, 比较器产生装载信号 Id (低电平 有效) , 将 m 装载至计数器初始值 d[3..0] , 同时输出超前滞后控制信号 ahead=l(当 q[3..0]=m+k时), lag=l(当 q[3..0]=m-k时), 其中 k为滤波系数。 随机徘徊滤波器在环路中具有重要作用, 可以滤除传输中产生的毛刺引起错 误的边沿检测脉冲和超前滞后脉冲。 此外, k值的选择越大, 其滤波效果越 好, 但会降低整个环路的锁定速度, 所以应当选择比较合适的 k值, 该值既 不能太大又不能太小, 需要通过实验的验证来确定。 其中, DLF的仿真波形 如图 9所示, 当仿真波形图中选择 k=3时, 由图可以看出, 即可实现上述的 滤波功能。 In this embodiment, the DLF uses a random chirp filter, and its structure is as shown in FIG. 8. It includes an up or down counter (U/D_CNT) and a comparator (CMP), and the clock signal is used by the phase detector unit. The output elk, the direction of adding or subtracting the count is determined by the output sign of the trigger type phase detector. When the sign is high, the counter is added and accumulated, and vice versa. The counter initial value d[3:0] is loaded by the comparator. When the counter output q[3..0] reaches m+k or mk, the comparator generates the load signal Id (active low) and loads m to the counter. The initial value d[3..0], and the output lead lag control signal assume=l (when q[3..0]=m+k), lag=l (when q[3..0]=mk ), where k is the filter coefficient. The random chirp filter plays an important role in the loop, and it can filter out the edge detection pulse and the leading lag pulse caused by the glitch generated in the transmission. In addition, the larger the value of k is selected, the better the filtering effect is, but the locking speed of the whole loop is reduced. Therefore, a suitable k value should be selected, which is neither too large nor too small, and needs to be verified by experiments. to make sure. Among them, the simulation waveform of DLF is shown in Figure 9. When k=3 is selected in the simulation waveform, it can be seen from the figure that the above filtering function can be realized.
数字压控振荡单元设置成将滤波处理后生成的信号 ahead和信号 lag进行 逻辑处理, 以实现所述信号 F。与所述信号 的锁定, 具体地, 数字压控振荡 单元可以进一步包括数模 ( DA )转换器和数字压控振荡器 (DCO ) , 如图 10所示; The digital voltage controlled oscillating unit is arranged to logically process the signal ahead and signal lag generated after the filtering process to implement the signal F. In combination with the signal, specifically, the digital voltage controlled oscillation unit may further include a digital to analog (DA) converter and a digital voltage controlled oscillator (DCO), as shown in FIG. 10;
其中, 数模(DA )转换器主要针对数字环路滤波单元输出的增减信号进 行处理, 该增减信号可以控制 DA转换器的电压输出信号进行相应的增大或 减小, 即, 当 ahead信号有效时, 说明 F。小于 。 此时相位控制器通过增大 int_d的值改变 DA转换器输入值, 那么 DA转换器的电压也会相应增大, 从 而使恒温晶体振荡器的输出频率减小, 调整 F。接近 ; 同理, 当 lag信号和响 应时钟信号有效时, DA转换器输入值减小; Wherein, the digital-to-analog (DA) converter mainly processes the increase and decrease signals outputted by the digital loop filter unit, and the increase/decrease signal can control the voltage output signal of the DA converter to be correspondingly increased or decreased, that is, when the head When the signal is valid, F is indicated. Less than . At this time, the phase controller changes the input value of the DA converter by increasing the value of int_d, and the voltage of the DA converter is also increased accordingly, thereby reducing the output frequency of the constant temperature crystal oscillator and adjusting F. Similarly, when the lag signal and the response clock signal are valid, the DA converter input value is decreased;
本实施例中选用的 DA转换器是 AD9777,是一种转换速率可达 400MSPS 的高速数模转换器, 其具有速度快、 功耗小等诸多优点。 图 3所示为 AD9777 与 CPLD接口的电路原理,其中, EPM240T100C5的 DLF单元中输出 AD9777 需要的转换控制信号 ahead和 lag, AD9777根据控制信号进行 DA转换器输 出电压的增减。 而 DA转换时间由时钟 CLK控制, CLK利用 TDC (时间间
隔计数)原理对误差信号计数的高速釆样时钟, 时钟 CLK频率选为 10MHz, 该***中时钟 CLK控制 DA转换器的转换速度。 The DA converter selected in this embodiment is the AD9777, which is a high-speed digital-to-analog converter with a conversion rate of up to 400 MSPS, which has many advantages such as high speed and low power consumption. Figure 3 shows the circuit principle of the interface between the AD9777 and the CPLD. The DLF unit of the EPM240T100C5 outputs the conversion control signals ahead and lag required by the AD9777. The AD9777 increases or decreases the output voltage of the DA converter according to the control signal. The DA conversion time is controlled by the clock CLK, and the CLK uses the TDC (time between Separate counting) The high-speed sampling clock that counts the error signal, the clock CLK frequency is chosen to be 10MHz. In this system, the clock CLK controls the conversion speed of the DA converter.
因为 DA转换器的输出电压范围与压控晶体振荡器所需的压控范围不同, 所以在 DA转换器后还可以接一个运算放大器。 运算放大器可以保证将 DA 转换器的输出电压变换到数字压控振荡器所需的压控范围。 Since the output voltage range of the DA converter is different from the voltage control range required for the voltage controlled crystal oscillator, an operational amplifier can be connected after the DA converter. The op amp ensures that the output voltage of the DA converter is converted to the voltage control range required for the digital voltage controlled oscillator.
数字压控振荡器主要对 DA转换器的电压输出进行压控振荡处理, 这样 DA转换器的电压输出的增减反映到晶体振荡器就成为了恒温晶体振荡器输 出频率的增减。 经过环路的反馈控制作用, 恒温晶体振荡器最终可以达到和 标准频率源的锁定; The digital voltage controlled oscillator mainly performs voltage controlled oscillation processing on the voltage output of the DA converter, so that the increase or decrease of the voltage output of the DA converter reflects that the crystal oscillator becomes the increase and decrease of the output frequency of the constant temperature crystal oscillator. Through the feedback control of the loop, the constant temperature crystal oscillator can finally reach the lock with the standard frequency source;
下面再介绍上述锁定***的工作原理: The following describes the working principle of the above locking system:
本地输出频率表示为 F。, 而标称频率表示为 。 数字鉴相及转换单元比 较两输入信号 和 F。的上升沿, 得到超前或者滞后信号 sign和对数字环路滤 波单元的脉冲控制信号 elk; 数字环路滤波单元利用 sign和 elk信号对误差信 号进行平滑滤波, 并生成控制数字压控振荡单元中的 DA转换器的输入增加 的信号 ahead以及输入减小的信号 lag; 从而增加或者减少 DA转换器的输入 以控制 DCO压控端电压信号的增加或者减小, 达到增加或减小 F。频率的目 的。 经过整个环路的反馈调节可以最终达到 Fi和 。锁定。 The local output frequency is expressed as F. , and the nominal frequency is expressed as . The digital phase discrimination and conversion unit compares the two input signals with F. a rising edge, obtaining a lead or lag signal sign and a pulse control signal elk for the digital loop filtering unit; the digital loop filtering unit smoothing the error signal by using the sign and elk signals, and generating a control in the digital voltage controlled oscillating unit The input of the DA converter adds the signal ahead and the input reduced signal lag; thereby increasing or decreasing the input of the DA converter to control the increase or decrease of the DCO voltage control terminal voltage signal to increase or decrease F. The purpose of the frequency. Feedback adjustments throughout the loop can ultimately reach Fi and . locking.
实施例 2 Example 2
本实施例与实施例 1 的不同之处, 仅在于数字压控振荡单元包括 PWM 模块, 利用 PWM波来实现实施案例 1中 DA转换器实现的功能。 The difference between this embodiment and Embodiment 1 is that the digital voltage-controlled oscillating unit includes a PWM module, and the PWM wave is used to implement the function realized by the DA converter in Embodiment 1.
其中, PWM模块可以利用锁定***的 FPGA (或者 CPLD ) 内置的处理 器内核来实现, 即使 FPGA (或者 CPLD )内置的处理器内核通过定时作用输 出一个周期不变、高电平脉宽可调(即高电平占空比可调 )的 PWM波。 FPGA (或者 CPLD ) 内置的处理器内核收到数字环路滤波单元输出的增减信号, 根据这个增减信号相应的增加和减少 PWM波的高电平宽度(即根据增减信 号进行相应的增加或者减小 PWM波高电平的占空比),由 FPGA输出的 PWM 波再通过 RC低通滤波器后接入到数字压控振荡器的压控输入端,通过 PWM 波高电平脉宽的改变便可以改变低通滤波器的输出电压, 数字压控振荡单元
的压控端也相应的变化, 达到改变恒温晶体振荡器的目的, 让恒温晶体振荡 器的频率输出和标准源最终实现锁定。 The PWM module can be implemented by using a built-in processor core of the FPGA (or CPLD) of the locking system, even if the processor core built in the FPGA (or CPLD) outputs a period constant and the high-level pulse width is adjustable by timing action ( That is, the high-frequency duty cycle is adjustable) of the PWM wave. The built-in processor core of the FPGA (or CPLD) receives the increase and decrease signals output from the digital loop filter unit, and accordingly increases and decreases the high-level width of the PWM wave according to the increase and decrease signal (ie, correspondingly increases according to the increase and decrease signals). Or reduce the duty cycle of the PWM wave high level), the PWM wave output by the FPGA is passed through the RC low-pass filter and then connected to the voltage-controlled input terminal of the digital voltage-controlled oscillator, and the PWM pulse high-level pulse width is changed. The output voltage of the low-pass filter can be changed, and the digital voltage-controlled oscillation unit The voltage control terminal also changes accordingly, achieving the purpose of changing the constant temperature crystal oscillator, so that the frequency output of the constant temperature crystal oscillator and the standard source are finally locked.
利用实施案例 2来实现该锁定***可以减小***所占用的体积, 节省相 对比较昂贵的高精密 DA转换器。 由于实施案例 2利用了 FPGA中的嵌入式 内核, 所以可以将锁相环中的鉴相器、 数字环路滤波器和 PWM波逻辑电路 部分全集成到 FPGA中, 这样就可以实现节省******电路复杂度, 减小电 路面积, 同时也达到了降低成本的目的。 Using the implementation case 2 to implement the locking system can reduce the volume occupied by the system and save relatively expensive high-precision DA converters. Since the implementation case 2 utilizes the embedded core in the FPGA, the phase detector, the digital loop filter, and the PWM wave logic circuit in the phase-locked loop can be fully integrated into the FPGA, thereby saving system peripheral circuits. Complexity, reducing circuit area, but also achieving cost reduction.
从上述实施例可以看出, 本发明技术方案对参差鉴相器进行了改进, 改 进的参差鉴相器可以对两个输入信号的频率大小关系直接判断, 避免了传统 锁相环在锁定过程中的振荡收敛过程, 从而可以实现快速的锁定。 并且在实 施例 1中利用了高精度的 DA转换器连接到恒温晶体振荡器, 可以实现高精 度的锁定; 在实施例 2中利用了 FPGA中的配置处理器来输出 PWM波, 然 后让 PWM波通过低通滤波器, 低通滤波器输出电压加到恒温晶体振荡器输 入端实现高精密的锁定, 这样, 直接利用了 FPGA中的资源, 可以减小电路 面积, 降低电路成本。 It can be seen from the above embodiment that the technical solution of the present invention improves the phase difference detector, and the improved phase detector can directly judge the frequency relationship between the two input signals, thereby avoiding the traditional phase-locked loop in the locking process. The oscillation convergence process allows for fast locking. And in Embodiment 1, the high-precision DA converter is connected to the constant temperature crystal oscillator, and high-precision locking can be realized; in Embodiment 2, the configuration processor in the FPGA is used to output the PWM wave, and then the PWM wave is made. Through the low-pass filter, the low-pass filter output voltage is applied to the input of the constant-temperature crystal oscillator to achieve high-precision locking. Thus, by directly utilizing the resources in the FPGA, the circuit area can be reduced and the circuit cost can be reduced.
以上所述仅为本发明的优选实施例而已, 并不用于限制本发明, 对于本 领域的技术人员来说, 本发明可以有各种变化和更改。 凡在本发明的精神和 原则之内, 所做的任何修改, 等同替换, 改进等, 均应包含在本发明的保护 范围之内。 The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various changes and modifications may be made to the present invention. All modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.
工业实用性 Industrial applicability
与现有技术相比, 本发明的技术方案避免了传统锁相环在锁定过程中的 振荡收敛过程, 从而可以实现快速高精度的锁定。 另外, 本发明技术方案减 小了电路面积, 降低了电路成本。
Compared with the prior art, the technical solution of the present invention avoids the oscillation convergence process of the traditional phase-locked loop during the locking process, so that fast and high-precision locking can be realized. In addition, the technical solution of the present invention reduces the circuit area and reduces the circuit cost.
Claims
1、 一种锁定***, 包括依次连接的数字鉴相及转换单元、 数字环路滤波 单元以及数字压控振荡单元, 其中: A locking system comprising a digital phase detecting and converting unit, a digital loop filtering unit and a digital voltage controlled oscillating unit connected in sequence, wherein:
所述数字鉴相及转换单元设置成将经过分频的外部标准源输入信号 和 本地的恒温晶体振荡器的反馈输出信号 F。进行鉴相及转换处理, 以生成时钟 信号 elk以及用于表示所述信号 和信号 F。之间的频率大小关系的信号 sign; 所述数字环路滤波单元设置成将所述信号 elk和信号 sign进行滤波处理, 生成用于表示信号 F。的频率小于信号 的频率的信号 ahead和用于表示信号 F。的频率大于信号 的频率的信号 lag; The digital phase detector and conversion unit is configured to input a divided standard external source input signal and a feedback output signal F of the local oven controlled crystal oscillator. A phase discrimination and conversion process is performed to generate a clock signal elk and to represent the signal and signal F. A signal sign of a frequency relationship between the numbers; the digital loop filtering unit is configured to filter the signal elk and the signal sign to generate a signal F. The frequency of the signal is less than the frequency of the signal and is used to represent the signal F. a signal having a frequency greater than the frequency of the signal lag;
所述数字压控振荡单元设置成将对信号 elk和信号 sign进行滤波处理后 生成的信号 ahead和信号 lag进行压控振荡处理,以实现所述信号 。与所述信 号^的锁定。 The digital voltage controlled oscillating unit is arranged to perform voltage controlled oscillating processing on the signal ahead and signal lag generated after filtering the signal elk and the signal sign to implement the signal. Locked with the signal ^.
2、 如权利要求 1所述的***, 其中, 所述数字鉴相及转换单元包括数 字参差鉴相器和转换模块, 其中: 2. The system of claim 1, wherein the digital phase discrimination and conversion unit comprises a digital phase detector and a conversion module, wherein:
所述数字参差鉴相器设置成对所述信号 和信号 F。进行鉴相处理, 生成 用于表示所述信号 和信号 F。之间的相位关系的脉冲信号 error; The digital phase detector is arranged in pairs with the signal and signal F. Phase discrimination processing is performed to generate the signal and signal F. Pulse signal between phase relationships;
所述转换模块设置成根据计数信号 count计算所述脉冲信号 error的脉宽, 生成表示所述信号 和信号 F。之间的频率大小关系的信号 sign, 以及表示相 邻脉宽是否相等的信号 equ nequ, 再将所述信号 equ nequ与所述信号 进行 与处理, 生成时钟信号 elk; The conversion module is configured to calculate a pulse width of the pulse signal error according to a count signal count, and generate a signal and a signal F. a signal sign between the frequency magnitude relationship, and a signal equ nequ indicating whether the adjacent pulse widths are equal, and then processing the signal equ nequ with the signal to generate a clock signal elk;
其中, 所述计数信号 count釆用时间间隔计算方式实现, 所述信号 sign 通过所述脉冲信号 error中相邻脉宽的大小关系以表示所述信号 和信号 F。之 间的频率大小关系。 The counting signal count is implemented by a time interval calculation manner, and the signal sign indicates the signal and the signal F by the magnitude relationship of adjacent pulse widths in the pulse signal error. The frequency relationship between them.
3、 如权利要求 1或 2所述的***, 其中, 所述数字压控振荡单元包括数 模 DA转换器和数字压控振荡器, 3. The system of claim 1 or 2, wherein the digital voltage controlled oscillating unit comprises a digital to analog converter and a digital voltage controlled oscillator.
所述 DA转换器设置成接收所述数字环路滤波单元输出的信号 ahead和 lag, 利用所接收的信号控制该 DA转换器进行数模转换后传送给所述数字压 控振荡器; 所述数字压控振荡器设置成对所述 DA转换器传送的信号进行压控振荡 处理。 The DA converter is configured to receive signals ahead and lag output by the digital loop filtering unit, and control the DA converter to perform digital-to-analog conversion by using the received signal, and then transmit the signal to the digital voltage-controlled oscillator; The digital voltage controlled oscillator is arranged to perform a voltage controlled oscillation process on a signal transmitted by the DA converter.
4、 如权利要求 1或 2所述的***, 其中, 所述数字压控振荡单元包括脉 冲宽度调制 PWM模块和数字压控振荡器, 4. The system of claim 1 or 2, wherein the digital voltage controlled oscillating unit comprises a pulse width modulation PWM module and a digital voltage controlled oscillator,
所述 PWM模块设置成: 生成周期不变且高电平脉宽可调的 PWM波, 利用所述数字环路滤波单元输出的信号 ahead和 lag对所述 PWM波进行脉冲 宽度调制, 并将脉冲宽度调制后的信号传送给所述数字压控振荡器; The PWM module is configured to: generate a PWM wave with a constant period and a high pulse width, and pulse width modulate the PWM wave by using signals ahead and lag output by the digital loop filtering unit, and pulse a width modulated signal is transmitted to the digital voltage controlled oscillator;
所述数字压控振荡器设置成对所述 PWM模块传送的信号进行压控振荡 处理。 The digital voltage controlled oscillator is arranged to perform a voltage controlled oscillation process on a signal transmitted by the PWM module.
5、 如权利要求 4所述的***, 其中, 5. The system of claim 4, wherein
所述 PWM模块由所述锁定***内现场可编程门阵列或者可编程逻辑器 件的处理器经过定时设置实现。 The PWM module is implemented by a timing setting of a field programmable gate array or a programmable logic device processor in the locking system.
6、 一种锁定方法, 包括: 6. A locking method, including:
锁定***先将经过分频的外部标准源输入信号 和本地的恒温晶体振荡 器的反馈输出信号 F。进行鉴相及转换处理,以生成时钟信号 elk以及用于表示 所述信号 和信号 F。之间的频率大小关系的信号 sign,再将所述信号 elk和信 号 sign进行滤波处理, 并将滤波处理后生成的用于表示信号 F。的频率小于信 号 的频率的信号 ahead和用于表示信号 F。的频率大于信号 的频率的信号 lag进行压控振荡处理, 以实现所述信号 F。与所述信号 的锁定。 The locking system first inputs the divided external standard source input signal and the feedback output signal F of the local oven-controlled crystal oscillator. Phase discrimination and conversion processing is performed to generate a clock signal elk and to represent the signal and signal F. The signal sign between the frequency magnitude relationship is filtered, and the signal elk and the signal sign are filtered, and the signal generated by the filtering process is used to represent the signal F. The frequency of the signal is less than the frequency of the signal and is used to represent the signal F. The signal lag having a frequency greater than the frequency of the signal is subjected to voltage-controlled oscillation processing to realize the signal F. Locked with the signal.
7、 如权利要求 6所述的方法, 其中, 7. The method of claim 6, wherein
锁定***将经过分频的信号 和信号 F。进行鉴相及转换处理, 以生成时 钟信号 elk以及用于表示所述信号 和信号 F。之间的频率大小关系的信号 sign 的步骤包括: The locking system will pass the divided signal and signal F. Phase discrimination and conversion processing is performed to generate a clock signal elk and to represent the signal and signal F. The steps between the signal signs of the frequency relationship between the steps include:
所述锁定***对所述信号 Fi和信号 F0先进行鉴相处理, 生成用于表示所 述信号 和信号 F。之间的相位关系的脉冲信号 error, 再根据计数信号 count 计算所述脉冲信号 error的脉宽, 生成表示所述信号 和信号 F。之间的频率大 小关系的信号 sign, 以及表示相邻脉宽是否相等的信号 equ nequ, 再将所述 信号 equ nequ与所述信号 进行与处理, 生成时钟信号 elk; 其中, 所述计数信号 count釆用时间间隔计算方式实现, 所述信号 sign 通过所述脉冲信号 error中相邻脉宽的大小关系以表示所述信号 和信号 F。之 间的频率大小关系。 The locking system performs phase discrimination processing on the signal Fi and the signal F 0 to generate the signal and the signal F. The pulse signal error of the phase relationship between the two, and then calculating the pulse width of the pulse signal error according to the count signal count, generating the signal and the signal F. a signal sign between the frequency magnitude relationship, and a signal equ nequ indicating whether the adjacent pulse widths are equal, and then processing the signal equ nequ with the signal to generate a clock signal elk; The counting signal count is implemented by a time interval calculation manner, and the signal sign indicates the signal and the signal F by the magnitude relationship of adjacent pulse widths in the pulse signal error. The relationship between frequency and size.
8、 如权利要求 6或 7所述的方法, 其在对信号 ahead和 lag进行压控振 荡处理的步骤之前, 还包括: 8. The method of claim 6 or 7, further comprising: before the step of voltage-controlled oscillating processing of the signals ahead and lag,
所述锁定***利用所述信号 ahead和 lag控制数模转换。 The locking system controls digital to analog conversion using the signals ahead and lag.
9、 如权利要求 6或 7所述的方法, 其在对信号 ahead和 lag进行压控振 荡处理的步骤之前, 还包括: 9. The method of claim 6 or 7, before the step of voltage-controlled oscillating processing of signals ahead and lag, further comprising:
所述锁定***通过所述信号 ahead和 lag对 PWM波进行脉冲宽度调制。 The locking system pulse width modulates the PWM waves by the signals ahead and lag.
10、 如权利要求 9所述的方法, 其中, 10. The method of claim 9, wherein
所述 PWM波为所述锁定***内现场可编程门阵列或者可编程逻辑器件 的处理器经过定时设置生成的周期不变、 高电平脉宽可调的 PWM波。 The PWM wave is a PWM wave with a constant period and a high pulse width adjustable by a processor of a field programmable gate array or a programmable logic device in the locking system.
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EP10826056.3A EP2482460B1 (en) | 2009-10-23 | 2010-10-22 | Locking system and method thereof |
US13/502,477 US8724765B2 (en) | 2009-10-23 | 2010-10-22 | Locking system and method thereof |
PL10826056T PL2482460T3 (en) | 2009-10-23 | 2010-10-22 | Locking system and method thereof |
ES10826056.3T ES2535497T3 (en) | 2009-10-23 | 2010-10-22 | Locking system and procedure |
DK10826056.3T DK2482460T3 (en) | 2009-10-23 | 2010-10-22 | Locking system and method thereof |
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US20120213268A1 (en) | 2012-08-23 |
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