TW444236B - Bumpless flip chip assembly with strips and via-fill - Google Patents

Bumpless flip chip assembly with strips and via-fill Download PDF

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Publication number
TW444236B
TW444236B TW087121131A TW87121131A TW444236B TW 444236 B TW444236 B TW 444236B TW 087121131 A TW087121131 A TW 087121131A TW 87121131 A TW87121131 A TW 87121131A TW 444236 B TW444236 B TW 444236B
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TW
Taiwan
Prior art keywords
scope
patent application
substrate
chip assembly
item
Prior art date
Application number
TW087121131A
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English (en)
Inventor
Charles Wen Chyang Lin
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Charles Wen Chyang Lin
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Publication of TW444236B publication Critical patent/TW444236B/zh

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    • H01L2924/30107—Inductance

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f Λ44 236 A7 B7 ~~ I ——- —_______1—^—· ·| . - — ----- _ 五、發明説明（1 ) 發明背景 1、 發明領域 概略而言本發明係關於半導體器件總成，特別係關於 一種晶片總成其包括單一或多層基材，其電路轨線係透過 導電材料沉積於通孔内部之預成形引線及端子墊而連結至 1C晶片之輸入/輸出端子塾β填補材料包括導電黏著劑及 焊料。 2、 相關技術 半導體封裝體之晚近發展提示該技術之重要性漸增。 新需求來自於每晶片需有更多引線，因而更小的輸入/輸 出端子節距，縮小模塊及封裝體占有面積，工作頻率增高 產生較大熱量’如此需有先進散熱設計全部此等考量皆 需吻合’此外也包括封裝趙增加半導體製造連鎖之成本。 習知有三種主要晶片層面的連結技術可用於積體電路 ’亦即接線，帶自動化接合（TAB)及倒裝晶片（FC)而以電 力或機械方式連結積體電路至引線框或基材電路β習知倒 裝晶片之技術係利用安裝未經封裝的半導體晶片，其主動 面向下透過某種接觸繫止塊如焊料、金或有機導電黏著劑 凸塊而安裝於互連基材》倒裝晶片技術之主要優點為互連 體短’因此可處理高速或高頻信號。大致並無寄生元件如 電感。不僅信號傳播延遲大減，同時許多波形失真也被消 除。倒裝晶片也允許陣列互連布局，其提供比較具有相等 模塊大小之周邊互連體提供更多Ι/〇β此外由於未使用額 外封裝且所需電路板空間減少，故減少安裝面積與重量， 本紙張尺财[家料（CNS ) A4· ( 2IGx297公楚） -----------等------.ΤΓ------> (#-先閲讀t面之注意事項再填寫本頁) 經濟部中央標準局員4消費合作社印裝 -4 - 經濟部中央揉準局貝工消费合作社印製 444 23 6 A7 __________ B7__ 五、發明説明（2 ) 結果導致總成本節省。此種方法之一例揭示於Casson等之 美國專利第5,261，593號。 雖然倒裝晶片技術藕示比較接線之重大進展，但其成 本與技術限制顯著。首先，先前之倒裝晶片技術必須面對 形成凸起的接觸繫止塊或凸塊作為積體電路晶片與基材電 路間之電連接的挑釁•此種辦法之例揭示於Yeh等之美國 專利第5,803,340號；Akram等之美國專利第5,736,456號。 其典型包括極為昂貴的真空方法來沉積中間凸塊下方層， 其作為黏著層及擴散障層。此障層典型係由膜堆疊組成， 可用於鉻/銅/金構造。凸塊材料如焊料隨後透過蒸鍍、濺 散、電鍍、焊料喷射或糊印刷法沉積於中間層上，接著為 再流步驟而形成焊料接點* 雖然蒸鍍及濺散技術可提供高密度凸堍，但此等方法 需要極為緊密之控制*通常導致產率不佳。此外由機械構 造觀點看來，矽與基材之熱膨脹係數（CTE)有相當大差異 ，故附接後此二部件間之應力將積聚且全然負荷於凸塊上 。隨後引起正常工作期間接頭嚴重斷裂而脫離連結問題。 結果習知倒裝晶片總成不僅償格昂贵，同時也有極為嚴重 的可靠度問題及高致命比》 有機接點其利用導電黏著劑來替代焊料也敘述於 Chillara之美國專利第5,627,405號；Kulesza等之美國專利 第5,611，140號。概略而言，經由添加導電填料至聚合物 黏著劑製成的導電黏著射可獲得多種技術優點，例如環保 相容，較低溫製程能力，精細節距及製程比較焊接簡化。 本紙張尺度適用中國國家橾率（CNS ) A4«l格（2丨0；<25>7公釐） (件先閲讀r面之注$項再填寫本頁) -訂 444 236 Α7 Β7 經濟部中央標準局貝工消賢合作社印裝 五、發明説明（3 ) 但此等類型黏著劑就傳統意義而言正常無法形成冶金交界 面。基本電路徑係透過彼此接觸且到達組件之二接面之導 電黏著劑粒子》 鍟於目前可利用之積體電路組裝方法之限制，大為需 要可有效互連積體電路至外部電路之高性能、可靠且經濟 的方法。 發明概述 因此本發明之目的係提供一種倒裝晶片總成蘭解決半 導體封裝艘之高密度、低成本與高性能需求。其涉及透過 通孔内部預成形的引線與1C端子墊之連結，接合基材電路 至半導韹器件，而無需習知凸塊'接線或其他媒介《此種 獨特接合技術可提供1C晶片與基材電路間之電力與機械連 結。 為了逮成前述目的，根據本發明，該總成包括一剛性 或撓性介電基材其具有複數導電基材及複數通孔成形於介 電基材。此等於基材表面之導電執線係經由引線延伸入各 特定通孔内部，引線係藉習知電路圖樣化製程、切割或衝 孔方法製造。 本發明之一具體例中，連結方法可利用焊料糊印刷， 焊料喷射或焊料粒子安置》今日使用之最常見焊料系統為 錫-鉛焊料’但本發明非僅限於此特殊類型。用於焊料糊 ’糊之典型例包括80%焊料固體及20%助焊劑糊，但其應 用非僅限於此種比例。如所述，焊料糊係呈糊狀使用，較 佳使用業界已知之網印程序使用。焊料糊配漿至絲網後， -^--- <诊先聞t».背面之注意事項再填寫本頁} ,11 本紙張尺度適用中國國家樣準（CNS ) A4规格（210X297公釐） -6- J ^44 236 a7
__!I 五、發明説明（4 ) 適當刮墨輥型器件拖曳通過絲網，迫使糊通過絲網之孔進 入基材通孔内部。然後移開絲網，留下預定量之糊於各通 孔内部。 根據本發明之又一態樣，連結材料可呈導電黏著劑而 提供1C端子墊與基材預先®樣化引線間的連結《導電黏著 劑系統比較焊接有多種技術優點，例如環保相容，較低溫 製程能力及製程簡化。典型導電黏著劑系統包含可聚合前 驅物、細金屬粒及硬化劑溶液形成糊◊糊藉網印、型版印 刷或直接配漿法填補於盲孔。於導電黏著劑糊填補後，施 加外部能量如熱或紫外光，此處黏著劑固化及硬化而提供 電路引線與1C端子墊間之有效電力與機械接觸之手段。此 點之重要性在於可確保獲得極為低成本且環保有善的封裝 體。其除了填補導電材料外可透過金屬化通孔壁連結，由 於接觸面積大故確保獲得基材與晶片間之交界面改良。 經濟部中央標準局貝工消費合作社印製 ^1 _ -1_ 1 I -i n I I 1 I --1 ^1 (t先閲讀t·面之注項再填寫本頁) 以塗布於鋁端子墊表面上之障層為佳，但對銅端子墊 而言無需進一步保護。此種頂塗布可提供墊表面進行焊料 濕潤*及保護連結材料不會滲濾、氧化或因暴露於烊接材 料與熱期間形成金屬間化合物造成分解。塗布方式係濺散 一疊薄膜於其上，或藉濕化學鍍敷技術如無電鍍鎳及浸潰 錢金完成。 位在通孔内部的接觸引線可呈多種形狀之長條。較佳 製法係藉習知微影術圖樣化及蝕刻方法*但也可藉顯微機 制或雷射切割製造。於形成引線後，引線朝向通孔内部臀 折俾獲得1C墊與電路間之有效連結路徑。引線彆折可藉多 本紙張尺度通用中國囷家標準（CNS ) A4規格（210X】97公釐） 經濟部中央標率局貝工消費合作社印掣 ΐ AA4 236 A7 _B7________ 五、發明説明（5 ) 種方法如真空抽取、吹喷空氣或機械推送達成。 基材電路通孔可藉多種技術形成，包括機械鑽孔、衝 孔 '電漿蝕刻或雷射鑽孔》依據基材製法而定通孔可於銅 層疊之前或之後形成。通孔之形成位置在於基材一邊之電 路可連結至安裝半導體晶片該邊反侧位I，及其輸入/輸 出端子墊可透過此等通孔暴露出》 使用延長引線及導電材料直接沉積於通孔可有效連結 1C晶片於介電基材電路而無需外部凸塊或導線《此種方法 允許達成高度可靠、低側錄、高性能及低成本的總成。特 別藉雷射或其他技術形成小通孔允許互連極為細微節距之 端子墊’顯著提升未來高I/O半導體晶片之封裝能力。 圖式之簡單說明 第1圖為基材之等角視圖，顯示通孔及基材電路軌線 〇 第2A至2E圈為圖解剖面圖，顯示根據本發明藉配漿 導電黏著劑於通孔製造積體電路總成涉及之步驟。 第3 A至3F囷為圖解剖面圖，顯示根據本發明之另一 具髏例藉焊料糊印刷入通孔内接著為再流動法製造積體電 路總成之相關步驟。 發明之詳細說明 根據本發明提供倒裝晶片總成來解決本發明封裝逋之 高密度、低成本與高性能需求，包括透過預先形成的引線 連結至通孔内部之1C端子整而接合基材電路至半導艘器件 且無需使用習知凸塊、接線或其他媒介。此種獨特接合方 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2Ι0Χ297公楚] ---------^------ir------: y, <谇先W讀背面之注意事項再填寫本頁) 444 ^36 經濟部中央樣準局貝工消费合作社印製 A7 B7 i、發明说明（6 ) 法可提供1C晶片與基材電路間之電力與機械連結。 為了達成前述目的根據本發明，總成包括一剛性或撓 性介電基材其具有複數導電電路及複數通孔成形於介電基 材。基材表面之導電軌線透過引線延長入各特定通孔，引 線係經由習知電路圈樣化製程、切割或衝孔方法製造。第 1囷為此種基材101—段之等角視圖，基材上通常藉雷射或 機械錢孔形成通孔102 »通孔102係用作電路軌線103與1C 端子墊透過預先形成的懸吊於通孔内部之引線104間的互 連通路。電路軌線103由通孔102沿著基材外表面伸展將導 引至次一階總成之另一墊連接。 接觸方向確保介電基材之通孔中之至少一孔係對正1C 晶片墊，故此等墊可全然或部分經基材對側暴露。對正後 ，1C晶片透過黏膠膜或糊或機械技術附接於介電基材而形 成一總成·導電材料隨後填補於通孔而連結此等引線及1C 晶片之輸入/輸出墊。填補於通孔之導電材料可提供晶片 與介電基材軌線間之電力舆機械連結。基材電路連結至端 子墊後，可去除用來附接晶片與基材的機械及化學手段》 替代例中可保留呈總成之一體部件，原因為此種附接也可 提供機械支承故。 如此處定義，較佳具體例特別係關於積體電路（1C)晶 片接合至撓性電路之基材，或接合至較為剛性電路之基材 ，後者特例為印刷電路板。但需瞭解本發明非僅限於附接 於印刷電路板，而可使用其他電路基材包括已知之撓性基 材帶或陶瓷基材。通常有機類型為較佳可達成較低成本、 本紙張尺度適用中國國家梂率（CNS) A4規格（21〇x297公釐） I:-II---->裝：-1:----訂------諫 (請先閱讀背面之注意事項再填寫本頁) *9- 經濟部中央標準局貝工消費合作杜印製 f* 444 2 3 6 A7 _B7__ 五、發明説明（7 ) 優異介電性質，而當需要高度散熱及匹配介電係數時則以 無機類型基材為佳。此處使用”基材’’一詞表示至少一層介 電材料其上有至少一層導電層。類似類型之印刷電路板為 電子業界眾所周知，其製法亦為眾所周知因此無需再做定 義》此種構造依據預定工作特徵而定包括超過第1至4圖闞 明之多種導電層。如已知，導電層可作為信號層、供電層 及/或接地層。 本發明之具體例中，連結方法呈焊接糊印刷，焊料喷 射或定置焊料粒子。今曰最常見方法為錫-鉛焊料，但本 發明非僅限於此特殊形式。用於焊料糊，糊之典型例包括 80%焊料固艘及20%助焊劑糊，但此種應用非僅限於此種 比例。如所述，焊料糊係呈糊狀使用，較佳使用業界已知 之網印方法使用》焊料糊配漿至絲網上後，可採用適當刮 墨輥型器件拖戈通過絲網，將焊料糊迫使通過絲網之孔並 進入基材通孔内部。然後移開絲網，留下預定量之糊於各 通孔内部。 由此處教示需瞭解前述焊料糊及配漿方法絕非意圖限 制本發明’也可藉型版印刷、直接配漿或其他方法安置焊 料糊。然後施熱至足夠使焊料糊，，滾珠”之預定溫度至總成 ，至少施熱於通孔附近*較佳施熱方式係使用雷射〃另外 ，附接總成可置於適當烘箱内來執行烊料之再流動及接合 至1C端子，及於通孔内側之延長引線。此種辦法之一例為 紅外線（IR)連續帶再流動烘箱。有另—替代例為可導引熱 氮氣至總成之焊接件上。此種再流動之形成導致焊接結構 本紙張尺度適用中β國家橾率（CNS ) Α4思格（2丨0父297公釐」 一~ -10- ——----->裝.—----訂------^ (t先閱讀背面之注意事項再填寫本頁) j 444 23 6 經濟部中央標準局貝工消費合作衽印裝 Α7 _______ Β7五、發明説明（8 ) 其以電力及實體方式互連引線與墊供最終永久性連結》此 點之重要性為其不僅可廣泛選擇嬋料系統，同時也可確保 極低應力’因而由於長條之撓性故可獲得基材與晶片間之 可靠的連結。 根據本發明之又一特點，連結材料可呈導電黏著劑而 提供1C端子墊與基材預圖樣化引線間的連結。導電黏著劑 系統可保有多種技術優點如環保相容，較低溫處理能力， 及比焊接製程簡化。典型導電黏著劑系統包含可聚合前驅 物、細金屬粒及硬化劑溶液形成糊。糊藉網印、型版印刷 或直接配漿法填補於盲孔*於導電黏著劑糊填補後，施加 外部能量如熱或紫外光，此處黏著劑被固化及硬化而提供 電路引線與1C端子墊間之有效電力與機械接觸手段。此點 之重要性在於可確保獲得極為低成本且環保有善的封裝體 。其除了填補導電材料外，透過金屬化通孔壁之連結，由 於接觸面積大故確保獲得基材與晶片間之交界面改良。 以塗布於鋁端子墊表面上之障層為佳，但對銅端子塾 而言無需進一步保護。此種頂塗布可提供墊表面進行焊料 濕潤’及保護連結材料不會滲濾、氧化或因暴露於焊接材 料與熱期間形成金屬間化合物造成的分解劣化。此塗布方 式係藉濺散一疊薄膜於其上，或藉濕化學鍍敷技術如無電 链鍊及浸潰鍵金達成。 根據本發明，位於通孔内側之接觸引線可呈多種形狀 之長條形式。較佳製法為習知微影術圖樣化及钱刻方法。 另外可藉顯微機制或雷射切割製造。於形成引線後其朝向 本紙張尺度適ϋ國國家標準（CNS ) Α4&格（2丨0X297公釐） ' ' -11 - ---------Ί------·ΐτ------或 (誇先聞瘦背面之注意事項再填寫本頁) r 444 236 A7 B7 經濟部中央標準局負工消費合作社印製 五、發明説明（9 ) 通孔内部彎折俾提供1C墊與電路間之有效連接路徑。引線 彎折可藉多種方法例如真空抽取、吹噴空氣或機械推送達 成。 根據本發明，基材電路之通孔可藉多種技術形成，包 括機械鑽孔、衝孔、電漿蝕刻或雷射鑽孔。依據基材製法 而定通孔可於銅層疊之前或之後形成。此等通孔形成於基 材之位置為基材一邊之電路可連結至安裝半導體晶片該面 對側位置’及其輪入/輪出端子墊可透過此等通孔暴露出 〇 若成品例如為球柵陣列封裝體（BGA)，則焊料珠通常 係位於介電基材表面之特定墊上◊此種封裝體成品可藉再 流動焊料珠連接至印刷電路板而形成附接至印刷電路板軌 線》 使用延長引線及導電材料直接沉積於通孔，可有效連 結1C晶片與介電基材電路而無需外部凸塊或導線。此種方 法可獲得可靠的低侧錄、高性能與低成本總成。特別可藉 雷射或其他技術形成的小通孔允許極為細微之節距端子墊 互連，而可顯著增進未來高I/C)半導體晶片之封裝能力。 將藉下列實例舉例說明本發明。此等實例僅供舉例說 明本發明而絕非意圖限制本發明，本發明範圍僅由隨附之 申請專利範圍界定。 實例1 第2A圖顯示積體電路晶片201附有各型電晶體、導線 等（圖中未顯示）有複數暴露的輸入/輸出端子墊2〇2(囷中僅 ---------------1T------嘁 * * * (诊先閱東背面之注意事項再填寫本頁) 本紙張·尺度適用中國國家榡準（CNS ) A4規格（2IOX297公餐） 12· 444 2 3b A7 B7 經濟部中央標準局負工消费合作社印製 五、發明説明（10 ) 顯示一者）。墊202首先藉將積體電路晶片201於室溫浸泡 於磷酸溶液歷10分鐘而去除表面氧化物膜進行清潔。其次 晶片浸泡於稀催化劑溶液Enthone “Alumon EN”（商品名） 於25 °C浸泡20秒形成辞薄膜（囷中未顯示）於鋁合金端子 202表面上。隨後各步驟包括徹底使用蒸餾水清洗，及於85 °C使用Shipley ’’NIPOSIT 468”（商品名）進行無電鍍敷。無 電鍍敷連續沉積含磷鎳膜203薄層（後文稱作鎳膜）於積體 電路晶片201之輸入/輸出端子墊202上。 第2B圏顯示介電基材204之剖面圖，其具有複數電路 軌線205係由焊接罩206部分遮蓋。此等軌線205延伸入通 孔207内部且分岔成複數引線208其彎折至通孔内部。通孔 207之成形方式為當積體電路晶片201安裝於基材204上時 ’積體電路晶片201之端子墊202全然或部分暴露出。引線 208朝向端子墊彎折，且作為基材204之軌線205與第2A圊 之積體電路晶片201之個別端子墊202間之電連結通路。 如第2C圖所示，基材204其次藉黏著劑糊ABLESTIK “ABLEBOND 961-2”(商品名）209牢固附接於1C晶片201 » 如第2D圖所示，導電糊So丨der-Sub，，Me 8659-SMI”（商 品名）210填補於通孔。填補後之導電環氧樹脂於i5〇t固 化5分鐘硬化，硬化可提高電路引線與ic端子墊間之接合 強度。此種接頭將提供輸入/輸出端子墊與介電電路軌線 之有效電力與機械連結手段，因而完成電接線互連體的製 造。 如第2E圖所示，焊料珠211附接於基材電路之連結墊 --------.裝— (请先閲i#.背面之注$項再填寫本頁) 订 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -13- 經濟部中央標準局員工消費合作社印策 444236 A7 __B7_五、發明説明（η ) ，封裝體準備用於下一階段組裝。 實例2 現在參照第3A圖，類似實例1之積體電路（1C)晶片301 於室溫（25 °C )浸泡於含〇.〇5 Μ磷酸之鹼性溶液内1分鐘清 潔。然後晶片於蒸餾水中徹底清洗而螻保1C晶片表面並無 殘留物。薄膜303之堆疊構造為鉻（500埃）/銅（700埃）/金 (1000埃）經沉積於端子墊302上並圖樣化作為障層及黏著 層。 第3Β圖顯示介電基材304有複數導電電路軌線305係 由焊接罩306部分遮蓋。基材上之軌線305延伸入通孔307 内部，且分岔成複數引線308其朝向通孔307内部彆折。通 孔307之形成方式為積體電路晶片301(第3Α圖）之端子墊 302(第3Α囷）於積體電路晶片301(第3Α圖）安裝於基材304 時可完全或部分暴露。彎折引線308係作為基材304之個別 軌線305與積體電路晶片301(第3Α圖）之個別端子墊302(第 3Α圖）之電連接通路。 如第3C圖所示，其次1C晶片301藉黏膠膜ABLESTIK “ABLEFILM 561Κ”（商品名）309牢固附接於基材電路304 〇 第3D圊所示，其次焊料糊KESTER焊料’’R253”（商品 名）310網印至通孔内。 如第3Ε圖所示，其次總成於210至215°C之峰溫再度 流動。再流動過程後，總成使用周圍空氣以每秒1°C之速 率冷卻而固化其中所含焊料。此種再流動製程可使填補之 1 - -I . I - I 1 -I I - HI I— -- 1--- -: - I— ( < t先閣免背面之注意事項再填寫本育) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •14- A7 B7 五、發明説明（η ) 焊料牢固連結通孔内部之引線以及通孔底部之端子墊。 如第3F圖所示，其次焊料珠311附接於基材電路之連 結墊，封裝體準備用於次一階段組裝。 雖然附囷僅顯示一個焊接系統，但需瞭解多個焊接系 統包括無引線系統也可應用作為連續用途。 本發明可未悖離其精髓或主要特點以其他特定形式具 體表現。因此本具體例於各方面僅供舉例說明之用而非限 制性’本發明之範圍係由隨附之申請專利範圍所限，而所 有屬於申請專利範圍之定義及相當範圍之變化皆涵蓋於本 發明之範圍。 ---------.裝— (#先閲t*-背面之注項再填寫本頁> 、11 -—球' 娌濟部中央標準局員工消費合作社印褽 準 標 家 國 國 中 用 一適 尺 I張 -紙 本
S N 公 7 29 -15- 經濟部中央標準局員工消費合作社印製 4 44 23 6 A7 B7 五、發明説明（13 ) 元件標號對照 101...基材 210‘” 鎳 102…通孔 211...焊料珠 103…軌線 301...積體電路晶片 104...引線 302...端子墊 201...積體電路晶片 303.:.薄膜 202...輪入/輸出端子墊 304...介電基材 203...鎳膜 305...軌線 204…基材 306...焊接罩 205...軌線 307…通孑L 206...焊接罩 308...引線 207…通孔 309..·黏合膜 208…引線 310…焊料糊 209...黏膠糊 311...焊料珠 ^^1· . - · ^^1 ^^1 —^1 ^^1 J- - - - n i^i ^^1 ί- U3 ·$ (^先閲讀•背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標牟（CNS > Α4規格（210 X 297公釐） -16-

Claims (1)

  1. 444 2 3 6 A8 B8 C8 D8 、申請專利範圍 L 一種倒裝晶片總成，其包含： U)—介電基材有複數通孔； <請先聞讀背面之注意事項再填寫本頁) (b) 介電基材有第一及第二相對面，及複數導電軌 線係於介電基材之第一表面上形成，該等軌線延伸入 特定通孔，較佳透過至少一引線但更佳透過製作於寶 折入通孔頂部之多條引線延伸； (c) 一半導體器件其具有第一表面及複數輸入/輸出 端子墊其有金屬膜堆疊成形於其上； (d) 該基材係由第二表面附接於半導體器件上，基 材通孔對正端子墊頂部，故端子墊之至少一者經由通 孔由基材之第一表面全然或部分暴露；及 (e) 基材至半導體器件之電連續性係經由沉積導電 材料於通孔其連結弯折引線與端子墊提供》 2. 如申請專利範圍第i項之倒裝晶片總成，其中（a)之基 材之介電材料係由塑膠製成。 3. 如申請專利範圍第1項之倒裝晶片總成，其中（a)之基 材之介電材料為撓性膜。 經濟部中央揉準局負工消費合作社印製 4·如申請專利範圍第1項之倒裝晶片總成’其中（a)之基 材之介電材料係由陶瓷製成》 5. 如申請專利範圍第1項之倒裝晶片總成，其中（b)之通 孔係藉雷射鑽孔形成。 6. 如申請專利範圍第1項之倒裝晶片總成’其中（b)之通 孔係藉機械衝孔形成* 7. 如申請專利範圍第1項之倒裝晶片總成’其中（b)之通 -17- 本紙張尺度逍用中國圃家標準（CNS ) A4说格（210X297公釐） 鲤濟部中央標準局負工消費合作社印装 444 236 A8 B8 C8 --_____DB_____ 、申請專利範圍 孔係藉電漿蝕刻形成。 8，如申請專利範圍第1項之倒裝晶片總成，其中（b)之通 孔係藉化學蝕刻形成》 9·如申請專利範圍第1項之倒裝晶片總成，其中彎折入（b) 之通孔之電引線係藉微影術及蝕刻方法製成。 10.如申請專利範圍第1項之倒裝晶片總成，其中弩折入（b) 之通孔之電引線係藉雷射切割製成》 11·如申請專利範圍第丨項之倒裝晶片總成，其中（c)之該 疊金屬膜係藉濺散方法沉積。 如申請專利範圍第1項之倒裝晶片總成，其中（c)之該 疊金屬膜係藉蒸鍍方法沉積。 13. 如申請專利範圍第i項之倒裝晶片總成，其中（c)之該 疊金屬膜係藉無電鍍敷方法沉積。 14. 如申請專利範圍第1項之倒裝晶片總成，其中於（句， 半導體器件附接至介電基材之材料為黏著劑糊/ 15. 如申請專利範圍第1項之倒裝晶片總成，其中於（d)， 半導體器件附接至介電基材之材料為黏著劑膜。 16. 如申請專利範圍第1項之倒裝晶片總成，其中（e)之導 電材料為導電黏著劑^ 17. 如申請專利範圍第1項之倒裝晶片總成，其中（e)之導 電材料為具導電性聚合物。 18·如申請專利範圍第1項之倒裝晶片總成，其中（e)之導 電材料為焊料。 19.如申請專利範圍第丨項之倒裝晶片總成，其中（e)之沉 本紙張尺度適用中阃國家梂準（CNS ) A4*t格（210X297公釐） -18- --------ά------ΐτ------0 . · Γ請先閲^'背面之注意事項再填寫本頁) ABCD 444 236 i、申請專利範圍 積方法為網印。 20_如申請專利範圍第1項之倒裝晶片總成，其中⑷之沉 積方法為配裝β 21，如申請專利範圍第1項之倒袭晶片總成，其中（e)之沉 積方法為喷射D ----.-----裝------訂------線 (贫先閲分背面之注意事項再填窝本肓) 經濟部中央樣率局貝工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） -19-
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