TW423081B - Semiconductor package - Google Patents
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- Publication number
- TW423081B TW423081B TW088100741A TW88100741A TW423081B TW 423081 B TW423081 B TW 423081B TW 088100741 A TW088100741 A TW 088100741A TW 88100741 A TW88100741 A TW 88100741A TW 423081 B TW423081 B TW 423081B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
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- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
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- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
1123^81 五、發明說明(1) [發明所屬之技術領域] 本發明係關於一種半導體封裝件,詳言之,即係 有機電路基扳,及倒裝接合法插裝之1(:晶片 格柵陣列(簡稱為BGA)型半導體封裝件者。 琢狀 [習用技術] :往,隨著半導體封裝件之小型化及高密度化有開 發直接以裸晶片面朝下,插裝於基板上之bga型半導體封 裝件者。於插裝裸晶片,係使用倒裝片接合的技術。 又因,近年來,為安裝攝影機一體型VTR或行動電話 機等播帶機器,對更小型化半導體封裝件的市場需求曰益 增加。因此,有所謂晶片尺寸/規模封裝件之倒裝片接合 半導體封裝件小型化為裸晶片略同尺寸 為CSP)之開發急速地進行。 T «裝件,(簡稱 兹參考第9圖及第10圖,冑習用一般性csp中之腿型 半導體之構成說明如下。第9圖為習用半導體封裝 面圖□第10圖(A)係於第9圖所示之半導體封裝件!之有機 電路基板13之頂視圖,而第10圖(3)為該有機電路基板13 之底面圖。 第9圖所示之半導體裝件丨係由:有機電路基板13,及 以倒裝片接合法插裝於有機電路基板之fc晶片ί〇構成。 於有機電路基板13之基材14之第1主表面13a形成κ晶 片接合用連接圖案15。然後,於第丨主表面側13a各連接圖 案15上,以具有開口部之抗蝕膜16覆蓋。又於第2主表面 側13B,有外部端子圖案17形成為格柵陣列。然後,以豆 C:\Program Files\Patent\310348. ptd 第 5 頁 咐方2308M 17« π修正 -__案號88100741 年彳月/占a 媒· τ:7年,月曰補充 五、發明說明(2) 1----- 開口部之抗蝕膜22覆蓋於第2主表面側13b,各外部端子圖 案17上。 , 又’因習用大部分之1C晶片係以焊線實裝為前提而設 叶’以電極墊11係沿1C晶片1〇之主表面i〇a外周部配設成 一排(周圍(peripheral)位置上)或交互之兩排。 然後,介由突起電極12以電性連接於電極墊u及連接 圖案15,將該1C晶片10以面朝下之狀態以倒裝接合法插 裝於有機電路基板13。再者,1C晶片1〇與有機電路基板13 之間隙’係以熱硬化性封裝樹脂2 3,由側面澆注法以樹脂 封裝為一想。 又,於外部端子圖案17上,形成球狀電極21。半導體 封裝件1係藉該球狀電極21實裝於主機板上(未圖示 然而,形成於1C晶片10墊電極11上之突起電極12,由 於形成時或倒裝接合插裝時之回焊處理等熱處理時熱膨脹 及收縮之重複。且因突起電極12之熱膨脹率與墊電極11之 熱膨脹率的不同’由突起電極12之熱膨脹而對墊電極11及 其周圍之1C晶片部分於加應力。該結果,沿整電極周 圍,在墊電極11與1C晶片10之間發生龜裂,而由該毳驳, 在墊電極11與1C晶片10間發生導電不良,有使1C晶片引起 誤動作之虞《因此,產生龜裂,有降低半導體封裝件可靠 性之問題》 又’習用有機電路基板13之連接圏案係,在對應於 1C晶片10電極墊11位置之位置,如第1〇圖(a)所示沿四角 形四邊配置為一排。有機電路基板13之外部端子圖案丨7係
C:\My Documents\310348.ptc 第6頁 2000.09.13.006 4 23〇 S1 五、發明說明(3) 如第1 0圖(B)所示,配列成格栅陣列狀。 15之如ί10圖⑴所示,係以圍繞連接圖案 署ΐ: ! ί,四角形狀,沿有機電路基板1之外周配 置成為一排。即,如第10圖(8)所示係在外 子 1 7之形成領域外側,以圍繞該形成領域配置之。 然後,於第I主表面側,形成連接各連接圖案15與各 貫穿孔18之配線圖案19 ’而在第2主表面侧接 各貫穿孔18之配線圖案2〇。然後,介由 貫穿孔18將各連接圓案15與各外部端子圖案丨7予以電性 之連接。 如第10圖(β)所示,貫穿孔18係配置在外部端子 1 及7二領門域之:側。為此’在所鄰接之外部端子圖案… 之間,須配置與其他外部連接圖案連接之配線…。 :配:之數量,將隨外部連接圖案i7之數量而增加。然 j,*外部連接圖案間之配線數增加,則須擴大鄰接外 接圖案間之間隔。因此,在習用半導趙封裝件卜難二 在不減少外部連接圖. > 而予以小型化 態下縮小有機電路基板面積 之拉本發明係有幾於上述問題所成者,係於嶋型 機器半導ΐ封裝件,提供一種適合於小型攜帶型 :器等之小型而可靠性優’且廉價的半導體封裝件為目 [發明之揭示] 如本發明之半導體封裝件,係、由在第m面側形成 五、發明說明(4) i C晶片連接用 格栅陣列狀, 性連接用貫穿 ,介由形成在 前述有機電路 與前述IC晶片 上形成球狀電 前述電極墊上 電極係由具有 共晶焊錫所形 圖案,於第2主表面侧配置外部 以形成將料㈣案輿球狀電極端子予以電 孔之有機電路基板,及在主表面形成電極整 該電極墊上之突起電極以倒裝連接法實裝於 基板之1C晶片構成。又於前述有機電路基板 之間隙填充封裝樹脂,之前述外部端子圖案 極之半導體封裝件。前述1(:晶片主表面係由 具有開口部之有機樹脂膜覆蓋’而前述突起 較熔融溫度低於前述有機樹脂膜耐熱溫度之 成0 如上述’本發明之半導體封裝件係以有機樹脂膜覆蓋 [C晶片之電極塾周圍之主表Φ。因此,可緩和突起電極熱 膨脹所致之電極墊周圍1(:晶片部分之應力。其結果可抑 制電極塾與1C晶片間發生龜裂。因此,可提高半導體封裝 件之可靠性。 然而,有機樹脂膜之耐熱性低。因此,如以習用突起 電極使用之高融點焊錫材,因自動對準插裝而加熱突起電 極,會融化有機樹脂膜α因此,難以將1(:晶片以自動對準 插裝法使用於有機電路基板。 另一方面’若實行非自動對準插裝,需將ic晶片之突 起電極以高精度對準有機電路基板之連接圖案予以定位。 因此’該時需高價位的連接裝置,致使半導體封裝件之成 本上昇。 於是’本發明係於形成有機樹脂膜後,再使用具有熔
C:\Program F i1es\Patent\310348. ptd 第 8 頁 423081 ΐ _案號 88100741 修正___ 五、發明說明(5) 融溫度較低於有機樹脂臈耐熱溫度之共晶焊錫形成突起電 極。其結果,可將突起電極予以回焊(re flow)時,不融化 有機樹脂膜之狀態下,將1C晶片插裝於有機電路基板上。 因此’依本發明’可以廉價提供抑制發生龜裂之高可 靠性半導體封裝件。 又’在本發明之半導體封裝件中,係將前述有機樹脂 膜之膜厚設定於ljtzm至l〇em之範圍内為宜。 如上述,膜厚為Ι/zm以上,可確保有機樹脂膜表面之 平坦性,同時,能充分緩和突起電極熱膨脹而加於電極墊 周園之應力。又’若膜厚為以下,可用旋轉塗膠法 容易地形成有機樹脂膜,同時,亦可避免電極墊上之開口 部縱橫比過大。 又,在 胺樹脂形成 如上述 則較使用非 又,實 機樹脂膜部 如上述 之平坦性。 開口部之圖 又,在 之前述共晶 宜。 本發明 前述有 ,若用 感光性 施本發 分臈厚 ,膜厚 又,若 案時, 本發明 焊錫為 之半導 機樹脂 感光性 樹脂, 明,宜 設定在 為ί β m 膜厚為 抑制開 之半導 以具錫 膜為宜。 聚亞醮胺樹脂 可簡化開口部 以將前述再配 1微米至3微米 以上,則可確 3 ν m以下,即 口部邊緣部分 餿封裝件中, 與鉛之重量比 係用感光性聚亞醢 形成有機樹脂膜, 圖案形成之過程。 線構造上之前述有 之範圍内。 保有機樹脂膜表面 可於形成電極墊上 成為突起形狀。 構成前述突起電極 為以6 : 4之組成為
4230 8 五、發明說明(6) ------------- 一若共晶焊錫之組成為上述重量比時,可將共晶焊錫之 融化溫度抑低於2 3 0 °C以下。 又’在實施本發明,宜以將前述IC晶片與前述電路基 板之間隙高度設定為至150 之範圍内。如上述,間隙 高度為50 以上’可加快封裝樹脂之注入速度,以縮短 樹脂封裝所需時間。又’間隙高度為1 50 " m以下,則可避 免由有機電路基板第1主表面到插裝之1C晶片上面為止之 高度過高。 又,在本發明之半導體封裝件中,宜以由銅或鎳芯層 ’及形成在該芯層上之前述共晶焊錫構成前述突起電極。 銅及鎳均為易焊金屬。因此,設有銅或鎳芯層,突起 電極之共晶焊錫回焊時,可防止該共晶焊錫形狀之擴開。 因此’在回焊後亦可確保一定值以上之突起電極高度。其 結果’可保持1C晶片與有機電路基板之間隙於一定值以上 之高度。 然而’共晶焊錫構成成分之錫,具容易與電極墊成分 (例如銅)融合的性質。因此’在電極墊上直接形成共晶焊 錫’將使晶焊錫中之錫原子行金屬原子擴散而降低電極墊 之密接性’致使突起電極剝離而發生斷線。 因此’於實施本發明時,宜將前述芯層厚度設定為5 至20 /zm之範圍内。 如上述’若將芯層厚度設定為5μιπ以上,該金屬原子 係於共晶焊錫與芯層之間擴散,可避免電極墊密極接性之 降低。其結果’可抑制斷線發生,提高半導體封裝件之可
C:\Program Files\Patent\310348. ptd 第 10 頁 五、發明說明(9) 脂封裝倒裝法插裝之1C晶片與有機電路機板之間隙時,有 下述各種優點。如可避免封裝用樹脂流入貫穿孔内,得以 正確控制封裝樹脂之注入量。又,可防止封裝樹脂經由貫 穿孔流出在第2許表面側。再者’亦可防止由貫穿孔有空 氣混入封裝樹脂内而發生空隙。 又’僅覆蓋貫穿孔之入口,不需要以固體填充貫穿孔 内的製程。 又,在本發明之半導體封裝件中,宜以將前述ic晶片 連接用圖案配置於偏離前述貫穿孔頂上方位置。
如上述’避開貫穿孔頂上方配置連接圖案,可於倒裝 法插裝1C晶片時,確實地將突起電極與連接圖案予以電性 連接D 又,在本發明之半導體封裝件中’宜以由構成前述突 起電極之共晶焊錫成分之材料形成前述球形電極。 如上述構成,可用低於有機樹脂膜耐熱溫度的低溫將 球狀電極回焊。其結果,可不必熔化有機樹脂膜,而將半 導體封裝件插裝於主機板上。 又’因於突起電極及焊錫球使用同一材料,可降低材 料成本。 再者,在回焊球狀電極時,得以熱處理將突起電極予 以熔化◊唯因,突起電極係由封裝樹脂封裝,雖突起電極 熔化亦不成為問題。 [圖式之簡單說明] 第1圖為表示有關本發明實施形態。之半導體封裝件
C:\ProgramFiles\Patent\310348.ptd 第 13 頁 4230 8] 五、發明說明(ίο) 剖面圖。 第2圖(A)中之(a)至(8)為表示非感光性有機樹脂獏之 圖案形成法之剖面數程圖,(B)中之(£1)至((1)為表示感光 性有機樹脂膜之圖案形成法之剖面製程圖’中之及 (f)為表示有機樹脂突起部之要部放大剖面圖。 第3圖為有關本發明實施形態之IC晶片平面圖。 第4圖為有關本發明實施形態之半導體封裝件之要部 放大剖面圖。 第5圖為有關本發明實施形態之IC晶片要部放大剖面 圖。 第6圖為有關本發明實施形態之IC晶片之究起電極剖 面圖。 第7圖為有關本發明實施形態之有機電路基板第1主表 面側平面圖。 第8圖為有關本發明實施形態之IC晶片與有機電路基 板間隙之高度與注入封裝樹脂所須時間之關係圖表。 第9圖為習用半導體封裝件之剖面圖。 第10圖(A)為習用有機電路基板第1主表面侧之平面圖 ’(B)為其第2主表面側之平面圖。 [圖號之說明] 1〇 ic晶片 12 突起電極 13a第1主表面側 14 基材 I 半導體封裝件 II 墊電極 13 有機電路基板 13b第2主表面側
驗4 2 3 Ο 8】 -i號Jgl〇074]_<Pf车Y月/夯日_修正 五、發明說明(11) ' - 15 連 接 圖 案 16 抗 蝕 17 外 部 端 子 圖 案 18 貫 穿 孔 19 配 線 圖 案 20 配 線 圖 案 21 球 狀 電 極 22 抗 蝕 材 23 封 裝 樹 脂 24 有 機 樹 脂 m 25 再 配 線 構 造 25a 鉻 層 25b 鋁 層 26 第 2有機樹脂膜 27 有 機 樹 脂 m 31 聚 亞 醯 胺 樹脂臈 32 抗 蝕 膜 33 遮 罩 圖 案 34 聚 亞 酿 胺 樹 脂膜 100 半 導 體 封 裝件 [實施發明之最佳形態] 兹參考圖式將本發明之實施形態說明如下。唯參考之 圖式係將各構成成分之大小,形狀及配置關係予以概略性 之顯示以便於理解本發明者β因此,本發明並不限定於 示例。 參照第1圖’將本發明之半導體封裝件之實施形態說 明如下°第1圖為有關本發明實施形態之半導體封裝件1〇〇 之剖面囷。該半導體封裝件1〇〇係由有機電路基板〗3,及 以倒裝接合法插裝於有機電路基板13上之ic晶片10構成。 [有機樹脂膜] 首先,特就於1C晶片10側構成中,有機樹脂膜27說明 如下。 該1C晶片10主表面係以厚度數之有機樹脂膜27覆 蓋。該有機樹脂膜27係於電極墊(在第1圖中未顯示)上具
C:\My Documents\310348.ptc 第 15 頁 2000.09.13.015 d2308tm -- 案號:’狀〗mmi 年β月/古日_修正 __ 五、發明說明(12) 有開口部。於各電極墊上形成突起電極12。 如上述方式設有機樹脂膜27,可緩和突起電極12因熱 膨脹致使對電極墊周圍1C晶片部分之應力。其結果,可抑 制電極墊與1C晶片10間之毳裂發生得以提高半導體封裝件 100之可靠性。又,由設置有機樹脂膜,可提高1(:電晶艘 10主表面之平坦性,以抑制樹脂封裝時發生空隙。 有機樹脂膜之膜厚若為lem以上’即可充分地緩和應 力’且可確保其平坦性。 在本實施形態中,係以感光性聚亞醮胺樹脂形成有機 樹脂27。聚亞醯胺樹脂膜為,可由旋轉塗覆法於形成1(;晶 片之晶圓上塗敷形成,故可容易地形成厚度均勻的樹脂 膜。該感光性聚亞醢胺樹脂得使用旭化成公司之貝美爾 (商標名)及東麗公司之浮德尼斯(商標名 又’因有機樹脂膜,如係膜厚lem以下時,可用旋轉 塗覆法極容易形成,且開口部之縱橫比亦不致於過大。 再者,聚亞醯胺樹脂有下述3種理由對半導體封裝件 之可靠性提高有所貢獻。第一 ’因聚亞醢胺樹脂對無機膜 之純化(passivation)膜及封裝樹脂具有高密接力,可防 止1C晶片之剝離。第二,因聚亞醮胺樹脂’具有高絕緣 性’可抑制突起電極間之洩漏電流發生。第三,因聚亞醮 胺樹脂在半導體封裝件之通常使用環境下具有充分的耐熱 性。 …、 又因’本實施例使用之聚亞酿胺樹腊具感光性,故可 簡化圖案形成製程。 茲參考第2圖比較非感光性及感光性樹脂之圖案形成
C:\My Documents\310348.ptc 第16頁 2000. 09.13.016 fc 4 2 3 0 8; _案號88100741_<年f月名曰 修正_ 五、發明說明(13) 製程說明如下。第2圖左側(A)之(a)至(g)係為說明在矽晶 圓上形成非感光性聚亞醯胺樹脂圖案形成製程之剖面製程 圖。第2圖右側(B)之(a)至(d)則係說明於矽晶圓上形成感 光性聚亞醯胺樹脂圖案形成製程之剖面製程圖。 在非感光性聚亞醯胺樹脂圖案形成時,首先,於矽晶 圓10上塗敷聚亞醯胺樹脂,以形成聚亞醯胺樹脂膜31(如 (A)之(a))。其次,在聚亞醯胺樹脂膜31上形成抗蝕膜 32(如(A)之(b))。再次,於抗蝕膜32上形成遮罩圖案 33(如(A)之(c))。再藉由該遮罩圖案33對抗蝕膜32進行曝 光,顯像後形成抗蝕圖案32a(如(A)之(d))。其後,去除 遮罩圖案33後,以抗蝕圖案32a為遮罩,對聚亞醯胺樹脂 31進行蝕刻,以形成聚亞醯胺樹脂圖案31a(如(A) 之(e))。剝離抗蝕圖案32a後(如(A)之(f))。熱化(cure) 聚亞醯胺樹脂圖案31a,以形成聚亞醯胺樹脂圖案31b以完 成圖案形成製程(如(A)之(g))。 相對,於感光性聚亞醯胺樹脂之圖案形成時,首先, 於矽晶圓10上塗敷感光性之聚亞醯胺樹脂以形成聚亞醯胺 樹脂膜34 (如(B)之(a))。其次,在聚亞醯胺樹脂膜34上, 形成遮罩圖案33(如(B)之(b))。再次,介由該遮罩圖案 33,對聚亞醯胺樹脂膜34進行曝光,顯像,以形成聚亞醯 胺樹脂圖案34a。然後,去除遮罩圖案33(如(B)之(c))。 熱化聚亞醯胺樹脂圖案34a,以形成聚亞醢胺樹脂圖案34b 而完成圖案形成製程(如(B)之(d))。 如上述,若使用感光性聚亞醯胺樹脂,可不須使用蝕 刻劑以進行蝕刻製程,故可簡化圖案形成製程。
C:\My Documents\310348.ptc 第17頁 2000.09.13.017
修正 然而,感光性聚 熱化感光性聚亞醮胺 胺樹脂包含感光性成分。因此, 案號 88innj^ 五、發明說明(14) 使其膜厚較最初時之2脂骐時’由於感光性成分之反應而 胺樹脂膜塗成較所需厚為薄。因此,須將感光性聚亞醢 樹脂膜時,應塗軟形=膜厚為厚。例如,須形成有機 然而,在樹脂囷柰*^达4以®厚之感光性聚亞酿胺樹脂膜° 其他部分為少。因此緣部,熱化所成膜厚之減少量較 突起狀的高突起邹兮$沿圖案邊緣形成聚亞酿胺樹鹿膜 (Β)之U)係於第2圖〔^^況如第2圖(Β)之(e)所示。第2圖 圖。 ;之((1)中以S虛線圓圍繞部分之放大 如第2圖(B)之(〇所_ 電極膜“稱「突祿下二、跨越突椽,堆積BX腿(共同 雷键fw f椽下側金屬Under Bump Metal」)35及 馇细办接小’ P於第2圖(B)之(f )令以?所示之虛線圓圍 '刀犬、端部,發生異常電鍍。因此,如有突椽時, 難以控制該電鍍之厚度。 於是’測量熱化後之感光性聚亞醯胺樹脂膜(T),及 表面為基準之突椽高度(H)之結果,例如,T = 21ym時, Η = 0,2μιη’ 而 Τ = 3·〇"瓜時 ’ η = 〇·4//ιπ。唯 T = 4.0"m 時 Η = 5· 5//ιη°如前述’當骐厚超過3#11|時,突椽將急激升高。因 此’感光性聚亞醢胺樹脂膜之膜厚係以3//ιη以下為宜。 [突起電極] 其次特就1C晶片1〇構成中之突起電極12說明如下。 突起電極12係由熔融溫度低於有機電路基板14耐熱溫 度(最高260度C)及有機樹脂膜27耐熱溫度(400度C左右)的
C:\My Documents\310348.ptc 第18頁 2000.09.13.018 ^230 8]
五'發明說明(15) 共晶燁錫形成。本實施形態中,共晶焊踢係以錫(Sn)與錯 (Pb)的重量比為60 % : 40 %組成,且是有230度以下之低炼 融溫度。因此,得以不熔化有機樹脂膜27以自動對準倒裝 法插裝1C晶片10。其結果,對直徑120 之焊接圖案,以 6〇#m的容許偏倚量範圍之精度容易插裝。 若以,Sn與Pb之重量比為95%:5%,炼融溫度 至314 °C之高熔融點焊錫形成突起電極時,無法於倒|插 裝1C晶片時’熔融突起電極。因此,插裝ic晶片1〇時無法 利用自動對準功能。其結果,將對直徑1 20从^之連接圖案 要求5 以内之精度。 ' 為實現上述高定位精度’需要能認識1(:晶片與有機 路之圖案位置關係的高性能的連接裝置。因該裝置為言 價,若係不利用自動對準功能將使半導體封裝件之成 本上升。 [突起電極之配置] 1C 露 表 參考第3圖,就突起電極12之配置說明如下。第3 晶片主表面側平面圖。在第3圖令,為了方便起見夫、 於主表面之焊線用電極墊lla及再配線構造25亦以實線 本實施形態係,利用廉價烊線用IC晶片1〇。 用電極塾係沿1C晶片主表面之外周成為周圍狀配置 3圖中,係以用虛線Z表示電極墊i】a 一部分配置 於第 為實現自動對準插裝,須確保連接圖案相互間 為一定位以上0因it卜ϊίΓϊΡϋ 士生 間陳 因此IC晶片主表面之突起電極亦須以一
^ 4230 8 i 五、發明說明C16) 定值以上的間隔配置。為於〖C晶片主表面上,以確保一定 值間隔而設置更多電極墊,係將突起電極丨2配置成格栅陣 列狀較其配置為周圍狀更佳。 本實施例係於電極墊11 a圍繞之内側領域γ内將突起電 極12配置成格栅陣列。在第3圖中,係以虛線框袼子χ表示 突起電極12之一部分配置。框袼子交點則為突起電極12之 位置。 又’突起電極1 2之間距’係消除以自動對準插裝時, 鄰接連接圖案相互間之短路發生,須確保一定值以上的突 起電極間距’換言之,須確保連接圖案之間距。 通常量產基板之線/空間最小間距為,8〇 effi/80以肌。 因此’連接圖案之最小直徑為80只jj D須用自動對準功能 時’應於鄰接連接圖案相互間’保持只肌的圖案間隙。 又因,最小空間為8 0 # in,該最小連接間距應為2 〇 〇以 m〇80 em + 40 βιπ + 80 ym)。因此,連接圖案之間距係以2〇〇 β m以上為宜。 [再配線構造] 然後’如第3圖及第4圖所示,在有機樹脂膜27肀,設 有將電極墊11a及突起電極12電性連接予以用再配線構造 25。第4圖為半導體封裝件1〇〇之要部放大剖面圖。又於第 3圖中’以實線表示再配線構造25之配置。 如上,若設再配線構造25,即可利用習用之廉償連接 用1C晶電’以抑制製造成本之上昇,同時,亦可將突起電 極配置成格柵陣列狀。
C:\Program Files\Patent\310348. ptd 第 20 頁 423〇8ί __案號 88100741_f Ά I^Q 修正 __ 五、發明説明(17) 再配線構造25係如第4圖所示。形成於連接用電極塾 11a上具有開口部之第1有機樹脂膜24上。再配線構造25 上係由第2有機樹脂膜26覆蓋。 第2有機樹脂膜26具有格栅陣列狀的開口部,露出於 該開口部之再配線構造25部分為倒裝連接用之電極墊 lib。於本實施形態中,係於電極墊lib表面由無電界電鑛 形成Au層(未圖示)。且於該電極塾lib形成突起電極12。 又於’本實施形態’係如第5圖所示,再配線構造25 係由銘層25a及铭層25b形成雙層構造《絡層25a與有機樹 脂膜27之密接性良好’而鋁層25b之導電性高。因此,該 堆積雙層之結果’可獲得密接性良好且導電性極高的再配 線構造25。 上述鉻層25a及鋁層25b係於焊線用電極墊ila上之開 口部上沿開口部下凹,但在第5圈中省略該凹部圖示。 [突起電極之構造] 其次’參照第6圖,將突起電極12之構造說明如下。 第6圖為說明突起電極12構造用之剖面圖β於第6圖十,為 說明方便’將相當於第4圖所示,焊線用電極墊lla之電極 墊11上形成突起電極12為例說明如下。其形成於倒裝連接 用電極墊lib上之突起電極12之構造亦同。 如第6圖所示’突起電極係在鋁電極墊丨丨上,依序堆 積共同電極膜(突橡下側金屬)12a及芯層12b,再於芯層 12b上形成共晶焊錫12c之焊锡突椽。 該共同電極膜(突橡下側金屬)12a具有將鋁層
C:\My Documents\310348.ptc
2000.09.13.021 第21頁 4230 8 1 _案號 88100741 弧f月心 修正 一 五、發明說明(18) (Al)l2al、鉻層(Cr)12a2及銅層(Cu)12a3以濺射法依序堆 積之構造。上述,A1層12al係為確保與電極墊11之密接性 而設’又,Cr層12a2具有防止Cu從Cu層12a3擴散至A1層 12al之功能。銅層12a3與鉻層12a2之密接性良好,且具容 易與焊錫之接合性。再者,銅層12a3可容易除去形成在表 面之自然氧化膜。 然而’若為利用自動對準功能以插裝1C晶片10而熔融 共晶焊錫12c’則共晶焊錫12c中之Sn原子擴散。若Sn原子 到達Cr層12a2’可使Cr層12a2之密接性降低。在本實施形 態中設厚度5// m以上的芯層12b。因設有該芯層12b之結 果,得以抑制Sn原子對Cr層12a2之擴散。 亦因,設有芯層12b,可於插裝1C晶片時,確保一定 位以上之突起電極高度。 若時,芯層12b厚度設為20/im以下,則可避免由突起 電極之熱膨脹引起對A1電極塾之應力過大,故電極塾η不 致於由I C晶片1 〇剝離。 [有機電路基板] 其次’就有機電路基板13之構成說明如下。 有機電路基板13係如第1圖及第4圖所示,以玻璃環氧 樹脂為基材14’在第1主表面側13a形成1C晶片連接用圖案 15。此時因1C晶片10之突起電極12配置成格栅陣列狀,各 連接圖案15亦配置為格網陣列狀。該第1主表面i3a係由各 連接圖案15上之具開口部之抗蝕膜16覆蓋。 [貫穿孔之配置]
C:\My Documents\310348.ptc 第22頁 2〇〇〇, 09.13· 022 4230 8 1 _案號881t)0741 押#今月作日 條正__ 五、發明說明(19) 其次’參考第7圖就有機電路基板13中之貫穿孔18之 配置說明如下。 第7圖係有機電路基板13第2主表面13b之平面囷。如 第7圖所示’在第2主表面側13b上,有外部端子圖案I?係 以格概陣列狀形成。而第2主表面側13b係由各外部端子電 路圖案17上具有開口部之抗蝕膜22所覆蓋。在本實施形態 中’係如第7圖所示’將貫穿孔配置施對外部端子圖案17 之格栅位置,偏倚半袼網之位置。 又’在第7圖中’係表示將各外部端子圖案I?,與連 接該外部端子圖案17之貫穿孔18分別予以直線連結。 如上述’將大部分貫穿孔18配置在外部端子圖案之 間,即不必在其他外部端子圖案相互間設原則配線。因 此’較於在外部端子圖案之形成領域外部配置貫穿孔時, 得以不減少端子圖案數狀態下縮少有機電路基板面積。加 以’能縮短外部端子圖案與連接圖案間之配線徑路之長 度,因而可提高半導體封裝件之電氣特性β 又於有機電路基板13之第1主表面側13a上,將1C晶片 連接用圖案15’配置在偏離貫穿孔18頂上方位置。如此避 開貫穿孔頂上方配置連接圖案15,即於倒裝方式插裝1C晶 片10時,可將突起電極12與連接圖案15確實予以電性連 接。 [樹脂封裝] 其次’就樹脂封裝說明如下。 該1C晶片1〇係如第4圖所示,將電極墊lib及連接圖案 15藉由突起電極12予以電性連接之結果,得以面向下的狀
C:\My Documents\310348.ptc 第23頁 2000. 09.13. 023 4230 8 ί 五、發明說明(20) 態於有機電路基板13實施倒裝作業。再者,ic晶片1〇與有 機電路基板1 3間之間隙係以熱硬化性之封裝樹脂2 3由侧洗 注法,以樹脂封裝為一體。 又,為將該封裝樹脂23填充於有機電路基板13與1(:晶 片1 0間之間隙’宜以將間隙之尚度保持於一定值以上之高 度。 在第8圖之圖表中表示間隙高度與填充之所需時間之 關係。該圖表之橫軸係表示間隙之高度,縱軸係表示時間 (秒)。圖中實線[係表示在角之有機電路基板13與〖〇晶 體10之間,以25 t填充黏度90泊之環氧樹脂所須之時間c 如實線I所示’間隙高度如低於50只111時^其填充所須時間 將急激變長。因此,間隙高度係以5 〇 y m以上為宜。 又’為避免半導體晶體100之高度過高,間隙高度係 以150 /im以下為宜。 [貫穿孔之封閉] 如將貫穿孔18配置成為如第7圖所示時,大部分貫穿 孔18係位於由倒裝法插裝於有機電路基板13之1(:晶體1〇正 下方。其結果,若於1C晶片10與有機電路基板13間之間隙 注入封裝樹脂23時,多數貫穿孔18内亦有封裝樹脂23流 入。其結果,難以正確地控制封裝樹脂2 3之注入量。若注 入量過多,封裝樹脂23將溢流於1C晶片10上面,使半導體 封裝100之厚度變厚。又,若注入量少,則貫穿孔18有空 氣混入於封裝樹脂2 3内部容易發生空隙。 於是’於本實施形態,係如第4圖所示,於有機電路
C:\Program Files\Patent\310348. ptd 第 24 頁 423081 Λ ^ _m. 88100741 θ生 f 3 戌 a 修正__ 五、發明說明(21) 基板13内由封裝樹脂23封裝之領域中,係用抗焊錫膜16覆 蓋貫穿孔18第1主表面側i3a端部。又,於本實施形態中, 貫穿孔18第2主表面側13b之端部亦用抗焊錫之膜22覆蓋。 如上述將封裝領域之貫裝孔18入口予以覆蓋,即可防 止封裝樹脂流入貫穿孔内,因之,可正破控制封裝樹脂之 注入量。其結果’得以抑制封裝樹脂之溢出及空隙發生。 又’僅封閉貫穿孔進口 ,不需要以固體填充貫穿孔内的製 程。 又,於習用集體電路基板,係如第10圖所示,將貫孔 設於外周部,故無封裝樹脂流入貫穿孔内,或空氣由貫穿 孔混入封裝樹脂内部等問題。又,若將IC晶片以焊線連接 時,1C晶片係黏貼於有機電路基板,故無須於1C晶片及有 機電路基板間注入封裝樹脂。 [球狀電極] 其次,就形成於有機電路基板之球狀電極21說明如 下。 如第1及第4圖所示,在外部端子圖案17上形成有球狀 電極21。半導體封裝件100係藉該球狀電極21插裝於母機 板(未圖示)。 於本實施形態中,係以構成突起電極12共晶焊錫之同 一成分材料形成該球狀電極21。如此構成,可申低於有機 樹脂膜27耐熱溫度的低溫回焊(re flow)球狀電極21。其結 果,得以不熔化有機樹脂膜27,於主機板上插裝半導體封 裝件。
C:\My Documents\310348.ptc 第25頁 2000.09. 13.025 修正 _案號 88100741 五、發明說明¢22) 又,須回焊球狀電極時,以加熱處理熔化突起電極。 然而,突起電極係由封裝樹脂23封裝,雖突起電極熔化也 不成問題。 上述實施形態,係以使用特定的材料,以特定條件形 成之節例說明,然而,本發明很多變更及變形。舉例來 說,上述實施形態,係以感光性聚亞醯胺樹脂來形成有機 樹脂膜之例來說明,唯於本發明中,有機樹脂膜為並不限 定於感光性聚亞醯胺。又,可使用聚亞醯胺樹脂以外之樹 脂做為有機樹脂膜。 [產業上之利用可能性] 如上述,有關本發明之半導體封裝件,係適用於安裝 在攝影機一體型VTR及小型攜帶機器上之小塑且具優異之 可靠性而廉價的半導體封裝件。
C:\My Documents\310348.ptc 第26頁 2000.09.13.026
Claims (1)
- 30 8 1 案號 88100741 六、申請專利範圍 1. 一種半導 I C晶片連 案為格棚· 子予以電 面形成電 倒裝連接 又於前述 樹脂之前 裝件,其 前述 之有機樹 而前 機樹脂膜 2. 如申請專 件係採前 圍内者。 3. 如申請專 該封裝件 者。 4. 如申請專 件之前述 之範圍内 5. 如申請專 件構成前 的重量比 體封裝件 接用圖案 陣列狀, 性連接用 極塾,介 法插裝於 有機電路 述外部端 特徵為: IC晶片主 脂膜覆蓋 述突起電 耐熱溫度 利範圍第 述有機樹 利範圍第 之,前述 利範圍第 有機樹脂 者。 利範圍第 述突起電 為6 : 4者< ,該封 ,於第 以形成 貫穿孔 由形成 前述有 基板與 子圖案 裝件係由在第1主表面 2主表面側有配置外部成 將該連接ϋ案與球狀電極圖 之有機電路基板,及在 ^ 在該電極塾上之突起it i 2 電路基板之1C晶片槿 1C晶片之間隙壌古+/ 機電路基板之1C晶片構成 前述1C晶片之間陳填充封 上形成球狀電極之丰敗 表面係由前述電極墊上具有開α 部 極係由具有較熔融溫度低於 之共晶焊錫所形成者。 1項之半導體封裝件’其中,該封裝 脂膜之膜厚設定為leni至Ι〇/Ζω之範 1或第2項之半導體封裝件,其中, 有機樹鹿膜為感光性聚亞醯胺樹脂 3項之半導體封裝件,其中,該封裝 膜部分之膜厚係設定於Ι/zm至3仁《1 則述有 1項之半導體封裝件,其令,該封裝 極之前述共晶焊锡係包含有錫與鉛2000.09.13.027 423081S 申清專利範圍 -- — _ -- 6.如申請專利範圍第lJS$主速#& ^ ^ - 件之針、+,丨广曰4〜項之半導趙封裝件’其中’該封裝 為5 〇至]\ n aa 前述電路基板間之間隙高度係設定 马50至150以m之範圍内者。 7,請專利範圍第1項之半導體封裝件,其巾,該封裝 件係使用銅或鎳之兮恳,,敦件^ ... 丘㈢拽姐德+ 夭U層,以及形成在該芯層上之刚遂 ,、a日焊錫構成之前述突起電極者。 請專利範圍第7項之半導體封裝件,其中,係將該 :件之前述心層厚度設定在5αιπ至20ym之範圍内者 9.:申請專利範圍第!項之半導體 ,該封裝 件之配置係於前逑突故番技+^ 2〇〇〇w之範圍内者起電極之間距設定為20 0 ^至 10·ΪΠ專利範!第1項之半導想封裝件,其中,該封裝 片主表面之外周形成焊接用電極墊, Z达大起電極係在前述墊所圍領域内配置成格柵陣列 '且於前述有機樹脂膜設冑卩電性連接該電極墊 扁法插裝用之前述突起電極之再配線構造者。 .申請專利範圍第1 〇項之半導體封裝件,該封裝件之 前述再配線構造係以鉻層與鋁層所成之雙層構造者。 2.如申請專利範圍第丨項之半導體封裝件,其中,該封裝 件係於前述有機電路基板形成之至少一部分前述貫穿 孔’係對形成前述外部端+圖案之格柵位倚半格 柵之位置上者。 13.如申請專利範圍第12項之半導體封裝件,盆 該 裝件係於前述有機電路基板中之以前述封裝樹脂封裝笫2頁 2000.09.13.028 年〒月/5日 修正 案號 88100741 六、申請專利範圍 的領域中,將前述貫穿孔之前述第1主表面端部以抗烊 膜覆蓋者。 14.如申請專利範圍第12項之半導體封裝件,其中,該封 裝件係將前述1C晶片連接用圖案,配置在偏離前述貫 穿孔頂上方的位置者。 15.如申請專利範圍第1項之半導體封裝件,其中,該封裝 件係以構成前述突起電極之共晶焊錫同一成分之材料 形成前述球狀電極者。C:\My Documents\310348.ptc 第3頁 2000.09.13. 029
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1999
- 1999-01-19 TW TW088100741A patent/TW423081B/zh not_active IP Right Cessation
- 1999-01-19 KR KR1019997008486A patent/KR100551607B1/ko not_active IP Right Cessation
- 1999-01-19 US US09/380,243 patent/US6177731B1/en not_active Expired - Lifetime
- 1999-01-19 WO PCT/JP1999/000140 patent/WO1999036957A1/ja active IP Right Grant
Cited By (3)
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US8178967B2 (en) | 2001-09-17 | 2012-05-15 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
US9369175B2 (en) | 2001-09-17 | 2016-06-14 | Qualcomm Incorporated | Low fabrication cost, high performance, high reliability chip scale package |
US8481418B2 (en) | 2002-05-01 | 2013-07-09 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
Also Published As
Publication number | Publication date |
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US6177731B1 (en) | 2001-01-23 |
WO1999036957A1 (fr) | 1999-07-22 |
KR20000076384A (ko) | 2000-12-26 |
KR100551607B1 (ko) | 2006-02-13 |
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