TW338188B - Output circuit - Google Patents

Output circuit

Info

Publication number
TW338188B
TW338188B TW085111054A TW85111054A TW338188B TW 338188 B TW338188 B TW 338188B TW 085111054 A TW085111054 A TW 085111054A TW 85111054 A TW85111054 A TW 85111054A TW 338188 B TW338188 B TW 338188B
Authority
TW
Taiwan
Prior art keywords
potential
pull
circuit
control signal
output
Prior art date
Application number
TW085111054A
Other languages
English (en)
Inventor
Shoichi Yoshizaki
Hisanori Yuki
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Application granted granted Critical
Publication of TW338188B publication Critical patent/TW338188B/zh

Links

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
TW085111054A 1995-09-21 1996-09-10 Output circuit TW338188B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24289495 1995-09-21
JP21826196A JP3530315B2 (ja) 1995-09-21 1996-08-20 出力回路

Publications (1)

Publication Number Publication Date
TW338188B true TW338188B (en) 1998-08-11

Family

ID=26522477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085111054A TW338188B (en) 1995-09-21 1996-09-10 Output circuit

Country Status (2)

Country Link
JP (1) JP3530315B2 (zh)
TW (1) TW338188B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917358A (en) * 1997-12-09 1999-06-29 Motorola, Inc. Method and output buffer with programmable bias to accommodate multiple supply voltages
JP2009147985A (ja) * 2001-08-31 2009-07-02 Renesas Technology Corp 半導体装置
US7145364B2 (en) * 2005-02-25 2006-12-05 Agere Systems Inc. Self-bypassing voltage level translator circuit
US7605618B2 (en) * 2006-01-12 2009-10-20 Qualcomm, Incorporated Digital output driver and input buffer using thin-oxide field effect transistors
JP4724575B2 (ja) * 2006-03-03 2011-07-13 Ｏｋｉセミコンダクタ株式会社 レベル変換回路
JP5095184B2 (ja) * 2006-11-22 2012-12-12 フリースケール セミコンダクター インコーポレイテッド レベルシフタ回路
JP2008199153A (ja) * 2007-02-09 2008-08-28 Matsushita Electric Ind Co Ltd レベルシフタ
JP5966402B2 (ja) * 2012-02-10 2016-08-10 凸版印刷株式会社 半導体集積回路
JP5838141B2 (ja) * 2012-02-27 2015-12-24 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5886112B2 (ja) * 2012-04-11 2016-03-16 ルネサスエレクトロニクス株式会社 半導体集積回路装置、レベルシフト回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637624A (ja) * 1992-07-13 1994-02-10 Nec Corp レベル変換回路
JPH0774616A (ja) * 1993-07-06 1995-03-17 Seiko Epson Corp 信号電圧レベル変換回路及び出力バッファ回路
JP2901171B2 (ja) * 1993-10-08 1999-06-07 日本電信電話株式会社 ディープサブミクロンｍｏｓｆｅｔ出力バッファ回路
US5493244A (en) * 1994-01-13 1996-02-20 Atmel Corporation Breakdown protection circuit using high voltage detection

Also Published As

Publication number Publication date
JP3530315B2 (ja) 2004-05-24
JPH09148915A (ja) 1997-06-06

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees