TW338188B - Output circuit - Google Patents

Output circuit

Info

Publication number
TW338188B
TW338188B TW085111054A TW85111054A TW338188B TW 338188 B TW338188 B TW 338188B TW 085111054 A TW085111054 A TW 085111054A TW 85111054 A TW85111054 A TW 85111054A TW 338188 B TW338188 B TW 338188B
Authority
TW
Taiwan
Prior art keywords
potential
pull
circuit
control signal
output
Prior art date
Application number
TW085111054A
Other languages
Chinese (zh)
Inventor
Shoichi Yoshizaki
Hisanori Yuki
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Application granted granted Critical
Publication of TW338188B publication Critical patent/TW338188B/en

Links

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  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

An output circuit featuring the first potential as input signal of the circuit of the power potential for input and, based on the output circuit of the circuit and the second potential for power supply and other circuit output signals, featuring: signal generator circuit, for the first and the second control signals according to the output signal of said circuit for the first potential and the grounding potential in difference of undulation; voltage change circuit with the first control signal produced by said signal generator circuit for input and by change of the undulation of the first control signal for pulling up the control signal for output; pull-up circuit, with the pull-up control signal from the voltage change citcuit for input and based on the indication of the pull-up control signal for the control of the potential of the output to determine its pull-up to the second potential; and pull down circuit, with the second control signal generated by the signal generator for input of pull down signal and based on the indication of the pull-down control signal for the control of the potential of the output to determine its pull-down to the grounding potential; said pull-up circuit having the P-type MOS transistor for the supply of the second potential to the power supply and input of the pull-up control signal of the gate and in the connection of the power supply to the said P-type MOS transistor drain, making the drain be connected to the output as the second P-type MOS transistor on the third potential gate; said pull-down circuit having the P-type MOS transistor for the supply of the second potential to the power supply and input of the pull-up control signal of the gate and in the connection of the power supply to the said S N-type MOS transistor drain, making the drain be connected to the output as the first N-type MOS transistor on the third potential gate; said voltage change circuit indicating when the pull-up circuit pulls up the output potential to the second potential,the pull-up control signal potential making it to second potential deducting the 1 P-type MOS transistor critical value and make the second potential deduct the P-type MOS transistor gate oxidized membrane to over relevant voltage, without indicating the pull-up circuit to the second potential by keeping the pull-up control signal potential as the second potential.
TW085111054A 1995-09-21 1996-09-10 Output circuit TW338188B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24289495 1995-09-21
JP21826196A JP3530315B2 (en) 1995-09-21 1996-08-20 Output circuit

Publications (1)

Publication Number Publication Date
TW338188B true TW338188B (en) 1998-08-11

Family

ID=26522477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085111054A TW338188B (en) 1995-09-21 1996-09-10 Output circuit

Country Status (2)

Country Link
JP (1) JP3530315B2 (en)
TW (1) TW338188B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917358A (en) * 1997-12-09 1999-06-29 Motorola, Inc. Method and output buffer with programmable bias to accommodate multiple supply voltages
JP2009147985A (en) * 2001-08-31 2009-07-02 Renesas Technology Corp Semiconductor device
US7145364B2 (en) * 2005-02-25 2006-12-05 Agere Systems Inc. Self-bypassing voltage level translator circuit
US7605618B2 (en) * 2006-01-12 2009-10-20 Qualcomm, Incorporated Digital output driver and input buffer using thin-oxide field effect transistors
JP4724575B2 (en) * 2006-03-03 2011-07-13 Ｏｋｉセミコンダクタ株式会社 Level conversion circuit
JP5095184B2 (en) * 2006-11-22 2012-12-12 フリースケール セミコンダクター インコーポレイテッド Level shifter circuit
JP2008199153A (en) * 2007-02-09 2008-08-28 Matsushita Electric Ind Co Ltd Level shifter
JP5966402B2 (en) * 2012-02-10 2016-08-10 凸版印刷株式会社 Semiconductor integrated circuit
JP5838141B2 (en) * 2012-02-27 2015-12-24 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
JP5886112B2 (en) * 2012-04-11 2016-03-16 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device, level shift circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637624A (en) * 1992-07-13 1994-02-10 Nec Corp Level conversion circuit
JPH0774616A (en) * 1993-07-06 1995-03-17 Seiko Epson Corp Signal voltage level converting circuit and output buffer circuit
JP2901171B2 (en) * 1993-10-08 1999-06-07 日本電信電話株式会社 Deep submicron MOSFET output buffer circuit
US5493244A (en) * 1994-01-13 1996-02-20 Atmel Corporation Breakdown protection circuit using high voltage detection

Also Published As

Publication number Publication date
JP3530315B2 (en) 2004-05-24
JPH09148915A (en) 1997-06-06

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees