TW202339160A - 半導體裝置及半導體裝置的測試方法 - Google Patents
半導體裝置及半導體裝置的測試方法 Download PDFInfo
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Abstract
提供一種半導體裝置和半導體裝置的測試方法,能夠在不增加電路面積的情況下對在半導體封裝的內部連接的內部佈線進行連接檢測測試。
本實施形態的半導體裝置具有:第一焊墊;第二焊墊;內部佈線;電源電路;開關;及控制電路。第一焊墊,形成在第一半導體晶片上,並且連接到配置在電源焊墊與接地焊墊之間的保護二極體。第二焊墊,形成在第二半導體晶片上。內部佈線,其在半導體裝置的內部進行第一焊墊和第二焊墊的連接。電源電路,其向第二焊墊輸出電流。開關,其設置在第二焊墊與電源電路之間。控制電路,當其被輸入連接檢測測試用的測試信號時,輸出第一控制信號用於控制開關成為接通/斷開,輸出第二控制信號以使電源電路輸出電流。
Description
[關連申請]
本申請主張日本專利申請2022-043053號(申請日:2022年3月17日)的基礎申請的優先權。本申請藉由參照該基礎申請而包含基礎申請的全部內容。
本實施形態關於半導體裝置及半導體裝置的測試方法。
已知一種將多個半導體晶片搭載在一個半導體封裝中的多晶片封裝(MCP)。多個半導體晶片的一部分佈線在半導體封裝內部連接並且不連接到半導體封裝外部。在對在半導體封裝內部連接的內部佈線進行連接檢測測試時,需要在半導體晶片內設置用於連接檢測的電路,導致增加了電路面積。
本實施形態的目的是提供一種半導體裝置及半導體裝置的測試方法,其能夠在不增加電路面積的情況下對連接在半導體封裝內部的內部佈線進行連接檢測測試。
本實施形態的半導體裝置具有:第一焊墊;第二焊墊;內部佈線;電源電路;開關;及控制電路。第一焊墊,其形成在至少2個以上的半導體晶片中的第一半導體晶片上,並且連接到配置在電源焊墊與接地焊墊之間的保護二極體。第二焊墊,其形成在至少2個以上的半導體晶片中的第二半導體晶片上。內部佈線,其在半導體裝置的內部進行第一焊墊和第二焊墊的連接。電源電路,其向第二焊墊輸出電流。開關,其設置在第二焊墊與電源電路之間。控制電路,當其被輸入連接檢測測試用的測試信號時,輸出第一控制信號用於控制開關成為接通/斷開(ON/OFF),並且輸出第二控制信號以使電源電路輸出電流。
以下,參照圖面說明實施形態。
(第一實施形態)
圖1是表示第一實施形態的半導體裝置的結構的剖面圖。圖1所示的半導體裝置100具備多個半導體晶片10、20、30、40、佈線基板50、間隔物60、多個接合導線70a、70b、70c、70d、70e、70f和密封樹脂80。又,表示多個接合導線70a、70b、70c、70d、70e和70f中的任一者或全部時統稱為接合導線70。此外,半導體裝置100具有四個半導體晶片10、20、30、40,但也可以具有至少兩個以上的半導體晶片。
佈線基板50具有第一表面50a和第二表面50b。此外,佈線基板50在其表面和內部具有多個佈線層51a、51b、51c。又,表示佈線層51a、51b、51c中的任意一層或全部時稱為佈線層51。佈線基板50是絕緣樹脂佈線基板、陶瓷佈線基板等。具體而言,例如,可以使用使用了玻璃環氧樹脂的印刷佈線基板。通常,佈線基板50的表面覆蓋有用於保護佈線的阻焊劑等。
多個接合焊墊52a、52b、52c、52d形成在佈線基板50的第一表面50a上。當表示多個接合焊墊52a、52b、52c、52d中的任何一個或所有時稱為接合焊墊52。
多個外部端子53a、53b、53c、53d形成在佈線基板50的第二表面50b上。外部端子53a、53b、53c、53d是例如焊錫球等突起狀端子。當表示多個外部端子53a、53b、53c、53d中的任意一個或全部時稱為外部端子53。
接合焊墊52a、52d和外部端子53a、53b分別藉由佈線層51a、51b電連接。此外,接合焊墊52b、52c經由佈線層51c電連接。圖1所示的佈線基板50表示佈線層51的一部分、接合焊墊52的一部分以及外部端子53的一部分。
半導體晶片10設置在佈線基板50的第一表面50a上。間隔物60設置在半導體晶片10上。半導體晶片20、30、40按順序堆疊在間隔物60上。例如,半導體晶片10是記憶體控制器等半導體晶片,半導體晶片20、30、40是由記憶體控制器控制的NAND快閃記憶體等半導體晶片,但不限於此。半導體晶片10、20、30、40例如可以是DRAM等記憶體元件、或微處理器等運算元件、或信號處理元件等任意的半導體晶片。
焊墊11a和11b形成在半導體晶片10的表面上。焊墊21a和31a分別形成在半導體晶片20和30的表面上。焊墊41a和41b形成在半導體晶片40的表面上。圖1所示的半導體晶片10、20、30、40示出了焊墊的一部分。例如,在半導體晶片10、20、30、40中的每一個都形成有用於電源、接地和多個信號(例如,輸入/輸出信號、時序信號、時脈信號、致能信號(enable signal)、就緒/忙碌等信號)的多個焊墊。
焊墊11a和11b以及接合焊墊52a和52b分別藉由接合導線70a和70b電連接。焊墊21a和接合焊墊52c藉由接合導線70c電連接。焊墊21a和焊墊31a藉由接合導線70d電連接。焊墊31a和焊墊41a藉由接合導線70e電連接。焊墊41b和接合焊墊52d藉由接合導線70f電連接。
在下面的說明中,連接半導體晶片10和半導體晶片40的半導體封裝(半導體裝置1)的內部的佈線,即接合導線70b、佈線層51c、接合導線70c、70d、70e的佈線被稱為內部佈線90(參照圖2)。
半導體晶片10和半導體晶片20係藉由接合導線70b、接合焊墊52b、佈線層51c、接合焊墊52c和接合導線70c連接,但不限於此。例如,半導體晶片10的焊墊11b和半導體晶片20的焊墊21a可以藉由接合導線70直接連接的構成。取代經由接合導線70的連接,可以使用半導體晶片10的焊墊和佈線基板50上的電極直接連接的所謂的倒裝晶片(Flip Chip)連接。此外,半導體晶片20的焊墊和佈線基板50上的電極可以藉由倒裝晶片連接。此時,半導體晶片10和半導體晶片20可以經由設置在佈線基板50上的佈線連接。在這種構成中,將從半導體晶片10的焊墊到設置在佈線基板50上的佈線和半導體晶片20的焊墊為止稱為內部佈線90。
半導體晶片10、20、30和40的外周由設置在佈線基板50的上表面側的密封樹脂80密封。
在如上所述構成的半導體裝置100中,使用測試器等進行連接檢測測試以測試接合導線70是否在半導體封裝的內部正常被連接。這種連接檢測測試通常稱為開路/短路(open/short)測試。在該開路/短路測試中,使用測試器從外部端子53將大約幾十至100μA的電流通到測量對象的焊墊。藉此,電流經由與電源端子連接的靜電破壞對策用的保護二極體從電源端子輸出。在這種狀態下,測量電源端子與接地端子之間的電壓,並根據測量的電壓值檢測連接狀態。
這種開路/短路測試可以對經由佈線層51和接合焊墊52直接連接到外部端子53的接合導線70進行連接檢測測試,但無法對在半導體封裝內部連接的內部佈線90進行連接檢測測試。
例如,在圖1的例子中,能夠對經由佈線層51a、51b連接到外部端子53a、53b的佈線(接合導線70a、70f)進行連接檢測測試。另一方面,對未連接到外部端子53的內部佈線90不能進行連接檢測測試。
為了確認半導體封裝的內部佈線90的連接狀態,以往使用藉由X射線穿透半導體封裝來觀察,或從動作測試的結果來推斷的方法。然而,在用X射線穿透半導體封裝的方法中,很難判定是否存在電氣開路或短路。另外,在藉由從動作測試的結果推斷的方法中,難以判斷半導體晶片內部是否存在不良或連接多個半導體晶片的內部佈線90是否存在不良。
本實施形態的半導體裝置100具有如下所述能夠檢測內部佈線90的連接狀態的構成。特別地,當堆疊多個半導體晶片10、20、30和40時,藉由在內部佈線90的最遠端的半導體晶片彼此之間進行連接檢測測試,即在圖1的示例中在半導體晶片10和40之間進行連接檢測測試,從而,也可以對連接到半導體晶片20和30的接合導線70c和70d進行連接檢測測試。
圖2是表示第一實施形態的半導體裝置的構成的方塊圖。另外,在圖2中,對與圖1相同的構成要素標註相同的符號並省略說明。
除了焊墊11a、11b之外,半導體晶片10還具備電源焊墊11c、接地焊墊11d、保護二極體12a、12b和內部電路13。電源焊墊11c和接地焊墊11d經由佈線基板50的佈線層51連接到外部端子(電源端子)53c和外部端子(接地端子)53d。
保護二極體12a和12b是用於防止靜電破壞的保護二極體,並且設置在電源焊墊11c和接地焊墊11d之間。保護二極體12b的陽極與接地焊墊11d連接,陰極與保護二極體12a的陽極連接。保護二極體12a的陰極連接到電源焊墊11c。
焊墊11b,係連接到保護二極體12a和12b之間的節點,並且連接到內部電路13。此外,焊墊11b經由半導體封裝內的內部佈線90連接到半導體晶片40的焊墊41a。
除了焊墊41a、41b之外,半導體晶片40還具有開關42、電源電路43和控制電路44。
焊墊41a經由內部佈線90與半導體晶片10的焊墊11b連接。焊墊41b經由接合導線70f、接合焊墊52d、佈線層51b連接到外部端子53b。焊墊41b,係與控制電路44連接,例如使用測試器110等從外部端子53b輸入測試信號。該測試信號經由焊墊41b輸入到控制電路44。
開關42設置在焊墊41a與電源電路43之間。開關42由MOS電晶體構成,藉由來自控制電路44的第一控制信號(接通/斷開控制信號)來控制其接通/斷開。
電源電路43設置在開關42與接地之間,由來自控制電路44的第二控制信號控制。當從控制電路44輸入第二控制信號時,電源電路43輸出電流(恆定電流)。具體而言,當輸入第二控制信號時,電源電路43持續輸出例如幾十μA~100μA左右的電流。
當從焊墊41b供給測試信號時,控制電路44向開關42輸出第一控制信號以接通開關42。此外,當從焊墊41b供給測試信號時,控制電路44向電源電路43輸出第二控制信號以連續輸出電流。
當從電源電路43輸出電流並接通開關42時,電流經由焊墊41a、內部佈線90、焊墊11b、保護二極體12a流入電源焊墊11c。以這種方式,在電流連續輸出到與內部佈線90連接的特定的焊墊41a的狀態下,測試器110可以測量半導體晶片10的電源焊墊11c與接地焊墊11d之間的電壓,從而判定內部佈線90的連接狀態。
儘管數值取決於保護二極體12a的接通特性,例如當在電源焊墊11c與接地焊墊11d之間的測量電壓為0.3V以下時,測試器110判定內部佈線90短路(短路不良),如果是0.9V以上時,則判定內部佈線90開路(開路不良),如果測量電壓高於0.3V且低於0.9V,則判定內部佈線90正常連接(測試經由)。
在圖2的例子中,僅對連接半導體晶片10的焊墊11b和半導體晶片40的焊墊41a的內部佈線90進行連接檢測測試,但半導體裝置100具有多個內部佈線90。例如,半導體裝置100具有用於在半導體晶片10和半導體晶片40之間發送和接收輸入/輸出信號、時序信號、時脈信號、致能信號、就緒/忙碌信號等。因此,半導體裝置100具有能夠對除了電源佈線和接地佈線以外的多個內部佈線90進行連接檢測測試的構成。參照圖3說明能夠對多個內部佈線90執行連接檢測測試的構成。
圖3是表示對多個內部佈線進行連接檢測測試的半導體裝置的構成的方塊圖。另外,在圖3中,對與圖2相同的構成要素標註相同的符號並省略說明。
半導體晶片10具備多個輸入/輸出用的焊墊15a、15b和15c。當表示多個焊墊15a、15b和15c中的任何一個或全部時稱為焊墊15。
半導體晶片40具備分別對應於多個焊墊15a、15b和15c的多個輸入/輸出用的焊墊45a、45b和45c。當表示多個焊墊45a、45b和45c中的任何一個或全部時稱為焊墊45。
焊墊15a、15b和15c以及焊墊45a、45b和45c分別藉由內部佈線90a、90b和90c連接。當表示內部佈線90a、90b和90c中的任何一個或全部時稱為內部佈線90。
焊墊15a、15b和15c中的每一個連接到保護二極體12a和12b之間的節點。開關42a、42b和42c分別設置在焊墊45a、45b和45c與電源電路43之間。即,從電源電路43輸出的電流被供給到多個開關42a、42b和42c。
開關42a、42b和42c被來自控制電路44的第一控制信號個別控制為接通/斷開(ON/OFF)。當表示多個開關42a、42b和42c中的任何一個或全部時稱為開關42。
當輸入測試信號時,控制電路44向電源電路43輸出第二控制信號,並控制電源電路43輸出電流。然後,控制電路44向開關42a、42b、42c的每一個輸出第一控制信號,依次控制開關42a、42b、42c的接通/斷開,對內部佈線90a、90b、90c進行連接檢測測試。
具體而言,控制電路44向開關42a、42b和42c的每一個輸出用於接通開關42a以及用於斷開開關42b和42c的第一控制信號。由此,對與焊墊45a連接的內部佈線90a進行連接檢測測試。
接著,控制電路44向開關42a、42b和42c的每一個輸出用於接通開關42b以及用於斷開開關42a和42c的第一控制信號。由此,對與焊墊45b連接的內部佈線90b進行連接檢測測試。
接著,控制電路44向開關42a、42b和42c的每一個輸出用於接通開關42c以及用於斷開開關42a和42b的第一控制信號。由此,對與焊墊45c連接的內部佈線90c進行連接檢測測試。
以這種方式,控制電路44在從電源電路43持續輸出電流的狀態下,選擇性地接通開關42a、42b和42c。藉此,電流可以僅流過焊墊45a、45b、45c之中與特定的焊墊45連接的內部佈線90。結果,半導體裝置100能夠依次進行與焊墊45a、45b、45c連接的內部佈線90a、90b、90c的連接檢測測試。
圖4是表示第一實施形態的半導體裝置的連接檢測測試的一個例子的流程圖。
首先,向半導體晶片40輸入測試信號(步驟S1)。該測試信號從測試器110經由焊墊41b輸入到控制電路44。
當輸入測試信號時,控制電路44將第一控制信號輸出到開關42(步驟S2)。此時,控制電路44輸出用於接通開關42的第一控制信號,該開關42是設置在要進行連接檢測測試的內部佈線90所連接的焊墊45與電源電路43之間。
接著,控制電路44向電源電路43輸出第二控制信號以使連續輸出電流。(步驟S3)。藉此,從電源電路43連續輸出例如100μA左右的電流,該電流經由焊墊45、內部佈線90、焊墊15、保護二極體12a流入電源焊墊11c。
接著,測試器110測量電源焊墊11c和接地焊墊11d之間的電壓(步驟S4)。測試器110根據測量到的電壓檢測半導體裝置100的內部佈線90的連接狀態(步驟S5)。如上所述,測試器110在測量電壓為0.3V以下時判定為短路不良,當測量電壓為0.9V以上時判定為開路不良,並且當測量電壓高於0.3且低於0.9V時判斷為測試經由。
接著,控制電路44判斷是否已經檢測了全部的內部佈線90的連接狀態(步驟S6)。當控制電路44判定未檢測全部的內部佈線90的連接狀態時,變更要接通的開關42 (步驟S7),並返回到步驟S4的處理。另一方面,當控制電路44判定已經檢測了全部的內部佈線90的連接狀態時,處理結束。
如上所述,半導體裝置100向控制電路44輸入測試信號以接通/斷開開關42,並控制電源電路43進行內部佈線90的連接檢測測試。半導體晶片40例如是NAND型快閃記憶體,並且具備進行資料的寫入及讀出的電源電路43和控制電路44。
亦即,半導體裝置100僅藉由在現有的電路構成中的電源電路43與焊墊45之間設置開關42來進行內部佈線90的連接檢測測試。因此,半導體裝置100無需設置由例如比較器、邊界掃描單元(boundary scan cell)等構成的連接檢測用的電路,就能夠進行內部佈線90的連接檢測測試。
因此,本實施形態的半導體裝置100可以在不增大電路面積的情況下對在半導體封裝內部進行連接的內部佈線進行連接檢測測試。
(第二實施形態)
接著,說明第二實施形態。
圖5係表示第二實施形態的半導體裝置的構成的方塊圖。在圖5中,對與圖2相同的構成要素標記相同的符號,並省略說明。
如圖5所示,在半導體裝置100A中,取代圖2的半導體晶片10和40而使用半導體晶片10A和40A來構成。半導體晶片10A是對圖2的半導體晶片10追加焊墊11e。半導體晶片40A是對圖2的半導體晶片40追加開關46。
半導體晶片40A的焊墊41b不與外部端子53連接,而是與半導體裝置100A內部的焊墊11e連接。焊墊11e經由半導體封裝內的內部佈線90d與半導體晶片40A的焊墊41b連接。此外,開關46設置在焊墊41b與電源電路43之間。當不需要將內部佈線90d與其他內部佈線區分開來時,內部佈線90d被稱為內部佈線90。
當從測試器110輸入測試信號時,半導體晶片10A經由焊墊11e和內部佈線90d將測試信號輸出到半導體晶片40A。當從測試器110輸入用於開始連接檢測測試的信號時,半導體晶片10A在內部電路中可以產生用於連接檢測測試的測試信號,並且該測試信號可以經由焊墊11e和內部佈線90d輸出到半導體晶片40A。當半導體晶片10A向半導體晶片40A輸出測試信號時,停止來自測試器110的電源的供給。
輸入到半導體晶片40A的測試信號經由焊墊41b輸入到控制電路44。當輸入測試信號時,控制電路44與第一實施形態一樣執行內部佈線90的連接檢測測試。
此外,當輸入測試信號時,控制電路44輸出用於接通開關46的第一控制信號。結果,來自電源電路43的電流經由焊墊41b和內部佈線90d流到半導體晶片10A的焊墊11e,從而可以執行內部佈線90d的連接檢測測試。
在圖5的例子中,經由1個內部佈線90d在半導體晶片10A與40A之間傳送測試信號,但不限於這樣的構成。例如,可以在半導體晶片10A與40A之間設置有用於收發資料等信號DQ<7:0>的信號線(內部佈線90d)。因此,半導體晶片10A可以經由八個內部佈線90d將測試信號傳送到半導體晶片40A的控制電路44。
圖6是表示第二實施形態的半導體裝置的連接檢測測試的一個例子的流程圖。另外,在圖6中,對與圖4相同的處理賦予相同的符號,並省略其說明。
首先,從半導體晶片10A向半導體晶片40A輸入測試信號(步驟S11)。該測試信號經由半導體晶片10A的焊墊11e、內部佈線90d以及半導體晶片40A的焊墊41b被輸入到控制電路44。當輸入測試信號時,控制電路44在步驟S2的處理中向開關42輸出第一控制信號,在步驟S3的處理中向電源電路43輸出第二控制信號。
接著,斷開半導體晶片10A的電源(步驟S12)。即,停止從測試器110向半導體晶片10A的電源供給。藉此,不向半導體晶片10A的電源焊墊11c施加電源,從而可以測量電源焊墊11c與接地焊墊11d之間的電壓。
當半導體晶片10A的電源被斷開時,測試器110在步驟S4的處理中測量電源焊墊11c與接地焊墊11d之間的電壓,並在步驟S5的處理中根據測量到的電壓來檢測半導體裝置100A的內部佈線90的連接狀態。
接著,在步驟S6的處理中,控制電路44判斷是否已經檢測過所有內部佈線90的連接狀態。如果判定沒有檢測所有內部佈線90的連接狀態,則在步驟S7的處理中變更要接通的開關,並且處理返回到步驟S4。另一方面,如果判定已經檢測過所有內部佈線90的連接狀態,則處理結束。
如上所述,在半導體裝置100A中,即使構成為不能將測試信號從測試器110直接輸入到半導體晶片40A時,也可以經由半導體晶片10A將測試信號傳送到半導體晶片40A。藉此,和第一實施形態同樣地,接收到測試信號的半導體晶片40A可以執行內部佈線90的連接檢測測試。
因此,和第一實施形態同樣地,半導體裝置100A可以在不增加電路面積的情況下,對在半導體封裝內部連接的內部佈線進行連接檢測測試。
需要說明的是,本說明書中的流程圖中的每個步驟,只要不違背其性質,可以變更執行順序,可以同時執行多個步驟,也可以每次執行的順序不同。
以上說明本發明之幾個實施形態,但是該等實施形態僅為提示之例,並非用來限定發明之範圍者。彼等新規的實施形態可以用其他各種形態來實施,在不脫離發明之要旨的範圍內可以進行各種省略、替換、變更。彼等實施形態或其變形亦包含在發明之範圍或要旨內,並且包含在與申請專利範圍中記載的發明具有均等範圍者之內。
10,10A,20,30,40,40A:半導體晶片
11,15,21,31,41,45:焊墊
11c:電源焊墊
11d:接地焊墊
12a,12b:保護二極體
13:內部電路
42,46:開關
43:電源電路
44:控制電路
50:佈線基板
51:內部佈線
52:接合焊墊
53:外部端子
60:間隔物
70:接合導線
80:封止樹脂
90:內部佈線
100,100A:半導體裝置
110:測試器
[圖1]是表示第一實施形態的半導體裝置的結構的剖面圖。
[圖2]是表示第一實施形態的半導體裝置的構成的方塊圖。
[圖3]是表示進行多個內部佈線的連接檢測測試的半導體裝置的構成的方塊圖。
[圖4]是表示第一實施形態的半導體裝置的連接檢測測試的一個例子的流程圖。
[圖5]是表示第二實施形態的半導體裝置的構成的方塊圖。
[圖6]是表示第二實施形態的半導體裝置的連接檢測測試的一個例子的流程圖。
10,40:半導體晶片
11a,11b,41a,41b:焊墊
11c:電源焊墊
11d:接地焊墊
12a,12b:保護二極體
13:內部電路
42:開關
43:電源電路
44:控制電路
53a,53b,53c,53d:外部端子
90:內部佈線
100:半導體裝置
110:測試器
Claims (9)
- 一種半導體裝置,係具備至少2個以上的半導體晶片者,並且該半導體裝置具備: 第一焊墊,其形成在前述至少2個以上的半導體晶片中的第一半導體晶片上,並且連接到配置在電源焊墊與接地焊墊之間的二極體; 第二焊墊,其形成在前述至少2個以上的半導體晶片中的第二半導體晶片上; 內部佈線,其在前述半導體裝置的內部連接前述第一焊墊與前述第二焊墊; 電源電路,其向前述第二焊墊輸出電流; 開關,其設置在前述第二焊墊與前述電源電路之間;及 控制電路,當其被輸入連接檢測測試用的測試信號時,輸出第一控制信號用於控制前述開關成為接通/斷開,輸出第二控制信號以使前述電源電路輸出前述電流。
- 如請求項1之半導體裝置,其中 前述第一半導體晶片具有多個前述第一焊墊, 前述第二半導體晶片具有:與多個前述第一焊墊的每一個對應的多個前述第二焊墊;將多個前述第一焊墊和多個前述第二焊墊進行連接的多個前述內部佈線;及設置於多個前述第二焊墊與前述電源電路之間的多個前述開關; 前述控制電路輸出前述第一控制信號用於依次控制多個前述開關的接通/斷開。
- 如請求項1之半導體裝置,其中 前述第一半導體晶片和前述第二半導體晶片連接到前述內部佈線的最遠端。
- 如請求項1之半導體裝置,其中 前述測試信號從測試器輸入到前述第二半導體晶片。
- 如請求項1之半導體裝置,其中 前述測試信號經由前述第一半導體晶片輸入到前述第二半導體晶片。
- 如請求項1之半導體裝置,其中 前述內部佈線包含接合導線。
- 如請求項1之半導體裝置,其中 前述第一焊墊和前述第二焊墊直接連接到佈線基板。
- 一種半導體裝置的測試方法,該半導體裝置係具備:第一焊墊,其形成在至少2個以上的半導體晶片中的第一半導體晶片上,並且連接到配置在電源焊墊與接地焊墊之間的二極體;第二焊墊,其形成在前述至少2個以上的半導體晶片中的第二半導體晶片上;及內部佈線,其在內部連接前述第一焊墊與前述第二焊墊;在該測試方法中, 輸出第二控制信號用於使前述電源電路輸出前述電流, 輸出第一控制信號用於接通設置在前述第二焊墊與前述電源電路之間的開關, 測量前述電源焊墊與前述接地焊墊之間的電壓, 根據測量結果來檢測前述內部佈線的連接狀態。
- 如請求項8之半導體裝置的測試方法,其中 在輸出前述第一控制信號之後, 斷開前述第二半導體晶片的電源。
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