TW202038425A - Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device - Google Patents

Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device Download PDF

Info

Publication number
TW202038425A
TW202038425A TW108141611A TW108141611A TW202038425A TW 202038425 A TW202038425 A TW 202038425A TW 108141611 A TW108141611 A TW 108141611A TW 108141611 A TW108141611 A TW 108141611A TW 202038425 A TW202038425 A TW 202038425A
Authority
TW
Taiwan
Prior art keywords
wafer
chip
adhesive sheet
substrate
semiconductor device
Prior art date
Application number
TW108141611A
Other languages
Chinese (zh)
Other versions
TWI814944B (en
Inventor
夏川昌典
蘇德軒
上田麻未
平本祐也
Original Assignee
日商日立化成股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商日立化成股份有限公司 filed Critical 日商日立化成股份有限公司
Publication of TW202038425A publication Critical patent/TW202038425A/en
Application granted granted Critical
Publication of TWI814944B publication Critical patent/TWI814944B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Adhesive Tapes (AREA)

Abstract

This manufacturing method of a semiconductor device involves (A) a step for preparing a structure that is provided with a substrate, a first chip arranged on the substrate, and multiple spacers arranged on the substrate and around the first chip, (B) a step for preparing a chip with an adhesive piece, said chip with an adhesive piece comprising a second chip larger than the first chip and an adhesive piece arranged on one side of the second chip, (C) a step for arranging the second chip above the first chip such that the adhesive piece contacts the top of the multiple spacers, and (D) a step for sealing the first chip, the spacers and the second chip. The height of the top of the spacers and the height of the top of the first chip coincide prior to carrying out step (D).

Description

半導體裝置及其製造方法、以及在半導體裝置的製造中使用的結構體Semiconductor device, manufacturing method thereof, and structure used in manufacturing semiconductor device

本揭示是有關於一種半導體裝置及其製造方法、以及在半導體裝置的製造中使用的結構體。The present disclosure relates to a semiconductor device, a manufacturing method thereof, and a structure used in the manufacture of the semiconductor device.

以前，於將半導體晶片（chip）與基板連接時，一直廣泛地應用打線接合（wire bonding）。打線接合是使用金線等金屬細線連接半導體晶片與基板的方式。為了應對針對半導體裝置（以下，有時稱為「半導體封裝」）的高功能化、高積體化及高速化等要求，被稱為覆晶（flip chip）連接的方式正在推廣。覆晶連接是在半導體晶片或基板上形成稱為凸塊（bump）的導電性突起而在半導體晶片與基板之間直接連接的方式。In the past, wire bonding has been widely used when connecting a semiconductor chip to a substrate. Wire bonding is a method in which thin metal wires such as gold wires are used to connect a semiconductor chip and a substrate. In order to meet the requirements for high functionality, high integration, and high speed for semiconductor devices (hereinafter, sometimes referred to as "semiconductor packages"), a method called flip chip connection is being promoted. Flip-chip connection is a method in which conductive bumps called bumps are formed on a semiconductor wafer or a substrate to directly connect the semiconductor wafer and the substrate.

如上所述，半導體封裝除了高功能化以外，還要求薄型化及小型化。作為要求進一步的小型化、薄型化及高功能化的半導體封裝，晶片堆疊（chip stack）型封裝、封裝堆疊封裝（Package On Package，POP）、矽穿孔（Through-Silicon Via，TSV）等亦開始普及。由於晶片被配置為立體狀而不是平面狀，故所述半導體封裝可以減小尺寸。例如，專利文獻1揭示了第一半導體元件（例如控制器）被埋入用於接著第二半導體元件的接著膜的形態的半導體裝置。 [現有技術文獻] [專利文獻]As described above, in addition to higher functionality, semiconductor packages are also required to be thinner and smaller. As semiconductor packages that require further miniaturization, thinning and high functionality, chip stack packaging, package on package (POP), and through-silicon via (TSV) have also begun universal. Since the wafer is configured in a three-dimensional shape instead of a planar shape, the semiconductor package can be reduced in size. For example, Patent Document 1 discloses a semiconductor device in which a first semiconductor element (for example, a controller) is embedded in an adhesive film for bonding the second semiconductor element. [Prior Art Literature] [Patent Literature]

[專利文獻1]日本專利特開2015-120836號公報[Patent Document 1] Japanese Patent Laid-Open No. 2015-120836

[發明所欲解決之課題] 根據本發明者等人的研究，如專利文獻1所記載的半導體裝置般，在將基板上的第一晶片埋入接著膜的情況下，存在容易產生空隙的問題。另外，為了抑制空隙產生，使用流動性優異的比較軟的接著膜時，經由接著膜接著的第二晶片的位置發生偏移或應變，在此基礎上再積層多個晶片容易變得困難。此外，需要使用具有能夠埋入第一晶片的充分的厚度的接著膜，從而存在半導體封裝變厚的傾向。[The problem to be solved by the invention] According to research by the inventors, there is a problem that voids are likely to occur when the first wafer on the substrate is embedded in the adhesive film like the semiconductor device described in Patent Document 1. In addition, in order to suppress the generation of voids, when a relatively soft adhesive film with excellent fluidity is used, the position of the second wafer adhered via the adhesive film is shifted or strained, and it is likely to be difficult to stack multiple wafers on this basis. In addition, it is necessary to use an adhesive film having a sufficient thickness to be embedded in the first wafer, and there is a tendency for the semiconductor package to become thick.

本發明者等人研究了代替將第一晶片埋入接著膜，而在配置第一晶片的位置周圍配置間隔物來形成空間，在該空間內配置第一晶片後，用密封材填充空間的構成。其結果發現，在利用密封材填充空間時，如果間隔物的上表面的高度與第一晶片的上表面的高度存在偏差，則利用密封材的填充容易變得困難。The inventors of the present invention have studied a structure in which spacers are arranged around the position where the first wafer is arranged to form a space instead of embedding the first wafer in the adhesive film, and after the first wafer is arranged in the space, the space is filled with a sealing material . As a result, it was found that when filling the space with the sealing material, if the height of the upper surface of the spacer differs from the height of the upper surface of the first wafer, filling with the sealing material is likely to become difficult.

本揭示提供一種將第一晶片搭載於基板上且將第二晶片配置於第一晶片的上方的構成的半導體裝置的製造方法，其能夠抑制半導體裝置變得過厚，同時能夠容易實施用密封材密封第一晶片及第二晶片的作業。另外，本揭示還提供一種不過厚且密封材的填充性優異的半導體裝置及在該半導體裝置的製造中使用的結構體。 [解決課題之手段]The present disclosure provides a method for manufacturing a semiconductor device having a configuration in which a first wafer is mounted on a substrate and a second wafer is arranged above the first wafer, which can prevent the semiconductor device from becoming excessively thick and can easily implement a sealing material The operation of sealing the first wafer and the second wafer. In addition, the present disclosure also provides a semiconductor device that is not too thick and has excellent filling properties of the sealing material, and a structure used in the manufacture of the semiconductor device. [Means to solve the problem]

本揭示所涉及的半導體裝置的製造方法包括：（A）準備結構體的步驟，所述結構體包括基板、配置於基板上的第一晶片、及配置於基板上且配置於第一晶片的周圍的多個間隔物；（B）準備帶接著劑片的晶片的步驟，所述帶接著劑片的晶片包括尺寸大於第一晶片的第二晶片、及設置於第二晶片的一個面的接著劑片；（C）以帶接著劑片的晶片的接著劑片與多個間隔物的上表面接觸的方式，將第二晶片配置於第一晶片的上方的步驟；以及（D）將第一晶片、間隔物、及第二晶片密封的步驟，且在實施（D）步驟之前，間隔物的上表面的高度與第一晶片的上表面的高度一致。再者，此處所謂「一致」是指間隔物的上表面的高度與第一晶片的上表面的高度之差小於10 μm。The method of manufacturing a semiconductor device according to the present disclosure includes: (A) a step of preparing a structure, the structure including a substrate, a first wafer arranged on the substrate, and a first wafer arranged on the substrate and arranged around the first wafer (B) the step of preparing a wafer with adhesive sheet, the wafer with adhesive sheet includes a second wafer larger in size than the first wafer, and an adhesive disposed on one side of the second wafer (C) the step of arranging the second wafer above the first wafer in such a way that the adhesive sheet of the wafer with the adhesive sheet is in contact with the upper surface of the plurality of spacers; and (D) the first wafer , Spacers, and the step of sealing the second wafer, and before performing step (D), the height of the upper surface of the spacer is consistent with the height of the upper surface of the first wafer. Furthermore, the term “coincidence” here means that the difference between the height of the upper surface of the spacer and the height of the upper surface of the first wafer is less than 10 μm.

在實施上述（D）步驟之前，間隔物的上表面的高度與第一晶片的上表面的高度一致是指在（C）步驟中配置的帶接著劑片的晶片的接著劑片亦與第一晶片的上表面接觸。假設第一晶片的上表面與接著劑片不接觸，兩者之間存在間隙，則在該間隙中難以填充密封材，容易產生空隙。另一方面，如果充分擴大第一晶片的上表面與接著劑片之間的間隔，則雖然密封材的填充性提高，但是有半導體裝置變厚的傾向。與此相對，根據本揭示的製造方法，能夠兼顧密封材的優異填充性與半導體裝置的薄型化。Before performing step (D) above, the height of the upper surface of the spacer is consistent with the height of the upper surface of the first wafer. This means that the adhesive sheet of the wafer with adhesive sheet arranged in step (C) is also the same as that of the first wafer. The upper surface of the wafer is in contact. Assuming that the upper surface of the first wafer and the adhesive sheet are not in contact with each other, and there is a gap between the two, it is difficult to fill the sealing material in the gap, and a gap is likely to occur. On the other hand, if the space between the upper surface of the first wafer and the adhesive sheet is sufficiently enlarged, although the filling property of the sealing material is improved, the semiconductor device tends to become thicker. In contrast, according to the manufacturing method of the present disclosure, it is possible to achieve both excellent filling properties of the sealing material and thinning of the semiconductor device.

在本揭示的製造方法中，只要在實施（D）步驟之前，間隔物的上表面的高度與第一晶片的上表面的高度一致即可。例如，在（A）步驟中準備的結構體中，間隔物的上表面的高度與第一晶片的上表面的高度可一致，或者，在（A）步驟中準備的結構體中，間隔物的上表面高於第一晶片的上表面，在之後的（C）步驟中，可用帶接著劑片的晶片壓扁間隔物，使間隔物的上表面的高度與第一晶片的上表面的高度一致。In the manufacturing method of the present disclosure, it is sufficient that the height of the upper surface of the spacer is the same as the height of the upper surface of the first wafer before the step (D) is implemented. For example, in the structure prepared in step (A), the height of the upper surface of the spacer and the height of the upper surface of the first wafer may be the same, or, in the structure prepared in step (A), the height of the spacer The upper surface is higher than the upper surface of the first wafer. In the subsequent step (C), the spacer can be flattened with the wafer with adhesive sheet, so that the height of the upper surface of the spacer is consistent with the height of the upper surface of the first wafer .

所述間隔物的一個形態是包括晶片、及設置在所述晶片的一個面的接著劑片的虛設晶片。如上所述，在（C）步驟中，在藉由用帶接著劑片的晶片壓扁間隔物來調整間隔物的高度的情況下，較佳為虛設晶片所具備的接著劑片較帶接著劑片的晶片所具備的接著劑片軟。另外，較佳為虛設晶片所具備的接著劑片較帶接著劑片的晶片所具備的接著劑片厚。One form of the spacer is a dummy wafer including a wafer and an adhesive sheet provided on one surface of the wafer. As described above, in the step (C), in the case of adjusting the height of the spacer by squeezing the spacer with a wafer with an adhesive sheet, it is preferable that the adhesive sheet provided on the dummy chip is better than the adhesive sheet. The adhesive sheet included in the wafer is soft. In addition, it is preferable that the adhesive sheet provided in the dummy chip is thicker than the adhesive sheet provided in the wafer with the adhesive sheet.

就半導體裝置的高速化的觀點而言，較佳為第一晶片藉由覆晶連接而搭載於基板。在藉由覆晶連接將第一晶片搭載於基板的情況下，與使用接著膜接著於基板的情況相比，連接部的高度容易產生偏差，其結果，第一晶片的上表面的高度位置容易產生偏差。因此，在藉由覆晶連接搭載第一晶片的情況下，較佳為在（A）步驟中準備間隔物的上表面高於第一晶片的上表面的結構體，以便在（C）步驟中能夠藉由用帶接著劑片的晶片壓扁間隔物來調整間隔物的高度。From the viewpoint of increasing the speed of the semiconductor device, it is preferable that the first chip be mounted on the substrate by flip chip connection. When the first chip is mounted on the substrate by flip chip connection, the height of the connection portion is likely to vary compared with the case where the adhesive film is used to adhere to the substrate. As a result, the height position of the upper surface of the first chip is easy Create a deviation. Therefore, in the case of mounting the first chip by flip chip connection, it is better to prepare a structure with the upper surface of the spacer higher than the upper surface of the first chip in step (A) so that in step (C) The height of the spacer can be adjusted by squeezing the spacer with a wafer with an adhesive sheet.

本揭示所涉及的半導體裝置包括：基板；第一晶片，配置於基板上；多個間隔物，配置於基板上且配置於第一晶片的周圍；第二晶片，配置於第一晶片的上方，尺寸較第一晶片大；接著劑片，將多個間隔物與第二晶片接著；以及密封材，將第一晶片、間隔物及第二晶片密封，且接著劑片與第一晶片的上表面接觸。第一晶片例如是控制器晶片。The semiconductor device involved in the present disclosure includes: a substrate; a first chip arranged on the substrate; a plurality of spacers arranged on the substrate and arranged around the first chip; a second chip arranged above the first chip, The size is larger than that of the first chip; the adhesive sheet is used to bond a plurality of spacers with the second chip; and the sealing material is used to seal the first chip, the spacers and the second chip, and the adhesive sheet is connected to the upper surface of the first chip contact. The first chip is, for example, a controller chip.

所述半導體裝置能夠藉由本揭示所涉及的製造方法來製造。本揭示所涉及的半導體裝置中，由於接著劑片與第一晶片的上表面接觸，故不會過厚且密封材的填充性優異。The semiconductor device can be manufactured by the manufacturing method according to the present disclosure. In the semiconductor device according to the present disclosure, since the adhesive sheet is in contact with the upper surface of the first wafer, it is not too thick and the sealing material has excellent filling properties.

本揭示提供一種在所述半導體裝置的製造中使用的結構體。第一形態的結構體包括基板、配置在基板上的第一晶片、以及配置在基板上且配置在第一晶片周圍的多個間隔物，且間隔物的上表面的高度與第一晶片的上表面的高度一致。第二形態的結構體包括基板、配置在基板上的第一晶片、以及配置在基板上且配置在第一晶片的周圍的多個間隔物，且間隔物的上表面高於第一晶片的上表面，間隔物包含藉由被壓扁，使間隔物的上表面的高度與第一晶片的上表面的高度一致的材料。The present disclosure provides a structure used in the manufacture of the semiconductor device. The structure of the first form includes a substrate, a first wafer arranged on the substrate, and a plurality of spacers arranged on the substrate and arranged around the first wafer. The height of the upper surface of the spacers is the same as that of the upper surface of the first wafer. The height of the surface is uniform. The structure of the second form includes a substrate, a first wafer arranged on the substrate, and a plurality of spacers arranged on the substrate and arranged around the first wafer. The upper surface of the spacers is higher than that of the first wafer. On the surface, the spacer includes a material that is squashed so that the height of the upper surface of the spacer is consistent with the height of the upper surface of the first chip.

本揭示的結構體亦可為更包括第二晶片的形態。所述形態的結構體包括：基板；第一晶片，配置於基板上；多個間隔物，配置於基板上且配置於第一晶片的周圍；第二晶片，配置於第一晶片的上方，尺寸較第一晶片大；以及接著劑片，將多個間隔物與第二晶片接著，且接著劑片與第一晶片的上表面接觸。 [發明的效果]The structure of the present disclosure may also have a form that further includes a second chip. The structure of the form includes: a substrate; a first wafer arranged on the substrate; a plurality of spacers arranged on the substrate and arranged around the first wafer; a second wafer arranged above the first wafer with a size Larger than the first wafer; and an adhesive sheet, bonding a plurality of spacers with the second wafer, and the adhesive sheet is in contact with the upper surface of the first wafer. [Effects of the invention]

根據本揭示，提供一種將第一晶片搭載於基板上且將第二晶片配置於第一晶片的上方的構成的半導體裝置的製造方法，其能夠抑制半導體裝置變得過厚，同時能夠容易實施用密封材密封第一晶片及第二晶片的作業。另外，根據本揭示，提供一種不過厚且密封材的填充性優異的半導體裝置及在該半導體裝置的製造中使用的結構體。According to the present disclosure, there is provided a method of manufacturing a semiconductor device having a configuration in which a first wafer is mounted on a substrate and a second wafer is arranged above the first wafer, which can prevent the semiconductor device from becoming too thick and can be easily implemented. The sealing material seals the operation of the first wafer and the second wafer. In addition, according to the present disclosure, a semiconductor device that is not too thick and has excellent filling properties of the sealing material and a structure used in the manufacture of the semiconductor device are provided.

以下，一邊適宜參照圖式，一邊對本揭示的實施方式進行說明。於以下的說明中，對相同或相當部分標註相同符號，省略重覆說明。另外，上下左右等位置關係只要無特別說明，則是指基於圖式所示的位置關係。進而，圖式的尺寸比率並不限於圖示的比率。再者，本說明書中，所謂「(甲基)丙烯酸」是指「丙烯酸」或與其相對應的「甲基丙烯酸」。Hereinafter, the embodiments of the present disclosure will be described while referring to the drawings as appropriate. In the following description, the same or corresponding parts are denoted by the same symbols, and repeated descriptions are omitted. In addition, the positional relationship such as up, down, left, and right refers to the positional relationship shown in the drawings unless otherwise specified. Furthermore, the size ratio of the drawing is not limited to the ratio shown in the figure. In addition, in this specification, "(meth)acrylic acid" refers to "acrylic acid" or "methacrylic acid" corresponding to it.

＜第一實施方式＞ （半導體裝置） 圖1是示意性表示本實施方式的半導體裝置的剖面圖。該圖所示的半導體裝置100包括：基板10、配置在基板10的表面上的晶片S1（第一晶片）、配置在基板10的表面上且配置在晶片S1周圍的兩個虛設晶片D（間隔物）、配置在晶片S1上方的晶片S2（第二晶片）、以及積層在晶片S2上的晶片S3、晶片S4、將基板10的表面上的電極（未示出）與晶片S2、晶片S3、晶片S4分別電連接的線w；以及將晶片S1、晶片S2、晶片S3、晶片S4、虛設晶片D及線w密封的密封材50。在晶片S1的上表面及多個虛設晶片D的上表面與晶片S2之間配置有接著劑片的硬化物Sc。在半導體裝置100中，晶片S1的上表面的高度與虛設晶片D的上表面的高度一致。也就是說，硬化物Sc與晶片S1的上表面及虛設晶片D的上表面接觸。<First Embodiment> (Semiconductor device) FIG. 1 is a cross-sectional view schematically showing the semiconductor device of this embodiment. The semiconductor device 100 shown in the figure includes a substrate 10, a wafer S1 (first wafer) arranged on the surface of the substrate 10, and two dummy wafers D (spaced apart) arranged on the surface of the substrate 10 and arranged around the wafer S1. ), wafer S2 (second wafer) arranged above wafer S1, wafer S3, wafer S4 laminated on wafer S2, and electrode (not shown) on the surface of substrate 10 with wafer S2, wafer S3, A wire w electrically connected to the wafer S4; and a sealing material 50 that seals the wafer S1, the wafer S2, the wafer S3, the wafer S4, the dummy wafer D, and the wire w. The cured product Sc of the adhesive sheet is arranged between the upper surface of the wafer S1 and the upper surface of the plurality of dummy wafers D and the wafer S2. In the semiconductor device 100, the height of the upper surface of the wafer S1 matches the height of the upper surface of the dummy wafer D. That is, the hardened object Sc is in contact with the upper surface of the wafer S1 and the upper surface of the dummy wafer D.

基板10可以是有機基板，亦可以是引線框架等金屬基板。關於基板10，就抑制半導體裝置100的翹曲的觀點而言，基板10的厚度例如為90 μm～300 μm，亦可以為90 μm～210 μm。The substrate 10 may be an organic substrate, or a metal substrate such as a lead frame. Regarding the substrate 10, from the viewpoint of suppressing the warpage of the semiconductor device 100, the thickness of the substrate 10 is, for example, 90 μm to 300 μm, or may be 90 μm to 210 μm.

晶片S1例如是控制器晶片，並藉由覆晶連接而搭載於基板10。俯視時晶片S1的形狀例如為矩形（正方形或長方形）。晶片S1的一邊的長度例如為5 mm以下，亦可以是2 mm～5 mm或1 mm～5 mm。晶片S1的厚度例如是10 μm～150 μm，亦可以是20 μm～100 μm。The chip S1 is, for example, a controller chip, and is mounted on the substrate 10 by flip chip connection. The shape of the wafer S1 in a plan view is, for example, a rectangle (square or rectangle). The length of one side of the wafer S1 is, for example, 5 mm or less, and may also be 2 mm to 5 mm or 1 mm to 5 mm. The thickness of the wafer S1 is, for example, 10 μm to 150 μm, or 20 μm to 100 μm.

晶片S2例如是記憶體晶片，經由接著劑片的硬化物Sc接著在晶片S1及虛設晶片D上。俯視觀察時，晶片S2具有較晶片S1大的尺寸。俯視時晶片S2的形狀例如為矩形（正方形或長方形）。晶片S2的一邊的長度例如為20 mm以下，亦可以是4 mm～20 mm或4 mm～12 mm。晶片S2的厚度例如是10 μm～170 μm，亦可以是20 μm～120 μm。再者，晶片S3、晶片S4亦例如為記憶體晶片，經由接著劑片的硬化物Sc而接著在晶片S2上。晶片S3、晶片S4的一邊的長度只要與晶片S2相同即可，晶片S3、晶片S4的厚度亦只要與晶片S2相同即可。The chip S2 is, for example, a memory chip, and the cured product Sc of the adhesive sheet is adhered to the chip S1 and the dummy chip D. When viewed from the top, wafer S2 has a larger size than wafer S1. The shape of the wafer S2 in a plan view is, for example, a rectangle (square or rectangle). The length of one side of the wafer S2 is, for example, 20 mm or less, and may also be 4 mm to 20 mm or 4 mm to 12 mm. The thickness of the wafer S2 is, for example, 10 μm to 170 μm, or 20 μm to 120 μm. Furthermore, the chip S3 and the chip S4 are, for example, memory chips, which are adhered to the chip S2 via the hardened material Sc of the adhesive sheet. The length of one side of wafer S3 and wafer S4 may be the same as wafer S2, and the thickness of wafer S3 and wafer S4 may be the same as wafer S2.

虛設晶片D起到在晶片S1的周圍形成空間的間隔物的作用。虛設晶片D包括晶片D1、及設置在晶片D1的一個面的接著劑片Da。如圖2（a）所示，可在遠離晶片S1的兩側的位置配置兩個虛設晶片D（形狀：長方形），亦可如圖2（b）所示，在對應於晶片S1的角的位置分別配置一個虛設晶片D（形狀：正方形，總共四個）。俯視時晶片D1的一邊的長度例如為20 mm以下，亦可為1 mm～20 mm或1 mm～12 mm。晶片D1的厚度例如是30 μm～150 μm，亦可以是80 μm～120 μm。The dummy wafer D functions as a spacer that forms a space around the wafer S1. The dummy wafer D includes a wafer D1 and an adhesive sheet Da provided on one surface of the wafer D1. As shown in Figure 2(a), two dummy wafers D (shape: rectangular) can be arranged at positions away from both sides of the wafer S1, or as shown in Figure 2(b), placed at the corners corresponding to the wafer S1 A dummy chip D (shape: square, four in total) is arranged in each position. The length of one side of the wafer D1 in a plan view is, for example, 20 mm or less, and may be 1 mm to 20 mm or 1 mm to 12 mm. The thickness of the wafer D1 is, for example, 30 μm to 150 μm, or 80 μm to 120 μm.

如上所述，虛設晶片D的上表面的高度與晶片S1的上表面的高度一致。例如，藉由調整接著劑片Da的厚度，能夠使覆晶連接的晶片S1的上表面的位置與虛設晶片D的上表面的位置一致。As described above, the height of the upper surface of the dummy wafer D coincides with the height of the upper surface of the wafer S1. For example, by adjusting the thickness of the adhesive sheet Da, the position of the upper surface of the flip-chip connected chip S1 can be aligned with the position of the upper surface of the dummy chip D.

參照圖3（a）至圖3（e），說明作為帶接著劑片的晶片的一個形態的虛設晶片D的製作方法的一例。首先，準備切晶黏晶一體型膜8（以下，有時稱為「膜8」），並將其配置在規定的裝置（未圖示）。膜8依次具備基材膜1、黏著劑層2、及接著劑層3A。基材膜1例如為聚對苯二甲酸乙二酯膜（PET（polyethylene terephthalate）膜）。黏著劑層2具有因紫外線照射而黏著性降低的性質。接著劑層3A包含熱硬化性樹脂組成物。3(a) to 3(e), an example of a method of manufacturing a dummy wafer D, which is one form of an adhesive sheet wafer, will be described. First, a dicing and die-bonding integrated film 8 (hereinafter, sometimes referred to as "film 8") is prepared, and it is arranged in a predetermined device (not shown). The film 8 includes a base film 1, an adhesive layer 2, and an adhesive layer 3A in this order. The base film 1 is, for example, a polyethylene terephthalate film (PET (polyethylene terephthalate) film). The adhesive layer 2 has a property that the adhesiveness decreases due to ultraviolet irradiation. The adhesive layer 3A contains a thermosetting resin composition.

如圖3（a）及圖3（b）所示，以接著劑層3A與晶圓W的一個面接觸的方式貼附膜8。晶圓W可以是單晶矽，亦可以是多晶矽、各種陶瓷、砷化鎵等的化合物半導體。再者，在製作虛設晶片D時，晶圓W不必是半導體，例如亦可是玻璃基板。As shown in FIG. 3(a) and FIG. 3(b), the film 8 is attached so that the adhesive layer 3A is in contact with one surface of the wafer W. Wafer W may be single crystal silicon, polycrystalline silicon, various ceramics, gallium arsenide and other compound semiconductors. Furthermore, when the dummy chip D is manufactured, the wafer W does not need to be a semiconductor, for example, it may be a glass substrate.

利用切割刀切斷晶圓W及接著劑層3A（參照圖3（c））。藉由切割將晶圓W單片化而成為晶片D1。藉由切割將接著劑層3A單片化而成為接著劑片Da。其後，如圖3（d）所示，對黏著劑層2照射紫外線，藉此使黏著劑層2與接著劑層3A之間的黏著力降低。紫外線照射後，如圖3（e）所示，藉由擴展基材膜1，使虛設晶片D相互分離。用針42上推虛設設晶片D，藉此使虛設晶片D自黏著劑層2剝離，並且用抽吸夾具44抽吸而拾取虛設晶片D。The wafer W and the adhesive layer 3A are cut by a dicing blade (see FIG. 3(c)). The wafer W is singulated by dicing to become a wafer D1. The adhesive layer 3A is singulated by cutting to form an adhesive sheet Da. After that, as shown in FIG. 3(d), the adhesive layer 2 is irradiated with ultraviolet rays, thereby reducing the adhesive force between the adhesive layer 2 and the adhesive layer 3A. After ultraviolet irradiation, as shown in FIG. 3(e), the dummy wafers D are separated from each other by expanding the base film 1. The dummy chip D is pushed up with the needle 42 to peel the dummy chip D from the adhesive layer 2, and the dummy chip D is sucked by the suction jig 44 to pick up the dummy chip D.

（半導體裝置的製造方法） 參照圖4至圖6來對半導體裝置100的製造方法進行說明。半導體裝置100的製造方法包括以下的（A）～（D）的步驟。 （A）準備結構體30A的步驟，所述結構體30A包括：基板10、配置在基板10上的晶片S1、以及配置在基本10上且配置在晶片S1的周圍的多個虛設晶片D（參照圖4）。 （B）準備帶接著劑片的晶片S2a的步驟，所述帶接著劑片的晶片S2a包括晶片S2、及設置在晶片S2的一個面的接著劑片Sa（參照圖5）。 （C）以接著劑片Sa接觸多個虛設晶片D的上表面及晶片S1的上表面的方式，將晶片S2配置在晶片S1的上方的步驟（參照圖6）。 （D）密封晶片S1、晶片S2、晶片S3、晶片S4及虛設晶片D等的步驟。(Method of manufacturing semiconductor device) A method of manufacturing the semiconductor device 100 will be described with reference to FIGS. 4 to 6. The manufacturing method of the semiconductor device 100 includes the following steps (A) to (D). (A) A step of preparing a structure 30A, which includes: a substrate 10, a wafer S1 arranged on the substrate 10, and a plurality of dummy wafers D arranged on the base 10 and arranged around the wafer S1 (see Figure 4). (B) A step of preparing a wafer S2a with an adhesive sheet. The wafer S2a with an adhesive sheet includes a wafer S2 and an adhesive sheet Sa provided on one surface of the wafer S2 (see FIG. 5). (C) A step of arranging the wafer S2 above the wafer S1 so that the adhesive sheet Sa contacts the upper surface of the plurality of dummy wafers D and the upper surface of the wafer S1 (see FIG. 6). (D) A step of sealing wafer S1, wafer S2, wafer S3, wafer S4, dummy wafer D, etc.

[（A）步驟] （A）步驟是準備圖4所示的結構體30A的步驟。結構體30A包括基板10、配置在基板10的表面上的晶片S1及多個虛設晶片D，晶片S1的上表面的高度與虛設晶片D的上表面的高度一致。例如，首先藉由覆晶連接將晶片S1搭載於基板10上的規定的位置處，其後，將虛設晶片D壓接於規定的位置即可。所述壓接處理例如較佳為在80℃～180℃、0.01 MPa～0.50 MPa條件下實施0.5秒～3.0秒。藉由調整施加於虛設晶片D的按壓力，可調整虛設晶片D的上表面的高度。虛設晶片D的接著劑片Da可在（A）步驟時完全硬化，亦可在此時不完全硬化，而在（C）步驟時完全硬化。[(A) Step] The step (A) is a step of preparing the structure 30A shown in FIG. 4. The structure 30A includes a substrate 10, a wafer S1 arranged on the surface of the substrate 10, and a plurality of dummy wafers D. The height of the upper surface of the wafer S1 is the same as the height of the upper surface of the dummy wafer D. For example, first, the chip S1 is mounted at a predetermined position on the substrate 10 by flip chip connection, and then, the dummy chip D may be crimped to the predetermined position. The pressure bonding treatment is preferably performed under conditions of 80°C to 180°C and 0.01 MPa to 0.50 MPa for 0.5 seconds to 3.0 seconds, for example. By adjusting the pressing force applied to the dummy chip D, the height of the upper surface of the dummy chip D can be adjusted. The adhesive sheet Da of the dummy chip D may be completely hardened in the step (A), or may not be completely hardened at this time, and completely hardened in the (C) step.

[（B）步驟] （B）步驟是準備圖5所示的帶接著劑片的晶片S2a的步驟。帶接著劑片的晶片S2a包括晶片S2、及設置在晶片S2的一個表面的接著劑片Sa。帶接著劑片的晶片S2a例如可使用切晶黏晶一體型膜，經由切割步驟而得到（參照圖3（a）～圖3（e））。[(B) Step] The step (B) is a step of preparing the wafer S2a with the adhesive sheet shown in FIG. 5. The wafer S2a with an adhesive sheet includes a wafer S2 and an adhesive sheet Sa provided on one surface of the wafer S2. The wafer S2a with an adhesive sheet can be obtained through a dicing step using, for example, a die-cutting and die-bonding integrated film (see FIGS. 3(a) to 3(e)).

[（C）步驟] （C）步驟是如下步驟：以接著劑片Sa與多個虛設晶片D的上表面及晶片S1的上表面接觸的方式，在晶片S1的上方配置帶接著劑片的晶片S2a的步驟。更具體而言，晶片S2經由接著劑片Sa而壓接於虛設晶片D的上表面及晶片S1的上表面。所述壓接處理例如較佳為在80℃～180℃、0.01 MPa～0.50 MPa條件下實施0.5秒～3.0秒。接著，藉由加熱使接著劑片Sa硬化。該硬化處理例如較佳為在60℃～175℃、0.01 MPa～1.0 MPa條件下實施5分鐘以上。藉此，接著劑片Sa成為硬化物Sc。[(C) Step] The step (C) is a step of arranging the wafer S2a with the adhesive sheet above the wafer S1 so that the adhesive sheet Sa is in contact with the upper surface of the plurality of dummy wafers D and the upper surface of the wafer S1. More specifically, the wafer S2 is crimped to the upper surface of the dummy wafer D and the upper surface of the wafer S1 via the adhesive sheet Sa. The pressure bonding treatment is preferably performed under conditions of 80°C to 180°C and 0.01 MPa to 0.50 MPa for 0.5 seconds to 3.0 seconds, for example. Next, the adhesive sheet Sa is hardened by heating. The hardening treatment is preferably carried out for 5 minutes or more under conditions of 60°C to 175°C and 0.01 MPa to 1.0 MPa, for example. Thereby, the adhesive sheet Sa becomes a hardened|cured material Sc.

在本實施方式所涉及的結構體30A中，如上所述，晶片S1的上表面的高度與虛設晶片D的上表面的高度一致。因此，接著劑片Sa與虛設晶片D的上表面及晶片S1的上表面兩者接觸。圖6是示意性表示經由（C）步驟得到的結構體的剖面圖。該圖所示的構造體40由於在硬化物Sc和晶片S1之間沒有間隙，故在（D）步驟中能夠實現密封材的優異的填充性。In the structure 30A according to this embodiment, as described above, the height of the upper surface of the wafer S1 and the height of the upper surface of the dummy wafer D match. Therefore, the adhesive sheet Sa is in contact with both the upper surface of the dummy wafer D and the upper surface of the wafer S1. Fig. 6 is a cross-sectional view schematically showing a structure obtained through step (C). In the structure 40 shown in the figure, since there is no gap between the cured product Sc and the wafer S1, it is possible to achieve excellent filling properties of the sealing material in the step (D).

在（C）步驟後、（D）步驟前，經由接著劑片在晶片S2上配置晶片S3，進而，經由接著劑片在晶片S3上配置晶片S4。接著劑片只要是與所述的接著劑片Sa同樣的熱硬化性樹脂組成物即可，藉由加熱硬化而成為硬化物Sc（參照圖1）。其後，藉由線w將晶片S2、晶片S3、晶片S4與基板10分別電連接。再者，積層在晶片S1的上方的晶片的數目不限於本實施方式中的三個，只要適當設定即可。After the step (C) and before the step (D), the wafer S3 is placed on the wafer S2 via the adhesive sheet, and further, the wafer S4 is placed on the wafer S3 via the adhesive sheet. The adhesive sheet may be the same thermosetting resin composition as the aforementioned adhesive sheet Sa, and is cured by heating to become a cured product Sc (see FIG. 1). Thereafter, the chip S2, the chip S3, the chip S4, and the substrate 10 are electrically connected by wires w. In addition, the number of wafers stacked above the wafer S1 is not limited to three in this embodiment, and may be appropriately set.

[（D）步驟] （D）步驟是藉由密封材50將晶片S1、晶片S2、晶片S3、晶片S4、虛設晶片D及線w密封的步驟。經過該步驟，圖1所示的半導體裝置100完成。[(D) Step] The step (D) is a step of sealing the wafer S1, the wafer S2, the wafer S3, the wafer S4, the dummy wafer D, and the wire w with the sealing material 50. After this step, the semiconductor device 100 shown in FIG. 1 is completed.

（熱硬化性樹脂組成物） 對構成接著劑片Da及接著劑片Sa的熱硬化性樹脂組成物進行說明。本實施方式所涉及的熱硬化性樹脂組成物經過半硬化（B階段）狀態，藉由之後的硬化處理能夠成為完全硬化物（C階段）狀態。熱硬化性樹脂組成物含有環氧樹脂、硬化劑和彈性體，根據需要更包括無機填料和硬化促進劑等。(Thermosetting resin composition) The thermosetting resin composition constituting the adhesive sheet Da and the adhesive sheet Sa will be described. The thermosetting resin composition according to the present embodiment passes through a semi-cured (B-stage) state, and can be in a fully cured (C-stage) state by subsequent curing treatment. The thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler, a curing accelerator, and the like as necessary.

[環氧樹脂] 關於環氧樹脂，只要為進行硬化而具有接著作用者，則並無特別限定。可使用雙酚A型環氧樹脂、雙酚F型環氧樹脂、雙酚S型環氧樹脂等二官能環氧樹脂；苯酚酚醛清漆型環氧樹脂、甲酚酚醛清漆型環氧樹脂等酚醛清漆型環氧樹脂等。另外，可應用多官能環氧樹脂、縮水甘油胺型環氧樹脂、含雜環的環氧樹脂、或脂環式環氧樹脂等普遍已知的樹脂。所述樹脂可單獨使用一種，亦可併用兩種以上。[Epoxy resin] The epoxy resin is not particularly limited as long as it has a connection agent for curing. Bifunctional epoxy resins such as bisphenol A epoxy resin, bisphenol F epoxy resin, and bisphenol S epoxy resin can be used; phenol novolac epoxy resin, cresol novolac epoxy resin, etc. Varnish type epoxy resin, etc. In addition, commonly known resins such as polyfunctional epoxy resins, glycidylamine epoxy resins, heterocyclic epoxy resins, or alicyclic epoxy resins can be used. The resin may be used alone or in combination of two or more.

[硬化劑] 作為硬化劑，例如，可列舉：酚樹脂、酯化合物、芳香族胺、脂肪族胺基及酸酐。該些中，就反應性及經時穩定性的觀點而言，較佳為酚樹脂。作為酚樹脂的市售品，例如可列舉迪愛生（Dainippon Ink and Chemicals，DIC）（股）製的菲諾萊特（Phenolite）KA及TD系列、三井化學股份有限公司製的美萊克（Milex）XLC-系列及XL系列（例如美萊克XLC-LL）、日本愛沃特（AIR WATER）（股）製的HE系列（例如HE100C-30）、明和化成股份有限公司製的MEHC-7800系列（例如，MEHC-7800-4S）。所述硬化劑可單獨使用一種，亦可併用兩種以上。[hardener] Examples of the curing agent include phenol resins, ester compounds, aromatic amines, aliphatic amine groups, and acid anhydrides. Among these, a phenol resin is preferable from the viewpoint of reactivity and stability over time. Commercial products of phenol resins include, for example, Phenolite KA and TD series manufactured by Dainippon Ink and Chemicals (DIC), and Milex XLC manufactured by Mitsui Chemicals Co., Ltd. -Series and XL series (such as Merak XLC-LL), HE series manufactured by AIR WATER (shares) (such as HE100C-30), MEHC-7800 series manufactured by Meiwa Chemical Co., Ltd. (such as, MEHC-7800-4S). The curing agent may be used alone or in combination of two or more.

關於環氧樹脂與酚樹脂的調配量，就硬化性的觀點而言，環氧當量與羥基當量的當量比分別較佳為0.30/0.70～0.70/0.30，更佳為0.35/0.65～0.65/0.35，進而佳為0.40/0.60～0.60/0.40，特佳為0.45/0.55～0.55/0.45。藉由使調配比在所述範圍內，容易將硬化性及流動性兩者達到足夠高的水準。Regarding the blending amount of epoxy resin and phenol resin, from the viewpoint of curability, the equivalent ratio of epoxy equivalent to hydroxyl equivalent is preferably 0.30/0.70 to 0.70/0.30, more preferably 0.35/0.65 to 0.65/0.35 , More preferably 0.40/0.60 to 0.60/0.40, particularly preferably 0.45/0.55 to 0.55/0.45. By making the blending ratio within the above-mentioned range, it is easy to achieve a sufficiently high level of both curability and fluidity.

[彈性體] 作為彈性體，例如可列舉：丙烯酸樹脂、聚酯樹脂、聚醯胺樹脂、聚醯亞胺樹脂、矽酮樹脂、聚丁二烯、丙烯腈、環氧改質聚丁二烯、順丁烯二酸酐改質聚丁二烯、酚改質聚丁二烯及羧基改質丙烯腈。[Elastomer] Examples of elastomers include acrylic resins, polyester resins, polyamide resins, polyimide resins, silicone resins, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, and maleic resins. Diacid anhydride modified polybutadiene, phenol modified polybutadiene and carboxyl modified acrylonitrile.

就在溶劑中的溶解性以及流動性的觀點而言，作為彈性體較佳為丙烯酸系樹脂，進而，進而佳為將丙烯酸縮水甘油酯或甲基丙烯酸縮水甘油酯等具有環氧基或縮水甘油基作為交聯性官能團的官能性單體聚合而得到的含環氧基的（甲基）丙烯酸共聚物等丙烯酸系樹脂。在丙烯酸系樹脂中，較佳為含環氧基的（甲基）丙烯酸酯共聚物以及含環氧基的丙烯酸橡膠，更佳為含環氧基的丙烯酸橡膠。含環氧基的丙烯酸橡膠是以丙烯酸酯為主要成分，主要包含丙烯酸丁酯與丙烯腈等共聚物、丙烯酸乙酯與丙烯腈等共聚物的，具有環氧基的橡膠。再者，丙烯酸系樹脂不僅可以具有環氧基，亦可具有醇性或酚性羥基、羧基等交聯性官能基。From the viewpoints of solubility in solvents and fluidity, acrylic resins are preferred as the elastomer, and it is more preferred that glycidyl acrylate or glycidyl methacrylate have epoxy groups or glycidyl groups. Acrylic resins such as epoxy group-containing (meth)acrylic copolymers obtained by polymerizing functional monomers having a crosslinkable functional group. Among acrylic resins, epoxy group-containing (meth)acrylate copolymers and epoxy group-containing acrylic rubbers are preferable, and epoxy group-containing acrylic rubbers are more preferable. Epoxy-containing acrylic rubber is mainly composed of acrylate and mainly contains copolymers such as butyl acrylate and acrylonitrile, and copolymers such as ethyl acrylate and acrylonitrile, and has epoxy groups. Furthermore, the acrylic resin may have not only an epoxy group but also a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group and a carboxyl group.

作為丙烯酸樹脂的市售品，可以列舉：長瀨化成（Nagase ChemteX）（股）製的SG-70L、SG-708-6、WS-023 EK30、SG-280 EK23、SG-P3溶劑變更品（商品名，丙烯酸橡膠，重量平均分子量：80萬，Tg：12℃，溶劑為環己酮）等。Commercially available acrylic resins include: SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, and SG-P3 solvent-modified products manufactured by Nagase ChemteX (stocks) ( Trade name, acrylic rubber, weight average molecular weight: 800,000, Tg: 12℃, solvent is cyclohexanone) etc.

丙烯酸樹脂的玻璃轉移溫度（Tg）較佳為-50℃～50℃，更佳為-30℃～30℃。丙烯酸樹脂的重量平均分子量（Mw）較佳為10萬～300萬，更佳為50萬～200萬。藉由在熱硬化性樹脂組成物中調配Mw為所述範圍的丙烯酸樹脂，容易將熱硬化性樹脂組成物形成為膜狀，容易適當地控制膜狀下的強度、可撓性、黏性。此外，回流性和埋入性都有提高的傾向。此處，Mw是指藉由凝膠滲透層析法（Gel Permeation Chromatography，GPC）測定，使用基於標準聚苯乙烯的標準曲線進行換算而得到的值。再者，藉由使用分子量分佈窄的丙烯酸樹脂，具有能夠形成埋入性優異且高彈性的接著劑片的傾向。The glass transition temperature (Tg) of the acrylic resin is preferably -50°C to 50°C, more preferably -30°C to 30°C. The weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3 million, more preferably 500,000 to 2 million. By blending the acrylic resin with Mw in the above-mentioned range in the thermosetting resin composition, the thermosetting resin composition can be easily formed into a film shape, and the strength, flexibility, and viscosity in the film shape can be easily controlled appropriately. In addition, both reflow properties and embedding properties tend to improve. Here, Mw refers to a value measured by Gel Permeation Chromatography (GPC) and converted using a standard curve based on standard polystyrene. Furthermore, by using an acrylic resin with a narrow molecular weight distribution, there is a tendency that an adhesive sheet having excellent embedding properties and high elasticity can be formed.

相對於環氧樹脂及環氧樹脂硬化劑的合計100質量份，熱硬化性樹脂組成物中所含的丙烯酸樹脂的量較佳為20質量份～200質量份，更佳為30質量份～100質量份。在該範圍內時，成形時的流動性控制、高溫下的處理性及埋入性可變得更好。The amount of acrylic resin contained in the thermosetting resin composition is preferably 20 parts by mass to 200 parts by mass, and more preferably 30 parts by mass to 100 parts by mass relative to 100 parts by mass of the total of epoxy resin and epoxy resin curing agent. Mass parts. Within this range, fluidity control during molding, handling properties at high temperatures, and embedding properties can be improved.

[無機填料] 作為無機填料，例如可列舉：氫氧化鋁、氫氧化鎂、碳酸鈣、碳酸鎂、矽酸鈣、矽酸鎂、氧化鈣、氧化鎂、氧化鋁、氮化鋁、硼酸鋁晶鬚、氮化硼、結晶性二氧化矽、非晶性二氧化矽。所述無機填料可單獨使用一種，亦可併用兩種以上。[Inorganic Filler] Examples of inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, and nitride Boron, crystalline silicon dioxide, amorphous silicon dioxide. The said inorganic filler may be used individually by 1 type, and may use 2 or more types together.

就提高接著性的觀點而言，無機填料的平均粒徑較佳為0.005 μm～1.0 μm，更佳為0.05 μm～0.5 μm。就溶劑及樹脂成分的相容性以及接著強度的觀點而言，無機填料的表面較佳為經化學修飾。適合作為對表面進行化學修飾的材料可以舉出矽烷偶合劑。作為矽烷偶合劑的官能基的種類，例如可以列舉乙烯基、丙烯醯基、環氧基、巰基、胺基、二胺基、烷氧基、乙氧基。From the viewpoint of improving adhesiveness, the average particle diameter of the inorganic filler is preferably 0.005 μm to 1.0 μm, more preferably 0.05 μm to 0.5 μm. From the viewpoint of the compatibility of the solvent and the resin component and the bonding strength, the surface of the inorganic filler is preferably chemically modified. Suitable materials for chemically modifying the surface include a silane coupling agent. As the type of the functional group of the silane coupling agent, for example, a vinyl group, an acryl group, an epoxy group, a mercapto group, an amino group, a diamine group, an alkoxy group, and an ethoxy group can be mentioned.

就控制熱硬化性樹脂組成物的流動性及斷裂性、以及硬化後的拉伸彈性模數和接著力的觀點而言，相對於熱硬化性樹脂組成物的樹脂成分100質量份，無機填料的含量較佳為20質量份～200質量份，更佳為30質量份～100質量份。From the viewpoint of controlling the fluidity and fracture properties of the thermosetting resin composition, and the tensile modulus of elasticity and adhesive force after curing, relative to 100 parts by mass of the resin component of the thermosetting resin composition, the amount of inorganic filler The content is preferably 20 parts by mass to 200 parts by mass, more preferably 30 parts by mass to 100 parts by mass.

[硬化促進劑] 作為硬化促進劑，例如可列舉：咪唑類及其衍生物、有機磷系化合物、二級胺類、三級胺類、四級銨鹽等。就適度的反應性的觀點而言，較佳為咪唑系化合物。咪唑類可以列舉2-甲基咪唑、1-苄基-2-甲基咪唑、1-氰基乙基-2-苯基咪唑、1-氰基乙基-2-甲基咪唑等。所述硬化促進劑可單獨使用一種，亦可併用兩種以上。[Hardening accelerator] Examples of hardening accelerators include imidazoles and their derivatives, organophosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. From the viewpoint of moderate reactivity, imidazole-based compounds are preferred. Examples of imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole, and the like. The said hardening accelerator may be used individually by 1 type, and may use 2 or more types together.

相對於環氧樹脂及環氧樹脂硬化劑的合計100質量份，熱硬化性樹脂組成物的硬化促進劑的含量較佳為0.04質量份～3質量份，更佳為0.04質量份～0.2質量份。當硬化促進劑的添加量在該範圍內時，可以兼顧硬化性與可靠性。The content of the curing accelerator of the thermosetting resin composition is preferably 0.04 parts by mass to 3 parts by mass, and more preferably 0.04 parts by mass to 0.2 parts by mass relative to the total of 100 parts by mass of the epoxy resin and the epoxy resin curing agent . When the addition amount of the hardening accelerator is within this range, both hardenability and reliability can be achieved.

＜第二實施方式＞ 在所述第一實施方式中，例示了在（A）步驟中準備虛設晶片D的上表面的高度與晶片S1的上表面的高度一致的結構體30A的方式，但亦可在（A）步驟中準備虛設晶片D的上表面較晶片S1的上表面高的結構體。圖7所示的結構體30B包括基板10、配置在基板10上的晶片S1、以及配置在基板10上並且配置在晶片S1周圍的多個虛設晶片D，虛設晶片D的上表面高於晶片S1的上表面。<Second Embodiment> In the first embodiment, the method of preparing the structure 30A in which the height of the upper surface of the dummy wafer D matches the height of the upper surface of the wafer S1 in the step (A) is exemplified, but it may also be prepared in the step (A) A structure in which the upper surface of the dummy wafer D is higher than the upper surface of the wafer S1 is prepared. The structure 30B shown in FIG. 7 includes a substrate 10, a wafer S1 arranged on the substrate 10, and a plurality of dummy wafers D arranged on the substrate 10 and arranged around the wafer S1. The upper surface of the dummy wafer D is higher than that of the wafer S1. The upper surface.

在第一實施方式的（D）步驟（用密封材50密封的步驟）之前，使虛設晶片D的上表面的高度與晶片S1的上表面的高度一致即可，但亦可在（C）步驟中，藉由用帶接著劑片的晶片S2a將虛設晶片D的接著劑片Da壓扁，而使虛設晶片D的高度與晶片S1的上表面的高度一致（參照圖8）。當藉由覆晶連接將晶片S1搭載於基板10時，覆晶的連接部的高度容易發生5 μm左右的偏差，其結果，在晶片S1的上表面的高度位置處產生5 μm左右的偏差。考慮該偏差而將虛設晶片D的上表面的位置設定為較連接後的晶片S1的上表面的設定位置高8 μm～12 μm左右，藉此具有在（A）步驟中無需使虛設晶片D的上表面的高度與晶片S1的上表面的高度嚴格地一致的優點。Before the step (D) of the first embodiment (the step of sealing with the sealing material 50), it is sufficient to make the height of the upper surface of the dummy wafer D coincide with the height of the upper surface of the wafer S1, but it may also be performed in the step (C) Here, by squashing the adhesive sheet Da of the dummy chip D with the adhesive sheet-attached wafer S2a, the height of the dummy chip D is made to coincide with the height of the upper surface of the wafer S1 (see FIG. 8). When the chip S1 is mounted on the substrate 10 by flip chip connection, the height of the connecting portion of the flip chip easily varies by about 5 μm. As a result, the height position of the upper surface of the chip S1 varies by about 5 μm. Considering this deviation, the position of the upper surface of the dummy wafer D is set to be about 8 μm to 12 μm higher than the setting position of the upper surface of the wafer S1 after the connection, so that there is no need to use the dummy wafer D in step (A). The advantage that the height of the upper surface is exactly the same as the height of the upper surface of the wafer S1.

在本實施方式中，虛設晶片D的接著劑片Da包含被帶接著劑片的晶片S2a壓扁的材料。具體而言，較佳為虛設晶片D的接著劑片Da較帶接著劑片的晶片S2a的接著劑片Sa軟。作為使接著劑片Da較接著劑片Sa軟的方法，例如可列舉使接著劑片Da的熱硬化性樹脂的含量多於接著劑片Sa，或使接著劑片Da的彈性體或無機填料的含量少於接著劑片Sa。In this embodiment, the adhesive sheet Da of the dummy wafer D includes a material crushed by the adhesive sheet-attached wafer S2a. Specifically, it is preferable that the adhesive sheet Da of the dummy wafer D is softer than the adhesive sheet Sa of the wafer S2a with the adhesive sheet. As a method of making the adhesive sheet Da softer than the adhesive sheet Sa, for example, the content of the thermosetting resin of the adhesive sheet Da is greater than that of the adhesive sheet Sa, or the elastomer or inorganic filler of the adhesive sheet Da The content is less than the adhesive sheet Sa.

較佳為虛設晶片D的接著劑片Da較帶接著劑片的晶片S2a的接著劑片Sa厚。本實施方式中，例如，接著劑片Da的厚度為接著劑片Sa的厚度的1.1倍～8倍，亦可以是1.2倍～6倍。It is preferable that the adhesive sheet Da of the dummy chip D is thicker than the adhesive sheet Sa of the chip S2a with the adhesive sheet. In this embodiment, for example, the thickness of the adhesive sheet Da is 1.1 to 8 times the thickness of the adhesive sheet Sa, and may be 1.2 to 6 times.

以上，對本揭示的實施方式進行了詳細說明，但本發明並不限定於所述實施方式。例如，在上述實施方式中，例示了藉由覆晶連接來搭載晶片S1的情況，但亦可在利用接著劑將晶片S1固定於基板10之後，藉由打線接合進行電連接。Above, the embodiments of the present disclosure have been described in detail, but the present invention is not limited to the embodiments. For example, in the above-mentioned embodiment, the case where the chip S1 is mounted by flip chip connection is exemplified, but after the chip S1 is fixed to the substrate 10 with an adhesive, electrical connection may be made by wire bonding.

以下，藉由實施例對本揭示進行詳細說明，但本發明並不限定於該些實施例。Hereinafter, the present disclosure will be described in detail with examples, but the present invention is not limited to these examples.

＜接著片的製作＞ 使用表1所示的成分，按照以下順序製備接著劑組成物的清漆A、清漆B。首先，調配後述的[環氧樹脂]、[硬化劑]及[填料]後，加入環己酮進行攪拌。其後，加入[彈性體]、[硬化促進劑]及[偶合劑]，攪拌至各成分均勻，藉此得到接著劑組成物的清漆。<Production of Adhesive Film> Using the components shown in Table 1, varnish A and varnish B of the adhesive composition were prepared in the following order. First, after mixing [epoxy resin], [hardener], and [filler] described later, cyclohexanone is added and stirred. After that, [elastomer], [hardening accelerator], and [coupling agent] are added and stirred until the components are uniform, thereby obtaining a varnish of the adhesive composition.

[彈性體] 丙烯酸橡膠：長瀨化成股份有限公司製商品名「HTR-860P-3」、重量平均分子量80萬，玻璃轉移點：12℃[Elastomer] Acrylic rubber: Nagase Chemical Co., Ltd. product name "HTR-860P-3", weight average molecular weight 800,000, glass transition point: 12°C

[環氧樹脂] 甲酚酚醛清漆型環氧樹脂：東都化成股份有限公司製造，商品名「YDCN-700-10」，環氧當量：210 雙酚F型環氧樹脂：迪愛生（DIC）股份有限公司、商品名「EXA-830CRP」、環氧當量：159[Epoxy resin] Cresol novolac epoxy resin: manufactured by Dongdu Chemical Co., Ltd., trade name "YDCN-700-10", epoxy equivalent: 210 Bisphenol F epoxy resin: DIC Co., Ltd., trade name "EXA-830CRP", epoxy equivalent: 159

[硬化劑] 酚樹脂：三井化學股份有限公司製造，商品名「米萊斯XLC-LL」、軟化點：75℃、羥基當量175[hardener] Phenolic resin: manufactured by Mitsui Chemicals Co., Ltd., trade name "Milais XLC-LL", softening point: 75°C, hydroxyl equivalent 175

[填料] 二氧化矽填料：日本艾羅西爾（Aerosil）股份有限公司製造，商品名「R972」，平均粒徑為0.500 μm 二氧化矽填料：雅都瑪科技（Admatechs）股份有限公司製造、商品名「SC-2050-HLG」、比表面積110m/g[filler] Silica filler: manufactured by Japan Aerosil Co., Ltd., trade name "R972", with an average particle size of 0.500 μm Silica filler: manufactured by Admatechs Co., Ltd., trade name "SC-2050-HLG", specific surface area 110m/g

[硬化促進劑] 1-氰乙基-2-苯基咪唑固唑：四國化成工業股份有限公司製造、商品名「2PZ-CN」[Hardening accelerator] 1-cyanoethyl-2-phenylimidazole azole: manufactured by Shikoku Chemical Industry Co., Ltd., trade name "2PZ-CN"

[偶合劑] γ-巰基丙基三甲氧基矽烷：日本尤尼卡（Nippon Unicar）股份股份有限公司製造，商品名「NUC A-189」 γ-脲基丙基三乙氧基矽烷：日本尤尼卡股份有限公司製造，商品名「NUC A-1160」[Coupling agent] γ-Mercaptopropyl trimethoxysilane: manufactured by Nippon Unicar Co., Ltd., trade name "NUC A-189" γ-ureidopropyl triethoxysilane: manufactured by Unika Co., Ltd., trade name "NUC A-1160"

[表1]   清漆A （質量份） 清漆B （質量份） 彈性體 HTR-860P-3 66 29 環氧樹脂 YDCN-700-10 13 16 EXA-830CRP - 14 硬化劑 XLC-LL 11 23 填料 R972 8 - SC2050-HLG - 17 硬化促進劑 2PZ-CN 0.1 0.1 偶合劑 NUC A-189 0.4 0.1 NUC A-1160 1.2 0.2 [Table 1] Varnish A (parts by mass) Varnish B (parts by mass) Elastomer HTR-860P-3 66 29 Epoxy resin YDCN-700-10 13 16 EXA-830CRP - 14 hardener XLC-LL 11 twenty three filler R972 8 - SC2050-HLG - 17 Hardening accelerator 2PZ-CN 0.1 0.1 Coupling agent NUC A-189 0.4 0.1 NUC A-1160 1.2 0.2

在基材膜（經脫模處理的聚對苯二甲酸乙二酯膜，厚度：38μm）上塗佈清漆A。在基材膜上以140℃加熱乾燥5分鐘，製作接著片A1（厚度20 μm）及接著片A2（厚度40 μm）。除了使用清漆B代替清漆A以外，與上述同樣地製作了接著片B（厚度40 μm）。Varnish A was coated on the base film (polyethylene terephthalate film with release treatment, thickness: 38 μm). The base film was heated and dried at 140°C for 5 minutes to produce an adhesive sheet A1 (thickness 20 μm) and an adhesive sheet A2 (thickness 40 μm). Except for using varnish B instead of varnish A, an adhesive sheet B (thickness 40 μm) was produced in the same manner as described above.

＜接著片的熔融黏度的測定＞ 使用旋轉式黏彈性測定裝置（日本TA儀器（TA Instruments Japan）股份有限公司製造，ARES-RDA），按照以下順序測定接著片的熔融黏度。首先，自接著片剝離基材膜後，在70℃下貼合多個接著劑層，得到厚度160 μm以上的積層膜。將其沖裁成直徑8 mm的圓形後，用兩個夾具（直徑：8 mm）夾住，得到測定用試樣。在以下條件下實施測定，將80℃下的值作為接著片的熔融黏度。接著片A1、接著片A2的熔融黏度為24000 Pa･S，接著片B的熔融黏度為2000 Pa･S。 ・頻率：1 Hz ・測定開始溫度：35℃ ・測定結束溫度：150℃ ・升溫速度5℃/分＜Measuring the melt viscosity of the adhesive sheet＞ Using a rotary viscoelasticity measuring device (manufactured by TA Instruments Japan Co., Ltd., ARES-RDA), the melt viscosity of the adhesive sheet was measured in the following procedure. First, after peeling the base film from the adhesive sheet, a plurality of adhesive layers were bonded at 70°C to obtain a laminated film having a thickness of 160 μm or more. After punching it into a circle with a diameter of 8 mm, it was clamped with two clamps (diameter: 8 mm) to obtain a test specimen. The measurement was performed under the following conditions, and the value at 80°C was used as the melt viscosity of the adhesive sheet. The melt viscosity of the next sheet A1 and the next sheet A2 is 24000 Pa･S, and the melt viscosity of the next sheet B is 2000 Pa･S. ・Frequency: 1 Hz ・Measurement start temperature: 35℃ ・Measurement end temperature: 150℃ ・The heating rate is 5℃/min

（實施例1） 在半導體晶圓（厚度：90 μm）上貼附接著片A1（厚度：20 μm）。使用切割機（迪士高（DISCO）製造的DFD-6361）將半導體晶圓單片化為5.0 mm×5.0 mm的半導體晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以120℃/0.1 MPa/1秒的條件熱壓接於在150℃下乾燥1小時的有機基板上，得到帶半導體晶片的基板。(Example 1) The adhesive sheet A1 (thickness: 20 μm) is attached to the semiconductor wafer (thickness: 90 μm). A dicing machine (DFD-6361 manufactured by DISCO) was used to singulate semiconductor wafers into 5.0 mm×5.0 mm semiconductor wafers. Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.), it was thermocompression bonded to an organic substrate dried at 150°C for 1 hour at 120°C/0.1 MPa/1 second to obtain a tape The substrate of the semiconductor wafer.

繼而，在半導體晶圓（厚度：80 μm）上貼附接著片B（厚度：40 μm）。使用切割機（迪士高製造的DFD-6361）將半導體晶圓單片化為1.5 mm×6.0 mm的晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），在以120℃/0.1 MPa/1秒隔開上述半導體晶片的2 mm空間的兩側的有機基板上，將上述晶片作為虛設晶片進行熱壓接。Then, the adhesive sheet B (thickness: 40 μm) was attached to the semiconductor wafer (thickness: 80 μm). Use a dicing machine (DFD-6361 manufactured by Disco) to singulate the semiconductor wafer into 1.5 mm × 6.0 mm wafers. Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.), the above-mentioned semiconductor wafers were placed on the organic substrates on both sides of the 2 mm space separated by 120°C/0.1 MPa/1 second. The wafer is used as a dummy wafer for thermal compression bonding.

繼而，在半導體晶圓（厚度：50 μm）上，用晶圓安裝器（迪士高製DFM-2800）以70℃/（10 mm/秒）貼附HR-900T-20-N50 （日立化成（股）製、接著劑層的厚度：20 μm）。其後，使用切割機（迪士高製DFD-6361）將半導體晶圓單片化為6.0 mm×12.0 mm的晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以100℃～120℃/0.05 MPa～0.20 MPa/0.5秒～2.0秒熱壓接在半導體晶片及兩個虛設晶片上。然後，在7 kg加壓氣氛下藉由以150℃加熱1小時的條件使接著劑硬化。藉此，得到了具備基板、兩個虛設晶片和兩個半導體晶片的結構體。Then, on the semiconductor wafer (thickness: 50 μm), the HR-900T-20-N50 (Hitachi Chemical Co., Ltd.) was attached with a wafer mounter (DFM-2800 manufactured by Disco) at 70°C/(10 mm/sec). (Strand) system, the thickness of the adhesive layer: 20 μm). After that, the semiconductor wafer was singulated into 6.0 mm × 12.0 mm wafers using a dicing machine (DFD-6361 manufactured by Disco). Use a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) to heat and compress the semiconductor chip and two dummy chips at 100℃～120℃/0.05 MPa～0.20 MPa/0.5sec～2.0sec on. Then, the adhesive was cured by heating at 150°C for 1 hour in a 7 kg pressurized atmosphere. Thereby, a structure including a substrate, two dummy wafers, and two semiconductor wafers was obtained.

（比較例1） 在半導體晶圓（厚度：90 μm）上貼附接著片A1（厚度：20 μm）。使用切割機（迪士高（DISCO）製造的DFD-6361）將半導體晶圓單片化為5.0 mm×5.0 mm的半導體晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以120℃/0.1 MPa/1秒的條件熱壓接於在150℃下乾燥1小時的有機基板上，得到帶半導體晶片的基板。(Comparative example 1) The adhesive sheet A1 (thickness: 20 μm) is attached to the semiconductor wafer (thickness: 90 μm). A dicing machine (DFD-6361 manufactured by DISCO) was used to singulate semiconductor wafers into 5.0 mm×5.0 mm semiconductor wafers. Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.), it was thermocompression bonded to an organic substrate dried at 150°C for 1 hour at 120°C/0.1 MPa/1 second to obtain a tape The substrate of the semiconductor wafer.

繼而，在半導體晶圓（厚度：90 μm）上貼附接著片A2（厚度：40 μm）。使用切割機（迪士高製造的DFD-6361）將半導體晶圓單片化為1.5 mm×6.0 mm的晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），在以120℃/0.1MPa/1秒隔開上述半導體晶片的2 mm空間的兩側的有機基板上，將上述晶片作為虛設晶片進行熱壓接。Next, the adhesive sheet A2 (thickness: 40 μm) was attached to the semiconductor wafer (thickness: 90 μm). Use a dicing machine (DFD-6361 manufactured by Disco) to singulate the semiconductor wafer into 1.5 mm × 6.0 mm wafers. Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.), on the organic substrate on both sides of the 2 mm space separated by the semiconductor wafer at 120°C/0.1MPa/1 second, the above The wafer is used as a dummy wafer for thermal compression bonding.

繼而，在半導體晶圓（厚度：50 μm）上，用晶圓安裝器（迪士高製DFM-2800）以70℃/（10 mm/秒）貼附HR-900T-20-N50（日立化成（股）製、接著劑層的厚度：20 μm）。其後，使用切割機（迪士高製DFD-6361）將半導體晶圓單片化為6.0 mm×12.0 mm的晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以120℃/0.10 MPa/1.0秒熱壓接在半導體晶片及兩個虛設晶片上。然後，在7 kg加壓氣氛下藉由以150℃加熱1小時的條件使接著劑硬化。藉此，得到了具備基板、兩個虛設晶片和兩個半導體晶片的結構體。Then, on the semiconductor wafer (thickness: 50 μm), the HR-900T-20-N50 (Hitachi Chemical Co., Ltd.) was attached with a wafer mounter (DFM-2800 manufactured by Disco (Strand) system, the thickness of the adhesive layer: 20 μm). After that, the semiconductor wafer was singulated into 6.0 mm × 12.0 mm wafers using a dicing machine (DFD-6361 manufactured by Disco). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was used to thermally compress the semiconductor chip and two dummy chips at 120°C/0.10 MPa/1.0 seconds. Then, the adhesive was cured by heating at 150°C for 1 hour in a 7 kg pressurized atmosphere. Thereby, a structure including a substrate, two dummy wafers, and two semiconductor wafers was obtained.

（比較例2） 在半導體晶圓（厚度：90 μm）上貼附接著片A1（厚度：20 μm）。使用切割機（迪士高（DISCO）製造的DFD-6361）將半導體晶圓單片化為5.0 mm×5.0 mm的半導體晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以120℃/0.1 MPa/1秒的條件熱壓接於在150℃下乾燥1小時的有機基板上，得到帶半導體晶片的基板。(Comparative example 2) The adhesive sheet A1 (thickness: 20 μm) is attached to the semiconductor wafer (thickness: 90 μm). A dicing machine (DFD-6361 manufactured by DISCO) was used to singulate semiconductor wafers into 5.0 mm×5.0 mm semiconductor wafers. Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.), it was thermocompression bonded to an organic substrate dried at 150°C for 1 hour at 120°C/0.1 MPa/1 second to obtain a tape The substrate of the semiconductor wafer.

繼而，在半導體晶圓（厚度：110 μm）上貼附接著片A1（厚度：20 μm）。使用切割機（迪士高製造的DFD-6361）將半導體晶圓單片化為1.5 mm×6.0 mm的晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以120℃/0.1 MPa/1秒的條件將上述晶片作為虛設晶片熱壓接在上述半導體晶片的隔開2 mm空間的兩側的有機基板上。Next, the adhesive sheet A1 (thickness: 20 μm) was attached to the semiconductor wafer (thickness: 110 μm). Use a dicing machine (DFD-6361 manufactured by Disco) to singulate the semiconductor wafer into 1.5 mm × 6.0 mm wafers. Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.), the above-mentioned chip was thermally compressed as a dummy chip at a distance of 2 mm from the above-mentioned semiconductor chip under the condition of 120℃/0.1 MPa/1 second On the organic substrate on both sides of the space.

繼而，在半導體晶圓（厚度：50 μm）上，用晶圓安裝器（迪士高製DFM-2800）以70℃/（10 mm/秒）貼附HR-900T-20-N50 （日立化成（股）製、接著劑層的厚度：20 μm）。使用切割機（迪士高製造的DFD-6361）將半導體晶圓單片化為6.0 mm×12.0 mm的晶片。使用可撓性固晶機（日立高科技儀器（股）製DB-830HSD），以120℃/0.10 MPa/1.0秒熱壓接在半導體晶片及兩個虛設晶片上。然後，在7 kg加壓氣氛下藉由以150℃加熱1小時的條件使黏接劑硬化。藉此，得到了具備基板、兩個虛設晶片和兩個半導體晶片的結構體。Then, on the semiconductor wafer (thickness: 50 μm), the HR-900T-20-N50 (Hitachi Chemical Co., Ltd.) was attached with a wafer mounter (DFM-2800 manufactured by Disco) at 70°C/(10 mm/sec). (Strand) system, the thickness of the adhesive layer: 20 μm). A dicing machine (DFD-6361 manufactured by Disco) was used to singulate the semiconductor wafer into 6.0 mm × 12.0 mm wafers. A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was used to thermally compress the semiconductor chip and two dummy chips at 120°C/0.10 MPa/1.0 seconds. Then, the adhesive was cured by heating at 150°C for 1 hour in a 7 kg pressurized atmosphere. Thereby, a structure including a substrate, two dummy wafers, and two semiconductor wafers was obtained.

（半導體封裝的製作及評估） 將日立化成股份有限公司製的密封材（商品名CEL-9750ZHF）在175℃/6.75 MPa/120秒的條件下分別成型在實施例及比較例的所述結構體上，在175℃下進行5小時的硬化處理，得到半導體封裝。藉由超音波影像診斷系統（英賽特（Insight）（股）公司製、英賽特（Insight）-300、掃描聲學顯微鏡（Scanning Acoustic Microscope，SAM）），觀察半導體封裝內部的剝離、有無空隙。另外，對得到的半導體封裝進行剖面觀察，確認了半導體晶片和虛設晶片的高度。(Production and evaluation of semiconductor packages) The sealing material (trade name CEL-9750ZHF) manufactured by Hitachi Chemical Co., Ltd. was molded on the structures of the Examples and Comparative Examples under the conditions of 175°C/6.75 MPa/120 seconds, respectively, and performed at 175°C. Hours of hardening treatment to obtain semiconductor packages. Use the ultrasonic imaging diagnostic system (Insight (Insight) Co., Ltd., Insight-300, Scanning Acoustic Microscope, SAM)) to observe the peeling and voids inside the semiconductor package . In addition, the cross-sectional observation of the obtained semiconductor package confirmed the height of the semiconductor wafer and the dummy wafer.

半導體封裝內部沒有剝離和空隙，良好者判斷為「A」，有剝離和空隙者判斷為「B」。另外，將半導體晶片上表面與虛設晶片上表面的高度的差小於10 μm者記為「A」，將10 μm以上者記為「B」。將結果示於表2中。There are no peeling and voids inside the semiconductor package. Good ones are judged as "A", and those with peeling and voids are judged as "B". In addition, the height difference between the upper surface of the semiconductor wafer and the upper surface of the dummy wafer is less than 10 μm as "A", and the height of 10 μm or more is regarded as "B". The results are shown in Table 2.

[表2]   實施例 1 比較例 1 比較例 2 半導體封裝內部的剝離及空隙有無 A B B 半導體晶片上表面與虛設晶片上表面的高度的差 A B B [產業上的可利用性][Table 2] Example 1 Comparative example 1 Comparative example 2 Existence of peeling and voids inside the semiconductor package A B B The height difference between the upper surface of the semiconductor wafer and the upper surface of the dummy wafer A B B [Industrial availability]

根據本揭示，提供一種將第一晶片搭載於基板上且將第二晶片配置於第一晶片的上方的構成的半導體裝置的製造方法，其能夠抑制半導體裝置變得過厚，同時容易實施用密封材密封第一晶片及第二晶片的作業。另外，根據本揭示，提供一種不過厚且密封材的填充性優異的半導體裝置及在該半導體裝置的製造中使用的結構體。According to the present disclosure, there is provided a method for manufacturing a semiconductor device having a configuration in which a first wafer is mounted on a substrate and a second wafer is arranged above the first wafer, which can prevent the semiconductor device from becoming excessively thick and facilitate sealing Material to seal the first wafer and the second wafer. In addition, according to the present disclosure, a semiconductor device that is not too thick and has excellent filling properties of the sealing material and a structure used in the manufacture of the semiconductor device are provided.

1:基材膜 2:黏著劑層 3A:接著劑層 8:切晶黏晶一體型膜/膜 10:基板 30A、30B、40:結構體 42:針 44:抽吸夾具 50:密封材 100:半導體裝置 D:虛設晶片（間隔物） D1:晶片 Da:接著劑片 S1:第一晶片 S2:第二晶片 S2a:帶接著劑片的晶片 S3、S4:晶片 Sa:接著劑片 Sc:硬化物（接著劑片） w:線 W:晶圓1: Base film 2: Adhesive layer 3A: Adhesive layer 8: Die-cutting and bonding integrated film/film 10: substrate 30A, 30B, 40: structure 42: Needle 44: Suction fixture 50: Sealing material 100: Semiconductor device D: Dummy chip (spacer) D1: chip Da: Adhesive tablets S1: First chip S2: second chip S2a: Chip with adhesive sheet S3, S4: chip Sa: Adhesive tablets Sc: hardened substance (adhesive sheet) w: line W: Wafer

圖1是示意性表示本揭示所涉及的半導體裝置的第一實施方式的剖面圖。 圖2（a）及圖2（b）是示意性地表示第一晶片與多個虛設晶片的位置關係的例子的平面圖。 圖3（a）～圖3（e）是示意性地表示製造虛設晶片的過程的一例的剖面圖。 圖4是示意性地表示本揭示所涉及的在半導體裝置的製造中使用的結構體的第一實施方式的剖面圖。 圖5是示意性地表示帶接著劑片的晶片的一例的剖面圖。 圖6是示意性地表示在圖4所示的結構體上壓接圖5所示的帶接著劑片的晶片的狀態的剖面圖。 圖7是示意性地表示本揭示所涉及的在半導體裝置的製造中使用的結構體的另一實施方式的剖面圖。 圖8是示意性地表示在圖7所示的結構體上壓接圖5所示的帶接著劑片的晶片的狀態的剖面圖。FIG. 1 is a cross-sectional view schematically showing the first embodiment of the semiconductor device according to the present disclosure. 2(a) and 2(b) are plan views schematically showing an example of the positional relationship between the first wafer and a plurality of dummy wafers. 3(a) to 3(e) are cross-sectional views schematically showing an example of a process of manufacturing a dummy wafer. 4 is a cross-sectional view schematically showing a first embodiment of a structure used in the manufacture of a semiconductor device according to the present disclosure. Fig. 5 is a cross-sectional view schematically showing an example of a wafer with an adhesive sheet. Fig. 6 is a cross-sectional view schematically showing a state in which the wafer with an adhesive sheet shown in Fig. 5 is crimped onto the structure shown in Fig. 4. FIG. 7 is a cross-sectional view schematically showing another embodiment of a structure used in the manufacture of a semiconductor device according to the present disclosure. FIG. 8 is a cross-sectional view schematically showing a state in which the wafer with the adhesive sheet shown in FIG. 5 is crimped on the structure shown in FIG. 7.

10:基板 10: substrate

50:密封材 50: Sealing material

100:半導體裝置 100: Semiconductor device

D:虛設晶片(間隔物) D: Dummy chip (spacer)

D1:晶片 D1: chip

Da:接著劑片 Da: Adhesive tablets

S1:第一晶片 S1: First chip

S2:第二晶片 S2: second chip

S3、S4:晶片 S3, S4: chip

Sc:硬化物(接著劑片) Sc: hardened substance (adhesive sheet)

w:線 w: line

Claims (13)

一種半導體裝置的製造方法，包括： （A）準備結構體的步驟，所述結構體包括基板、配置於所述基板上的第一晶片、以及配置於所述基板上且配置於所述第一晶片的周圍的多個間隔物； （B）準備帶接著劑片的晶片的步驟，所述帶接著劑片的晶片包括尺寸較所述第一晶片大的第二晶片、及設置在所述第二晶片的一個面的接著劑片； （C）以所述接著劑片接觸所述多個間隔物的上表面的方式，將所述第二晶片配置在所述第一晶片的上方的步驟；以及 （D）密封所述第一晶片、所述間隔物及所述第二晶片的步驟，且 在實施（D）步驟之前，所述間隔物的上表面的高度與所述第一晶片的上表面的高度一致。A method for manufacturing a semiconductor device includes: (A) The step of preparing a structure, the structure including a substrate, a first wafer arranged on the substrate, and a plurality of spacers arranged on the substrate and arranged around the first wafer; (B) A step of preparing a wafer with an adhesive sheet, the wafer with an adhesive sheet including a second wafer larger in size than the first wafer, and an adhesive sheet provided on one surface of the second wafer ； (C) a step of arranging the second wafer above the first wafer such that the adhesive sheet contacts the upper surface of the plurality of spacers; and (D) a step of sealing the first wafer, the spacer, and the second wafer, and Before performing step (D), the height of the upper surface of the spacer is consistent with the height of the upper surface of the first wafer. 如申請專利範圍第1項所述的半導體裝置的製造方法，其中在所述（A）步驟準備的所述結構體中，所述間隔物的高度與所述第一晶片的上表面的高度一致。The method of manufacturing a semiconductor device as described in the scope of patent application 1, wherein in the structure prepared in the step (A), the height of the spacer is equal to the height of the upper surface of the first wafer . 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法，其中所述間隔物是包括晶片、及設置在所述晶片的一個面的接著劑片的虛設晶片。The method of manufacturing a semiconductor device according to the first or second claim, wherein the spacer is a dummy wafer including a wafer and an adhesive sheet provided on one surface of the wafer. 如申請專利範圍第1項所述的半導體裝置的製造方法，其中在所述（A）步驟準備的所述結構體中，所述間隔物的上表面高於所述第一晶片的上表面， 在所述（C）步驟中，藉由用所述帶接著劑片的晶片壓扁所述間隔物，使所述間隔物的高度與所述第一晶片的上表面的高度一致。The method for manufacturing a semiconductor device according to the first claim, wherein in the structure prepared in the step (A), the upper surface of the spacer is higher than the upper surface of the first wafer, In the step (C), the spacer is crushed with the wafer with the adhesive sheet so that the height of the spacer is equal to the height of the upper surface of the first wafer. 如申請專利範圍第4項所述的半導體裝置的製造方法，其中所述間隔物是包括晶片、及設置在所述晶片的一個面的接著劑片的虛設晶片， 所述虛設晶片所包括的所述接著劑片較所述帶接著劑片的晶片所包括的接著劑片軟。The method for manufacturing a semiconductor device according to claim 4, wherein the spacer is a dummy wafer including a wafer and an adhesive sheet provided on one surface of the wafer, The adhesive sheet included in the dummy chip is softer than the adhesive sheet included in the chip with adhesive sheet. 如申請專利範圍第5項所述的半導體裝置的製造方法，其中所述虛設晶片所包括的所述接著劑片較所述帶接著劑片的晶片所包括的接著劑片厚。The method for manufacturing a semiconductor device as described in the 5th patent application, wherein the adhesive sheet included in the dummy wafer is thicker than the adhesive sheet included in the wafer with adhesive sheet. 如申請專利範圍第1項至第6項中任一項所述的半導體裝置的製造方法，其中所述第一晶片藉由覆晶連接而搭載於所述基板。The manufacturing method of a semiconductor device according to any one of the claims 1 to 6, wherein the first chip is mounted on the substrate by flip chip connection. 一種半導體裝置，是藉由如申請專利範圍第1項至第7項中任一項所述的半導體裝置的製造方法而製造。A semiconductor device is manufactured by the method for manufacturing a semiconductor device as described in any one of items 1 to 7 of the scope of patent application. 一種半導體裝置，包括： 基板； 第一晶片，配置於所述基板上； 多個間隔物，配置於所述基板上且配置於所述第一晶片的周圍； 第二晶片，配置於所述第一晶片的上方，尺寸較所述第一晶片大； 接著劑片，將所述多個間隔物與所述第二晶片接著；以及 密封材，將所述第一晶片、所述間隔物及所述第二晶片密封，且 所述接著劑片與所述第一晶片的上表面接觸。A semiconductor device including: Substrate The first chip is configured on the substrate; A plurality of spacers arranged on the substrate and arranged around the first chip; The second chip is arranged above the first chip and is larger in size than the first chip; Adhesive sheet, adhering the plurality of spacers to the second wafer; and A sealing material for sealing the first chip, the spacer and the second chip, and The adhesive sheet is in contact with the upper surface of the first wafer. 如申請專利範圍第9項所述的半導體裝置，其中所述第一晶片是控制器晶片。The semiconductor device described in claim 9, wherein the first chip is a controller chip. 一種結構體，在半導體裝置的製造中使用，其包括： 基板； 第一晶片，配置於所述基板上；以及 多個間隔物，配置於所述基板上且配置於所述第一晶片的周圍，且 所述間隔物的上表面的高度與所述第一晶片的上表面的高度一致。A structure used in the manufacture of semiconductor devices, which includes: Substrate The first chip is disposed on the substrate; and A plurality of spacers are arranged on the substrate and arranged around the first chip, and The height of the upper surface of the spacer is consistent with the height of the upper surface of the first wafer. 一種結構體，在半導體裝置的製造中使用，其包括： 基板； 第一晶片，配置於所述基板上；以及 多個間隔物，配置於所述基板上且配置於所述第一晶片的周圍，且 所述間隔物的上表面高於所述第一晶片的上表面， 所述間隔物包括因被壓扁而所述間隔物的上表面的高度與所述第一晶片的上表面的高度一致的材料。A structure used in the manufacture of semiconductor devices, which includes: Substrate The first chip is disposed on the substrate; and A plurality of spacers are arranged on the substrate and arranged around the first chip, and The upper surface of the spacer is higher than the upper surface of the first wafer, The spacer includes a material whose height of the upper surface of the spacer is the same as the height of the upper surface of the first wafer due to being squashed. 一種結構體，在半導體裝置的製造中使用，其包括： 基板； 第一晶片，配置於所述基板上； 多個間隔物，配置於所述基板上且配置於所述第一晶片的周圍； 第二晶片，配置於所述第一晶片的上方，尺寸較所述第一晶片大；以及 接著劑片，將所述多個間隔物與所述第二晶片接著；且 所述接著劑片與所述第一晶片的上表面接觸。A structure used in the manufacture of semiconductor devices, which includes: Substrate The first chip is configured on the substrate; A plurality of spacers arranged on the substrate and arranged around the first chip; The second chip is disposed above the first chip and has a larger size than the first chip; and Adhesive tablets, adhering the plurality of spacers to the second wafer; and The adhesive sheet is in contact with the upper surface of the first wafer.
TW108141611A 2018-11-16 2019-11-15 Semiconductor device and manufacturing method thereof TWI814944B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/JP2018/042551 WO2020100308A1 (en) 2018-11-16 2018-11-16 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device
WOPCT/JP2018/042551 2018-11-16

Publications (2)

Publication Number Publication Date
TW202038425A true TW202038425A (en) 2020-10-16
TWI814944B TWI814944B (en) 2023-09-11

Family

ID=70731439

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108141611A TWI814944B (en) 2018-11-16 2019-11-15 Semiconductor device and manufacturing method thereof

Country Status (6)

Country Link
JP (1) JPWO2020100998A1 (en)
KR (1) KR20210094555A (en)
CN (1) CN113039641A (en)
SG (1) SG11202104932XA (en)
TW (1) TWI814944B (en)
WO (2) WO2020100308A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202213552A (en) * 2020-07-03 2022-04-01 日商昭和電工材料股份有限公司 Semiconductor device and method for producing same
CN116210358A (en) * 2020-08-11 2023-06-02 株式会社力森诺科 Semiconductor device and method for manufacturing the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
JP2010147225A (en) * 2008-12-18 2010-07-01 Renesas Technology Corp Semiconductor device and its manufacturing method
KR20110041301A (en) * 2009-10-15 2011-04-21 삼성전자주식회사 Semiconductor package and method of manufacturing the semiconductor package
KR101774938B1 (en) * 2011-08-31 2017-09-06 삼성전자 주식회사 Semiconductor package having supporting plate and method of forming the same
KR101906269B1 (en) * 2012-04-17 2018-10-10 삼성전자 주식회사 Semiconductor package and method of fabricating the same
KR102012505B1 (en) * 2012-12-20 2019-08-20 에스케이하이닉스 주식회사 Stack package having token ring loop
JP2015120836A (en) 2013-12-24 2015-07-02 日東電工株式会社 Adhesive film, dicing/die-bonding film, manufacturing method of semiconductor device and semiconductor device
KR102247916B1 (en) * 2014-01-16 2021-05-04 삼성전자주식회사 Semiconductro pacakages having stepwised stacking structures
US9418974B2 (en) * 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
KR20170014746A (en) * 2015-07-31 2017-02-08 에스케이하이닉스 주식회사 Stacked package and method for fabricating the same
CN108292653B (en) * 2015-09-25 2022-11-08 英特尔公司 Method, apparatus and system for interconnecting packaged integrated circuit dies
KR102576764B1 (en) * 2016-10-28 2023-09-12 에스케이하이닉스 주식회사 Semiconductor packages of asymmetric chip stacks
TWI613772B (en) * 2017-01-25 2018-02-01 力成科技股份有限公司 Thin fan-out type multi-chip stacked package

Also Published As

Publication number Publication date
WO2020100308A1 (en) 2020-05-22
JPWO2020100998A1 (en) 2021-09-30
CN113039641A (en) 2021-06-25
WO2020100998A1 (en) 2020-05-22
TWI814944B (en) 2023-09-11
KR20210094555A (en) 2021-07-29
SG11202104932XA (en) 2021-06-29

Similar Documents

Publication Publication Date Title
KR102067945B1 (en) Adhesive sheet and method for manufacturing semiconductor device
TWI362708B (en) A manufacturing method of semiconductor device
JP7298613B2 (en) Semiconductor device manufacturing method, thermosetting resin composition, and dicing/die bonding integrated film
JP5390209B2 (en) Thermosetting die bond film
TWI814944B (en) Semiconductor device and manufacturing method thereof
JP7247733B2 (en) Manufacturing method of semiconductor device having dolmen structure
JP7136200B2 (en) Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture
TW202105620A (en) Method for manufacturing semiconductor device having dolmen structure, method for manufacturing support piece, and laminated film
TW202107670A (en) Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor
JP7322897B2 (en) Adhesive film, dicing/die bonding integrated film, and method for manufacturing semiconductor package
TW202107667A (en) Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor
TWI830901B (en) Semiconductor device manufacturing method
TWI827779B (en) Chip-bonding integrated film and method for manufacturing semiconductor device
TWI844668B (en) Method for manufacturing semiconductor device having dolmen structure, method for manufacturing support sheet, and laminated film for forming support sheet
TWI830905B (en) Semiconductor device having a dolmen structure and its manufacturing method, and laminated film for supporting sheet formation and its manufacturing method
TW202107665A (en) Method for manufacturing semiconductor device having dolmen structure, method for manufacturing support piece, and laminate film for support piece formation
JP7351335B2 (en) Semiconductor device having dolmen structure, method for manufacturing the same, method for manufacturing support piece, and laminated film for forming support piece
WO2023152837A1 (en) Film-form adhesive, dicing and die-bonding two-in-one film, semiconductor device, and method for manufacturing same
WO2023157846A1 (en) Film-like adhesive and method for producing same, integrated dicing/die bonding film, and semiconductor device and method for producing same
JP2021180285A (en) Semiconductor device, manufacturing method thereof, and structure used in manufacturing of semiconductor device
TW202237786A (en) Adhesive agent composition, film-form adhesive agent, dicing/die-bonding integrated film, semiconductor device, and method for manufacturing same
TW202107671A (en) Method for manufacturing semiconductor device having dolmen structure, and method for manufacturing support piece
TW202414550A (en) Semiconductor device manufacturing method, adhesive layer and die-cut die-bonding integrated film
TW202107668A (en) Method for producing semiconductor device having dolmen structure and method for producing supporting pieces