WO2020100998A1 - Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device - Google Patents

Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device Download PDF

Info

Publication number
WO2020100998A1
WO2020100998A1 PCT/JP2019/044761 JP2019044761W WO2020100998A1 WO 2020100998 A1 WO2020100998 A1 WO 2020100998A1 JP 2019044761 W JP2019044761 W JP 2019044761W WO 2020100998 A1 WO2020100998 A1 WO 2020100998A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
adhesive piece
substrate
semiconductor device
height
Prior art date
Application number
PCT/JP2019/044761
Other languages
French (fr)
Japanese (ja)
Inventor
昌典 夏川
▲徳▼軒 蘇
麻未 上田
祐也 平本
Original Assignee
日立化成株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立化成株式会社 filed Critical 日立化成株式会社
Priority to KR1020217017011A priority Critical patent/KR20210094555A/en
Priority to JP2020556180A priority patent/JPWO2020100998A1/en
Priority to CN201980074797.0A priority patent/CN113039641A/en
Priority to SG11202104932XA priority patent/SG11202104932XA/en
Publication of WO2020100998A1 publication Critical patent/WO2020100998A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor device, a method for manufacturing the same, and a structure used for manufacturing the semiconductor device.
  • Wire bonding is a method of connecting a semiconductor chip and a substrate by using a metal thin wire such as a gold wire.
  • a method called flip chip connection is becoming widespread.
  • Flip-chip connection is a method in which conductive protrusions called bumps are formed on a semiconductor chip or a substrate to directly connect the semiconductor chip and the substrate.
  • Patent Document 1 discloses a semiconductor device in which a first semiconductor element (for example, a controller) is embedded in an adhesive film for adhering a second semiconductor element.
  • the present inventors formed a space by arranging a spacer around the position where the first chip is arranged instead of embedding the first chip with an adhesive film, and the first chip is arranged in this space. After the arrangement, a structure for filling the space with a sealing material was examined. As a result, it has been found that when the space is filled with the sealing material, if the height of the upper surface of the spacer is different from the height of the upper surface of the first chip, the filling with the sealing material tends to be difficult.
  • the present disclosure is a method for manufacturing a semiconductor device in which a first chip is mounted on a substrate and a second chip is arranged above the first chip, and it is possible to prevent the semiconductor device from becoming excessively thick.
  • EN Provided is a manufacturing method capable of easily performing an operation of sealing a first chip and a second chip with a sealing material. Further, the present disclosure provides a semiconductor device which is not excessively thick and has an excellent filling property with an encapsulant, and a structure used for manufacturing the semiconductor device.
  • a method of manufacturing a semiconductor device includes (A) a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate and around the first chip.
  • a step of preparing a structure includes (B) preparing a chip with an adhesive piece, comprising a second chip having a size larger than that of the first chip, and an adhesive piece provided on one surface of the second chip And (C) arranging the second chip above the first chip so that the adhesive pieces of the adhesive piece-attached chip are in contact with the upper surfaces of the plurality of spacers, and (D) the first chip ,
  • the step of sealing the spacer and the second chip, and the height of the upper surface of the spacer and the height of the upper surface of the first chip match before performing the step (D).
  • the term “coincidence” here means that the difference between the height of the upper surface of the spacer and the height of the upper surface of the first chip is less than 10 ⁇ m.
  • the height of the upper surface of the spacer matches the height of the upper surface of the first chip before the step (D) is carried out means that the chip with the adhesive piece arranged in the step (C) is It means that the adhesive piece is also in contact with the upper surface of the first chip. If the upper surface of the first chip and the adhesive piece are not in contact with each other and there is a gap between the two, it is difficult to fill the gap with the sealing material and a void is likely to occur. On the other hand, if the gap between the upper surface of the first chip and the adhesive piece is sufficiently wide, the filling property of the sealing material is improved, but the semiconductor device tends to be thick. On the other hand, according to the manufacturing method of the present disclosure, excellent filling properties of the sealing material and thinning of the semiconductor device can both be achieved.
  • the height of the upper surface of the spacer and the height of the upper surface of the first chip may match before the step (D) is performed.
  • the height of the upper surface of the spacer may be equal to the height of the upper surface of the first chip, or the structure prepared in the step (A).
  • the upper surface of the spacer is higher than the upper surface of the first chip, and in the subsequent step (C), the height of the upper surface of the spacer and the upper surface of the first chip are crushed by crushing the spacer with the chip with the adhesive piece. May be matched.
  • One mode of the spacer is a dummy chip including a chip and an adhesive piece provided on one surface of the chip.
  • the adhesive piece included in the dummy chip is larger than the adhesive piece included in the chip with the adhesive piece. Is also preferably soft. Further, the adhesive piece included in the dummy chip is preferably thicker than the adhesive piece included in the chip with the adhesive piece.
  • the first chip is mounted on the substrate by flip chip connection.
  • the height of the connecting portion is more likely to vary than when the adhesive film is used to adhere to the board.
  • the top surface of the first chip Is likely to vary in height position. Therefore, when the first chip is mounted by flip-chip connection, in the step (C), the height of the spacer can be adjusted by pressing the spacer with the chip with the adhesive piece so that the height of the spacer can be adjusted.
  • a semiconductor device includes a substrate, a first chip arranged on the substrate, a plurality of spacers arranged on the substrate around the first chip, and above the first chip.
  • a second chip that is arranged and has a larger size than the first chip, an adhesive piece that bonds a plurality of spacers to the second chip, a first chip, a spacer, and a second chip.
  • a sealing material that seals the adhesive chip, and the adhesive piece is in contact with the upper surface of the first chip.
  • the first chip is, for example, a controller chip.
  • the above semiconductor device can be manufactured by the manufacturing method according to the present disclosure.
  • the adhesive piece is in contact with the upper surface of the first chip, it is not excessively thick and is excellent in the filling property of the sealing material.
  • the present disclosure provides a structure used for manufacturing the semiconductor device.
  • the structure according to the first aspect includes a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip, and the upper surface of the spacer And the height of the upper surface of the first chip match.
  • a structure according to a second aspect includes a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip, and the upper surface of the spacer Is higher than the upper surface of the first chip, and the spacer is crushed, so that the spacer includes a material whose upper surface height matches the upper surface height of the first chip.
  • the structure according to the present disclosure may be a mode further including a second chip.
  • the structure according to this aspect includes a substrate, a first chip arranged on the substrate, a plurality of spacers arranged on the substrate around the first chip, and arranged above the first chip. And a second chip having a size larger than that of the first chip, and an adhesive piece adhering a plurality of spacers to the second chip, the adhesive piece being an upper surface of the first chip. Touches.
  • a manufacturing method capable of suppressing the above-mentioned problem and easily carrying out the work of sealing the first chip and the second chip with a sealing material.
  • a semiconductor device which is not excessively thick and has an excellent filling property with a sealing material, and a structure used for manufacturing the semiconductor device.
  • FIG. 1 is a sectional view schematically showing a first embodiment of a semiconductor device according to the present disclosure.
  • 2A and 2B are plan views schematically showing an example of the positional relationship between the first chip and the plurality of dummy chips.
  • 3A to 3E are sectional views schematically showing an example of a process of manufacturing a dummy chip.
  • FIG. 4 is a cross-sectional view schematically showing the first embodiment of the structure used for manufacturing the semiconductor device according to the present disclosure.
  • FIG. 5: is sectional drawing which shows an example of the chip
  • FIG. 6 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded to the structure shown in FIG.
  • FIG. 5 is sectional drawing which shows an example of the chip
  • FIG. 6 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded
  • FIG. 7 is a sectional view schematically showing another embodiment of a structure used for manufacturing a semiconductor device according to the present disclosure.
  • 8 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded to the structure shown in FIG.
  • FIG. 1 is a sectional view schematically showing the semiconductor device according to the present embodiment.
  • the semiconductor device 100 shown in this figure includes a substrate 10, a chip S1 (first chip) arranged on the surface of the substrate 10, and two chips S1 arranged on the surface of the substrate 10 and around the chip S1.
  • Dummy chip D spacer
  • chip S2 second chip
  • a wire w for electrically connecting the chips S2, S3, S4 to each other
  • a sealing material 50 for sealing the chips S1, S2, S3, S4, the dummy chip D and the wire w.
  • a cured product Sc of the adhesive piece is arranged between the upper surface of the chip S1 and the upper surfaces of the plurality of dummy chips D and the chip S2.
  • the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D match. That is, the cured product Sc is in contact with the upper surface of the chip S1 and the upper surface of the dummy chip D.
  • the substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing the warpage of the semiconductor device 100, the substrate 10 has a thickness of, for example, 90 to 300 ⁇ m, or may be 90 to 210 ⁇ m.
  • the chip S1 is, for example, a controller chip, and is mounted on the substrate 10 by flip chip connection.
  • the shape of the chip S1 in a plan view is, for example, a rectangle (square or rectangle).
  • the length of one side of the chip S1 is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm.
  • the thickness of the chip S1 is, for example, 10 to 150 ⁇ m, and may be 20 to 100 ⁇ m.
  • the chip S2 is, for example, a memory chip, and is bonded onto the chip S1 and the dummy chip D via the cured product Sc of the adhesive piece.
  • the chip S2 has a larger size than the chip S1 in a plan view.
  • the shape of the chip S2 in a plan view is, for example, a rectangle (square or rectangle).
  • the length of one side of the chip S2 is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm.
  • the thickness of the chip S2 is, for example, 10 to 170 ⁇ m, and may be 20 to 120 ⁇ m.
  • the chips S3 and S4 are also memory chips, for example, and are bonded onto the chip S2 via the cured product Sc of the adhesive pieces.
  • the length of one side of the chips S3, S4 may be the same as that of the chip S2, and the thickness of the chips S3, S4 may be the same as that of the chip S2.
  • the dummy chip D plays a role of a spacer that forms a space around the chip S1.
  • the dummy chip D is composed of a chip D1 and an adhesive piece Da provided on one surface of the chip D1.
  • two dummy chips D may be arranged at separate positions on both sides of the chip S1, or as shown in FIG.
  • One dummy chip D (shape: square, total of four) may be arranged at a position corresponding to each corner of.
  • the length of one side of the chip D1 in a plan view is, for example, 20 mm or less, and may be 1 to 20 mm or 1 to 12 mm.
  • the thickness of the chip D1 is, for example, 30 to 150 ⁇ m, and may be 80 to 120 ⁇ m.
  • the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 match.
  • the position of the upper surface of the chip S1 that is flip-chip connected and the position of the upper surface of the dummy chip D can be matched.
  • a dicing die bonding integrated film 8 (hereinafter, referred to as “film 8” in some cases) is prepared and placed in a predetermined device (not shown).
  • the film 8 includes the base film 1, the pressure-sensitive adhesive layer 2, and the adhesive layer 3A in this order.
  • the base film 1 is, for example, a polyethylene terephthalate film (PET film).
  • PET film polyethylene terephthalate film
  • the pressure-sensitive adhesive layer 2 has a property that its adhesiveness is lowered by being irradiated with ultraviolet rays.
  • the adhesive layer 3A is made of a thermosetting resin composition.
  • the film 8 is attached so that the adhesive layer 3A is in contact with one surface of the wafer W.
  • the wafer W may be single crystal silicon, or may be polycrystal silicon, various ceramics, or a compound semiconductor such as gallium arsenide.
  • the wafer W does not have to be a semiconductor and may be, for example, a glass substrate.
  • the wafer W and the adhesive layer 3A are cut with a dicing blade (see FIG. 3 (c)).
  • the wafer W is diced into individual pieces to form the chips D1.
  • the adhesive layer 3A is diced into individual pieces to form the adhesive pieces Da.
  • the adhesive force between the adhesive layer 2 and the adhesive layer 3A is reduced by irradiating the adhesive layer 2 with ultraviolet rays.
  • the dummy film D is separated from each other by expanding the base film 1.
  • the dummy chip D is peeled from the adhesive layer 2 by pushing up the dummy chip D with the needle 42, and the dummy chip D is picked up by suction with the suction collet 44.
  • a method of manufacturing the semiconductor device 100 will be described with reference to FIGS.
  • the method for manufacturing the semiconductor device 100 includes the following steps (A) to (D).
  • (A) A step of preparing a structure 30A including a substrate 10, a chip S1 arranged on the substrate 10, and a plurality of dummy chips D arranged on the substrate 10 around the chip S1 (FIG. 4). reference).
  • (B) A step of preparing a chip S2a with an adhesive piece, which includes the chip S2 and an adhesive piece Sa provided on one surface of the chip S2 (see FIG. 5).
  • (C) A step of disposing the chip S2 above the chip S1 such that the adhesive pieces Sa are in contact with the upper surfaces of the plurality of dummy chips D and the upper surface of the chip S1 (see FIG. 6).
  • (D) A step of sealing the chips S1, S2, S3, S4, the dummy chip D, and the like.
  • the step (A) is a step of preparing the structure 30A shown in FIG.
  • the structure 30A includes a substrate 10, a chip S1 and a plurality of dummy chips D arranged on the surface thereof, and the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D are the same.
  • the chip S1 may be mounted at a predetermined position on the substrate 10 by flip chip connection, and then the dummy chip D may be pressure-bonded to the predetermined position.
  • This pressure bonding treatment is preferably carried out, for example, under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds.
  • the adhesive piece Da of the dummy chip D may be completely cured at the time of the (A) process, may not be completely cured at this time, and may be completely cured at the time of the (C) process. ..
  • the step (B) is a step of preparing the chip S2a with the adhesive piece shown in FIG.
  • the chip with adhesive piece S2a includes the chip S2 and the adhesive piece Sa provided on one surface thereof.
  • the chip S2a with the adhesive piece can be obtained through a dicing process using, for example, a dicing die bonding integral type film (see FIGS. 3A to 3E).
  • the step (C) is a step of arranging the chip S2a with the adhesive piece above the chip S1 so that the adhesive piece Sa contacts the upper surfaces of the plurality of dummy chips D and the upper surface of the chip S1.
  • the chip S2 is pressure-bonded to the upper surface of the dummy chip D and the upper surface of the chip S1 via the adhesive piece Sa.
  • This pressure bonding treatment is preferably carried out, for example, under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds.
  • the adhesive piece Sa is cured by heating. This curing treatment is preferably carried out, for example, under conditions of 60 to 175 ° C. and 0.01 to 1.0 MPa for 5 minutes or more. As a result, the adhesive piece Sa becomes the cured product Sc.
  • FIG. 6 is a sectional view schematically showing a structure obtained through the step (C).
  • the structure 40 shown in this figure since there is no gap between the cured product Sc and the chip S1, excellent filling properties of the encapsulant can be achieved in the step (D).
  • the chip S3 is arranged on the chip S2 via the adhesive piece, and further, the chip S4 is arranged on the chip S3 via the adhesive piece. ..
  • the adhesive piece may be a thermosetting resin composition similar to the adhesive piece Sa described above, and becomes a cured product Sc by heat curing (see FIG. 1).
  • the chips S2, S3, S4 and the substrate 10 are electrically connected by the wires w. Note that the number of chips stacked above the chip S1 is not limited to three in this embodiment, and may be set appropriately.
  • Step (D) is a step of sealing the chips S1, S2, S3, S4, the dummy chip D and the wire w with the sealing material 50. Through these steps, the semiconductor device 100 shown in FIG. 1 is completed.
  • thermosetting resin composition The thermosetting resin composition constituting the adhesive piece Da and the adhesive piece Sa will be described.
  • the thermosetting resin composition according to the present embodiment is capable of undergoing a semi-cured (B stage) state and then a completely cured (C stage) state by a subsequent curing treatment.
  • the thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler, a curing accelerator, and the like, if necessary.
  • the epoxy resin is not particularly limited as long as it cures and has an adhesive action.
  • Bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin and bisphenol S type epoxy resin, and novolac type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin can be used.
  • polyfunctional epoxy resin glycidylamine type epoxy resin, heterocycle-containing epoxy resin or alicyclic epoxy resin can be applied. These may be used alone or in combination of two or more.
  • the curing agent examples include phenolic resins, ester compounds, aromatic amines, aliphatic amines, and acid anhydrides. Of these, a phenol resin is preferable from the viewpoint of reactivity and stability over time.
  • Commercially available phenolic resins include, for example, Phenolite KA and TD series manufactured by DIC Corporation, Mirex XLC-series and XL series manufactured by Mitsui Chemicals, Inc. (for example, MIlex XLC-LL), Air Water Co., Ltd.
  • HE series for example, HE100C-30
  • MEHC-7800 series for example, MEHC-7800-4S manufactured by Meiwa Kasei Co., Ltd. may be mentioned. These may be used alone or in combination of two or more.
  • the mixing ratio of the epoxy resin and the phenol resin is such that the equivalent ratio of the epoxy equivalent and the hydroxyl equivalent is preferably 0.30 / 0.70 to 0.70 / 0.30, and more preferably 0. 35 / 0.65 to 0.65 / 0.35, more preferably 0.40 / 0.60 to 0.60 / 0.40, and particularly preferably 0.45 / 0.55 to 0.55 / 0. 45.
  • the compounding ratio is within the above range, both curability and fluidity can be easily achieved at sufficiently high levels.
  • Examples of the elastomer include acrylic resin, polyester resin, polyamide resin, polyimide resin, silicone resin, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, maleic anhydride-modified polybutadiene, phenol-modified polybutadiene, and carboxy-modified acrylonitrile.
  • an acrylic resin is preferable as the elastomer, and further obtained by polymerizing a functional monomer having an epoxy group or a glycidyl group such as glycidyl acrylate or glycidyl methacrylate as a crosslinkable functional group.
  • An acrylic resin such as an epoxy group-containing (meth) acrylic copolymer is more preferable.
  • an epoxy group-containing (meth) acrylic acid ester copolymer and an epoxy group-containing acrylic rubber are preferable, and an epoxy group-containing acrylic rubber is more preferable.
  • the epoxy group-containing acrylic rubber is a rubber having an epoxy group, which is mainly composed of an acrylic ester and is mainly composed of a copolymer such as butyl acrylate and acrylonitrile or a copolymer such as ethyl acrylate and acrylonitrile.
  • the acrylic resin may have a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group and a carboxyl group, as well as an epoxy group.
  • acrylic resins are SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, SG-P3 manufactured by Nagase Chemtech Co., Ltd. (product name, acrylic rubber, weight) Average molecular weight: 800,000, Tg: 12 ° C., solvent is cyclohexanone, etc.
  • the glass transition temperature (Tg) of the acrylic resin is preferably ⁇ 50 to 50 ° C., more preferably ⁇ 30 to 30 ° C.
  • the weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3,000,000, more preferably 500,000 to 2,000,000.
  • Mw means a value measured by gel permeation chromatography (GPC) and converted using a calibration curve based on standard polystyrene. The use of an acrylic resin having a narrow molecular weight distribution tends to form an adhesive piece having excellent embedding properties and high elasticity.
  • the amount of acrylic resin contained in the thermosetting resin composition is preferably 20 to 200 parts by mass, and more preferably 30 to 100 parts by mass, based on 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent. More preferable. Within this range, control of fluidity during molding, handling at high temperature, and embedding property can be further improved.
  • inorganic filler examples include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride and crystallinity.
  • examples thereof include silica and amorphous silica. These may be used alone or in combination of two or more.
  • the average particle size of the inorganic filler is preferably 0.005 ⁇ m to 1.0 ⁇ m, and more preferably 0.05 to 0.5 ⁇ m, from the viewpoint of improving adhesiveness.
  • the surface of the inorganic filler is preferably chemically modified from the viewpoint of compatibility with a solvent and a resin component and adhesive strength. Suitable materials for chemically modifying the surface include silane coupling agents. Examples of the functional group of the silane coupling agent include vinyl group, acryloyl group, epoxy group, mercapto group, amino group, diamino group, alkoxy group and ethoxy group.
  • the content of the inorganic filler with respect to 100 parts by mass of the resin component of the thermosetting resin composition is preferably 20 to 200 parts by mass, more preferably 30 to 100 parts by mass.
  • curing accelerator examples include imidazoles and their derivatives, organic phosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. Imidazole compounds are preferable from the viewpoint of appropriate reactivity.
  • imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole and the like. These may be used alone or in combination of two or more.
  • the content of the curing accelerator in the thermosetting resin composition is preferably 0.04 to 3 parts by mass, and 0.04 to 0.2 parts by mass based on 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent. More preferable. When the amount of the curing accelerator added is within this range, both curability and reliability can be achieved.
  • the structure 30A in which the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 are the same is prepared in the step (A).
  • a structure whose upper surface is higher than the upper surface of the chip S1 may be prepared in the step (A).
  • the structure 30B shown in FIG. 7 includes a substrate 10, a chip S1 arranged on the substrate 10, and a plurality of dummy chips D arranged on the substrate 10 around the chip S1. Is higher than the upper surface of the chip S1.
  • the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 match before the step (D) of the first embodiment (step of sealing with the sealing material 50).
  • the height of the dummy chip D and the height of the upper surface of the chip S1 may be matched by crushing the adhesive piece Da of the dummy chip D with the chip S2a having the adhesive piece (see FIG. 8).
  • the height of the connection portion of the flip chip tends to vary by about 5 ⁇ m, and as a result, the height position of the upper surface of the chip S1 varies by about 5 ⁇ m.
  • the upper surface of the dummy chip D in the step (A) is set.
  • the height and the height of the upper surface of the chip S1 do not have to be exactly the same.
  • the adhesive piece Da of the dummy chip D is made of a material that is crushed by the adhesive piece chip S2a.
  • the adhesive piece Da of the dummy chip D is preferably softer than the adhesive piece Sa of the chip S2a with an adhesive piece.
  • the content of the thermosetting resin of the adhesive piece Da is made larger than that of the adhesive piece Sa, or the elastomer or the inorganic filler of the adhesive piece Da is used. The content of may be smaller than that of the adhesive piece Sa.
  • the adhesive piece Da of the dummy chip D is preferably thicker than the adhesive piece Sa of the chip Sa2 with an adhesive piece.
  • the thickness of the adhesive piece Da is 1.1 to 8 times the thickness of the adhesive piece Sa, and may be 1.2 to 6 times.
  • the present invention is not limited to the above embodiments.
  • the case where the chip S1 is mounted by flip-chip connection is illustrated, but the chip S1 may be fixed to the substrate 10 by an adhesive and then electrically connected by wire bonding.
  • Varnishes A and B of the adhesive composition were prepared using the components shown in Table 1 by the following procedure. First, after mixing [epoxy resin], [curing agent] and [filler] described below, cyclohexanone was added and stirred. Then, [elastomer], [curing accelerator] and [coupling agent] were added and stirred until each component became uniform to obtain a varnish of the adhesive composition.
  • Acrylic rubber product name by Nagase Chemtex Co., Ltd., product name “HTR-860P-3”, weight average molecular weight 800,000, glass transition point: 12 ° C.
  • Phenolic resin manufactured by Mitsui Chemicals, Inc., trade name "Milex XLC-LL", softening point: 75 ° C, hydroxyl equivalent 175
  • Silica filler Nippon Aerosil Co., Ltd., trade name “R972”, average particle size 0.500 ⁇ m Silica filler: manufactured by Admatechs Co., Ltd., trade name "SC2050-HLG", specific surface area 110 m / g
  • Varnish A was applied on a base film (polyethylene terephthalate film having a release treatment, thickness: 38 ⁇ m).
  • the adhesive sheet A1 (thickness 20 ⁇ m) and the adhesive sheet A2 (thickness 40 ⁇ m) were produced by heating and drying at 140 ° C. for 5 minutes on the base film.
  • An adhesive sheet B (thickness 40 ⁇ m) was produced in the same manner as above except that the varnish B was used instead of the varnish A.
  • melt viscosity of adhesive sheet was measured by the following procedure using a rotary viscoelasticity measuring device (ARES-RDA manufactured by TA Instruments Japan Co., Ltd.). First, after peeling the substrate film from the adhesive sheet, a plurality of adhesive layers were attached at 70 ° C. to obtain a laminated film having a thickness of 160 ⁇ m or more. This was punched into a circle having a diameter of 8 mm and then sandwiched by two jigs (diameter: 8 mm) to obtain a measurement sample. The measurement was carried out under the following conditions, and the value at 80 ° C was taken as the melt viscosity of the adhesive sheet.
  • the adhesive sheets A1 and A2 had a melt viscosity of 24000 Pa ⁇ s, and the adhesive sheet B had a melt viscosity of 2000 Pa ⁇ s.
  • Example 1 The adhesive sheet A1 (thickness: 20 ⁇ m) was attached to a semiconductor wafer (thickness: 90 ⁇ m). A semiconductor wafer was diced into 5.0 mm ⁇ 5.0 mm semiconductor chips by using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto an organic substrate dried at 120 ° C./0.1 MPa / sec for 1 hour at 150 ° C. to obtain a substrate with a semiconductor chip.
  • DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.
  • the adhesive sheet B (thickness: 40 ⁇ m) was attached to the semiconductor wafer (thickness: 80 ⁇ m).
  • the semiconductor wafer was diced into chips of 1.5 mm ⁇ 6.0 mm using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) at 120 ° C./0.1 MPa / 1 second, thermocompression bonding the above chips as dummy chips on the organic substrates on both sides with a space of 2 mm. did.
  • HR-900T-20-N50 manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness: 20 ⁇ m
  • a semiconductor wafer thickness: 50 ⁇ m
  • DISCO DFM-2800 wafer mounter
  • / (10 mm / sec) was applied.
  • the semiconductor wafer was diced into chips of 6.0 mm ⁇ 12.0 mm by using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto a semiconductor chip and two dummy chips at 100 to 120 ° C./0.05 to 0.20 MPa / 0.5 to 2.0 seconds. ..
  • the adhesive was cured under the conditions of heating at 150 ° C. for 1 hour in a pressurized atmosphere of 7 kg. As a result, a structure including the substrate, the two dummy chips, and the two semiconductor chips was obtained.
  • the adhesive sheet A1 (thickness: 20 ⁇ m) was attached to a semiconductor wafer (thickness: 90 ⁇ m).
  • a semiconductor wafer was diced into 5.0 mm ⁇ 5.0 mm semiconductor chips by using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto an organic substrate dried at 120 ° C./0.1 MPa / sec for 1 hour at 150 ° C. to obtain a substrate with a semiconductor chip.
  • the adhesive sheet A2 (thickness: 40 ⁇ m) was attached to the semiconductor wafer (thickness: 90 ⁇ m).
  • the semiconductor wafer was diced into 1.5 mm ⁇ 6.0 mm chips using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) at 120 ° C./0.1 MPa / 1 second, thermocompression bonding the above chips as dummy chips on the organic substrates on both sides with a space of 2 mm. did.
  • HR-900T-20-N50 manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness: 20 ⁇ m
  • a semiconductor wafer thickness: 50 ⁇ m
  • DISCO DFM-2800 wafer mounter
  • / (10 mm / sec) was applied.
  • the semiconductor wafer was diced into chips of 6.0 mm ⁇ 12.0 mm by using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto the semiconductor chip and the two dummy chips at 120 ° C./0.10 MPa / 1.0 seconds.
  • the adhesive was cured under the conditions of heating at 150 ° C. for 1 hour in a pressurized atmosphere of 7 kg. As a result, a structure including the substrate, the two dummy chips, and the two semiconductor chips was obtained.
  • the adhesive sheet A1 (thickness: 20 ⁇ m) was attached to a semiconductor wafer (thickness: 90 ⁇ m).
  • a semiconductor wafer was diced into 5.0 mm ⁇ 5.0 mm semiconductor chips by using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto an organic substrate dried at 150 ° C. for 1 hour at 120 ° C./0.1 MPa / 1 second to obtain a substrate with a semiconductor chip.
  • the adhesive sheet A1 (thickness: 20 ⁇ m) was attached to the semiconductor wafer (thickness: 110 ⁇ m).
  • the semiconductor wafer was diced into 1.5 mm ⁇ 6.0 mm chips using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) at 120 ° C./0.1 MPa / 1 second, thermocompression bonding the above chips as dummy chips on the organic substrates on both sides with a space of 2 mm. did.
  • a semiconductor wafer (thickness: 50 ⁇ m) was loaded with HR-900T-20-N50 (manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness: 20 ⁇ m) at 70 ° C. with a wafer mounter (DISCO DFM-2800). / (10 mm / sec) was applied.
  • the semiconductor wafer was diced into chips of 6.0 mm ⁇ 12.0 mm using a dicer (DFD-6361 manufactured by DISCO).
  • a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto the semiconductor chip and the two dummy chips at 120 ° C./0.10 MPa / 1.0 seconds.
  • the adhesive was cured under the conditions of heating at 150 ° C. for 1 hour in a pressurized atmosphere of 7 kg. As a result, a structure including the substrate, the two dummy chips, and the two semiconductor chips was obtained.
  • Encapsulating material (trade name CEL-9750ZHF) manufactured by Hitachi Chemical Co., Ltd. was molded on each of the structures according to the example and the comparative example under the conditions of 175 ° C./6.75 MPa / 120 seconds, and was molded at 175 ° C. for 5 hours. Was cured to obtain a semiconductor package.
  • An ultrasonic image diagnostic system (Insight Co., Ltd., Insight-300 Scanning Acoustic Microscope: SAM) was used to observe peeling and voids inside the semiconductor package. The height of the semiconductor chip and the dummy chip was confirmed by observing the cross section of the obtained semiconductor package.
  • a manufacturing method capable of suppressing the above-mentioned problem and easily carrying out the work of sealing the first chip and the second chip with a sealing material.
  • a semiconductor device which is not excessively thick and has an excellent filling property with a sealing material, and a structure used for manufacturing the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Adhesive Tapes (AREA)

Abstract

This manufacturing method of a semiconductor device involves (A) a step for preparing a structure that is provided with a substrate, a first chip arranged on the substrate, and multiple spacers arranged on the substrate and around the first chip, (B) a step for preparing a chip with an adhesive piece, said chip with an adhesive piece comprising a second chip larger than the first chip and an adhesive piece arranged on one side of the second chip, (C) a step for arranging the second chip above the first chip such that the adhesive piece contacts the top of the multiple spacers, and (D) a step for sealing the first chip, the spacers and the second chip. The height of the top of the spacers and the height of the top of the first chip coincide prior to carrying out step (D).

Description

半導体装置及びその製造方法、並びに半導体装置の製造に使用される構造体SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND STRUCTURE USED IN MANUFACTURING SEMICONDUCTOR DEVICE
　本開示は半導体装置及びその製造方法、並びに半導体装置の製造に使用される構造体に関する。 The present disclosure relates to a semiconductor device, a method for manufacturing the same, and a structure used for manufacturing the semiconductor device.
　従来、半導体チップと基板の接続にはワイヤーボンディングが広く適用されている。ワイヤーボンディングは、金ワイヤ等の金属細線を用いて半導体チップと基板を接続する方式である。半導体装置（以下、場合により、「半導体パッケージ」という。）に対する高機能化、高集積化及び高速化等の要求に対応するため、フリップチップ接続と称される方式が広まりつつある。フリップチップ接続は、半導体チップ又は基板にバンプと呼ばれる導電性突起を形成して、半導体チップと基板間で直接接続する方式である。 Conventionally, wire bonding has been widely applied to connect semiconductor chips and substrates. Wire bonding is a method of connecting a semiconductor chip and a substrate by using a metal thin wire such as a gold wire. In order to meet the demand for higher functionality, higher integration and higher speed of semiconductor devices (hereinafter, sometimes referred to as “semiconductor package”), a method called flip chip connection is becoming widespread. Flip-chip connection is a method in which conductive protrusions called bumps are formed on a semiconductor chip or a substrate to directly connect the semiconductor chip and the substrate.
　上述のとおり、半導体パッケージは高機能化の他に、薄型化及び小型化が求められている。更なる小型化及び薄型化及び高機能化が要求される半導体パッケージとして、チップスタック型パッケージ、ＰＯＰ（Ｐａｃｋａｇｅ　Ｏｎ　Ｐａｃｋａｇｅ）、ＴＳＶ（Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）等も普及し始めている。これらの半導体パッケージは、平面状でなく立体状にチップが配置されるため、サイズを小さくできる。例えば、特許文献１は、第１半導体素子（例えば、コントローラ）が第２半導体素子を接着するための接着フィルムに埋め込まれている態様の半導体装置を開示する。 As mentioned above, in addition to high functionality, semiconductor packages are required to be thin and compact. Chip stack type packages, POP (Package On Package), TSV (Through Silicon Via), etc. are beginning to spread as semiconductor packages that require further miniaturization, thinning, and high functionality. Since these semiconductor packages have chips arranged in a three-dimensional shape instead of a two-dimensional shape, the size can be reduced. For example, Patent Document 1 discloses a semiconductor device in which a first semiconductor element (for example, a controller) is embedded in an adhesive film for adhering a second semiconductor element.
特開２０１５－１２０８３６号公報JP, 2015-120836, A
　本発明者らの検討によると、特許文献１に記載の半導体装置のように、基板上の第一のチップを接着フィルムに埋め込む場合、ボイドが発生しやすいという課題がある。また、ボイド発生を抑制するため、流動性に優れる比較的軟らかい接着フィルムを使用すると、接着フィルムを介して接着される第二のチップの位置がずれたり歪みが生じたりして、その上に更に複数のチップを積層することが困難となりやすい。これに加え、第一のチップを埋め込むことができる十分な厚さを有する接着フィルムを使用する必要があり、半導体パッケージが厚くなる傾向にある。 According to the study by the present inventors, when the first chip on the substrate is embedded in the adhesive film as in the semiconductor device described in Patent Document 1, there is a problem that voids are likely to occur. Further, in order to suppress the occurrence of voids, if a relatively soft adhesive film with excellent fluidity is used, the position of the second chip bonded via the adhesive film may be displaced or distorted, and It is difficult to stack a plurality of chips. In addition to this, it is necessary to use an adhesive film having a sufficient thickness to embed the first chip, which tends to increase the thickness of the semiconductor package.
　本発明者らは、第一のチップを接着フィルムで埋め込む代わりに、第一のチップが配置される位置の周囲にスペーサーを配置することによって空間を形成し、この空間内に第一のチップを配置した後、封止材で空間を充填する構成を検討した。その結果、封止材によって空間を充填する際、スペーサーの上面の高さと第一のチップの上面の高さにずれがあると、封止材による充填が困難となりやすいことが見出された。 The present inventors formed a space by arranging a spacer around the position where the first chip is arranged instead of embedding the first chip with an adhesive film, and the first chip is arranged in this space. After the arrangement, a structure for filling the space with a sealing material was examined. As a result, it has been found that when the space is filled with the sealing material, if the height of the upper surface of the spacer is different from the height of the upper surface of the first chip, the filling with the sealing material tends to be difficult.
　本開示は、第一のチップが基板上に搭載され且つ第一のチップの上方に第二のチップが配置された構成の半導体装置の製造方法であって半導体装置が過度に厚くなることを抑制できるとともに、第一のチップ及び第二のチップを封止材で封止する作業を容易に実施することができる製造方法を提供する。また、本開示は、過度に厚くなく且つ封止材の充填性に優れた半導体装置及びこの半導体装置の製造に使用される構造体を提供する。 The present disclosure is a method for manufacturing a semiconductor device in which a first chip is mounted on a substrate and a second chip is arranged above the first chip, and it is possible to prevent the semiconductor device from becoming excessively thick. (EN) Provided is a manufacturing method capable of easily performing an operation of sealing a first chip and a second chip with a sealing material. Further, the present disclosure provides a semiconductor device which is not excessively thick and has an excellent filling property with an encapsulant, and a structure used for manufacturing the semiconductor device.
　本開示に係る半導体装置の製造方法は、（Ａ）基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数のスペーサーとを備える構造体を準備する工程と、（Ｂ）第一のチップよりもサイズが大きい第二のチップと、第二のチップの一方の面に設けられた接着剤片とを備える接着剤片付きチップを準備する工程と、（Ｃ）複数のスペーサーの上面に接着剤片付きチップの接着剤片が接するように、第一のチップの上方に第二のチップを配置する工程と、（Ｄ）第一のチップ、スペーサー及び第二のチップを封止する工程とを含み、（Ｄ）工程を実施する前において、スペーサーの上面の高さと、第一のチップの上面の高さとが一致している。なお、ここでいう「一致」とは、スペーサーの上面の高さと第一のチップの上面の高さの差が１０μｍ未満であることを意味する。 A method of manufacturing a semiconductor device according to the present disclosure includes (A) a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate and around the first chip. A step of preparing a structure; (B) preparing a chip with an adhesive piece, comprising a second chip having a size larger than that of the first chip, and an adhesive piece provided on one surface of the second chip And (C) arranging the second chip above the first chip so that the adhesive pieces of the adhesive piece-attached chip are in contact with the upper surfaces of the plurality of spacers, and (D) the first chip , The step of sealing the spacer and the second chip, and the height of the upper surface of the spacer and the height of the upper surface of the first chip match before performing the step (D). It should be noted that the term “coincidence” here means that the difference between the height of the upper surface of the spacer and the height of the upper surface of the first chip is less than 10 μm.
　上記（Ｄ）工程が実施される前に、スペーサーの上面の高さと、第一のチップの上面の高さとが一致しているということは、（Ｃ）工程で配置された接着剤片付きチップの接着剤片が第一のチップの上面にも接していることを意味する。仮に、第一のチップの上面と接着剤片とが接しておらず、両者の間に隙間があると、この隙間に封止材を充填しにくく、ボイドが発生しやすい。他方、第一のチップの上面と接着剤片との間隔を十分に広くすれば、封止材の充填性が高まるものの、半導体装置が厚くなる傾向にある。これに対し、本開示の製造方法によれば、封止材の優れた充填性と半導体装置の薄型化を両立できる。 The fact that the height of the upper surface of the spacer matches the height of the upper surface of the first chip before the step (D) is carried out means that the chip with the adhesive piece arranged in the step (C) is It means that the adhesive piece is also in contact with the upper surface of the first chip. If the upper surface of the first chip and the adhesive piece are not in contact with each other and there is a gap between the two, it is difficult to fill the gap with the sealing material and a void is likely to occur. On the other hand, if the gap between the upper surface of the first chip and the adhesive piece is sufficiently wide, the filling property of the sealing material is improved, but the semiconductor device tends to be thick. On the other hand, according to the manufacturing method of the present disclosure, excellent filling properties of the sealing material and thinning of the semiconductor device can both be achieved.
　本開示の製造方法において、（Ｄ）工程が実施される前に、スペーサーの上面の高さと、第一のチップの上面の高さとが一致していればよい。例えば、（Ａ）工程で準備された構造体において、スペーサーの上面の高さと、第一のチップの上面の高さとが一致していてもよく、あるいは、（Ａ）工程で準備された構造体において、スペーサーの上面が第一のチップの上面よりも高く、その後の（Ｃ）工程において、接着剤片付きチップでスペーサーを押し潰すことによってスペーサーの上面の高さと第一のチップの上面の高さとを一致させてもよい。 In the manufacturing method of the present disclosure, the height of the upper surface of the spacer and the height of the upper surface of the first chip may match before the step (D) is performed. For example, in the structure prepared in the step (A), the height of the upper surface of the spacer may be equal to the height of the upper surface of the first chip, or the structure prepared in the step (A). In, the upper surface of the spacer is higher than the upper surface of the first chip, and in the subsequent step (C), the height of the upper surface of the spacer and the upper surface of the first chip are crushed by crushing the spacer with the chip with the adhesive piece. May be matched.
　上記スペーサーの一態様は、チップと、このチップの一方の面に設けられた接着剤片とを備えるダミーチップである。上記のように、（Ｃ）工程において、接着剤片付きチップでスペーサーを押し潰すことによってスペーサーの高さを調整する場合、ダミーチップが備える接着剤片は、接着剤片付きチップが備える接着剤片よりも軟らかいことが好ましい。また、ダミーチップが備える接着剤片は、接着剤片付きチップが備える接着剤片よりも厚いことが好ましい。 One mode of the spacer is a dummy chip including a chip and an adhesive piece provided on one surface of the chip. As described above, in the step (C), when adjusting the height of the spacer by crushing the spacer with the chip with the adhesive piece, the adhesive piece included in the dummy chip is larger than the adhesive piece included in the chip with the adhesive piece. Is also preferably soft. Further, the adhesive piece included in the dummy chip is preferably thicker than the adhesive piece included in the chip with the adhesive piece.
　半導体装置の高速化の観点から、第一のチップは、フリップチップ接続によって基板に搭載されていることが好ましい。フリップチップ接続によって第一のチップを基板に搭載する場合、接着フィルムを使用して基板に接着する場合と比較して接続部の高さにばらつきが生じやすく、その結果、第一のチップの上面の高さ位置にばらつきが生じやすい。このため、第一のチップがフリップチップ接続によって搭載されている場合、（Ｃ）工程において、接着剤片付きチップでスペーサーを押し潰すことによって、スペーサーの高さを調整できるように、（Ａ）工程において、スペーサーの上面が第一のチップの上面よりも高い構造体を準備することが好ましい。 From the viewpoint of speeding up the semiconductor device, it is preferable that the first chip is mounted on the substrate by flip chip connection. When the first chip is mounted on the board by flip-chip connection, the height of the connecting portion is more likely to vary than when the adhesive film is used to adhere to the board. As a result, the top surface of the first chip Is likely to vary in height position. Therefore, when the first chip is mounted by flip-chip connection, in the step (C), the height of the spacer can be adjusted by pressing the spacer with the chip with the adhesive piece so that the height of the spacer can be adjusted. In, it is preferable to prepare a structure in which the upper surface of the spacer is higher than the upper surface of the first chip.
　本開示に係る半導体装置は、基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数のスペーサーと、第一のチップの上方に配置されており、第一のチップよりもサイズが大きい第二のチップと、複数のスペーサーと第二のチップとを接着している接着剤片と、第一のチップ、スペーサー及び第二のチップを封止している封止材とを備え、接着剤片が第一のチップの上面に接している。第一のチップは、例えば、コントローラーチップである。 A semiconductor device according to the present disclosure includes a substrate, a first chip arranged on the substrate, a plurality of spacers arranged on the substrate around the first chip, and above the first chip. A second chip that is arranged and has a larger size than the first chip, an adhesive piece that bonds a plurality of spacers to the second chip, a first chip, a spacer, and a second chip. And a sealing material that seals the adhesive chip, and the adhesive piece is in contact with the upper surface of the first chip. The first chip is, for example, a controller chip.
　上記半導体装置は、本開示に係る製造方法によって製造することができる。本開示に係る半導体装置は、接着剤片が第一のチップの上面に接しているため、過度に厚くなく且つ封止材の充填性に優れている。 The above semiconductor device can be manufactured by the manufacturing method according to the present disclosure. In the semiconductor device according to the present disclosure, since the adhesive piece is in contact with the upper surface of the first chip, it is not excessively thick and is excellent in the filling property of the sealing material.
　本開示は、上記半導体装置の製造に使用される構造体を提供する。第一の態様に係る構造体は、基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数のスペーサーとを備え、スペーサーの上面の高さと、第一のチップの上面の高さとが一致している。第二の態様に係る構造体は、基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数のスペーサーとを備え、スペーサーの上面が第一のチップの上面よりも高く、スペーサーは押し潰されることによって、スペーサーの上面の高さが第一のチップの上面の高さと一致する材料を含む。 The present disclosure provides a structure used for manufacturing the semiconductor device. The structure according to the first aspect includes a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip, and the upper surface of the spacer And the height of the upper surface of the first chip match. A structure according to a second aspect includes a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip, and the upper surface of the spacer Is higher than the upper surface of the first chip, and the spacer is crushed, so that the spacer includes a material whose upper surface height matches the upper surface height of the first chip.
　本開示に係る構造体は、第二のチップを更に備えた態様であってもよい。この態様の構造体は、基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数のスペーサーと、第一のチップの上方に配置されており、第一のチップよりもサイズが大きい第二のチップと、複数のスペーサーと第二のチップとを接着している接着剤片とを備え、接着剤片が第一のチップの上面に接している。 The structure according to the present disclosure may be a mode further including a second chip. The structure according to this aspect includes a substrate, a first chip arranged on the substrate, a plurality of spacers arranged on the substrate around the first chip, and arranged above the first chip. And a second chip having a size larger than that of the first chip, and an adhesive piece adhering a plurality of spacers to the second chip, the adhesive piece being an upper surface of the first chip. Touches.
　本開示によれば、第一のチップが基板上に搭載され且つ第一のチップの上方に第二のチップが配置された構成の半導体装置の製造方法であって半導体装置が過度に厚くなることを抑制できるとともに、第一のチップ及び第二のチップを封止材で封止する作業を容易に実施することができる製造方法が提供される。また、本開示によれば、過度に厚くなく且つ封止材の充填性に優れた半導体装置及びこの半導体装置の製造に使用される構造体が提供される。 According to the present disclosure, there is provided a method of manufacturing a semiconductor device having a configuration in which a first chip is mounted on a substrate and a second chip is arranged above the first chip, and the semiconductor device is excessively thick. There is provided a manufacturing method capable of suppressing the above-mentioned problem and easily carrying out the work of sealing the first chip and the second chip with a sealing material. Further, according to the present disclosure, there is provided a semiconductor device which is not excessively thick and has an excellent filling property with a sealing material, and a structure used for manufacturing the semiconductor device.
図１は本開示に係る半導体装置の第一実施形態を模式的に示す断面図である。FIG. 1 is a sectional view schematically showing a first embodiment of a semiconductor device according to the present disclosure. 図２（ａ）及び図２（ｂ）は第一のチップと複数のダミーチップとの位置関係の例を模式的に示す平面図である。2A and 2B are plan views schematically showing an example of the positional relationship between the first chip and the plurality of dummy chips. 図３（ａ）～図３（ｅ）は、ダミーチップを製造する過程の一例を模式的に示す断面図である。3A to 3E are sectional views schematically showing an example of a process of manufacturing a dummy chip. 図４は本開示に係る半導体装置の製造に使用される構造体の第一実施形態を模式的に示す断面図である。FIG. 4 is a cross-sectional view schematically showing the first embodiment of the structure used for manufacturing the semiconductor device according to the present disclosure. 図５は接着剤片付きチップの一例を模式的に示す断面図である。FIG. 5: is sectional drawing which shows an example of the chip | tip with an adhesive agent piece typically. 図６は図４に示す構造体に、図５に示す接着剤片付きチップを圧着させた状態を模式的に示す断面図である。FIG. 6 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded to the structure shown in FIG. 図７は本開示に係る半導体装置の製造に使用される構造体の他の実施形態を模式的に示す断面図である。FIG. 7 is a sectional view schematically showing another embodiment of a structure used for manufacturing a semiconductor device according to the present disclosure. 図８は図７に示す構造体に、図５に示す接着剤片付きチップを圧着させた状態を模式的に示す断面図である。8 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded to the structure shown in FIG.
　以下、図面を適宜参照しながら、本開示の実施形態について説明する。以下の説明では、同一又は相当部分には同一符号を付し、重複する説明は省略する。また、上下左右等の位置関係は、特に断らない限り、図面に示す位置関係に基づくものとする。更に、図面の寸法比率は図示の比率に限られるものではない。なお、本明細書における「（メタ）アクリル」の記載は、「アクリル」及びそれに対応する「メタクリル」を意味する。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings as appropriate. In the following description, the same or corresponding parts will be denoted by the same reference symbols, without redundant description. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios. In addition, the description of "(meth) acryl" in this specification means "acryl" and its corresponding "methacryl."
＜第一実施形態＞
（半導体装置）
　図１は本実施形態に係る半導体装置を模式的に示す断面図である。この図に示す半導体装置１００は、基板１０と、基板１０の表面上に配置されたチップＳ１（第一のチップ）と、基板１０の表面上であってチップＳ１の周囲に配置された二つのダミーチップＤ（スペーサー）と、チップＳ１の上方に配置されたチップＳ２（第二のチップ）と、チップＳ２上に積層されたチップＳ３，Ｓ４と、基板１０の表面上の電極（不図示）とチップＳ２，Ｓ３，Ｓ４とをそれぞれ電気的に接続するワイヤｗと、チップＳ１，Ｓ２，Ｓ３，Ｓ４、ダミーチップＤ及びワイヤｗを封止している封止材５０とを備える。チップＳ１の上面及び複数のダミーチップＤの上面と、チップＳ２との間には接着剤片の硬化物Ｓｃが配置されている。半導体装置１００において、チップＳ１の上面の高さと、ダミーチップＤの上面の高さとが一致している。つまり、硬化物Ｓｃは、チップＳ１の上面及びダミーチップＤの上面に接している。 <First embodiment>
(Semiconductor device)
FIG. 1 is a sectional view schematically showing the semiconductor device according to the present embodiment. The semiconductor device 100 shown in this figure includes a substrate 10, a chip S1 (first chip) arranged on the surface of the substrate 10, and two chips S1 arranged on the surface of the substrate 10 and around the chip S1. Dummy chip D (spacer), chip S2 (second chip) arranged above chip S1, chips S3 and S4 stacked on chip S2, and electrodes (not shown) on the surface of substrate 10. And a wire w for electrically connecting the chips S2, S3, S4 to each other, and a sealing material 50 for sealing the chips S1, S2, S3, S4, the dummy chip D and the wire w. A cured product Sc of the adhesive piece is arranged between the upper surface of the chip S1 and the upper surfaces of the plurality of dummy chips D and the chip S2. In the semiconductor device 100, the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D match. That is, the cured product Sc is in contact with the upper surface of the chip S1 and the upper surface of the dummy chip D.
　基板１０は、有機基板であってもよく、リードフレーム等の金属基板であってもよい。基板１０は、半導体装置１００の反りを抑制する観点から、基板１０の厚さは、例えば、９０～３００μｍであり、９０～２１０μｍであってもよい。 The substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing the warpage of the semiconductor device 100, the substrate 10 has a thickness of, for example, 90 to 300 μm, or may be 90 to 210 μm.
　チップＳ１は、例えば、コントローラーチップであり、フリップチップ接続によって基板１０に搭載されている。平面視におけるチップＳ１の形状は、例えば矩形（正方形又は長方形）である。チップＳ１の一辺の長さは、例えば、５ｍｍ以下であり、２～５ｍｍ又は１～５ｍｍであってもよい。チップＳ１の厚さは、例えば、１０～１５０μｍであり、２０～１００μｍであってもよい。 The chip S1 is, for example, a controller chip, and is mounted on the substrate 10 by flip chip connection. The shape of the chip S1 in a plan view is, for example, a rectangle (square or rectangle). The length of one side of the chip S1 is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm. The thickness of the chip S1 is, for example, 10 to 150 μm, and may be 20 to 100 μm.
　チップＳ２は、例えば、メモリチップであり、接着剤片の硬化物Ｓｃを介してチップＳ１及びダミーチップＤの上に接着されている。平面視でチップＳ２は、チップＳ１よりも大きいサイズを有する。平面視におけるチップＳ２の形状は、例えば矩形（正方形又は長方形）である。チップＳ２の一辺の長さは、例えば、２０ｍｍ以下であり、４～２０ｍｍ又は４～１２ｍｍであってもよい。チップＳ２の厚さは、例えば、１０～１７０μｍであり、２０～１２０μｍであってもよい。なお、チップＳ３，Ｓ４も、例えば、メモリチップであり、接着剤片の硬化物Ｓｃを介してチップＳ２の上に接着されている。チップＳ３，Ｓ４の一辺の長さは、チップＳ２と同様であればよく、チップＳ３，Ｓ４の厚さもチップＳ２と同様であればよい。 The chip S2 is, for example, a memory chip, and is bonded onto the chip S1 and the dummy chip D via the cured product Sc of the adhesive piece. The chip S2 has a larger size than the chip S1 in a plan view. The shape of the chip S2 in a plan view is, for example, a rectangle (square or rectangle). The length of one side of the chip S2 is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm. The thickness of the chip S2 is, for example, 10 to 170 μm, and may be 20 to 120 μm. The chips S3 and S4 are also memory chips, for example, and are bonded onto the chip S2 via the cured product Sc of the adhesive pieces. The length of one side of the chips S3, S4 may be the same as that of the chip S2, and the thickness of the chips S3, S4 may be the same as that of the chip S2.
　ダミーチップＤは、チップＳ１の周囲に空間を形成するスペーサーの役割を果たす。ダミーチップＤは、チップＤ１と、チップＤ１の一方の面に設けられた接着剤片Ｄａとによって構成されている。図２（ａ）に示すように、チップＳ１の両側の離れた位置に、二つのダミーチップＤ（形状：長方形）を配置してもよいし、図２（ｂ）に示すように、チップＳ１の角に対応する位置にそれぞれ一つのダミーチップＤ（形状：正方形、計４個）を配置してもよい。平面視におけるチップＤ１の一辺の長さは、例えば、２０ｍｍ以下であり、１～２０ｍｍ又は１～１２ｍｍであってもよい。チップＤ１の厚さは、例えば、３０～１５０μｍであり、８０～１２０μｍであってもよい。 The dummy chip D plays a role of a spacer that forms a space around the chip S1. The dummy chip D is composed of a chip D1 and an adhesive piece Da provided on one surface of the chip D1. As shown in FIG. 2A, two dummy chips D (shape: rectangle) may be arranged at separate positions on both sides of the chip S1, or as shown in FIG. One dummy chip D (shape: square, total of four) may be arranged at a position corresponding to each corner of. The length of one side of the chip D1 in a plan view is, for example, 20 mm or less, and may be 1 to 20 mm or 1 to 12 mm. The thickness of the chip D1 is, for example, 30 to 150 μm, and may be 80 to 120 μm.
　上述のとおり、ダミーチップＤの上面の高さと、チップＳ１の上面の高さとが一致している。例えば、接着剤片Ｄａの厚さを調整することで、フリップチップ接続されているチップＳ１の上面の位置とダミーチップＤの上面の位置を一致させることができる。 As described above, the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 match. For example, by adjusting the thickness of the adhesive piece Da, the position of the upper surface of the chip S1 that is flip-chip connected and the position of the upper surface of the dummy chip D can be matched.
　図３（ａ）～図３（ｅ）を参照しながら、接着剤片付きチップの一態様であるダミーチップＤの作製方法の一例について説明する。まず、ダイシングダイボンディング一体型フィルム８（以下、場合により「フィルム８」という。）を準備し、これを所定の装置（不図示）に配置する。フィルム８は、基材フィルム１と粘着剤層２と接着剤層３Ａとをこの順序で備える。基材フィルム１は、例えば、ポリエチレンテレフタレートフィルム（ＰＥＴフィルム）である。粘着剤層２は、紫外線が照射されることによって粘着性が低下する性質を有する。接着剤層３Ａは、熱硬化性樹脂組成物からなる。 An example of a method of manufacturing the dummy chip D, which is one mode of the chip with the adhesive piece, will be described with reference to FIGS. 3 (a) to 3 (e). First, a dicing die bonding integrated film 8 (hereinafter, referred to as “film 8” in some cases) is prepared and placed in a predetermined device (not shown). The film 8 includes the base film 1, the pressure-sensitive adhesive layer 2, and the adhesive layer 3A in this order. The base film 1 is, for example, a polyethylene terephthalate film (PET film). The pressure-sensitive adhesive layer 2 has a property that its adhesiveness is lowered by being irradiated with ultraviolet rays. The adhesive layer 3A is made of a thermosetting resin composition.
　図３（ａ）及び図３（ｂ）に示すように、ウェハＷの一方の面に接着剤層３Ａが接するようにフィルム８を貼り付ける。ウェハＷは、単結晶シリコンであってもよいし、多結晶シリコン、各種セラミック、ガリウム砒素等の化合物半導体であってもよい。なお、ダミーチップＤを作製する場合、ウェハＷは半導体ではなくてもよく、例えば、ガラス基板であってもよい。 As shown in FIGS. 3 (a) and 3 (b), the film 8 is attached so that the adhesive layer 3A is in contact with one surface of the wafer W. The wafer W may be single crystal silicon, or may be polycrystal silicon, various ceramics, or a compound semiconductor such as gallium arsenide. When the dummy chip D is manufactured, the wafer W does not have to be a semiconductor and may be, for example, a glass substrate.
　ウェハＷ及び接着剤層３Ａをダイシングブレードによって切断する（図３（ｃ）参照）。ウェハＷがダイシングによって個片化されることでチップＤ１となる。接着剤層３Ａがダイシングによって個片化されることで接着剤片Ｄａとなる。その後、図３（ｄ）に示すように、粘着剤層２に対して紫外線を照射することにより、粘着剤層２と接着剤層３Ａとの間の粘着力を低下させる。紫外線照射後、図３（ｅ）に示されるように、基材フィルム１をエキスパンドすることで、ダミーチップＤを互いに離間させる。ダミーチップＤをニードル４２で突き上げることによって粘着剤層２からダミーチップＤを剥離させるとともに、吸引コレット４４で吸引してダミーチップＤをピックアップする。 The wafer W and the adhesive layer 3A are cut with a dicing blade (see FIG. 3 (c)). The wafer W is diced into individual pieces to form the chips D1. The adhesive layer 3A is diced into individual pieces to form the adhesive pieces Da. After that, as shown in FIG. 3D, the adhesive force between the adhesive layer 2 and the adhesive layer 3A is reduced by irradiating the adhesive layer 2 with ultraviolet rays. After the ultraviolet irradiation, as shown in FIG. 3E, the dummy film D is separated from each other by expanding the base film 1. The dummy chip D is peeled from the adhesive layer 2 by pushing up the dummy chip D with the needle 42, and the dummy chip D is picked up by suction with the suction collet 44.
（半導体装置の製造方法）
　図４～図６を参照しながら、半導体装置１００の製造方法について説明する。半導体装置１００の製造方法は、以下の（Ａ）～（Ｄ）の工程を含む。
（Ａ）基板１０と、基板１０上に配置されたチップＳ１と、基板１０上であってチップＳ１の周囲に配置された複数のダミーチップＤとを備える構造体３０Ａを準備する工程（図４参照）。
（Ｂ）チップＳ２と、チップＳ２の一方の面に設けられた接着剤片Ｓａとを備える接着剤片付きチップＳ２ａを準備する工程（図５参照）。
（Ｃ）複数のダミーチップＤの上面及びチップＳ１の上面に接着剤片Ｓａが接するように、チップＳ１の上方にチップＳ２を配置する工程（図６参照）。
（Ｄ）チップＳ１，Ｓ２，Ｓ３，Ｓ４及びダミーチップＤ等を封止する工程。 (Method of manufacturing semiconductor device)
A method of manufacturing the semiconductor device 100 will be described with reference to FIGS. The method for manufacturing the semiconductor device 100 includes the following steps (A) to (D).
(A) A step of preparing a structure 30A including a substrate 10, a chip S1 arranged on the substrate 10, and a plurality of dummy chips D arranged on the substrate 10 around the chip S1 (FIG. 4). reference).
(B) A step of preparing a chip S2a with an adhesive piece, which includes the chip S2 and an adhesive piece Sa provided on one surface of the chip S2 (see FIG. 5).
(C) A step of disposing the chip S2 above the chip S1 such that the adhesive pieces Sa are in contact with the upper surfaces of the plurality of dummy chips D and the upper surface of the chip S1 (see FIG. 6).
(D) A step of sealing the chips S1, S2, S3, S4, the dummy chip D, and the like.
［（Ａ）工程］
　（Ａ）工程は、図４に示す構造体３０Ａを準備する工程である。構造体３０Ａは、基板１０と、その表面上に配置されたチップＳ１及び複数のダミーチップＤとを備え、チップＳ１の上面の高さと、ダミーチップＤの上面の高さとが一致している。例えば、まず、フリップチップ接続によってチップＳ１を基板１０上の所定の位置に搭載し、その後、ダミーチップＤを所定の位置に圧着すればよい。この圧着処理は、例えば、８０～１８０℃、０．０１～０．５０ＭＰａの条件で、０．５～３．０秒間にわたって実施することが好ましい。ダミーチップＤに加える押圧力を調整することで、ダミーチップＤの上面の高さを調整することができる。ダミーチップＤの接着剤片Ｄａは（Ａ）工程の時点で完全に硬化していてもよく、この時点では完全には硬化しておらず、（Ｃ）工程の時点で完全に硬化させてよい。 [Step (A)]
The step (A) is a step of preparing the structure 30A shown in FIG. The structure 30A includes a substrate 10, a chip S1 and a plurality of dummy chips D arranged on the surface thereof, and the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D are the same. For example, first, the chip S1 may be mounted at a predetermined position on the substrate 10 by flip chip connection, and then the dummy chip D may be pressure-bonded to the predetermined position. This pressure bonding treatment is preferably carried out, for example, under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds. By adjusting the pressing force applied to the dummy chip D, the height of the upper surface of the dummy chip D can be adjusted. The adhesive piece Da of the dummy chip D may be completely cured at the time of the (A) process, may not be completely cured at this time, and may be completely cured at the time of the (C) process. ..
［（Ｂ）工程］
　（Ｂ）工程は、図５に示す接着剤片付きチップＳ２ａを準備する工程である。接着剤片付きチップＳ２ａは、チップＳ２と、その一方の表面に設けられた接着剤片Ｓａとを備える。接着剤片付きチップＳ２ａは、例えば、ダイシングダイボンディング一体型フィルムを使用し、ダイシング工程を経て得ることができる（図３（ａ）～図３（ｅ）参照）。 [Step (B)]
The step (B) is a step of preparing the chip S2a with the adhesive piece shown in FIG. The chip with adhesive piece S2a includes the chip S2 and the adhesive piece Sa provided on one surface thereof. The chip S2a with the adhesive piece can be obtained through a dicing process using, for example, a dicing die bonding integral type film (see FIGS. 3A to 3E).
［（Ｃ）工程］
　（Ｃ）工程は、複数のダミーチップＤの上面及びチップＳ１の上面に接着剤片Ｓａが接するように、チップＳ１の上方に接着剤片付きチップＳ２ａを配置する工程である。具体的には、ダミーチップＤの上面及びチップＳ１の上面に接着剤片Ｓａを介してチップＳ２を圧着する。この圧着処理は、例えば、８０～１８０℃、０．０１～０．５０ＭＰａの条件で、０．５～３．０秒間にわたって実施することが好ましい。次に、加熱によって接着剤片Ｓａを硬化させる。この硬化処理は、例えば、６０～１７５℃、０．０１～１．０ＭＰａの条件で、５分間以上にわたって実施することが好ましい。これにより、接着剤片Ｓａが硬化物Ｓｃとなる。 [Step (C)]
The step (C) is a step of arranging the chip S2a with the adhesive piece above the chip S1 so that the adhesive piece Sa contacts the upper surfaces of the plurality of dummy chips D and the upper surface of the chip S1. Specifically, the chip S2 is pressure-bonded to the upper surface of the dummy chip D and the upper surface of the chip S1 via the adhesive piece Sa. This pressure bonding treatment is preferably carried out, for example, under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds. Next, the adhesive piece Sa is cured by heating. This curing treatment is preferably carried out, for example, under conditions of 60 to 175 ° C. and 0.01 to 1.0 MPa for 5 minutes or more. As a result, the adhesive piece Sa becomes the cured product Sc.
　本実施形態に係る構造体３０Ａにおいては、上述のとおり、チップＳ１の上面の高さと、ダミーチップＤの上面の高さとが一致している。このため、接着剤片ＳａはダミーチップＤの上面及びチップＳ１の上面の両方に接している。図６は（Ｃ）工程を経て得られる構造体を模式的に示す断面図である。この図に示す構造体４０は、硬化物ＳｃとチップＳ１の間に隙間がないため、（Ｄ）工程において封止材の優れた充填性を達成できる。 In the structure 30A according to the present embodiment, as described above, the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D match. Therefore, the adhesive piece Sa is in contact with both the upper surface of the dummy chip D and the upper surface of the chip S1. FIG. 6 is a sectional view schematically showing a structure obtained through the step (C). In the structure 40 shown in this figure, since there is no gap between the cured product Sc and the chip S1, excellent filling properties of the encapsulant can be achieved in the step (D).
　（Ｃ）工程後であって（Ｄ）工程前に、チップＳ２の上に接着剤片を介してチップＳ３を配置し、更に、チップＳ３の上に接着剤片を介してチップＳ４を配置する。接着剤片は上述の接着剤片Ｓａと同様の熱硬化性樹脂組成物であればよく、加熱硬化によって硬化物Ｓｃとなる（図１参照）。その後、チップＳ２，Ｓ３，Ｓ４と基板１０とをワイヤｗで電気的にそれぞれ接続する。なお、チップＳ１の上方に積層するチップの数は本実施形態の三つに限定されず、適宜設定すればよい。 After the step (C) and before the step (D), the chip S3 is arranged on the chip S2 via the adhesive piece, and further, the chip S4 is arranged on the chip S3 via the adhesive piece. .. The adhesive piece may be a thermosetting resin composition similar to the adhesive piece Sa described above, and becomes a cured product Sc by heat curing (see FIG. 1). After that, the chips S2, S3, S4 and the substrate 10 are electrically connected by the wires w. Note that the number of chips stacked above the chip S1 is not limited to three in this embodiment, and may be set appropriately.
［（Ｄ）工程］
　（Ｄ）工程は、チップＳ１，Ｓ２，Ｓ３，Ｓ４、ダミーチップＤ及びワイヤｗを封止材５０によって封止する工程である。この工程を経て図１に示す半導体装置１００が完成する。 [Step (D)]
The step (D) is a step of sealing the chips S1, S2, S3, S4, the dummy chip D and the wire w with the sealing material 50. Through these steps, the semiconductor device 100 shown in FIG. 1 is completed.
（熱硬化性樹脂組成物）
　接着剤片Ｄａ及び接着剤片Ｓａを構成する熱硬化性樹脂組成物について説明する。本実施形態に係る熱硬化性樹脂組成物は、半硬化（Ｂステージ）状態を経て、その後の硬化処理によって完全硬化物（Ｃステージ）状態となり得るものである。熱硬化性樹脂組成物は、エポキシ樹脂と、硬化剤と、エラストマとを含み、必要に応じて、無機フィラー及び硬化促進剤等を更に含む。 (Thermosetting resin composition)
The thermosetting resin composition constituting the adhesive piece Da and the adhesive piece Sa will be described. The thermosetting resin composition according to the present embodiment is capable of undergoing a semi-cured (B stage) state and then a completely cured (C stage) state by a subsequent curing treatment. The thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler, a curing accelerator, and the like, if necessary.
［エポキシ樹脂］
　エポキシ樹脂は、硬化して接着作用を有するものであれば特に限定されない。ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂等の二官能エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂などを使用することができる。また、多官能エポキシ樹脂、グリシジルアミン型エポキシ樹脂、複素環含有エポキシ樹脂または脂環式エポキシ樹脂など、一般に知られているものを適用することができる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Epoxy resin]
The epoxy resin is not particularly limited as long as it cures and has an adhesive action. Bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin and bisphenol S type epoxy resin, and novolac type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin can be used. Further, generally known ones such as polyfunctional epoxy resin, glycidylamine type epoxy resin, heterocycle-containing epoxy resin or alicyclic epoxy resin can be applied. These may be used alone or in combination of two or more.
［硬化剤］
　硬化剤として、例えば、フェノール樹脂、エステル化合物、芳香族アミン、脂肪族アミン及び酸無水物が挙げられる。これらのうち、反応性及び経時安定性の観点から、フェノール樹脂が好ましい。フェノール樹脂の市販品として、例えば、ＤＩＣ（株）製のフェノライトＫＡ及びＴＤシリーズ、三井化学株式会社製のミレックスＸＬＣ－シリーズとＸＬシリーズ（例えば、ミレックスＸＬＣ－ＬＬ）、エア・ウォーター（株）製のＨＥシリーズ（例えば、ＨＥ１００Ｃ－３０）、明和化成株式会社製のＭＥＨＣ－７８００シリーズ（例えばＭＥＨＣ－７８００－４Ｓ）が挙げられる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Curing agent]
Examples of the curing agent include phenolic resins, ester compounds, aromatic amines, aliphatic amines, and acid anhydrides. Of these, a phenol resin is preferable from the viewpoint of reactivity and stability over time. Commercially available phenolic resins include, for example, Phenolite KA and TD series manufactured by DIC Corporation, Mirex XLC-series and XL series manufactured by Mitsui Chemicals, Inc. (for example, MIlex XLC-LL), Air Water Co., Ltd. HE series (for example, HE100C-30) manufactured by Meiwa Kasei Co., Ltd. and MEHC-7800 series (for example, MEHC-7800-4S) manufactured by Meiwa Kasei Co., Ltd. may be mentioned. These may be used alone or in combination of two or more.
　エポキシ樹脂とフェノール樹脂の配合量は、硬化性の観点から、それぞれエポキシ当量と水酸基当量の当量比が、好ましくは０．３０／０．７０～０．７０／０．３０、より好ましくは０．３５／０．６５～０．６５／０．３５、更に好ましくは０．４０／０．６０～０．６０／０．４０、特に好ましくは０．４５／０．５５～０．５５／０．４５である。配合比が上記範囲内であることで、硬化性及び流動性の両方を十分に高水準に達成しやすい。 From the viewpoint of curability, the mixing ratio of the epoxy resin and the phenol resin is such that the equivalent ratio of the epoxy equivalent and the hydroxyl equivalent is preferably 0.30 / 0.70 to 0.70 / 0.30, and more preferably 0. 35 / 0.65 to 0.65 / 0.35, more preferably 0.40 / 0.60 to 0.60 / 0.40, and particularly preferably 0.45 / 0.55 to 0.55 / 0. 45. When the compounding ratio is within the above range, both curability and fluidity can be easily achieved at sufficiently high levels.
［エラストマ］
　エラストマとして、例えば、アクリル樹脂、ポリエステル樹脂、ポリアミド樹脂、ポリイミド樹脂、シリコーン樹脂、ポリブタジエン、アクリロニトリル、エポキシ変性ポリブタジエン、無水マレイン酸変性ポリブタジエン、フェノール変性ポリブタジエン及びカルボキシ変性アクリロニトリルが挙げられる。 [Elastomer]
Examples of the elastomer include acrylic resin, polyester resin, polyamide resin, polyimide resin, silicone resin, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, maleic anhydride-modified polybutadiene, phenol-modified polybutadiene, and carboxy-modified acrylonitrile.
　溶剤への溶解性及び流動性の観点から、エラストマとしてアクリル系樹脂が好ましく、更に、グリシジルアクリレート又はグリシジルメタクリレート等のエポキシ基又はグリシジル基を架橋性官能基として有する官能性モノマーを重合して得たエポキシ基含有（メタ）アクリル共重合体等のアクリル系樹脂がより好ましい。アクリル系樹脂のなかでもエポキシ基含有（メタ）アクリル酸エステル共重合体及びエポキシ基含有アクリルゴムが好ましく、エポキシ基含有アクリルゴムがより好ましい。エポキシ基含有アクリルゴムは、アクリル酸エステルを主成分とし、主として、ブチルアクリレートとアクリロニトリル等の共重合体、エチルアクリレートとアクリロニトリル等の共重合体などからなる、エポキシ基を有するゴムである。なお、アクリル系樹脂は、エポキシ基だけでなく、アルコール性又はフェノール性水酸基、カルボキシル基等の架橋性官能基を有していてもよい。 From the viewpoint of solubility and fluidity in a solvent, an acrylic resin is preferable as the elastomer, and further obtained by polymerizing a functional monomer having an epoxy group or a glycidyl group such as glycidyl acrylate or glycidyl methacrylate as a crosslinkable functional group. An acrylic resin such as an epoxy group-containing (meth) acrylic copolymer is more preferable. Among the acrylic resins, an epoxy group-containing (meth) acrylic acid ester copolymer and an epoxy group-containing acrylic rubber are preferable, and an epoxy group-containing acrylic rubber is more preferable. The epoxy group-containing acrylic rubber is a rubber having an epoxy group, which is mainly composed of an acrylic ester and is mainly composed of a copolymer such as butyl acrylate and acrylonitrile or a copolymer such as ethyl acrylate and acrylonitrile. The acrylic resin may have a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group and a carboxyl group, as well as an epoxy group.
　アクリル樹脂の市販品としては、ナガセケムテック（株）製のＳＧ－７０Ｌ、ＳＧ－７０８－６、ＷＳ－０２３　ＥＫ３０、ＳＧ－２８０　ＥＫ２３、ＳＧ－Ｐ３溶剤変更品（商品名、アクリルゴム、重量平均分子量：８０万、Ｔｇ：１２℃、溶剤はシクロヘキサノン）等が挙げられる。 Commercially available acrylic resins are SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, SG-P3 manufactured by Nagase Chemtech Co., Ltd. (product name, acrylic rubber, weight) Average molecular weight: 800,000, Tg: 12 ° C., solvent is cyclohexanone, etc.
　アクリル樹脂のガラス転移温度（Ｔｇ）は－５０～５０℃であることが好ましく、－３０～３０℃であることがより好ましい。アクリル樹脂の重量平均分子量（Ｍｗ）は、１０万～３００万であることが好ましく、５０万～２００万であることがより好ましい。Ｍｗがこの範囲のアクリル樹脂を熱硬化性樹脂組成物に配合することで、熱硬化性樹脂組成物をフィルム状に形成しやすく、フィルム状での強度、可撓性、タック性を適切に制御しやすい。これに加え、リフロー性及び埋込性の両方が向上する傾向にある。ここで、Ｍｗは、ゲルパーミエーションクロマトグラフィー（ＧＰＣ）で測定し、標準ポリスチレンによる検量線を用いて換算した値を意味する。なお、分子量分布の狭いアクリル樹脂を用いることにより、埋込性に優れ且つ高弾性の接着剤片を形成できる傾向にある。 The glass transition temperature (Tg) of the acrylic resin is preferably −50 to 50 ° C., more preferably −30 to 30 ° C. The weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3,000,000, more preferably 500,000 to 2,000,000. By mixing an acrylic resin having an Mw in this range with a thermosetting resin composition, the thermosetting resin composition can be easily formed into a film shape, and the strength, flexibility, and tackiness of the film shape can be appropriately controlled. It's easy to do. In addition to this, both the reflow property and the embedding property tend to be improved. Here, Mw means a value measured by gel permeation chromatography (GPC) and converted using a calibration curve based on standard polystyrene. The use of an acrylic resin having a narrow molecular weight distribution tends to form an adhesive piece having excellent embedding properties and high elasticity.
　熱硬化性樹脂組成物に含まれるアクリル樹脂の量は、エポキシ樹脂及びエポキシ樹脂硬化剤の合計１００質量部に対して２０～２００質量部であることが好ましく、３０～１００質量部であることがより好ましい。この範囲にあると、成形時の流動性の制御、高温での取り扱い性及び埋込性をより一層良好にすることができる。 The amount of acrylic resin contained in the thermosetting resin composition is preferably 20 to 200 parts by mass, and more preferably 30 to 100 parts by mass, based on 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent. More preferable. Within this range, control of fluidity during molding, handling at high temperature, and embedding property can be further improved.
［無機フィラー］
　無機フィラーとして、例えば、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、酸化アルミニウム、窒化アルミニウム、ホウ酸アルミウィスカ、窒化ホウ素及び結晶性シリカ、非晶性シリカが挙げられる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Inorganic filler]
Examples of the inorganic filler include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride and crystallinity. Examples thereof include silica and amorphous silica. These may be used alone or in combination of two or more.
　無機フィラーの平均粒径は、接着性を向上する観点から、０．００５μｍ～１．０μｍが好ましく、０．０５～０．５μｍがより好ましい。無機フィラーの表面は、溶剤及び樹脂成分との相溶性、並びに接着強度の観点から化学修飾されていることが好ましい。表面を化学修飾する材料として適したものにシランカップリング剤が挙げられる。シランカップリング剤の官能基の種類として、例えば、ビニル基、アクリロイル基、エポキシ基、メルカプト基、アミノ基、ジアミノ基、アルコキシ基、エトキシ基が挙げられる。 The average particle size of the inorganic filler is preferably 0.005 μm to 1.0 μm, and more preferably 0.05 to 0.5 μm, from the viewpoint of improving adhesiveness. The surface of the inorganic filler is preferably chemically modified from the viewpoint of compatibility with a solvent and a resin component and adhesive strength. Suitable materials for chemically modifying the surface include silane coupling agents. Examples of the functional group of the silane coupling agent include vinyl group, acryloyl group, epoxy group, mercapto group, amino group, diamino group, alkoxy group and ethoxy group.
　熱硬化性樹脂組成物の流動性及び破断性、並びに硬化後の引張弾性率及び接着力を制御する観点から、熱硬化性樹脂組成物の樹脂成分１００質量部に対して、無機フィラーの含有量は２０～２００質量部であることが好ましく、３０～１００質量部であることがより好ましい。 From the viewpoint of controlling the fluidity and breakability of the thermosetting resin composition, and the tensile modulus and adhesive strength after curing, the content of the inorganic filler with respect to 100 parts by mass of the resin component of the thermosetting resin composition. Is preferably 20 to 200 parts by mass, more preferably 30 to 100 parts by mass.
［硬化促進剤］
　硬化促進剤として、例えば、イミダゾール類及びその誘導体、有機リン系化合物、第二級アミン類、第三級アミン類、及び第四級アンモニウム塩が挙げられる。適度な反応性の観点からイミダゾール系の化合物が好ましい。イミダゾール類としては、２－メチルイミダゾール、１－ベンジル－２－メチルイミダゾール、１－シアノエチル－２－フェニルイミダゾール、１－シアノエチルー２－メチルイミダゾール等が挙げられる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Curing accelerator]
Examples of the curing accelerator include imidazoles and their derivatives, organic phosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. Imidazole compounds are preferable from the viewpoint of appropriate reactivity. Examples of the imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole and the like. These may be used alone or in combination of two or more.
　熱硬化性樹脂組成物における硬化促進剤の含有量は、エポキシ樹脂及びエポキシ樹脂硬化剤の合計１００質量部に対して０．０４～３質量部が好ましく、０．０４～０．２質量部がより好ましい。硬化促進剤の添加量がこの範囲にあると、硬化性と信頼性を両立することができる。 The content of the curing accelerator in the thermosetting resin composition is preferably 0.04 to 3 parts by mass, and 0.04 to 0.2 parts by mass based on 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent. More preferable. When the amount of the curing accelerator added is within this range, both curability and reliability can be achieved.
＜第二実施形態＞
　上記第一実施形態においては、ダミーチップＤの上面の高さと、チップＳ１の上面の高さが一致している構造体３０Ａを（Ａ）工程で準備する形態を例示したが、ダミーチップＤの上面がチップＳ１の上面よりも高い構造体を（Ａ）工程で準備してもよい。図７に示す構造体３０Ｂは、基板１０と、基板１０上に配置されたチップＳ１と、基板１０上であってチップＳ１の周囲に配置された複数のダミーチップＤとを備え、ダミーチップＤの上面がチップＳ１の上面よりも高い。 <Second embodiment>
In the above first embodiment, the structure 30A in which the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 are the same is prepared in the step (A). A structure whose upper surface is higher than the upper surface of the chip S1 may be prepared in the step (A). The structure 30B shown in FIG. 7 includes a substrate 10, a chip S1 arranged on the substrate 10, and a plurality of dummy chips D arranged on the substrate 10 around the chip S1. Is higher than the upper surface of the chip S1.
　第一実施形態の（Ｄ）工程（封止材５０で封止する工程）の前までに、ダミーチップＤの上面の高さと、チップＳ１の上面の高さとが一致していればよく、（Ｃ）工程において、接着剤片付きチップＳ２ａでダミーチップＤの接着剤片Ｄａを押し潰すことによってダミーチップＤの高さとチップＳ１の上面の高さとを一致させればよい（図８参照）。フリップチップ接続によってチップＳ１を基板１０に搭載する場合、フリップチップの接続部の高さに５μｍ程度のばらつきが生じやすく、その結果、チップＳ１の上面の高さ位置に５μｍ程度のばらつきが生じる。このばらつきを見越してダミーチップＤの上面の位置を、接続後のチップＳ１の上面の設定位置よりも８～１２μｍ程度高めに設定しておくことで、（Ａ）工程においてダミーチップＤの上面の高さとチップＳ１の上面の高さを厳密に一致させる必要がないという利点がある。 It is sufficient that the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 match before the step (D) of the first embodiment (step of sealing with the sealing material 50). In the step C), the height of the dummy chip D and the height of the upper surface of the chip S1 may be matched by crushing the adhesive piece Da of the dummy chip D with the chip S2a having the adhesive piece (see FIG. 8). When the chip S1 is mounted on the substrate 10 by flip-chip connection, the height of the connection portion of the flip chip tends to vary by about 5 μm, and as a result, the height position of the upper surface of the chip S1 varies by about 5 μm. In consideration of this variation, by setting the position of the upper surface of the dummy chip D to be higher than the set position of the upper surface of the chip S1 after connection by about 8 to 12 μm, the upper surface of the dummy chip D in the step (A) is set. There is an advantage that the height and the height of the upper surface of the chip S1 do not have to be exactly the same.
　本実施形態においては、ダミーチップＤの接着剤片Ｄａは、接着剤片付きチップＳ２ａで押し潰される材料からなる。具体的には、ダミーチップＤの接着剤片Ｄａは、接着剤片付きチップＳ２ａの接着剤片Ｓａよりも軟らかいことが好ましい。接着剤片Ｄａを接着剤片Ｓａよりも軟らかくする手法として、例えば、接着剤片Ｄａの熱硬化性樹脂の含有量を接着剤片Ｓａよりも多くしたり、接着剤片Ｄａのエラストマ又は無機フィラーの含有量を接着剤片Ｓａよりも少なくしたりすることが挙げられる。 In the present embodiment, the adhesive piece Da of the dummy chip D is made of a material that is crushed by the adhesive piece chip S2a. Specifically, the adhesive piece Da of the dummy chip D is preferably softer than the adhesive piece Sa of the chip S2a with an adhesive piece. As a method of making the adhesive piece Da softer than the adhesive piece Sa, for example, the content of the thermosetting resin of the adhesive piece Da is made larger than that of the adhesive piece Sa, or the elastomer or the inorganic filler of the adhesive piece Da is used. The content of may be smaller than that of the adhesive piece Sa.
　ダミーチップＤの接着剤片Ｄａは、接着剤片付きチップＳａ２の接着剤片Ｓａよりも厚いことが好ましい。本実施形態において、例えば、接着剤片Ｄａの厚さは接着剤片Ｓａの厚さの１．１～８倍であり、１．２～６倍であってもよい。 The adhesive piece Da of the dummy chip D is preferably thicker than the adhesive piece Sa of the chip Sa2 with an adhesive piece. In the present embodiment, for example, the thickness of the adhesive piece Da is 1.1 to 8 times the thickness of the adhesive piece Sa, and may be 1.2 to 6 times.
　以上、本開示の実施形態について詳細に説明したが、本発明は上記実施形態に限定されるものではない。例えば、上記実施形態においては、チップＳ１をフリップチップ接続によって搭載する場合を例示したが、接着剤によってチップＳ１を基板１０に固定した後、ワイヤーボンディングによって電気的な接続を行ってもよい。 Although the embodiments of the present disclosure have been described in detail above, the present invention is not limited to the above embodiments. For example, in the above embodiment, the case where the chip S1 is mounted by flip-chip connection is illustrated, but the chip S1 may be fixed to the substrate 10 by an adhesive and then electrically connected by wire bonding.
　以下、本開示を実施例により詳細に説明するが、本発明はこれらに制限されるものではない。 Hereinafter, the present disclosure will be described in detail with reference to Examples, but the present invention is not limited thereto.
＜接着シートの作製＞
　表１に示される成分を用いて、以下の手順により、接着剤組成物のワニスＡ，Ｂを調製した。まず、後述の［エポキシ樹脂］、［硬化剤］及び［フィラー］を配合した後に、シクロヘキサノンを加えて撹拌した。その後、［エラストマ］、［硬化促進剤］及び［カップリング剤］を加えて各成分が均一になるまで撹拌することによって、接着剤組成物のワニスを得た。 <Preparation of adhesive sheet>
Varnishes A and B of the adhesive composition were prepared using the components shown in Table 1 by the following procedure. First, after mixing [epoxy resin], [curing agent] and [filler] described below, cyclohexanone was added and stirred. Then, [elastomer], [curing accelerator] and [coupling agent] were added and stirred until each component became uniform to obtain a varnish of the adhesive composition.
［エラストマ］
　アクリルゴム：ナガセケムテックス株式会社製商品名、商品名「ＨＴＲ－８６０Ｐ－３」、重量平均分子量８０万、ガラス転移点：１２℃ [Elastomer]
Acrylic rubber: product name by Nagase Chemtex Co., Ltd., product name “HTR-860P-3”, weight average molecular weight 800,000, glass transition point: 12 ° C.
［エポキシ樹脂］
　クレゾールノボラック型エポキシ樹脂：東都化成株式会社（株）製、商品名「ＹＤＣＮ－７００－１０」、エポキシ当量：２１０
　ビスフェノールＦ型エポキシ樹脂：ＤＩＣ株式会社、商品名「ＥＸＡ－８３０ＣＲＰ」、エポキシ当量：１５９ [Epoxy resin]
Cresol novolac type epoxy resin: manufactured by Tohto Kasei Co., Ltd., trade name "YDCN-700-10", epoxy equivalent: 210
Bisphenol F type epoxy resin: DIC Corporation, trade name "EXA-830CRP", epoxy equivalent: 159
［硬化剤］
　フェノール樹脂：三井化学株式会社（株）製、商品名「ミレックスＸＬＣ－ＬＬ」、軟化点：７５℃、水酸基当量１７５ [Curing agent]
Phenolic resin: manufactured by Mitsui Chemicals, Inc., trade name "Milex XLC-LL", softening point: 75 ° C, hydroxyl equivalent 175
［フィラー］
　シリカフィラー：日本アエロジル株式会社製、商品名「Ｒ９７２」、平均粒径０．５００μｍ
　シリカフィラー：アドマテックス株式会社製、商品名「ＳＣ２０５０－ＨＬＧ」、比表面積１１０ｍ／ｇ [Filler]
Silica filler: Nippon Aerosil Co., Ltd., trade name “R972”, average particle size 0.500 μm
Silica filler: manufactured by Admatechs Co., Ltd., trade name "SC2050-HLG", specific surface area 110 m / g
［硬化促進剤］
　１－シアノエチル－２－フェニルイミダゾールキュアゾール：四国化成工業株式会社（株）製、商品名「２ＰＺ－ＣＮ」 [Curing accelerator]
1-Cyanoethyl-2-phenylimidazole cure azole: Shikoku Chemicals Co., Ltd., trade name "2PZ-CN"
［カップリング剤］
　γ―メルカプトプロピルトリメトキシシラン：日本ユニカー株式会社（株）製、商品名「ＮＵＣ　Ａ－１８９」
　γ―ウレイドプロピルトリエトキシシラン：日本ユニカー株式会社（株）製、商品名「ＮＵＣ　Ａ－１１６０」 [Coupling agent]
γ-Mercaptopropyltrimethoxysilane: Nippon Unicar Co., Ltd., trade name “NUC A-189”
γ-Ureidopropyltriethoxysilane: manufactured by Nippon Unicar Co., Ltd., trade name “NUC A-1160”
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　基材フィルム（離型処理したポリエチレンテレフタレートフィルム、厚さ：３８μｍ）上にワニスＡを塗布した。基材フィルム上において１４０℃で５分間加熱乾燥させ、接着シートＡ１（厚さ２０μｍ）及び接着シートＡ２（厚さ４０μｍ）を作製した。ワニスＡの代わりにワニスＢを使用したことの他は、上記と同様にして接着シートＢ（厚さ４０μｍ）を作製した。 Varnish A was applied on a base film (polyethylene terephthalate film having a release treatment, thickness: 38 μm). The adhesive sheet A1 (thickness 20 μm) and the adhesive sheet A2 (thickness 40 μm) were produced by heating and drying at 140 ° C. for 5 minutes on the base film. An adhesive sheet B (thickness 40 μm) was produced in the same manner as above except that the varnish B was used instead of the varnish A.
＜接着シートの溶融粘度の測定＞
　回転式粘弾性測定装置（ティー・エイ・インスツルメント・ジャパン株式会社製、ＡＲＥＳ－ＲＤＡ）を用いて接着シートの溶融粘度を以下の手順で測定した。まず、接着シートから基材フィルムを剥離した後、７０℃で複数の接着剤層を貼り合わせて厚さ１６０μｍ以上の積層フィルムを得た。これを直径８ｍｍの円形に打ち抜いた後、これを二枚の治具（直径：８ｍｍ）で挟むことによって測定用試料を得た。以下の条件で測定を実施し、８０℃での値を接着シートの溶融粘度とした。接着シートＡ１，Ａ２の溶融粘度は２４０００Ｐａ・ｓであり、粘着シートＢの溶融粘度は２０００Ｐａ・ｓであった。
・周波数：１Ｈｚ
・測定開始温度：３５℃
・測定終了温度：１５０℃
・昇温速度５℃／分 <Measurement of melt viscosity of adhesive sheet>
The melt viscosity of the adhesive sheet was measured by the following procedure using a rotary viscoelasticity measuring device (ARES-RDA manufactured by TA Instruments Japan Co., Ltd.). First, after peeling the substrate film from the adhesive sheet, a plurality of adhesive layers were attached at 70 ° C. to obtain a laminated film having a thickness of 160 μm or more. This was punched into a circle having a diameter of 8 mm and then sandwiched by two jigs (diameter: 8 mm) to obtain a measurement sample. The measurement was carried out under the following conditions, and the value at 80 ° C was taken as the melt viscosity of the adhesive sheet. The adhesive sheets A1 and A2 had a melt viscosity of 24000 Pa · s, and the adhesive sheet B had a melt viscosity of 2000 Pa · s.
・ Frequency: 1 Hz
・ Measurement start temperature: 35 ° C
・ Measurement end temperature: 150 ℃
・ Raising rate 5 ℃ / min
（実施例１）
　半導体ウェハ（厚さ：９０μｍ）に、接着シートＡ１（厚さ：２０μｍ）を貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを５．０ｍｍ×５．０ｍｍの半導体チップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１ＭＰａ／１秒で１５０℃１時間乾燥した有機基板上に熱圧着し、半導体チップ付基板を得た。 (Example 1)
The adhesive sheet A1 (thickness: 20 μm) was attached to a semiconductor wafer (thickness: 90 μm). A semiconductor wafer was diced into 5.0 mm × 5.0 mm semiconductor chips by using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto an organic substrate dried at 120 ° C./0.1 MPa / sec for 1 hour at 150 ° C. to obtain a substrate with a semiconductor chip.
　次に、半導体ウェハ（厚さ：８０μｍ）に、接着シートＢ（厚さ：４０μｍ）を貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを１．５ｍｍ×６．０ｍｍのチップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１ＭＰａ／１秒で上記半導体チップの２ｍｍスペースをあけた両横の有機基板上に上記チップをダミーチップとして熱圧着した。 Next, the adhesive sheet B (thickness: 40 μm) was attached to the semiconductor wafer (thickness: 80 μm). The semiconductor wafer was diced into chips of 1.5 mm × 6.0 mm using a dicer (DFD-6361 manufactured by DISCO). Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) at 120 ° C./0.1 MPa / 1 second, thermocompression bonding the above chips as dummy chips on the organic substrates on both sides with a space of 2 mm. did.
　次に、半導体ウェハ（厚さ：５０μｍ）に、ＨＲ－９００Ｔ－２０－Ｎ５０（日立化成（株）製、接着剤層の厚さ：２０μｍ）をウエハマウンター（ＤＩＳＣＯ製ＤＦＭ－２８００）で７０℃／（１０ｍｍ／秒）で貼り付けた。その後、ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを６．０ｍｍ×１２．０ｍｍのチップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１００～１２０℃／０．０５～０．２０ＭＰａ／０．５～２．０秒で半導体チップ及び二つのダミーチップ上に熱圧着した。その後、７ｋｇの加圧雰囲気下で１５０℃／１時間加熱する条件により接着剤を硬化させた。これにより、基板と、二つのダミーチップと、二つの半導体チップとを備える構造体を得た。 Next, HR-900T-20-N50 (manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness: 20 μm) was applied to a semiconductor wafer (thickness: 50 μm) at 70 ° C. with a wafer mounter (DISCO DFM-2800). / (10 mm / sec) was applied. After that, the semiconductor wafer was diced into chips of 6.0 mm × 12.0 mm by using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto a semiconductor chip and two dummy chips at 100 to 120 ° C./0.05 to 0.20 MPa / 0.5 to 2.0 seconds. .. Then, the adhesive was cured under the conditions of heating at 150 ° C. for 1 hour in a pressurized atmosphere of 7 kg. As a result, a structure including the substrate, the two dummy chips, and the two semiconductor chips was obtained.
（比較例１）
　半導体ウェハ（厚さ：９０μｍ）に、接着シートＡ１（厚さ：２０μｍ）を貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを５．０ｍｍ×５．０ｍｍの半導体チップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１ＭＰａ／１秒で１５０℃１時間乾燥した有機基板上に熱圧着し、半導体チップ付基板を得た。 (Comparative Example 1)
The adhesive sheet A1 (thickness: 20 μm) was attached to a semiconductor wafer (thickness: 90 μm). A semiconductor wafer was diced into 5.0 mm × 5.0 mm semiconductor chips by using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto an organic substrate dried at 120 ° C./0.1 MPa / sec for 1 hour at 150 ° C. to obtain a substrate with a semiconductor chip.
　次に、半導体ウェハ（厚さ：９０μｍ）に、接着シートＡ２（厚さ：４０μｍ）を貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを１．５ｍｍ×６．０ｍｍのチップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１ＭＰａ／１秒で上記半導体チップの２ｍｍスペースをあけた両横の有機基板上に上記チップをダミーチップとして熱圧着した。 Next, the adhesive sheet A2 (thickness: 40 μm) was attached to the semiconductor wafer (thickness: 90 μm). The semiconductor wafer was diced into 1.5 mm × 6.0 mm chips using a dicer (DFD-6361 manufactured by DISCO). Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) at 120 ° C./0.1 MPa / 1 second, thermocompression bonding the above chips as dummy chips on the organic substrates on both sides with a space of 2 mm. did.
　次に、半導体ウェハ（厚さ：５０μｍ）に、ＨＲ－９００Ｔ－２０－Ｎ５０（日立化成（株）製、接着剤層の厚さ：２０μｍ）をウエハマウンター（ＤＩＳＣＯ製ＤＦＭ－２８００）で７０℃／（１０ｍｍ／秒）で貼り付けた。その後、ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを６．０ｍｍ×１２．０ｍｍのチップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１０ＭＰａ／１．０秒で半導体チップ及び二つのダミーチップ上に熱圧着した。その後、７ｋｇの加圧雰囲気下で１５０℃／１時間加熱する条件により接着剤を硬化させた。これにより、基板と、二つのダミーチップと、二つの半導体チップとを備える構造体を得た。 Next, HR-900T-20-N50 (manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness: 20 μm) was applied to a semiconductor wafer (thickness: 50 μm) at 70 ° C. with a wafer mounter (DISCO DFM-2800). / (10 mm / sec) was applied. After that, the semiconductor wafer was diced into chips of 6.0 mm × 12.0 mm by using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto the semiconductor chip and the two dummy chips at 120 ° C./0.10 MPa / 1.0 seconds. Then, the adhesive was cured under the conditions of heating at 150 ° C. for 1 hour in a pressurized atmosphere of 7 kg. As a result, a structure including the substrate, the two dummy chips, and the two semiconductor chips was obtained.
（比較例２）
　半導体ウェハ（厚さ：９０μｍ）に、接着シートＡ１（厚さ：２０μｍ）を貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを５．０ｍｍ×５．０ｍｍの半導体チップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１ＭＰａ／１秒で１５０℃１時間乾燥した有機基板上に熱圧着し、半導体チップ付基板を得た。 (Comparative example 2)
The adhesive sheet A1 (thickness: 20 μm) was attached to a semiconductor wafer (thickness: 90 μm). A semiconductor wafer was diced into 5.0 mm × 5.0 mm semiconductor chips by using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto an organic substrate dried at 150 ° C. for 1 hour at 120 ° C./0.1 MPa / 1 second to obtain a substrate with a semiconductor chip.
　次に、半導体ウェハ（厚さ：１１０μｍ）に、接着シートＡ１（厚さ：２０μｍ）を貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを１．５ｍｍ×６．０ｍｍのチップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１ＭＰａ／１秒で上記半導体チップの２ｍｍスペースをあけた両横の有機基板上に上記チップをダミーチップとして熱圧着した。 Next, the adhesive sheet A1 (thickness: 20 μm) was attached to the semiconductor wafer (thickness: 110 μm). The semiconductor wafer was diced into 1.5 mm × 6.0 mm chips using a dicer (DFD-6361 manufactured by DISCO). Using a flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) at 120 ° C./0.1 MPa / 1 second, thermocompression bonding the above chips as dummy chips on the organic substrates on both sides with a space of 2 mm. did.
　次に、半導体ウェハ（厚さ：５０μｍ）に、ＨＲ－９００Ｔ－２０－Ｎ５０（日立化成（株）製、接着剤層の厚さ：２０μｍ）をウエハマウンター（ＤＩＳＣＯ製ＤＦＭ－２８００）で７０℃／（１０ｍｍ／秒）で貼り付けた。ダイサー（ＤＩＳＣＯ製ＤＦＤ－６３６１）を用いて半導体ウェハを６．０ｍｍ×１２．０ｍｍのチップに個片化した。フレキシブルダイボンダ（（株）日立ハイテクインスツルメンツ製ＤＢ－８３０ＨＳＤ）にて１２０℃／０．１０ＭＰａ／１．０秒で半導体チップ及び２つのダミーチップ上に熱圧着した。その後、７ｋｇの加圧雰囲気下で１５０℃／１時間加熱する条件により接着剤を硬化させた。これにより、基板と、二つのダミーチップと、二つの半導体チップとを備える構造体を得た。 Next, a semiconductor wafer (thickness: 50 μm) was loaded with HR-900T-20-N50 (manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness: 20 μm) at 70 ° C. with a wafer mounter (DISCO DFM-2800). / (10 mm / sec) was applied. The semiconductor wafer was diced into chips of 6.0 mm × 12.0 mm using a dicer (DFD-6361 manufactured by DISCO). A flexible die bonder (DB-830HSD manufactured by Hitachi High-Tech Instruments Co., Ltd.) was thermocompression bonded onto the semiconductor chip and the two dummy chips at 120 ° C./0.10 MPa / 1.0 seconds. Then, the adhesive was cured under the conditions of heating at 150 ° C. for 1 hour in a pressurized atmosphere of 7 kg. As a result, a structure including the substrate, the two dummy chips, and the two semiconductor chips was obtained.
（半導体パッケージの作製及び評価）
　実施例及び比較例に係る上記構造体上に日立化成株式会社製の封止材（商品名ＣＥＬ－９７５０ＺＨＦ）を１７５℃／６．７５ＭＰa／１２０秒の条件でそれぞれ成型し、１７５℃で５時間の硬化処理を行ない、半導体パッケージを得た。超音波映像診断システム（インサイト（株）社製、Ｉｎｓｉｇｈｔ－３００　ＳｃａｎｎｉｎｇＡｃｏｕｓｔｉｃＭｉｃｒｏｓｃｏｐｅ：ＳＡＭ）により、半導体パッケージ内部の剥離、ボイド有無を観察した。また、得られた半導体パッケージを断面観察し、半導体チップとダミーチップの高さを確認した。 (Production and evaluation of semiconductor packages)
Encapsulating material (trade name CEL-9750ZHF) manufactured by Hitachi Chemical Co., Ltd. was molded on each of the structures according to the example and the comparative example under the conditions of 175 ° C./6.75 MPa / 120 seconds, and was molded at 175 ° C. for 5 hours. Was cured to obtain a semiconductor package. An ultrasonic image diagnostic system (Insight Co., Ltd., Insight-300 Scanning Acoustic Microscope: SAM) was used to observe peeling and voids inside the semiconductor package. The height of the semiconductor chip and the dummy chip was confirmed by observing the cross section of the obtained semiconductor package.
　半導体パッケージ内部の剥離及びボイドがなく良好なものは「Ａ」、剥離及びボイドがあるものは「Ｂ」と判断した。また、半導体チップ上面とダミーチップ上面の高さの差が１０μｍ未満であるものを「Ａ」、１０μｍ以上であるものを「Ｂ」とした。結果を表２に示す。 ㆍ We judged that there was no peeling or void inside the semiconductor package and that it was good, and that if there was peeling or void, it was “B”. The height difference between the upper surface of the semiconductor chip and the upper surface of the dummy chip is less than 10 μm, and the difference is 10 μm or more. The results are shown in Table 2.
Figure JPOXMLDOC01-appb-T000002
 
Figure JPOXMLDOC01-appb-T000002
 
　本開示によれば、第一のチップが基板上に搭載され且つ第一のチップの上方に第二のチップが配置された構成の半導体装置の製造方法であって半導体装置が過度に厚くなることを抑制できるとともに、第一のチップ及び第二のチップを封止材で封止する作業を容易に実施することができる製造方法が提供される。また、本開示によれば、過度に厚くなく且つ封止材の充填性に優れた半導体装置及びこの半導体装置の製造に使用される構造体が提供される。 According to the present disclosure, there is provided a method of manufacturing a semiconductor device having a configuration in which a first chip is mounted on a substrate and a second chip is arranged above the first chip, and the semiconductor device is excessively thick. There is provided a manufacturing method capable of suppressing the above-mentioned problem and easily carrying out the work of sealing the first chip and the second chip with a sealing material. Further, according to the present disclosure, there is provided a semiconductor device which is not excessively thick and has an excellent filling property with a sealing material, and a structure used for manufacturing the semiconductor device.
１０…基板、３０Ａ，３０Ｂ，４０…構造体、５０…封止材、１００…半導体装置、Ｄ…ダミーチップ（スペーサー）、Ｄ１…チップ、Ｄａ…接着剤片、Ｓ１…第一のチップ、Ｓ２…第二のチップ、Ｓ２ａ…接着剤片付きチップ、Ｓａ…接着剤片、Ｓｃ…硬化物（接着剤片） 10 ... Substrate, 30A, 30B, 40 ... Structure, 50 ... Sealing material, 100 ... Semiconductor device, D ... Dummy chip (spacer), D1 ... Chip, Da ... Adhesive piece, S1 ... First chip, S2 ... second chip, S2a ... chip with adhesive piece, Sa ... adhesive piece, Sc ... cured product (adhesive piece)

Claims (13)

  1. （Ａ）基板と、前記基板上に配置された第一のチップと、前記基板上であって前記第一のチップの周囲に配置された複数のスペーサーとを備える構造体を準備する工程と、
    （Ｂ）前記第一のチップよりもサイズが大きい第二のチップと、前記第二のチップの一方の面に設けられた接着剤片とを備える接着剤片付きチップを準備する工程と、
    （Ｃ）前記複数のスペーサーの上面に前記接着剤片が接するように、前記第一のチップの上方に前記第二のチップを配置する工程と、
    （Ｄ）前記第一のチップ、前記スペーサー及び前記第二のチップを封止する工程と、
    を含み、
    　（Ｄ）工程を実施する前において、前記スペーサーの上面の高さと、前記第一のチップの上面の高さとが一致している、半導体装置の製造方法。     (A) preparing a structure provided with a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip;
    (B) preparing a chip with an adhesive piece, which includes a second chip having a size larger than that of the first chip and an adhesive piece provided on one surface of the second chip;
    (C) disposing the second chip above the first chip so that the adhesive pieces come into contact with the upper surfaces of the plurality of spacers;
    (D) sealing the first chip, the spacer, and the second chip;
    Including,
    Before carrying out the step (D), a method of manufacturing a semiconductor device, wherein the height of the upper surface of the spacer and the height of the upper surface of the first chip are the same.
  2. 　前記（Ａ）工程で準備された前記構造体において、前記スペーサーの高さと、前記第一のチップの上面の高さとが一致している、請求項１に記載の製造方法。 The manufacturing method according to claim 1, wherein, in the structure prepared in the step (A), the height of the spacer and the height of the upper surface of the first chip are the same.
  3. 　前記スペーサーが、チップと、前記チップの一方の面に設けられた接着剤片とを備えるダミーチップである、請求項１又は２に記載の製造方法。 The manufacturing method according to claim 1 or 2, wherein the spacer is a dummy chip including a chip and an adhesive piece provided on one surface of the chip.
  4. 　前記（Ａ）工程で準備された前記構造体において、前記スペーサーの上面が前記第一のチップの上面よりも高く、
    　前記（Ｃ）工程において、前記接着剤片付きチップで前記スペーサーを押し潰すことによって前記スペーサーの高さと前記第一のチップの上面の高さとを一致させる、請求項１に記載の製造方法。     In the structure prepared in the step (A), the upper surface of the spacer is higher than the upper surface of the first chip,
    The manufacturing method according to claim 1, wherein in the step (C), the height of the spacer and the height of the upper surface of the first chip are matched by pressing the spacer with the chip with the adhesive piece.
  5. 　前記スペーサーが、チップと、前記チップの一方の面に設けられた接着剤片とを備えるダミーチップであり、
    　前記ダミーチップが備える前記接着剤片は、前記接着剤片付きチップが備える接着剤片よりも軟らかい、請求項４に記載の製造方法。     The spacer is a dummy chip including a chip and an adhesive piece provided on one surface of the chip,
    The manufacturing method according to claim 4, wherein the adhesive piece included in the dummy chip is softer than the adhesive piece included in the chip with the adhesive piece.
  6. 　前記ダミーチップが備える前記接着剤片は、前記接着剤片付きチップが備える接着剤片よりも厚い、請求項５に記載の製造方法。 The manufacturing method according to claim 5, wherein the adhesive piece included in the dummy chip is thicker than the adhesive piece included in the chip with the adhesive piece.
  7. 　前記第一のチップは、フリップチップ接続によって前記基板に搭載されている、請求項１～６のいずれか一項に記載の製造方法。 The manufacturing method according to any one of claims 1 to 6, wherein the first chip is mounted on the substrate by flip-chip connection.
  8. 　請求項１～７のいずれか一項に記載の半導体装置の製造方法によって製造された半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 7.
  9. 　基板と、
    　前記基板上に配置された第一のチップと、
    　前記基板上であって前記第一のチップの周囲に配置された複数のスペーサーと、
    　前記第一のチップの上方に配置されており、前記第一のチップよりもサイズが大きい第二のチップと、
    　前記複数のスペーサーと前記第二のチップとを接着している接着剤片と、
    　前記第一のチップ、前記スペーサー及び前記第二のチップを封止している封止材と、
    を備え、
    　前記接着剤片が前記第一のチップの上面に接している、半導体装置。     Board,
    A first chip disposed on the substrate,
    A plurality of spacers arranged on the substrate and around the first chip;
    A second chip, which is arranged above the first chip and has a larger size than the first chip,
    An adhesive piece that adheres the plurality of spacers and the second chip,
    A sealing material that seals the first chip, the spacer, and the second chip,
    Equipped with
    A semiconductor device, wherein the adhesive piece is in contact with the upper surface of the first chip.
  10. 　前記第一のチップは、コントローラーチップである、請求項９に記載の半導体装置。 The semiconductor device according to claim 9, wherein the first chip is a controller chip.
  11. 　半導体装置の製造に使用される構造体であって、
    　基板と、
    　前記基板上に配置された第一のチップと、
    　前記基板上であって前記第一のチップの周囲に配置された複数のスペーサーと、
    を備え、
    　前記スペーサーの上面の高さと、前記第一のチップの上面の高さとが一致している、構造体。     A structure used for manufacturing a semiconductor device,
    Board,
    A first chip disposed on the substrate,
    A plurality of spacers arranged on the substrate and around the first chip;
    Equipped with
    A structure in which the height of the upper surface of the spacer and the height of the upper surface of the first chip are the same.
  12. 　半導体装置の製造に使用される構造体であって、
    　基板と、
    　前記基板上に配置された第一のチップと、
    　前記基板上であって前記第一のチップの周囲に配置された複数のスペーサーと、
    を備え、
    　前記スペーサーの上面が前記第一のチップの上面よりも高く、
    　前記スペーサーは押し潰されることによって、前記スペーサーの上面の高さが前記第一のチップの上面の高さと一致する材料を含む、構造体。     A structure used for manufacturing a semiconductor device,
    Board,
    A first chip disposed on the substrate,
    A plurality of spacers arranged on the substrate and around the first chip;
    Equipped with
    The upper surface of the spacer is higher than the upper surface of the first chip,
    The structure includes a material in which a height of an upper surface of the spacer matches a height of an upper surface of the first chip when the spacer is crushed.
  13. 　半導体装置の製造に使用される構造体であって、
    　基板と、
    　前記基板上に配置された第一のチップと、
    　前記基板上であって前記第一のチップの周囲に配置された複数のスペーサーと、
    　前記第一のチップの上方に配置されており、前記第一のチップよりもサイズが大きい第二のチップと、
    　前記複数のスペーサーと前記第二のチップとを接着している接着剤片と、
    を備え、
    　前記接着剤片が前記第一のチップの上面に接している、構造体。     A structure used for manufacturing a semiconductor device,
    Board,
    A first chip disposed on the substrate,
    A plurality of spacers arranged on the substrate and around the first chip;
    A second chip, which is arranged above the first chip and has a larger size than the first chip,
    An adhesive piece that adheres the plurality of spacers and the second chip,
    Equipped with
    A structure in which the adhesive piece is in contact with the upper surface of the first chip.
PCT/JP2019/044761 2018-11-16 2019-11-14 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device WO2020100998A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020217017011A KR20210094555A (en) 2018-11-16 2019-11-14 Semiconductor device and method for manufacturing same, and structure used for manufacturing semiconductor device
JP2020556180A JPWO2020100998A1 (en) 2018-11-16 2019-11-14 Semiconductor devices, their manufacturing methods, and structures used in the manufacture of semiconductor devices.
CN201980074797.0A CN113039641A (en) 2018-11-16 2019-11-14 Semiconductor device, method for manufacturing same, and structure used for manufacturing semiconductor device
SG11202104932XA SG11202104932XA (en) 2018-11-16 2019-11-14 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/JP2018/042551 WO2020100308A1 (en) 2018-11-16 2018-11-16 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device
JPPCT/JP2018/042551 2018-11-16

Publications (1)

Publication Number Publication Date
WO2020100998A1 true WO2020100998A1 (en) 2020-05-22

Family

ID=70731439

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2018/042551 WO2020100308A1 (en) 2018-11-16 2018-11-16 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device
PCT/JP2019/044761 WO2020100998A1 (en) 2018-11-16 2019-11-14 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/042551 WO2020100308A1 (en) 2018-11-16 2018-11-16 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device

Country Status (6)

Country Link
JP (1) JPWO2020100998A1 (en)
KR (1) KR20210094555A (en)
CN (1) CN113039641A (en)
SG (1) SG11202104932XA (en)
TW (1) TWI814944B (en)
WO (2) WO2020100308A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202213552A (en) * 2020-07-03 2022-04-01 日商昭和電工材料股份有限公司 Semiconductor device and method for producing same
CN116210358A (en) * 2020-08-11 2023-06-02 株式会社力森诺科 Semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132753B1 (en) * 2003-11-10 2006-11-07 Amkor Technology, Inc. Stacked die assembly having semiconductor die overhanging support
JP2010147225A (en) * 2008-12-18 2010-07-01 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2011086943A (en) * 2009-10-15 2011-04-28 Samsung Electronics Co Ltd Semiconductor package, and electronic device and memory storage apparatus using the semiconductor package
US20130270717A1 (en) * 2012-04-17 2013-10-17 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101774938B1 (en) * 2011-08-31 2017-09-06 삼성전자 주식회사 Semiconductor package having supporting plate and method of forming the same
KR102012505B1 (en) * 2012-12-20 2019-08-20 에스케이하이닉스 주식회사 Stack package having token ring loop
JP2015120836A (en) 2013-12-24 2015-07-02 日東電工株式会社 Adhesive film, dicing/die-bonding film, manufacturing method of semiconductor device and semiconductor device
KR102247916B1 (en) * 2014-01-16 2021-05-04 삼성전자주식회사 Semiconductro pacakages having stepwised stacking structures
US9418974B2 (en) * 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
KR20170014746A (en) * 2015-07-31 2017-02-08 에스케이하이닉스 주식회사 Stacked package and method for fabricating the same
CN108292653B (en) * 2015-09-25 2022-11-08 英特尔公司 Method, apparatus and system for interconnecting packaged integrated circuit dies
KR102576764B1 (en) * 2016-10-28 2023-09-12 에스케이하이닉스 주식회사 Semiconductor packages of asymmetric chip stacks
TWI613772B (en) * 2017-01-25 2018-02-01 力成科技股份有限公司 Thin fan-out type multi-chip stacked package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132753B1 (en) * 2003-11-10 2006-11-07 Amkor Technology, Inc. Stacked die assembly having semiconductor die overhanging support
JP2010147225A (en) * 2008-12-18 2010-07-01 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2011086943A (en) * 2009-10-15 2011-04-28 Samsung Electronics Co Ltd Semiconductor package, and electronic device and memory storage apparatus using the semiconductor package
US20130270717A1 (en) * 2012-04-17 2013-10-17 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Also Published As

Publication number Publication date
WO2020100308A1 (en) 2020-05-22
JPWO2020100998A1 (en) 2021-09-30
CN113039641A (en) 2021-06-25
TWI814944B (en) 2023-09-11
TW202038425A (en) 2020-10-16
KR20210094555A (en) 2021-07-29
SG11202104932XA (en) 2021-06-29

Similar Documents

Publication Publication Date Title
KR102067945B1 (en) Adhesive sheet and method for manufacturing semiconductor device
WO2020100998A1 (en) Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device
JP7247733B2 (en) Manufacturing method of semiconductor device having dolmen structure
JP7136200B2 (en) Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture
WO2020218523A1 (en) Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor
WO2020218526A1 (en) Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor
JP7322897B2 (en) Adhesive film, dicing/die bonding integrated film, and method for manufacturing semiconductor package
JP7452545B2 (en) Method for manufacturing a support piece, method for manufacturing a semiconductor device, and laminated film for forming a support piece
JP7294410B2 (en) Semiconductor device having dolmen structure and manufacturing method thereof
JP7482112B2 (en) Manufacturing method of semiconductor device having dolmen structure, manufacturing method of support piece, and laminated film for forming support piece
JP7351335B2 (en) Semiconductor device having dolmen structure, method for manufacturing the same, method for manufacturing support piece, and laminated film for forming support piece
TWI844668B (en) Method for manufacturing semiconductor device having dolmen structure, method for manufacturing support sheet, and laminated film for forming support sheet
WO2020218524A1 (en) Semiconductor device having dolmen structure and method for manufacturing same, and laminated film for forming support piece and method for manufacturing same
TWI827779B (en) Chip-bonding integrated film and method for manufacturing semiconductor device
WO2023079693A1 (en) Reinforced semiconductor chip production method, semiconductor chip with film, semiconductor chip reinforcement method, reinforcement film and semiconductor device
JP2021180285A (en) Semiconductor device, manufacturing method thereof, and structure used in manufacturing of semiconductor device
JP2022153830A (en) Method for manufacturing support member and method for manufacturing semiconductor device
TW202414550A (en) Semiconductor device manufacturing method, adhesive layer and die-cut die-bonding integrated film

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19885248

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020556180

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20217017011

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 19885248

Country of ref document: EP

Kind code of ref document: A1