TW201916174A - 半導體結構和半導體製造方法 - Google Patents
半導體結構和半導體製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 238000002955 isolation Methods 0.000 claims abstract description 70
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 42
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 36
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- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 13
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- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
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- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
本揭露揭示一種半導體結構。該半導體結構包含:一基板;一隔離區,其毗鄰於汲極區;一閘極電極,其位於該基板上方且進一步向下延伸至該基板中,其中該閘極電極在該基板之一頂部表面下方之一部分鄰接該隔離區;以及一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。本揭露亦揭示一種用於製造該半導體結構之相關聯方法。
Description
本發明實施例係有關半導體結構和半導體製造方法。
高電壓金屬氧化物半導體(MOS)電晶體(諸如,橫向擴散的金屬氧化物半導體(LDMOS)電晶體)廣泛地用於如汽車工業、顯示器驅動器、可攜式電信裝置及醫療裝備等應用中。LDMOS電晶體通常用於高電壓應用。期望LDMOS電晶體具備一較高崩潰電壓及一較低導通電阻(RON)。
根據本發明的一實施例,一種半導體結構包括:一基板;一隔離區,其位於該基板中;一閘極電極,其位於該基板上方且進一步向下延伸至該基板中,其中該閘極電極在該基板之一頂部表面下方之一部分鄰接該隔離區;以及一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。 根據本發明的另一實施例,一種半導體結構包括:一基板;一閘極電極,其具有一第一部分及一第二部分,該第一部分位於該基板之一頂部表面上方且該第二部分位於該基板之該頂部表面下方,該第一部分自該第二部分之一側壁橫向地突出,且該第二部分係藉由該基板中之一介電區與該基板隔離;以及一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。 根據本發明的又一實施例,一種用於製造一半導體結構之方法包括:提供一基板;在該基板中形成一隔離溝槽;形成一個氧化矽溝槽填充層以至少填充該隔離溝槽;在該隔離溝槽中移除該氧化矽溝槽填充層之一部分;在該基板上方形成一閘極介電層;及在該基板上方形成一閘極層以填充該隔離溝槽。
以下揭露內容提供諸多不同實施例或實例以實施本揭露之不同特徵。下文闡述組件及配置之具體實例以簡化本揭露。當然,此等組件及配置僅係實例且並不意欲具限制性。舉例而言,在以下說明中,一第一構件形成於一第二構件上方或第二構件上可包含其中第一構件及第二構件直接接觸而形成之實施例,且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件與第二構件可不直接接觸之實施例。另外,本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡化及清晰目的且本身並不決定所論述之各種實施例及/或組態之間的一關係。 此外,為便於說明,本文中可使用空間相對術語(諸如,「下邊」、「下方」、「下部」、「上邊」、「上部」等)來闡述一個元件或構件與另一元件或構件之關係,如圖中所圖解說明。除了圖中所繪示之定向外,該等相關術語意欲囊括裝置在使用或操作中之不同定向。可以其他方式(旋轉90度或呈其他定向)定向設備且可因此以其他方式解釋本文中所使用之空間相對描述符。 儘管陳述本揭露之寬廣範圍之數值範圍及參數係近似值,但在具體實例中儘可能精確地報告所陳述之數值。然而,任何數值固有地含有必然由存在於相應測試量測中之標準偏差所引起之特定誤差。此外,如本文中所使用,術語「約」通常意指在一給定值或範圍之10%、5%、1%或0.5%內。另一選擇係,熟習此項技術者認為,術語「約」意指在平均值之一可接受標準誤差內。除了在操作/工作實例之外,或除非另有明確規定,否則所有數值、量、值及百分比(諸如,本文中所揭示之材料數量、持續時間、溫度、操作條件、量比率等之數值、量、值及百分比)應被理解為在所有例項中由術語「約」修飾。 因此,除非有相反指示,否則本揭露及申請專利範圍中所陳述之數值參數係可視需要變化之近似值。起碼,應至少鑒於所報告之有效數位之數目且藉由應用四捨五入技術來解釋每一數值參數。本文中範圍可被表達為自一個端點至另一端點或介於兩個端點之間。本文所揭示之範圍包含端點,除非另有規定。 本揭露係關於一橫向擴散的金屬氧化物半導體(LDMOS)電晶體及其一製作方法。根據實施例論述LDMOS電晶體之變化。圖解說明製造LDMOS電晶體之各個階段。貫穿各個視圖及說明性實施例,相似元件符號用於指定相似元件。 圖1係根據本揭露之一第一實施例之一MOS電晶體100之一剖面圖。MOS電晶體100包含一半導體基板102、一第一導電類型之一第一井區114、與第一導電類型相反之一第二導電類型之一第二井區112、隔離區121及122、一源極區132、一汲極區134、一拾取(pickup)區136、一閘極介電層120、一閘極電極150以及間隔件162、164。為了增大裝置崩潰電壓且減小導通電阻(RON),閘極電極150向下延伸至第一井區114中且橫向地毗鄰於隔離區121。 半導體基板102可由半導體材料(諸如,矽、鍺、矽鍺、碳化矽)及本質上由III-V族化合物半導體組成之材料(例如,GaAs及Si/Ge)製成。半導體基板102可係非晶質、多晶質或單晶質。半導體基板102可係N型或P型的。在一項實施例中,MOS電晶體20係一P型MOS電晶體且被製造於一P型半導體基板210中,且第一導電類型係P型且第二導電類型係N型。 第一導電類型之源極區132及第一導電類型之汲極區134放置於半導體基板210中。在MOS電晶體100係一P型MOS電晶體之實施例中,源極區132及汲極區134摻雜有具有自約1013
cm-3
至約1015
cm-3
之一摻雜濃度之P型摻雜物,諸如硼、鎵、鋁、銦或上述各項之一組合。 第一導電類型之第一井區114充當汲極區134之一延伸區,第一井區114經放置成橫向地毗鄰於第二井區112且環繞隔離區121及汲極區134。在MOS電晶體20係一P型MOS電晶體之實施例中,第一井區114摻雜有具有比汲極區134之摻雜濃度小之一摻雜濃度之P型摻雜物,諸如硼、鎵、鋁、銦或上述各項之一組合;亦即,第一井區114可係一P型井(PW)區或一高電壓P型井(HVPW)區。 第二導電類型之第二井區112位於源極區132側處之半導體基板102中且環繞隔離區122、源極區132及拾取區136。在MOS電晶體100係一P型MOS電晶體之實施例中,第二井區112摻雜有N型摻雜物;換言之,第二井區112被視為一N型井(NW)區或一高電壓N型井(HVNW)區。 閘極介電層120放置於半導體基板102上方且包含一第一閘極介電層部分120_1、一第二閘極介電層部分120_2及一第三閘極介電層部分120_3。特定而言,第一閘極介電層部分120_1放置於第二井區112之一頂部表面上且毗鄰於源極區132,且第一閘極介電層部分120_1延伸至第一井區114之一頂部表面且接觸第二閘極介電層部分120_2。第二閘極介電層部分120_2放置於內凹至第一井區114中之一側壁119上且接觸隔離區121。第三閘極介電層部分120_3放置於隔離區121之一頂部表面上且毗鄰於汲極區134。由側壁119與隔離區121之一底部表面118相交而形成之一角度α可大於約90度且小於約180度。閘極介電層120之一厚度係約80埃至約250埃。然而,此並非對本揭露之一限制。 隔離區121位於半導體基板102中且毗鄰於汲極區134。隔離區121可包含一種氧化物材料或氮化物材料。隔離區121用於減小汲極區134附近之裝置電場。在一項實施例中,隔離區121係一淺溝槽隔離(STI)區。在另一實施例中,隔離區121係一場氧化物(FOX)區。如自圖1可見,隔離區121並不雙邊對稱。隔離區121之一頂部表面與第一井區114之頂部表面實質上共面。隔離區121之一側壁116與隔離區121之底部表面118相交且形成一角度β。在某些實施例中,角度β可實質上等於角度α。隔離區121之另一側壁117可實質上垂直於隔離區121之頂部表面,且側壁119之一部分位於隔離區121的側壁117與底部表面118之間。側壁117自隔離區121之頂部表面延伸至隔離區121中達一深度d1。隔離區121之頂部表面與底部表面118之間的一距離d2大於距離d1。在某些實施例中,d1對d2之一比率在自約0.4至約0.85之一範圍中。然而,此並非對本揭露之一限制。 閘極電極150放置於閘極介電層120上方。具體而言,閘極電極150包含一第一閘極電極部分150_1及一第二閘極電極部分150_2。第一閘極電極部分150_1自靠近於源極區132之第一閘極介電層部分120_1延伸至第三閘極介電層部分120_3。第二閘極電極部分150_2向下延伸至第一井區114中且填充隔離區121與第二閘極介電層部分120_2之間的一區。第二閘極電極部分150_2具有一個三角形輪廓,如自剖面圖可見。第一閘極電極部分150_1具有一矩形輪廓,如自剖面圖可見。第一閘極電極部分150_1自第二閘極電極部分150_2雙側地突出。第一閘極電極部分150_1之一側壁比第二閘極電極部分150_2之側壁117更靠近汲極區134。第一閘極電極部分150_1之一頂部表面與第一閘極電極部分150_1之一底部相距達一距離d3。在某些實施例中,d3對d2之一比率在自約0.3至約0.6之一範圍中。閘極電極150可由一導電材料製成,諸如多晶矽(poly)、金屬或金屬合金。在一項實施例中,閘極電極150包含多晶矽。在各種實施例中,閘極電極150具有在約500至10,000埃之一範圍中之一厚度。 在各種實施例中,作為一特定構件,閘極電極150具有在半導體基板102上方之第一閘極電極部分150_1及在半導體基板102中之第二閘極電極部分150_2。第二閘極電極部分150_2替換最初用於隔離區121之空間之一部分。隔離區121與第二閘極介電層部分120_2之間的區具有比隔離區121低之一電阻。因此,當MOS電晶體100處於「導通」狀態中時,側壁119周圍之一電流密度可被增大,此會減小裝置導通電阻(RON)。另外,當MOS電晶體100處於「關斷」狀態中時,一衝擊游離化中心自第一閘極介電層部分120_1與第二閘極介電層部分120_2之間的一隅角移動至側壁119與底部表面118之間的一隅角,此會改良裝置崩潰電壓。 MOS電晶體100可選擇性地包含形成於間隔件162下方、鄰接源極區132之一LDD區。在MOS電晶體100係一P型MOS電晶體之實施例中,LDD區係一P型輕微摻雜汲極(PLDD)區。 間隔件162接觸閘極電極150之第一閘極電極部分150_1之一側壁111;間隔件164設置於隔離區121上且接觸第一閘極電極部分150_1之側壁113。氮化矽或二氧化矽可用於形成間隔件162及164。 值得注意的是,第二閘極電極部分150_2之一大小可經任意調整以滿足改良一電壓崩潰及裝置導通電阻(RON)之一需要,且因此並不限於本揭露之實施例中所展示之實施例。圖2係根據本揭露之一第二實施例之一MOS電晶體200之一剖面圖。為了使說明清晰且避免重複,上文用於闡述MOS電晶體100之相似數字及字母用於圖2中之MOS電晶體200。此外,先前所闡述之元件符號本文中不再詳細闡述。MOS電晶體100與MOS電晶體200之間的差異係與MOS電晶體100相比,MOS電晶體200包含一更大第二閘極電極部分150_2。MOS電晶體200之第二閘極電極部分150_2之側壁117更靠近汲極區134,但仍未延伸至第一閘極電極部分150_1之側壁113。換言之,最初用於隔離區121之較多空間被第二閘極電極部分150_2替換。如此,側壁119周圍可吸引更多電流且裝置導通電阻(RON)可進一步被改良。在各種實施例中,第二閘極電極部分150_2之一底部表面215實質上平行於隔離區121之底部表面118。因此,MOS電晶體200之第二閘極電極部分150_2具有一梯形輪廓,如自圖2中之剖面圖可見。 圖3係根據本揭露之一第三實施例之一MOS電晶體300之一剖面圖。為了使說明清晰且避免重複,上文用於闡述MOS電晶體100之相似數字及字母用於圖3中之MOS電晶體300。此外,先前所闡述之元件符號本文中不再詳細闡述。MOS電晶體300與MOS電晶體200之間的差異係與MOS電晶體200想比,MOS電晶體300包含一更大第二閘極電極部分150_2。MOS電晶體300之第二閘極電極部分150_2之側壁117更靠近汲極區134且延伸至第一閘極電極部分150_1之側壁113。換言之,最初用於隔離區121之更大空間被第二閘極電極部分150_2替換。如此,側壁119周圍可吸收更多電流且裝置導通電阻(RON)可進一步被改良。MOS電晶體300之第二閘極電極部分150_2亦具有一梯形輪廓,如自圖3中之剖面圖可見。 圖4至圖12係製作MOS電晶體100之各個階段處之剖面圖。為了使說明清晰且避免重複,上文用於闡述MOS電晶體100之相似數字及字母在下圖中用於各種元件。此外,先前所闡述之元件符號本文中可不再闡述。 如圖4中所展示,提供一半導體基板102。在半導體基板102上方形成一層墊氧化物層104。墊氧化物層104可由熱生長材料(包含二氧化矽或氮化矽)製成,或由化學氣相沉積(CVD) (諸如,電漿輔助CVD (PECVD)、低壓CVD (LPCVD)或大氣壓CVD (APCVD))沉積而來。在某些實施例中,墊氧化物層104可在介於約850℃至950℃之間的一溫度範圍下熱生長且達到約100埃至250埃之間的一厚度。在墊氧化物層104上方形成一個氮化物層106。在某些實施例中,氮化物層106係藉由在一LPCVD室中在介於約750℃至850℃之間的一溫度下使二氯矽烷(SiCl2
H2
)與氨(NH3
)反應而形成。在某些實施例中,氮化物層106之厚度介於約1200埃至2500埃之間。 如圖5中所圖解說明,在氮化物層106、墊氧化物層104及半導體基板102中定義隔離溝槽501及502。隔離溝槽501具有一寬度W1及一高度H1,其中寬度W1較佳地大於約0.3微米,而高度H1較佳地係自約3000埃至約5000埃。 一圖案化氧化矽墊氧化物層104形成於半導體基板102上且定義隔離溝槽501及502之寬度W1,圖案化氧化矽墊氧化物層104上形成有一圖案化氮化矽層106且兩者對準。在本揭露方法之較佳實施例內,圖案化氮化矽層106用作一圖案化化學機械拋光(CMP)拋光停止層,而圖案化氧化矽墊氧化物層104用作半導體基板102與圖案化氮化矽層106之間的一黏合形成與應力減小層。雖然較佳地在本揭露方法之較佳實施例內採用圖案化氧化矽墊氧化物層104及圖案化氮化矽層106,但其在本揭露方法內並不需要。然而,透過本揭露方法之較佳實施例可知,兩者之存在提供用於在隔離溝槽501及502內最均勻地形成圖案化平坦化間隙填充氧化矽溝槽填充層之一方法。 可透過積體電路製造技術中習用之方法形成圖案化氧化矽墊氧化物層104及圖案化氮化矽層106,此等方法將通常(但並不排除其他)採用對形成於一對應毯覆式氮化矽層下方之一毯覆式氧化矽墊氧化物層之光微影圖案化。類似地,毯覆式氮化矽層及毯覆式氧化矽墊氧化物層可透過積體電路製造技術中習用之方法形成,該等技術包含不限於適合的熱氧化方法、化學氣相沉積(CVD)方法及物理氣相沉積(PVD)濺鍍方法。較佳地,圖案化氧化矽墊氧化物層104及對應毯覆式氧化矽墊氧化物層各自形成達自約90埃至約130埃之一厚度,其中毯覆式氧化矽墊氧化物層較佳地係透過在自約850℃至約950℃之一溫度下之一熱氧化方法而形成。較佳地,圖案化氮化矽層106及對應毯覆式氮化矽層各自形成達約1500埃至約2000埃之一厚度。 現在參考圖6,展示圖解說明進一步處理半導體基板102之結果之一示意性剖面圖,圖5中圖解說明半導體基板102之示意性剖面圖。圖6中展示一對圖案化氧化矽溝槽襯層601及602之存在,601及602形成至對應隔離溝槽501及502中。可採用一矽烷源材料、透過一電漿輔助化學氣相沉積(PECVD)方法以一自對準方式在每一隔離溝槽501或502內形成圖案化氧化矽溝槽襯層601及602。較佳地,如此形成之圖案化氧化矽溝槽襯層601及602各自具有自約300埃至約500埃之一厚度。圖案化氧化矽溝槽襯層601及602在半導體基板102與隨後形成於隔離溝槽501及502內之溝槽填充介電層之間提供一絕佳洩漏阻障物。 現在參考圖7,展示圖解說明進一步處理半導體基板102之結果之一示意性剖面圖,圖6中圖解說明半導體基板102之示意性剖面圖。圖7中形成一個氧化矽溝槽填充層701。在本揭露方法內,可透過一臭氧輔助次大氣壓熱化學氣相沉積(SACVD)方法形成氧化矽溝槽填充層701。由於在高壓下採用臭氧輔助次大氣壓熱化學氣相沉積(SACVD)方法,因此此等方法排除電漿活化,但為透過此等方法形成之氧化矽溝槽填充層701提供絕佳間隙填充及平坦化性質。較佳地,用於形成氧化矽溝槽填充層701之臭氧輔助次大氣壓熱化學氣相沉積(SACVD)方法採用在自約10:1至約15:1之一臭氧:TEOS體積比率下的一臭氧氧化劑及一正矽酸四乙酯(TEOS)矽源材料。較佳地,氧化矽溝槽填充層701在半導體基板102上方形成達自約6000埃至約8000埃之一厚度。 接下來,如圖8中所展示,在氧化矽溝槽填充層701上形成一抗蝕劑層803以至少覆蓋一隔離溝槽區域802及一隔離溝槽區域801之一部分。可使用習用方法中之任一者形成抗蝕劑層803。換言之,定義抗蝕劑層803之一開口804以自頂部暴露隔離溝槽區域801之一部分。開口804之一端延伸跨越隔離溝槽區域801之一左端達一距離W2。寬度W2小於隔離溝槽501之寬度W1。 如圖9中所展示,使用抗蝕劑層803來作為一蝕刻遮罩,蝕刻掉至少在開口804上方之氧化矽溝槽填充層701以改良後續CMP製程。此會減小隔離溝槽區域801及802中之溝槽凹陷效應。另外,亦蝕刻掉隔離溝槽區域801中之氧化矽溝槽填充層701之一部分以允許一閘極電極延伸至該部分中以改良電特性,如將詳細地闡述。在蝕刻製程之後,移除抗蝕劑層803。 轉至圖10,透過一CMP平坦化製程移除剩餘氧化矽溝槽填充層701,藉此將STI區中之介電層121及122平坦化。在移除氧化矽溝槽填充層701之後,亦移除墊氧化物層104上方之氮化物層106。 可在圖案化氧化矽墊氧化物層104之頂部表面上方沉積一光阻劑層(未展示)。第二導電類型之第二井區112之光阻劑層經受一微影製程。在待形成MOS電晶體係一P型MOS電晶體之實施例中,第二井區112摻雜有N型摻雜物;換言之,第二井區112被視為一N型井(NW)區或一高電壓N型井(HVNW)區。將光阻劑層顯影以暴露HVNW區112上方之墊氧化物層104。以一摻雜物佈植半導體基板102在經暴露墊氧化物層104下方之部分以形成HVNW區112。舉例而言,HVNW區112之摻雜物可包含磷。HVNW 112可包含介於約3.5 µm至4 µm之間的一深度,且可係在120 keV下使用大約1012
至1013
之一摻雜物佈植濃度來形成(舉例而言)。 然後,移除光阻劑層,且在墊氧化物層104上方沉積另一光阻劑層(未展示)。將光阻劑層圖案化成第一導電類型之第一井區114所要之圖案。在待形成MOS電晶體係一P型MOS電晶體之實施例中,第一井區114摻雜有P型摻雜物;換言之,第一井區114被視為一P型井(PW)區或一高電壓P型井(HVPW)區。將光阻劑層顯影以暴露HVPW區114上方之墊氧化物層104。以一摻雜物佈植半導體基板102在經暴露墊氧化物層104下方之部分以形成HVPW 區114。舉例而言,用於HVPW區114之摻雜物可包含硼。HVPW 114可包含介於約3.5 µm至4 µm之間的一深度,且可係在90 keV下使用大約1012
至1013
之一摻雜物佈植濃度來形成(舉例而言)。 接下來,如圖11中所圖解說明,移除墊氧化物層104。可藉由熱生長方法或沉積而在半導體基板102上方形成一閘極介電層1101。作為一實例,閘極介電層1101可由熱生長材料(包含二氧化矽或氮化矽)製成,或藉由化學氣相沉積(CVD) (諸如,電漿輔助CVD (PECVD)、低壓CVD (LPCVD)或大氣壓CVD (APCVD))沉積而來。接下來,如圖12中所展示,在閘極介電層1101上沉積一閘極層1201,諸如一多晶矽層。 最後,然後將閘極層1201圖案化以形成閘極電極150。從而,閘極電極150充當一遮罩,且對閘極介電層1101進行乾式蝕刻以在閘極電極150下方形成閘極介電層120。藉由任何習用方法來形成第一間隔件162及第二間隔件164、源極區132、汲極區134以及拾取區136。舉一實例,循序地執行沉積、光微影及蝕刻製程以在閘極電極150之相對側壁處形成第一間隔件162及第二間隔件164。然後,將第一導電類型之摻雜物分別佈植至第二井區112之一選擇性區域中及第一井區114之一選擇性區域中以形成如圖1中所展示之源極區132及汲極區134。 本揭露之某些實施例提供一種半導體結構。該半導體結構包含:一基板;一隔離區,其毗鄰於汲極區;一閘極電極,其位於該基板上方且進一步向下延伸至該基板中,其中該閘極電極在該基板之一頂部表面下方之一部分鄰接該隔離區;以及一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。 本揭露之某些實施例提供一種半導體結構。該半導體結構包含:一基板;一閘極電極,其具有一第一部分及一第二部分,該第一部分位於該基板之一頂部表面上方且該第二部分位於該基板之該頂部表面下方,第一部分自第二部分之一側壁橫向地突出,且該第二部分係藉由該基板中之一介電區與該基板隔離;以及一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。 本揭露之某些實施例提供一種製造一半導體結構之方法。該方法包含:提供一基板;在基板中形成一隔離溝槽;形成一個氧化矽溝槽填充層以至少填充該隔離溝槽;在該隔離溝槽中移除該氧化矽溝槽填充層之一部分;在該基板上方形成一閘極介電層;及在該基板上方形成一閘極層以填充該隔離溝槽。 前述內容概述數項實施例之特徵,使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者將瞭解,其可容易地使用本揭露來作為設計或修改其他製程及結構以實施相同目的及/或達成本文中所引入之實施例之相同有點之一基礎。熟習此項技術者亦應意識到,此等等效構造不背離本揭露之精神及範疇,且其可在不背離本揭露之精神及範疇之情況下做出各種改變、替代及更改。
100‧‧‧金屬氧化物半導體電晶體
102‧‧‧半導體基板
104‧‧‧墊氧化物層/圖案化氧化矽墊氧化物層/經暴露墊氧化物層
106‧‧‧氮化物層/圖案化氮化矽層
111‧‧‧側壁
112‧‧‧第二井區/高電壓N型井區/高電壓N型井
113‧‧‧側壁
114‧‧‧第一井區/高電壓P型井區/高電壓P型井
116‧‧‧側壁
117‧‧‧另一側壁/側壁
118‧‧‧底部表面
119‧‧‧側壁
120‧‧‧閘極介電層
120_1‧‧‧第一閘極介電層部分
120_2‧‧‧第二閘極介電層部分
120_3‧‧‧第三閘極介電層部分
121‧‧‧隔離區/介電層
122‧‧‧隔離區
132‧‧‧源極區
134‧‧‧汲極區
136‧‧‧拾取區
150‧‧‧閘極電極
150_1‧‧‧第一閘極電極部分
150_2‧‧‧第二閘極電極部分
162‧‧‧間隔件/第一間隔件
164‧‧‧間隔件/第二間隔件
200‧‧‧金屬氧化物半導體電晶體
215‧‧‧底部表面
300‧‧‧金屬氧化物半導體電晶體
501‧‧‧隔離溝槽
502‧‧‧隔離溝槽
601‧‧‧圖案化氧化矽溝槽襯層
602‧‧‧圖案化氧化矽溝槽襯層
701‧‧‧氧化矽溝槽填充層
801‧‧‧隔離溝槽區域
802‧‧‧隔離溝槽區域
803‧‧‧抗蝕劑層
804‧‧‧開口
1101‧‧‧閘極介電層
1201‧‧‧閘極層
d1‧‧‧深度/距離
d2‧‧‧距離
d3‧‧‧距離
H1‧‧‧高度
W1‧‧‧寬度
W2‧‧‧寬度
α‧‧‧角度
β‧‧‧角度
當搭配附圖閱讀時,依據以下詳細說明最佳地理解本揭露之態樣。應注意,根據行業中之標準實踐,各種構件未按比例繪製。實際上,為論述之清晰起見,可任意地增大或減小各種構件之尺寸。 圖1係根據本揭露之一第一實施例之一MOS電晶體之一剖面圖; 圖2係根據本揭露之一第二實施例之一MOS電晶體之一剖面圖; 圖3係根據本揭露之一第三實施例之一MOS電晶體之一剖面圖;且 圖4至圖12係製作MOS電晶體之各個階段處之剖面圖。
Claims (20)
- 一種半導體結構,其包括: 一基板; 一隔離區,其位於該基板中; 一閘極電極,其位於該基板上方且進一步向下延伸至該基板中,其中該閘極電極在該基板之一頂部表面下方之一部分鄰接該隔離區;及 一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。
- 如請求項1之半導體結構,其進一步包括一閘極介電層,該閘極介電層至少位於該閘極電極與該基板之該頂部表面之間。
- 如請求項2之半導體結構,其中該閘極介電層進一步向下延伸至該基板中該基板之該頂部表面下方。
- 如請求項3之半導體結構,其中該閘極電極在該基板之該頂部表面下方之該部分之一個側壁係藉由該閘極介電層與該基板分離。
- 如請求項1之半導體結構,其中自一剖面圖來看,該閘極電極在該基板之該頂部表面下方之該部分具有一個三角形輪廓。
- 如請求項1之半導體結構,其中該閘極電極在該基板之該頂部表面下方之該部分之一底部與該基板之該頂部表面相距達一第一深度,且該隔離區之一底部與該基板之該頂部表面相距達一第二深度,且該第一深度對該第二深度之一比率在自約0.4至約0.85之一範圍中。
- 如請求項1之半導體結構,其中自一俯視圖來看,該閘極電極與該隔離區重疊。
- 如請求項1之半導體結構,其進一步包括位於該基板中的一第一導電類型之一第一井區及一第二導電類型之一第二井區,該第二導電類型與該第一導電類型相反。
- 如請求項8之半導體結構,其中該隔離區及該閘極電極在該基板之該頂部表面下方之該部分位於該第一井區中且與該第二井區相距達大於0之一預定距離。
- 一種半導體結構,其包括: 一基板; 一閘極電極,其具有一第一部分及一第二部分,該第一部分位於該基板之一頂部表面上方且該第二部分位於該基板之該頂部表面下方,該第一部分自該第二部分之一側壁橫向地突出,且該第二部分係藉由該基板中之一介電區與該基板隔離;及 一源極區及一汲極區,其形成於該基板中該閘極結構之任一側上。
- 如請求項10之半導體結構,其中自一剖面圖來看,該閘極電極之該第二部分具有一個三角形輪廓。
- 如請求項10之半導體結構,其中自一剖面圖來看,該閘極電極之該第二部分具有一梯形輪廓。
- 如請求項10之半導體結構,其中自一剖面圖來看,該閘極電極之該第一部分具有一矩形輪廓。
- 如請求項13之半導體結構,其中該閘極電極之第一部分自該第二部分雙側地突出。
- 如請求項10之半導體結構,其中該閘極電極包含一導電材料。
- 如請求項10之半導體結構,其進一步包括一拾取區。
- 如請求項16之半導體結構,其進一步包括位於該基板中的一第一導電類型之一第一井區及一第二導電類型之一第二井區,該第二導電類型與該第一導電類型相反。
- 如請求項17之半導體結構,其中該汲極區、該介電區及該閘極電極之該第二部分位於該第一井區中。
- 如請求項17之半導體結構,其中該源極區及該拾取區位於該第二井區中。
- 一種用於製造一半導體結構之方法,其包括: 提供一基板; 在該基板中形成一隔離溝槽; 形成一個氧化矽溝槽填充層以至少填充該隔離溝槽; 在該隔離溝槽中移除該氧化矽溝槽填充層之一部分; 在該基板上方形成一閘極介電層;及 在該基板上方形成一閘極層以填充該隔離溝槽。
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US11158723B2 (en) | 2020-03-04 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structure and method of forming the same |
TWI747109B (zh) * | 2019-12-19 | 2021-11-21 | 世界先進積體電路股份有限公司 | 半導體結構及其形成方法 |
TWI748559B (zh) * | 2019-07-17 | 2021-12-01 | 美商茂力科技股份有限公司 | 橫向雙擴散金屬氧化物半導體場效應電晶體 |
US12020940B2 (en) | 2021-07-15 | 2024-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing thereof |
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JP7040976B2 (ja) | 2018-03-29 | 2022-03-23 | ラピスセミコンダクタ株式会社 | 半導体装置 |
US10903080B2 (en) * | 2018-08-21 | 2021-01-26 | Nanya Technology Corporation | Transistor device and method for preparing the same |
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CN112909095B (zh) * | 2021-01-21 | 2024-03-19 | 上海华虹宏力半导体制造有限公司 | Ldmos器件及工艺方法 |
US11417761B1 (en) * | 2021-02-09 | 2022-08-16 | United Microelectronics Corp. | Transistor structure and method for fabricating the same |
CN116913782A (zh) * | 2023-09-14 | 2023-10-20 | 粤芯半导体技术股份有限公司 | 复合场板结构的ldmos器件制备方法 |
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US7888732B2 (en) * | 2008-04-11 | 2011-02-15 | Texas Instruments Incorporated | Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric |
US8643090B2 (en) * | 2009-03-23 | 2014-02-04 | Infineon Technologies Ag | Semiconductor devices and methods for manufacturing a semiconductor device |
US9318370B2 (en) * | 2011-08-04 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k dielectric liners in shallow trench isolations |
US8987813B2 (en) * | 2012-08-10 | 2015-03-24 | United Microelectronics Corp. | High voltage metal-oxide-semiconductor transistor device |
US9166046B2 (en) * | 2014-02-14 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing |
JP6279346B2 (ja) * | 2014-02-27 | 2018-02-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN104900694A (zh) * | 2014-03-03 | 2015-09-09 | 无锡华润上华半导体有限公司 | 横向扩散金属氧化物半导体器件及其制造方法 |
CN105206665A (zh) * | 2014-05-27 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
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TWI724164B (zh) * | 2017-05-05 | 2021-04-11 | 聯華電子股份有限公司 | 半導體元件及其製作方法 |
US10680101B2 (en) * | 2017-07-31 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power metal-oxide-semiconductor field-effect transistor |
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Cited By (4)
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TWI748559B (zh) * | 2019-07-17 | 2021-12-01 | 美商茂力科技股份有限公司 | 橫向雙擴散金屬氧化物半導體場效應電晶體 |
TWI747109B (zh) * | 2019-12-19 | 2021-11-21 | 世界先進積體電路股份有限公司 | 半導體結構及其形成方法 |
US11158723B2 (en) | 2020-03-04 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structure and method of forming the same |
US12020940B2 (en) | 2021-07-15 | 2024-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing thereof |
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