TW201913714A - Liner, reaction chamber and semiconductor processing equipment - Google Patents
Liner, reaction chamber and semiconductor processing equipment Download PDFInfo
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本發明涉及半導體製造技術領域，具體地，涉及一種內襯、反應腔室及半導體加工設備。The present invention relates to the field of semiconductor manufacturing technology, and in particular to a lining, a reaction chamber, and a semiconductor processing apparatus.
在蝕刻製程中，必須嚴格控制電漿反應腔室的大量製程參數以保持高質量的蝕刻結果。其中，腔室內部結構的優化設計對設備本身的製程性能及製程蝕刻結果有著決定性的作用。In the etching process, a large number of process parameters of the plasma reaction chamber must be strictly controlled to maintain high quality etching results. Among them, the optimized design of the internal structure of the chamber plays a decisive role in the process performance of the device itself and the etching result of the process.
目前，通常在蝕刻機的反應腔室內部增設有內襯，該內襯主要用於改善腔室內部電漿的有效流動性，同時能夠約束電漿，保護腔室內壁與底部不被蝕刻。另外，增設的內襯更便於機台腔室的維護。At present, a lining is usually added inside the reaction chamber of the etching machine, and the lining is mainly used to improve the effective fluidity of the plasma inside the chamber, and at the same time, the plasma can be restrained, and the inner wall and the bottom of the chamber are not etched. In addition, the added lining is more convenient for the maintenance of the machine room.
現有的內襯環繞設置在反應腔室的側壁內側，且內襯的上端接地，內襯的下端設置有向其內側彎折的水平彎折部和自該水平彎折部垂直向上彎折的垂直彎折部，其中，垂直彎折部環繞在基座的周圍，用於改變基座及其周圍環境的阻抗模型，增強了基座邊緣處的電場強度，從而可以提高晶片邊緣的蝕刻效率，進而可以提高晶片的蝕刻均勻性。水平彎折部用於防止電漿自內襯與基座之間的間隙通過，進入腔室底部，以保護腔室底部不被蝕刻。The existing inner liner is disposed around the inner side of the side wall of the reaction chamber, and the upper end of the inner liner is grounded, and the lower end of the inner liner is provided with a horizontal bending portion bent toward the inner side thereof and a vertical bending portion bent from the horizontal bending portion. a vertical bending portion, wherein a vertical bending portion surrounds the susceptor for changing an impedance model of the pedestal and its surrounding environment, and enhancing an electric field strength at the edge of the pedestal, thereby improving etching efficiency of the edge of the wafer, Further, the etching uniformity of the wafer can be improved. The horizontal bend is used to prevent plasma from passing through the gap between the liner and the base, entering the bottom of the chamber to protect the bottom of the chamber from being etched.
上述內襯在實際應用中不可避免地存在以下問題：The above liners inevitably have the following problems in practical applications:
由於僅內襯的上端接地，導致在射頻環境中內襯的回路較長，內襯的彎折結構會呈現較大的電感特性，同時上述垂直彎折部與基座之間形成電容特性，從而內襯等效形成了如第1圖示出的等效模型。該等效模型的諧振頻率的公式為： Since only the upper end of the lining is grounded, the loop of the lining is long in the radio frequency environment, and the bent structure of the lining exhibits a large inductance characteristic, and at the same time, a capacitance characteristic is formed between the vertical bending portion and the pedestal, thereby The liner is equivalently formed as an equivalent model as shown in Fig. 1. The formula for the resonant frequency of this equivalent model is:
其中，f為諧振頻率；L為等效電感，由內襯的彎折結構產生；C為等效電容，由上述垂直彎折部與基座產生。在射頻環境的頻率接近系統的諧振頻率時，系統產生諧振，從而造成射頻環境的直流自偏壓突變，如第2圖所示，直流自偏壓突然降低，出現異常曲線，從而影響製程穩定性。Where f is the resonant frequency; L is the equivalent inductance, which is produced by the bent structure of the inner liner; C is the equivalent capacitance generated by the vertical bent portion and the base. When the frequency of the RF environment is close to the resonant frequency of the system, the system generates resonance, which causes the DC self-bias of the RF environment to be abrupt. As shown in Figure 2, the DC self-bias voltage suddenly decreases, and an abnormal curve appears, which affects the stability of the process. .
本發明旨在至少解決先前技術中存在的技術問題之一，提出了一種內襯、反應腔室及半導體加工設備，其可以避免系統產生諧振，從而可以增強製程穩定性。The present invention is directed to at least one of the technical problems existing in the prior art, and proposes a lining, a reaction chamber, and a semiconductor processing apparatus which can avoid resonance of the system, thereby enhancing process stability.
為實現本發明的目的而提供一種內襯，設置在反應腔室內，該內襯包括：In order to achieve the object of the present invention, an inner liner is provided which is disposed in a reaction chamber, the inner liner comprising:
內襯主體，其環繞設置在該反應腔室的側壁內側，且接地；a lining body disposed around the side wall of the reaction chamber and grounded;
第一分體，其環繞在設置於該反應腔室內的基座的周圍，且該第一分體的下端通過該基座接地；並且，在該第一分體的內周壁與該基座的外周壁之間環繞設置有介電質環；a first split body surrounding the base disposed in the reaction chamber, and a lower end of the first split body is grounded through the base; and an inner peripheral wall of the first split body and the base a dielectric ring is disposed around the outer peripheral wall;
第二分體，其環繞設置在該內襯主體的下端與該第一分體的外周壁之間。a second split body is disposed between the lower end of the lining body and the outer peripheral wall of the first split body.
可選的，該第二分體與該內襯主體連為一體。Optionally, the second split body is integrally connected to the lining body.
可選的，該第二分體與該第一分體連為一體。Optionally, the second split body is integrated with the first split body.
可選的，該內襯主體與該第二分體連為一體；該第二分體與該第一分體連為一體。Optionally, the lining body is integrally connected with the second split body; the second split body is integrally connected with the first split body.
可選的，該第一分體環的下端相對於該第二分體的下端面垂直向下凸出。Optionally, a lower end of the first split ring protrudes vertically downward with respect to a lower end surface of the second split body.
可選的，該第一分體的上端與該介電質環的上端相平齊；該第一分體的下端與該介電質環的下端相平齊。Optionally, an upper end of the first split body is flush with an upper end of the dielectric ring; a lower end of the first split body is flush with a lower end of the dielectric ring.
另一技術方案，本發明還提供一種反應腔室，在該反應腔室內設置有基座，在該反應腔室內還設置有如本發明提供的上述內襯。In another technical solution, the present invention also provides a reaction chamber in which a susceptor is disposed, and the above-mentioned lining provided by the present invention is further disposed in the reaction chamber.
可選的，該基座包括由上而下依次設置的基座本體、隔離層和金屬介面盤，其中，該金屬介面盤接地；Optionally, the base includes a base body, an isolation layer, and a metal interface disk disposed in sequence from top to bottom, wherein the metal interface disk is grounded;
該第一分體的下端與該金屬介面盤電導通。The lower end of the first body is electrically connected to the metal interface disk.
可選的，該金屬介面盤包括相對於該隔離層的外周壁凸出的第一凸臺；Optionally, the metal interface disk includes a first protrusion protruding from a peripheral wall of the isolation layer;
在該第一分體的下端設置有相對於該第一分體的外周壁凸出的第二凸臺，該第二凸臺與該第一凸臺相互疊置，且二者通過螺釘固定連接。a second boss protruding from the outer peripheral wall of the first split body is disposed at a lower end of the first split body, the second boss and the first boss are overlapped with each other, and the two are fixedly connected by screws .
可選的，在該第二凸臺與該第一凸臺相接觸的二表面之間設置有導電層。Optionally, a conductive layer is disposed between the two surfaces of the second boss that are in contact with the first boss.
可選的，該導電層採用電鍍的方式設置在該第二凸臺與該第一凸臺相接觸的二表面中的至少一表面上。Optionally, the conductive layer is disposed on the at least one surface of the two surfaces in contact with the first protrusion by electroplating.
另一技術方案，本發明還提供一種半導體加工設備，包括本發明提供的上述反應腔室。In another aspect, the present invention also provides a semiconductor processing apparatus comprising the above reaction chamber provided by the present invention.
本發明具有以下有益效果：The invention has the following beneficial effects:
本發明提供的內襯，其包括內襯主體、第一分體和第二分體，其中，內襯主體環繞設置在反應腔室的側壁內側，且接地。第一分體環繞在基座的周圍，且該第一分體的下端通過該基座接地，並且在第一分體的內周壁與基座的外周壁之間設置有介電質環。第二分體設置在內襯的下端與第一分體的外周壁之間，用於防止電漿自二者之間的間隙通過。由於第一分體的下端通過基座接地，僅靠該第一分體與基座產生的電容無法產生諧振。此外，第一分體與內襯主體之間產生的電容的量級遠小於第一分體與基座產生的電容，同時由於上述第一分體的下端接地，使得內襯產生的電感較小，從而根據諧振頻率的公式可知，系統的諧振頻率大大增加，使得射頻環境的頻率很難接近系統的諧振頻率，進而避免了系統產生諧振，從而可以增強製程穩定性。The invention provides an inner liner comprising a liner main body, a first split body and a second split body, wherein the liner main body is disposed around the side wall of the reaction chamber and is grounded. The first split body surrounds the base, and the lower end of the first split body is grounded through the base, and a dielectric ring is disposed between the inner peripheral wall of the first split body and the outer peripheral wall of the base. The second split body is disposed between the lower end of the inner liner and the outer peripheral wall of the first split body for preventing plasma from passing through the gap between the two. Since the lower end of the first split body is grounded through the base, the capacitance generated by the first split body and the base alone cannot resonate. In addition, the capacitance generated between the first body and the body of the lining is much smaller than the capacitance generated by the first body and the pedestal, and the inductance of the lining is small due to the grounding of the lower end of the first body. Therefore, according to the formula of the resonant frequency, the resonant frequency of the system is greatly increased, so that the frequency of the radio frequency environment is difficult to approach the resonant frequency of the system, thereby avoiding resonance of the system, thereby enhancing process stability.
本發明提供的反應腔室，其通過採用本發明提供的上述內襯，可以避免系統產生諧振，從而可以增強製程穩定性。The reaction chamber provided by the present invention can avoid resonance of the system by using the above-mentioned inner liner provided by the present invention, thereby enhancing process stability.
本發明提供的半導體加工設備，其通過採用本發明提供的上述反應腔室，可以避免系統產生諧振，從而可以增強製程穩定性。The semiconductor processing apparatus provided by the present invention can avoid resonance of the system by using the above reaction chamber provided by the present invention, thereby enhancing process stability.
為使本領域的技術人員更好地理解本發明的技術方案，下面結合附圖來對本發明提供的內襯、反應腔室及半導體加工設備進行詳細描述。In order to enable those skilled in the art to better understand the technical solutions of the present invention, the lining, the reaction chamber and the semiconductor processing apparatus provided by the present invention are described in detail below with reference to the accompanying drawings.
請一併參閱第3A圖和第3B圖，本發明第一實施例提供一種內襯，其設置在反應腔室6內，該反應腔室6內還設置有基座1，用於承載被加工工件，且基座1接地。內襯包括內襯主體2、第一分體32和第二分體31。其中，內襯主體2環繞設置在反應腔室6的側壁內側，且接地，在本實施例中，內襯主體2的上端與反應腔室6的側壁連接，且電導通，並且反應腔室6的側壁接地，從而實現內襯主體2接地。Referring to FIG. 3A and FIG. 3B together, the first embodiment of the present invention provides an inner liner disposed in the reaction chamber 6, and the reaction chamber 6 is further provided with a base 1 for carrying the processed The workpiece and the base 1 are grounded. The inner liner includes a liner main body 2, a first split body 32, and a second split body 31. Wherein, the lining main body 2 is disposed around the inner side wall of the reaction chamber 6 and grounded. In the present embodiment, the upper end of the lining main body 2 is connected to the side wall of the reaction chamber 6, and is electrically connected, and the reaction chamber 6 is The side wall is grounded to achieve grounding of the lining body 2.
第一分體32環繞在基座1的周圍，且第一分體32的下端通過基座1接地，並且在第一分體32的內周壁與基座1的外周壁之間的間隔D1中設置有介電質環4。第二分體31設置在內襯主體2的下端與第一分體32的外周壁之間，用於防止電漿自內襯主體2與第一分體32之間的間隙通過，擴散至反應腔室6的底部。The first split body 32 surrounds the base 1 and the lower end of the first split body 32 is grounded through the base 1 and in the space D1 between the inner peripheral wall of the first split body 32 and the outer peripheral wall of the base 1 A dielectric ring 4 is provided. The second split body 31 is disposed between the lower end of the inner liner main body 2 and the outer peripheral wall of the first split body 32 for preventing plasma from passing through the gap between the inner liner main body 2 and the first split body 32, and diffusing to the reaction The bottom of the chamber 6.
由於基座1的表面與電漿鞘層之間會呈現電容效應，並產生電場，該電場在基座1的邊緣處會向外扭曲而造成場強減小，從而使得晶片邊緣的蝕刻效率降低。為此，通過設置上述第一分體32，同時在第一分體32的內周壁與基座1的外周壁之間設置有介電質環4，可以使第一分體32與基座1產生的電容為C1，這可以改變基座1及其周圍環境的阻抗模型，增強了基座邊緣處的電場強度，從而可以提高晶片邊緣的蝕刻效率，進而增大晶片的蝕刻均勻性。上述介電質環4可以起到增大電容C1的作用，該介電質環4例如可以採用陶瓷製作。Since the surface of the susceptor 1 and the plasma sheath layer exhibit a capacitive effect and generate an electric field, the electric field is outwardly twisted at the edge of the susceptor 1 to cause a decrease in field strength, thereby reducing etching efficiency at the edge of the wafer. . Therefore, by providing the first split body 32 while the dielectric ring 4 is disposed between the inner peripheral wall of the first split body 32 and the outer peripheral wall of the base 1, the first split body 32 and the base 1 can be made. The resulting capacitance is C1, which can change the impedance model of the susceptor 1 and its surroundings, and enhance the electric field strength at the edge of the pedestal, thereby improving the etching efficiency of the wafer edge and thereby increasing the etch uniformity of the wafer. The dielectric ring 4 can function to increase the capacitance C1, and the dielectric ring 4 can be made of ceramic, for example.
在實際應用中，根據第一分體32和第二分體31各自的作用，第一分體32的徑向厚度遠小於其軸向長度，即，第一分體32呈筒狀，以保證其與基座1之間形成電容效應。至於第二分體31，其徑向厚度應保證其能夠遮擋內襯主體2的下端與第一分體32的外周壁之間的間隙。可選的，第二分體31為環形板體。In practical applications, according to the respective roles of the first split body 32 and the second split body 31, the radial thickness of the first split body 32 is much smaller than the axial length thereof, that is, the first split body 32 has a cylindrical shape to ensure It forms a capacitive effect with the susceptor 1. As for the second split body 31, its radial thickness is such that it can block the gap between the lower end of the lining main body 2 and the outer peripheral wall of the first split body 32. Optionally, the second split body 31 is an annular plate body.
可選的，第一分體32的下端相對於第二分體31的下端面垂直向下凸出，以便於實現接地。Optionally, the lower end of the first split body 32 protrudes vertically downward with respect to the lower end surface of the second split body 31 to facilitate grounding.
另外，可選的，第一分體32的上端與介電質環4的上端相平齊；第一分體32的下端與介電質環4的下端相平齊，以增大第一分體32與基座1產生的電容C1。In addition, optionally, the upper end of the first body 32 is flush with the upper end of the dielectric ring 4; the lower end of the first body 32 is flush with the lower end of the dielectric ring 4 to increase the first point. The body 32 and the capacitor C1 generated by the susceptor 1.
在本實施例中，第二分體31與內襯主體2連為一體，換言之，第二分體31是內襯主體2的下端向內側彎折形成的水平彎折部。並且，第二分體31的自由端與第一分體32的外周壁相互間隔，且間隔距離為D2，從而實現第一分體32與內襯主體2相分離。需要說明的是，上述第二分體31的自由端與第一分體32的外周壁之間的間隔距離D2應盡可能地減小，以能夠防止電漿自二者之間的間隙通過，同時在該間隔距離D2足夠小時，第二分體31的自由端相當於接地。In the present embodiment, the second split body 31 is integrally connected to the lining main body 2, in other words, the second split body 31 is a horizontal bent portion formed by bending the lower end of the lining main body 2 inward. Further, the free ends of the second split body 31 are spaced apart from the outer peripheral wall of the first split body 32 by a distance D2, thereby achieving separation of the first split body 32 from the lining main body 2. It should be noted that the distance D2 between the free end of the second split body 31 and the outer peripheral wall of the first split body 32 should be reduced as much as possible to prevent the plasma from passing through the gap between the two. At the same time, when the separation distance D2 is sufficiently small, the free end of the second split body 31 corresponds to the ground.
由於第一分體32的下端通過基座1接地，內襯形成的等效模型如第3C圖所示，僅靠第一分體32與基座1產生的電容C1無法產生諧振。而且，第一分體32與內襯主體2之間產生的電容C2的量級遠小於上述電容C1，同時由於上述第一分體32的下端通過基座1接地，相當於內襯主體2相對於先前技術沒有垂直彎折部，從而產生的電感較小，從而根據諧振頻率的公式可知，由於上述電容C2和電感大大減小，使得系統的諧振頻率大大增加，從而射頻環境的頻率很難接近系統的諧振頻率，進而避免了系統產生諧振，從而可以增強製程穩定性。Since the lower end of the first split body 32 is grounded through the susceptor 1, the equivalent model of the inner liner is as shown in FIG. 3C, and the capacitance C1 generated by the first split body 32 and the susceptor 1 alone cannot resonate. Moreover, the capacitance C2 generated between the first split body 32 and the lining main body 2 is much smaller than the above-mentioned capacitor C1, and at the same time, since the lower end of the first split body 32 is grounded through the susceptor 1, the lining main body 2 is opposite. In the prior art, there is no vertical bending portion, so that the inductance is small, so that according to the formula of the resonance frequency, since the capacitance C2 and the inductance are greatly reduced, the resonance frequency of the system is greatly increased, and the frequency of the radio frequency environment is hard to be close. The resonant frequency of the system, which in turn avoids resonance in the system, thereby enhancing process stability.
請參閱第4圖，本發明第二實施例提供的反應腔室，其與上述第一實施例相比，其區別僅在於：第一分體32和第二分體31的結構不同。Referring to FIG. 4, a reaction chamber according to a second embodiment of the present invention is different from the first embodiment described above in that the structure of the first split body 32 and the second split body 31 are different.
具體地，內襯主體2與第二分體31連為一體；第二分體31與第一分體32連為一體。其中，第二分體31是自內襯主體2的下端向內側彎折形成的水平彎折部，該水平彎折部的自由端與第一分體32的外周壁連為一體。這同樣可以使內襯形成如第3B圖所示的等效模型，從而可以射頻環境的頻率很難接近系統的諧振頻率，進而避免了系統產生諧振，從而可以增強製程穩定性。Specifically, the lining main body 2 and the second split body 31 are integrally connected; the second split body 31 is integrally connected with the first split body 32. The second split body 31 is a horizontal bent portion that is bent inward from the lower end of the lining main body 2, and the free end of the horizontal bent portion is integrally connected with the outer peripheral wall of the first split body 32. This also makes the inner liner form an equivalent model as shown in FIG. 3B, so that it is difficult to approach the resonance frequency of the system in the frequency of the radio frequency environment, thereby avoiding resonance of the system, thereby enhancing process stability.
請參閱第5圖，本發明第三實施例提供的反應腔室，其與上述第一、第二實施例相比，其區別僅在於：第一分體32和第二分體31的結構不同。Referring to FIG. 5, a reaction chamber according to a third embodiment of the present invention is different from the first and second embodiments described above in that the structure of the first split body 32 and the second split body 31 are different. .
具體地，第二分體31與第一分體32連為一體，即，第二分體31的內周壁與第一分體32的外周壁連為一體，這同樣可以使內襯形成如第3B圖所示的等效模型。而且，由於內襯主體2的回路進一步縮短，因此進一步減小了內襯主體2的電感。另外，第二分體31的外周壁與內襯主體2之間具有間隔D3，該間隔D3應盡可能地減小，以能夠防止電漿自二者之間的間隙通過。Specifically, the second split body 31 is integrally connected with the first split body 32, that is, the inner peripheral wall of the second split body 31 is integrally connected with the outer peripheral wall of the first split body 32, which can also form the inner liner as the first The equivalent model shown in Figure 3B. Moreover, since the circuit of the lining main body 2 is further shortened, the inductance of the lining main body 2 is further reduced. Further, there is a space D3 between the outer peripheral wall of the second divided body 31 and the lining main body 2, and the interval D3 should be reduced as much as possible to prevent the plasma from passing through the gap therebetween.
綜上所述，本發明上述各個實施例提供的內襯，其通過採用分體式結構，可以避免系統產生諧振，從而可以增強製程穩定性。In summary, the lining provided by the above various embodiments of the present invention can avoid resonance of the system by using a split structure, thereby enhancing process stability.
另一技術方案，本發明實施例還提供一種反應腔室，其結構與第3A圖示出的反應腔室6的結構相類似，在反應腔室6內設置有基座1，以及本發明上述各個實施例提供的內襯。In another technical solution, the embodiment of the present invention further provides a reaction chamber having a structure similar to that of the reaction chamber 6 shown in FIG. 3A, in which the susceptor 1 is disposed in the reaction chamber 6, and the present invention The liners provided by the various embodiments.
在本實施例中，如第6A圖所示，基座1包括由上而下依次設置的基座本體11、隔離層12和金屬介面盤13，其中，基座本體11用於承載晶片。隔離層12採用陶瓷等絕緣材料製作，用於將基座本體11與金屬介面盤13電絕緣。金屬介面盤13接地。並且，第一分體32的下端通過與金屬介面盤13電導通而接地。In the present embodiment, as shown in FIG. 6A, the susceptor 1 includes a susceptor body 11, a separator 12, and a metal interface disk 13 which are disposed in this order from top to bottom, wherein the susceptor body 11 is used to carry a wafer. The isolation layer 12 is made of an insulating material such as ceramic for electrically insulating the base body 11 from the metal interface disk 13. The metal interface disk 13 is grounded. Further, the lower end of the first split body 32 is grounded by being electrically connected to the metal interface disk 13.
為了保證第一分體32的下端與金屬介面盤13電導通良好，如第6B圖所示，金屬介面盤13包括相對於隔離層12的外周壁凸出的第一凸臺131；並且，在第一分體32的下端設置有相對於第一分體32的外周壁凸出的第二凸臺321，該第二凸臺321與第一凸臺131相互疊置，且二者通過螺釘5固定連接。借助第二凸臺321與第一凸臺131，可以增大第一分體32與金屬介面盤13的接觸面積，從而保證第一分體32的下端與金屬介面盤13電導通良好。In order to ensure that the lower end of the first split body 32 is electrically connected to the metal interface disk 13, as shown in FIG. 6B, the metal interface disk 13 includes a first boss 131 protruding from the outer peripheral wall of the isolation layer 12; The lower end of the first split body 32 is provided with a second boss 321 protruding from the outer peripheral wall of the first split body 32, and the second boss 321 and the first boss 131 are overlapped with each other, and the two are passed through the screw 5. Fixed connection. By the second boss 321 and the first boss 131, the contact area of the first split 32 and the metal interface disk 13 can be increased, thereby ensuring good electrical conduction between the lower end of the first split 32 and the metal interface disk 13.
進一步較佳的，在第二凸臺321與第一凸臺131相接觸的二表面之間設置有導電層（圖中未示出），用於使第二凸臺321與第一凸臺131接觸良好。具體地，上述導電層可以採用電鍍的方式設置在第二凸臺321與第一凸臺131相接觸的二表面中的至少一表面上，即，上述導電層可以電鍍在第二凸臺321的下表面，和/或第一凸臺131的上表面。Further preferably, a conductive layer (not shown) is disposed between the two surfaces of the second boss 321 and the first boss 131 for making the second boss 321 and the first boss 131 Good contact. Specifically, the conductive layer may be disposed on at least one of the two surfaces of the second protrusion 321 and the first protrusion 131 in an electroplating manner, that is, the conductive layer may be plated on the second protrusion 321 The lower surface, and/or the upper surface of the first boss 131.
本發明實施例提供的反應腔室，其通過採用本發明上述各個實施例提供的內襯，可以避免系統產生諧振，從而可以增強製程穩定性。The reaction chamber provided by the embodiment of the present invention can avoid resonance of the system by using the inner liner provided by the above various embodiments of the present invention, thereby enhancing process stability.
另一技術方案，本發明實施例還提供一種半導體加工設備，該半導體加工設備包括本發明上述各個實施例提供的反應腔室。In another technical solution, an embodiment of the present invention further provides a semiconductor processing apparatus including the reaction chamber provided by the above various embodiments of the present invention.
本發明實施例提供的半導體加工設備，其通過採用本發明上述各個實施例提供的反應腔室，可以避免系統產生諧振，從而可以增強製程穩定性。The semiconductor processing apparatus provided by the embodiments of the present invention can avoid resonance of the system by using the reaction chamber provided by the above various embodiments of the present invention, thereby enhancing process stability.
可以理解的是，以上實施方式僅僅是為了說明本發明的原理而採用的示例性實施方式，然而本發明並不侷限於此。對於本領域內的普通技術人員而言，在不脫離本發明的精神和實質的情況下，可以做出各種變型和改進，這些變型和改進也視為本發明的保護範圍。It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.
C‧‧‧等效電容C‧‧‧ equivalent capacitance
C1、C2‧‧‧電容C1, C2‧‧‧ capacitor
D1‧‧‧間隔D1‧‧‧ interval
D2‧‧‧間隔距離D2‧‧‧ separation distance
L‧‧‧等效電感L‧‧‧ equivalent inductance
1‧‧‧基座1‧‧‧Base
2‧‧‧內襯主體2‧‧‧ lining body
4‧‧‧介電質環4‧‧‧ dielectric ring
5‧‧‧螺釘5‧‧‧ screws
6‧‧‧反應腔室6‧‧‧Reaction chamber
11‧‧‧基座本體11‧‧‧Base body
12‧‧‧隔離層12‧‧‧Isolation
13‧‧‧金屬介面盤13‧‧‧Metal interface plate
31‧‧‧第二分體31‧‧‧Second split
32‧‧‧第一分體32‧‧‧ first split
131‧‧‧第一凸臺131‧‧‧First boss
321‧‧‧第二凸臺321‧‧‧second boss
第1圖為現有的內襯等效形成的等效模型圖； 第2圖為採用現有的內襯獲得的自偏壓的曲線圖； 第3A圖為本發明第一實施例採用的反應腔室的剖視圖； 第3B圖為本發明第一實施例提供的內襯的剖視圖； 第3C圖為本發明第一實施例提供的內襯形成的等效模型圖； 第4圖為本發明第二實施例提供的內襯的剖視圖； 第5圖為本發明第三實施例提供的內襯的剖視圖； 第6A圖為本發明第四實施例提供的反應腔室的內襯的剖視圖； 第6B圖為第6A圖中I區域的放大圖。1 is an equivalent model diagram of a conventional inner liner; FIG. 2 is a graph of self-bias obtained by using a conventional inner liner; FIG. 3A is a reaction chamber used in the first embodiment of the present invention; 3B is a cross-sectional view of a liner provided by a first embodiment of the present invention; FIG. 3C is an equivalent model diagram of a liner formed by a first embodiment of the present invention; FIG. 4 is a second embodiment of the present invention 5 is a cross-sectional view of a liner provided by a third embodiment of the present invention; FIG. 6A is a cross-sectional view of a liner of a reaction chamber according to a fourth embodiment of the present invention; An enlarged view of the I area in Fig. 6A.
Claims (12)
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| ??201710708391.6 | 2017-08-17 | ||
| CN201710708391.6A CN107578975B (en) | 2017-08-17 | 2017-08-17 | Reaction chamber and semiconductor processing equipment |
| CN201710708391.6 | 2017-08-17 |
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| TW201913714A true TW201913714A (en) | 2019-04-01 |
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| SG11202001343SA (en) * | 2017-08-17 | 2020-03-30 | Beijing Naura Microelectronics Equipment Co Ltd | Liner, reaction chamber, and semiconductor processing device |
| CN112017933B (en) * | 2019-05-31 | 2024-03-26 | 北京北方华创微电子装备有限公司 | Liner, reaction chamber and semiconductor processing equipment |
| CN112185786B (en) * | 2019-07-03 | 2024-04-05 | 中微半导体设备(上海)股份有限公司 | Plasma processing apparatus and ground ring assembly for the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6170429B1 (en) * | 1998-09-30 | 2001-01-09 | Lam Research Corporation | Chamber liner for semiconductor process chambers |
| US8956457B2 (en) * | 2006-09-08 | 2015-02-17 | Tokyo Electron Limited | Thermal processing system for curing dielectric films |
| US20090188625A1 (en) * | 2008-01-28 | 2009-07-30 | Carducci James D | Etching chamber having flow equalizer and lower liner |
| US7987814B2 (en) * | 2008-04-07 | 2011-08-02 | Applied Materials, Inc. | Lower liner with integrated flow equalizer and improved conductance |
| US9953825B2 (en) * | 2011-11-24 | 2018-04-24 | Lam Research Corporation | Symmetric RF return path liner |
| CN103811258A (en) * | 2012-11-06 | 2014-05-21 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Plasma reaction chamber |
| US10163656B2 (en) * | 2013-11-16 | 2018-12-25 | Applied Materials, Inc. | Methods for dry etching cobalt metal using fluorine radicals |
| CN104746043B (en) * | 2013-12-31 | 2017-10-13 | 北京北方华创微电子装备有限公司 | Reaction chamber and plasma processing device |
| CN105304519A (en) * | 2014-07-11 | 2016-02-03 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Lining, lining preparation method and reaction chamber |
| US10041868B2 (en) * | 2015-01-28 | 2018-08-07 | Lam Research Corporation | Estimation of lifetime remaining for a consumable-part in a semiconductor manufacturing chamber |
| CN106340478A (en) * | 2016-10-09 | 2017-01-18 | 无锡宏纳科技有限公司 | Support bench of wafer spray apparatus |
| CN207183210U (en) * | 2017-08-17 | 2018-04-03 | 北京北方华创微电子装备有限公司 | Reaction chamber and semiconductor processing equipment |
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| CN107578975A (en) | 2018-01-12 |
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