TWI690973B - Lining, reaction chamber and semiconductor processing equipment - Google Patents

Lining, reaction chamber and semiconductor processing equipment Download PDF

Info

Publication number
TWI690973B
TWI690973B TW107125039A TW107125039A TWI690973B TW I690973 B TWI690973 B TW I690973B TW 107125039 A TW107125039 A TW 107125039A TW 107125039 A TW107125039 A TW 107125039A TW I690973 B TWI690973 B TW I690973B
Authority
TW
Taiwan
Prior art keywords
reaction chamber
lining
boss
peripheral wall
pedestal
Prior art date
Application number
TW107125039A
Other languages
Chinese (zh)
Other versions
TW201913714A (en
Inventor
趙晉榮
常楷
Original Assignee
大陸商北京北方華創微電子裝備有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大陸商北京北方華創微電子裝備有限公司 filed Critical 大陸商北京北方華創微電子裝備有限公司
Publication of TW201913714A publication Critical patent/TW201913714A/en
Application granted granted Critical
Publication of TWI690973B publication Critical patent/TWI690973B/en

Links

Images

Landscapes

  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)

Abstract

本發明提供一種內襯、反應腔室及半導體加工設備,該內襯設置在反應腔室內,且包括:內襯主體,其環繞設置在反應腔室的側壁內側,且接地;第一部分,其環繞在設置於反應腔室內的基座的周圍,且第一部分的下端通過基座接地;並且,在第一部分的內周壁與基座的外周壁之間環繞設置有介電質環;第二部分,其環繞設置在內襯主體的下端與第一部分的外周壁之間。本發明提供的內襯,其可以避免系統產生諧振,從而可以增強製程穩定性。 The invention provides an inner lining, a reaction chamber and a semiconductor processing equipment. The inner lining is arranged in the reaction chamber and includes: an inner lining main body which is arranged around the inner side of the side wall of the reaction chamber and is grounded; Around the pedestal provided in the reaction chamber, and the lower end of the first part is grounded through the pedestal; and a dielectric ring is provided between the inner peripheral wall of the first part and the outer peripheral wall of the pedestal; the second part, It surrounds the lower end of the lining body and the outer peripheral wall of the first part. The lining provided by the present invention can avoid resonance of the system, thereby enhancing the stability of the manufacturing process.

Description

內襯、反應腔室及半導體加工設備 Lining, reaction chamber and semiconductor processing equipment

本發明涉及半導體製造技術領域,具體地,涉及一種內襯、反應腔室及半導體加工設備。 The invention relates to the technical field of semiconductor manufacturing, in particular, to an inner liner, a reaction chamber and semiconductor processing equipment.

在蝕刻製程中,必須嚴格控制電漿反應腔室的大量製程參數以保持高質量的蝕刻結果。其中,腔室內部結構的優化設計對設備本身的製程性能及製程蝕刻結果有著決定性的作用。 In the etching process, a large number of process parameters of the plasma reaction chamber must be strictly controlled to maintain high-quality etching results. Among them, the optimal design of the internal structure of the chamber has a decisive effect on the process performance of the device itself and the etching results of the process.

目前,通常在蝕刻機的反應腔室內部增設有內襯,該內襯主要用於改善腔室內部電漿的有效流動性,同時能夠約束電漿,保護腔室內壁與底部不被蝕刻。另外,增設的內襯更便於機台腔室的維護。 At present, a lining is usually added inside the reaction chamber of the etching machine. The lining is mainly used to improve the effective fluidity of the plasma inside the chamber, and at the same time, it can restrain the plasma and protect the inner wall and the bottom of the chamber from being etched. In addition, the additional lining makes it easier to maintain the machine chamber.

現有的內襯環繞設置在反應腔室的側壁內側,且內襯的上端接地,內襯的下端設置有向其內側彎折的水平彎折部和自該水平彎折部垂直向上彎折的垂直彎折部,其中,垂直彎折部環繞在基座的周圍,用於改變基座及其周圍環境的阻抗模型,增強了基座邊緣處的電場強度,從而可以提高晶片邊緣的蝕刻效率,進而可以提高晶片的蝕刻均勻性。水平彎折部用於防止電漿自內襯與基座之間的間隙通過,進入腔室底部,以保護腔室底部不被蝕刻。 The existing lining is arranged around the inside of the side wall of the reaction chamber, and the upper end of the lining is grounded, and the lower end of the lining is provided with a horizontal bending portion bent toward the inner side and vertically bent upward from the horizontal bending portion Vertical bending part, wherein the vertical bending part surrounds the pedestal, used to change the impedance model of the pedestal and its surrounding environment, enhances the electric field strength at the edge of the pedestal, and thus can improve the etching efficiency of the wafer edge, Furthermore, the etching uniformity of the wafer can be improved. The horizontal bending part is used to prevent the plasma from passing through the gap between the lining and the base and enter the bottom of the chamber to protect the bottom of the chamber from being etched.

上述內襯在實際應用中不可避免地存在以下問題:由於僅內襯的上端接地,導致在射頻環境中內襯的回路較長,內襯的彎折結構會呈現較大的電感特性,同時上述垂直彎折部與基座之間形 成電容特性,從而內襯等效形成了如第1圖示出的等效模型。該等效模型的諧振頻率的公式為:

Figure 107125039-A0305-02-0003-2
The above lining inevitably has the following problems in practical applications: Because only the upper end of the lining is grounded, the loop of the lining is longer in the RF environment, and the bending structure of the lining will exhibit greater inductance characteristics. Capacitive characteristics are formed between the vertical bent portion and the base, so that the liner equivalently forms an equivalent model as shown in FIG. The formula of the resonance frequency of the equivalent model is:
Figure 107125039-A0305-02-0003-2

其中,f為諧振頻率;L為等效電感,由內襯的彎折結構產生;C為等效電容,由上述垂直彎折部與基座產生。在射頻環境的頻率接近系統的諧振頻率時,系統產生諧振,從而造成射頻環境的直流自偏壓突變,如第2圖所示,直流自偏壓突然降低,出現異常曲線,從而影響製程穩定性。 Among them, f is the resonance frequency; L is the equivalent inductance, which is generated by the bending structure of the inner liner; C is the equivalent capacitance, which is generated by the above-mentioned vertical bending portion and the base. When the frequency of the RF environment is close to the resonant frequency of the system, the system resonates, causing a sudden change in the DC self-bias voltage in the RF environment. As shown in Figure 2, the DC self-bias voltage suddenly decreases and an abnormal curve appears, which affects the stability of the process .

本發明旨在至少解決先前技術中存在的技術問題之一,提出了一種內襯、反應腔室及半導體加工設備,其可以避免系統產生諧振,從而可以增強製程穩定性。 The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a lining, a reaction chamber, and a semiconductor processing equipment, which can avoid resonance of the system and thus can enhance the stability of the process.

為實現本發明的目的而提供一種內襯,設置在反應腔室內,該內襯包括:內襯主體,其環繞設置在該反應腔室的側壁內側,且接地;第一部分,其環繞在設置於該反應腔室內的基座的周圍,且該第一部分的下端通過該基座接地;並且,在該第一部分的內周壁與該基座的外周壁之間環繞設置有介電質環;第二部分,其環繞設置在該內襯主體的下端與該第一部分的外周壁之間。 To achieve the object of the present invention, an inner lining is provided, which is provided in the reaction chamber. The inner lining includes: an inner lining main body, which surrounds the inner side wall of the reaction chamber, and is grounded; the first part, which surrounds the Around the pedestal in the reaction chamber, and the lower end of the first part is grounded through the pedestal; and a dielectric ring is provided between the inner peripheral wall of the first part and the outer peripheral wall of the pedestal; second Part, which is circumferentially disposed between the lower end of the liner body and the outer peripheral wall of the first part.

可選的,該第二部分與該內襯主體連為一體。 Optionally, the second part is integral with the liner body.

可選的,該第二部分與該第一部分連為一體。 Optionally, the second part is integrated with the first part.

可選的,該內襯主體與該第二部分連為一體;該第二部分與該第一部分連為一體。 Optionally, the liner body is integral with the second part; the second part is integral with the first part.

可選的,該第一部分的下端相對於該第二部分的下端面垂直向下凸出。 Optionally, the lower end of the first portion protrudes vertically downward relative to the lower end surface of the second portion.

可選的,該第一部分的上端與該介電質環的上端相平齊;該第一部分的下端與該介電質環的下端相平齊。 Optionally, the upper end of the first part is flush with the upper end of the dielectric ring; the lower end of the first part is flush with the lower end of the dielectric ring.

另一技術方案,本發明還提供一種反應腔室,在該反應腔室內設置有基座,在該反應腔室內還設置有如本發明提供的上述內襯。 In another technical solution, the present invention further provides a reaction chamber, a base is provided in the reaction chamber, and the above-mentioned lining provided in the present invention is further provided in the reaction chamber.

可選的,該基座包括由上而下依次設置的基座本體、隔離層和金屬介面盤,其中,該金屬介面盤接地;該第一部分的下端與該金屬介面盤電導通。 Optionally, the pedestal includes a pedestal body, an isolation layer, and a metal interface plate disposed in this order from top to bottom, wherein the metal interface plate is grounded; the lower end of the first portion is electrically connected to the metal interface plate.

可選的,該金屬介面盤包括相對於該隔離層的外周壁凸出的第一凸臺;在該第一部分的下端設置有相對於該第一部分的外周壁凸出的第二凸臺,該第二凸臺與該第一凸臺相互疊置,且二者通過螺釘固定連接。 Optionally, the metal interface plate includes a first boss protruding relative to the outer peripheral wall of the isolation layer; a second boss protruding relative to the outer peripheral wall of the first portion is provided at the lower end of the first portion, the The second boss and the first boss overlap each other, and the two are fixedly connected by screws.

可選的,在該第二凸臺與該第一凸臺相接觸的二表面之間設置有導電層。 Optionally, a conductive layer is provided between the two surfaces contacting the second boss and the first boss.

可選的,該導電層採用電鍍的方式設置在該第二凸臺與該第一凸臺相接觸的二表面中的至少一表面上。 Optionally, the conductive layer is disposed on at least one of the two surfaces where the second boss and the first boss are in contact by electroplating.

另一技術方案,本發明還提供一種半導體加工設備,包括本發明提供的上述反應腔室。 In another technical solution, the present invention also provides a semiconductor processing device, including the above-mentioned reaction chamber provided by the present invention.

本發明具有以下有益效果:本發明提供的內襯,其包括內襯主體、第一部分和第二部分,其中,內襯主體環繞設置在反應腔室的側壁內側,且接地。第一部分環繞在基座的周圍,且該第一部分的下端通過該基座接地,並且在第一部分的內周壁與基座的外周壁之間設置有介電質環。第二部分設置在內襯的下端與 第一部分的外周壁之間,用於防止電漿自二者之間的間隙通過。由於第一部分的下端通過基座接地,僅靠該第一部分與基座產生的電容無法產生諧振。此外,第一部分與內襯主體之間產生的電容的量級遠小於第一部分與基座產生的電容,同時由於上述第一部分的下端接地,使得內襯產生的電感較小,從而根據諧振頻率的公式可知,系統的諧振頻率大大增加,使得射頻環境的頻率很難接近系統的諧振頻率,進而避免了系統產生諧振,從而可以增強製程穩定性。 The present invention has the following beneficial effects: The lining provided by the present invention includes a lining body, a first portion, and a second portion, wherein the lining body is disposed around the inside of the side wall of the reaction chamber and is grounded. The first part surrounds the base, and the lower end of the first part is grounded through the base, and a dielectric ring is provided between the inner peripheral wall of the first part and the outer peripheral wall of the base. The second part is set at the lower end of the lining with The outer wall of the first part is used to prevent the plasma from passing through the gap between the two. Since the lower end of the first part is grounded through the base, the capacitance generated by the first part and the base alone cannot generate resonance. In addition, the magnitude of the capacitance generated between the first part and the liner body is much smaller than that generated by the first part and the base. At the same time, due to the grounding of the lower end of the first part, the inductance generated by the liner is small, so according to the resonance frequency It can be seen from the formula that the resonance frequency of the system is greatly increased, making it difficult for the frequency of the RF environment to be close to the resonance frequency of the system, thereby avoiding the resonance of the system, which can enhance the stability of the process.

本發明提供的反應腔室,其通過採用本發明提供的上述內襯,可以避免系統產生諧振,從而可以增強製程穩定性。 The reaction chamber provided by the present invention can avoid the resonance of the system by adopting the above-mentioned lining provided by the present invention, thereby enhancing the stability of the process.

本發明提供的半導體加工設備,其通過採用本發明提供的上述反應腔室,可以避免系統產生諧振,從而可以增強製程穩定性。 The semiconductor processing equipment provided by the present invention can avoid the resonance of the system by adopting the above reaction chamber provided by the present invention, thereby enhancing the stability of the manufacturing process.

C:等效電容 C: equivalent capacitance

C1、C2:電容 C1, C2: capacitance

D1:間隔 D1: interval

D2:間隔距離 D2: Separation distance

L:等效電感 L: equivalent inductance

1:基座 1: pedestal

2:內襯主體 2: lined body

4:介電質環 4: Dielectric ring

5:螺釘 5: screw

6:反應腔室 6: reaction chamber

11:基座本體 11: Base body

12:隔離層 12: isolation layer

13:金屬介面盤 13: Metal interface board

31:第二部分 31: Part Two

32:第一部分 32: Part One

131:第一凸臺 131: First boss

321:第二凸臺 321: Second boss

第1圖為現有的內襯等效形成的等效模型圖;第2圖為採用現有的內襯獲得的自偏壓的曲線圖;第3A圖為本發明第一實施例採用的反應腔室的剖視圖;第3B圖為本發明第一實施例提供的內襯的剖視圖;第3C圖為本發明第一實施例提供的內襯形成的等效模型圖;第4圖為本發明第二實施例提供的內襯的剖視圖;第5圖為本發明第三實施例提供的內襯的剖視圖;第6A圖為本發明第四實施例提供的反應腔室的內襯的剖視圖;第6B圖為第6A圖中I區域的放大圖。 Figure 1 is an equivalent model diagram of the existing liner equivalent formation; Figure 2 is a graph of the self-bias voltage obtained by using the existing liner; Figure 3A is a reaction chamber used in the first embodiment of the present invention 3B is a cross-sectional view of the liner provided by the first embodiment of the present invention; FIG. 3C is an equivalent model diagram of the liner formed by the first embodiment of the present invention; FIG. 4 is a second embodiment of the present invention Figure 5 is a cross-sectional view of the liner provided by the third embodiment; Figure 6A is a cross-sectional view of the liner provided by the third embodiment of the present invention; Figure 6A is a cross-sectional view of the liner of the reaction chamber provided by the fourth embodiment of the present invention; Figure 6B is Enlarged view of area I in Figure 6A.

為使本領域的技術人員更好地理解本發明的技術方案,下面結合附圖來對本發明提供的內襯、反應腔室及半導體加工設備進行詳細描述。 In order to enable those skilled in the art to better understand the technical solutions of the present invention, the lining, the reaction chamber and the semiconductor processing equipment provided by the present invention will be described in detail below with reference to the drawings.

請一併參閱第3A圖和第3B圖,本發明第一實施例提供一種內襯,其設置在反應腔室6內,該反應腔室6內還設置有基座1,用於承載被加工工件,且基座1接地。內襯包括內襯主體2、第一部分32和第二部分31。其中,內襯主體2環繞設置在反應腔室6的側壁內側,且接地,在本實施例中,內襯主體2的上端與反應腔室6的側壁連接,且電導通,並且反應腔室6的側壁接地,從而實現內襯主體2接地。 Please refer to FIG. 3A and FIG. 3B together, the first embodiment of the present invention provides a liner, which is disposed in the reaction chamber 6, and the reaction chamber 6 is also provided with a base 1 for carrying the processed The workpiece, and the base 1 is grounded. The liner includes a liner body 2, a first portion 32, and a second portion 31. Wherein, the lining body 2 is disposed around the inside of the side wall of the reaction chamber 6 and is grounded. In this embodiment, the upper end of the lining body 2 is connected to the side wall of the reaction chamber 6 and is electrically conductive, and the reaction chamber 6 The side wall of is grounded, so that the liner body 2 is grounded.

第一部分32環繞在基座1的周圍,且第一部分32的下端通過基座1接地,並且在第一部分32的內周壁與基座1的外周壁之間的間隔D1中設置有介電質環4。第二部分31設置在內襯主體2的下端與第一部分32的外周壁之間,用於防止電漿自內襯主體2與第一部分32之間的間隙通過,擴散至反應腔室6的底部。 The first part 32 surrounds the base 1, and the lower end of the first part 32 is grounded through the base 1, and a dielectric ring is provided in the interval D1 between the inner peripheral wall of the first part 32 and the outer peripheral wall of the base 1 4. The second portion 31 is provided between the lower end of the lining body 2 and the outer peripheral wall of the first portion 32 to prevent the plasma from passing through the gap between the lining body 2 and the first portion 32 to diffuse to the bottom of the reaction chamber 6 .

由於基座1的表面與電漿鞘層之間會呈現電容效應,並產生電場,該電場在基座1的邊緣處會向外扭曲而造成場強減小,從而使得晶片邊緣的蝕刻效率降低。為此,通過設置上述第一部分32,同時在第一部分32的內周壁與基座1的外周壁之間設置有介電質環4,可以使第一部分32與基座1產生的電容為C1,這可以改變基座1及其周圍環境的阻抗模型,增強了基座邊緣處的電場強度,從而可以提高晶片邊緣的蝕刻效率,進而增大晶片的蝕刻均勻性。上述介電質環4可以起到增大電容C1的作用,該介電質環4例如可以採用陶瓷製作。 Due to the capacitance effect between the surface of the susceptor 1 and the plasma sheath, and an electric field is generated, the electric field will be twisted outward at the edge of the susceptor 1 to cause a decrease in the field strength, thereby reducing the etching efficiency of the wafer edge . For this reason, by providing the above-mentioned first portion 32, and at the same time providing a dielectric ring 4 between the inner peripheral wall of the first portion 32 and the outer peripheral wall of the base 1, the capacitance generated by the first portion 32 and the base 1 can be C1, This can change the impedance model of the susceptor 1 and its surrounding environment, enhance the electric field strength at the edge of the susceptor, and thus can improve the etching efficiency of the wafer edge, thereby increasing the etching uniformity of the wafer. The above-mentioned dielectric ring 4 can function to increase the capacitance C1. The dielectric ring 4 can be made of ceramics, for example.

在實際應用中,根據第一部分32和第二部分31各自的作用,第一部分32的徑向厚度遠小於其軸向長度,即,第一部分32呈筒狀,以保證其 與基座1之間形成電容效應。至於第二部分31,其徑向厚度應保證其能夠遮擋內襯主體2的下端與第一部分32的外周壁之間的間隙。可選的,第二部分31為環形板體。 In practical applications, according to the respective functions of the first part 32 and the second part 31, the radial thickness of the first part 32 is much smaller than its axial length, that is, the first part 32 is cylindrical to ensure that A capacitance effect is formed with the base 1. As for the second portion 31, its radial thickness should ensure that it can cover the gap between the lower end of the liner body 2 and the outer peripheral wall of the first portion 32. Optionally, the second part 31 is an annular plate body.

可選的,第一部分32的下端相對於第二部分31的下端面垂直向下凸出,以便於實現接地。 Optionally, the lower end of the first portion 32 protrudes vertically downward relative to the lower end surface of the second portion 31, so as to facilitate grounding.

另外,可選的,第一部分32的上端與介電質環4的上端相平齊;第一部分32的下端與介電質環4的下端相平齊,以增大第一部分32與基座1產生的電容C1。 In addition, optionally, the upper end of the first portion 32 is flush with the upper end of the dielectric ring 4; the lower end of the first portion 32 is flush with the lower end of the dielectric ring 4 to increase the first portion 32 and the base 1 Produced capacitance C1.

在本實施例中,第二部分31與內襯主體2連為一體,換言之,第二部分31是內襯主體2的下端向內側彎折形成的水平彎折部。並且,第二部分31的自由端與第一部分32的外周壁相互間隔,且間隔距離為D2,從而實現第一部分32與內襯主體2相分離。需要說明的是,上述第二部分31的自由端與第一部分32的外周壁之間的間隔距離D2應盡可能地減小,以能夠防止電漿自二者之間的間隙通過,同時在該間隔距離D2足夠小時,第二部分31的自由端相當於接地。 In this embodiment, the second portion 31 is integral with the lining body 2. In other words, the second portion 31 is a horizontal bent portion formed by bending the lower end of the lining body 2 inward. Moreover, the free end of the second portion 31 and the outer peripheral wall of the first portion 32 are spaced apart from each other by a distance D2, so that the first portion 32 is separated from the liner body 2. It should be noted that the distance D2 between the free end of the second portion 31 and the outer peripheral wall of the first portion 32 should be reduced as much as possible to prevent the plasma from passing through the gap between the two. The separation distance D2 is sufficiently small, and the free end of the second part 31 is equivalent to ground.

由於第一部分32的下端通過基座1接地,內襯形成的等效模型如第3C圖所示,僅靠第一部分32與基座1產生的電容C1無法產生諧振。而且,第一部分32與內襯主體2之間產生的電容C2的量級遠小於上述電容C1,同時由於上述第一部分32的下端通過基座1接地,相當於內襯主體2相對於先前技術沒有垂直彎折部,從而產生的電感較小,從而根據諧振頻率的公式可知,由於上述電容C2和電感大大減小,使得系統的諧振頻率大大增加,從而射頻環境的頻率很難接近系統的諧振頻率,進而避免了系統產生諧振,從而可以增強製程穩定性。 Since the lower end of the first part 32 is grounded through the base 1, the equivalent model formed by the lining is shown in FIG. 3C, and the capacitance C1 generated by the first part 32 and the base 1 alone cannot generate resonance. Moreover, the magnitude of the capacitance C2 generated between the first portion 32 and the liner body 2 is much smaller than that of the capacitance C1, and because the lower end of the first portion 32 is grounded through the base 1, it is equivalent to the liner body 2 not having The vertical bending part results in a small inductance, so according to the formula of the resonance frequency, the resonance frequency of the system is greatly increased due to the greatly reduced capacitance C2 and inductance, so that the frequency of the RF environment is difficult to approach the resonance frequency of the system , Thereby avoiding resonance in the system, which can enhance process stability.

請參閱第4圖,本發明第二實施例提供的反應腔室,其與上述第一實施例相比,其區別僅在於:第一部分32和第二部分31的結構不同。 Referring to FIG. 4, the reaction chamber provided in the second embodiment of the present invention is different from the first embodiment described above in that the structure of the first part 32 and the second part 31 is different.

具體地,內襯主體2與第二部分31連為一體;第二部分31與第一部分32連為一體。其中,第二部分31是自內襯主體2的下端向內側彎折形成的水平彎折部,該水平彎折部的自由端與第一部分32的外周壁連為一體。這同樣可以使內襯形成如第3B圖所示的等效模型,從而可以射頻環境的頻率很難接近系統的諧振頻率,進而避免了系統產生諧振,從而可以增強製程穩定性。 Specifically, the lining body 2 is integrally connected with the second portion 31; the second portion 31 is integrally connected with the first portion 32. The second portion 31 is a horizontal bent portion formed by being bent inward from the lower end of the lining body 2, and the free end of the horizontal bent portion is integral with the outer peripheral wall of the first portion 32. This can also make the lining form an equivalent model as shown in Figure 3B, so that the frequency of the RF environment is difficult to approach the resonance frequency of the system, thereby avoiding the resonance of the system, which can enhance the stability of the process.

請參閱第5圖,本發明第三實施例提供的反應腔室,其與上述第一、第二實施例相比,其區別僅在於:第一部分32和第二部分31的結構不同。 Referring to FIG. 5, the reaction chamber provided in the third embodiment of the present invention is different from the above-mentioned first and second embodiments only in that the structure of the first part 32 and the second part 31 are different.

具體地,第二部分31與第一部分32連為一體,即,第二部分31的內周壁與第一部分32的外周壁連為一體,這同樣可以使內襯形成如第3B圖所示的等效模型。而且,由於內襯主體2的回路進一步縮短,因此進一步減小了內襯主體2的電感。另外,第二部分31的外周壁與內襯主體2之間具有間隔D3,該間隔D3應盡可能地減小,以能夠防止電漿自二者之間的間隙通過。 Specifically, the second part 31 is connected with the first part 32, that is, the inner peripheral wall of the second part 31 is connected with the outer peripheral wall of the first part 32, which can also form the lining as shown in FIG. 3B Effect model. Moreover, since the loop of the lining body 2 is further shortened, the inductance of the lining body 2 is further reduced. In addition, there is an interval D3 between the outer peripheral wall of the second portion 31 and the lining body 2, and the interval D3 should be reduced as much as possible to prevent the plasma from passing through the gap between the two.

綜上所述,本發明上述各個實施例提供的內襯,其通過採用分體式結構,可以避免系統產生諧振,從而可以增強製程穩定性。 In summary, the inner liner provided by the above embodiments of the present invention, by adopting a split structure, can avoid resonance in the system, thereby enhancing process stability.

另一技術方案,本發明實施例還提供一種反應腔室,其結構與第3A圖示出的反應腔室6的結構相類似,在反應腔室6內設置有基座1,以及本發明上述各個實施例提供的內襯。 In another technical solution, an embodiment of the present invention further provides a reaction chamber having a structure similar to that of the reaction chamber 6 shown in FIG. 3A. A base 1 is provided in the reaction chamber 6, and The liner provided by various embodiments.

在本實施例中,如第6A圖所示,基座1包括由上而下依次設置的基座本體11、隔離層12和金屬介面盤13,其中,基座本體11用於承載晶片。隔離層12採用陶瓷等絕緣材料製作,用於將基座本體11與金屬介面盤13電 絕緣。金屬介面盤13接地。並且,第一部分32的下端通過與金屬介面盤13電導通而接地。 In this embodiment, as shown in FIG. 6A, the susceptor 1 includes a susceptor body 11, an isolation layer 12, and a metal interface plate 13 arranged in this order from top to bottom. The susceptor body 11 is used to carry a wafer. The isolation layer 12 is made of insulating materials such as ceramics, and is used to electrically connect the base body 11 and the metal interface board 13 insulation. The metal interface board 13 is grounded. Moreover, the lower end of the first portion 32 is grounded by electrically conducting with the metal interface plate 13.

為了保證第一部分32的下端與金屬介面盤13電導通良好,如第6B圖所示,金屬介面盤13包括相對於隔離層12的外周壁凸出的第一凸臺131;並且,在第一部分32的下端設置有相對於第一部分32的外周壁凸出的第二凸臺321,該第二凸臺321與第一凸臺131相互疊置,且二者通過螺釘5固定連接。借助第二凸臺321與第一凸臺131,可以增大第一部分32與金屬介面盤13的接觸面積,從而保證第一部分32的下端與金屬介面盤13電導通良好。 In order to ensure good electrical conduction between the lower end of the first portion 32 and the metal interface plate 13, as shown in FIG. 6B, the metal interface plate 13 includes a first boss 131 protruding relative to the outer peripheral wall of the isolation layer 12; The lower end of the 32 is provided with a second boss 321 protruding relative to the outer peripheral wall of the first portion 32. The second boss 321 and the first boss 131 overlap each other, and the two are fixedly connected by screws 5. With the aid of the second boss 321 and the first boss 131, the contact area between the first portion 32 and the metal interface plate 13 can be increased, thereby ensuring good electrical conduction between the lower end of the first portion 32 and the metal interface plate 13.

進一步較佳的,在第二凸臺321與第一凸臺131相接觸的二表面之間設置有導電層(圖中未示出),用於使第二凸臺321與第一凸臺131接觸良好。具體地,上述導電層可以採用電鍍的方式設置在第二凸臺321與第一凸臺131相接觸的二表面中的至少一表面上,即,上述導電層可以電鍍在第二凸臺321的下表面,和/或第一凸臺131的上表面。 Further preferably, a conductive layer (not shown in the figure) is provided between the two surfaces where the second boss 321 and the first boss 131 are in contact, for making the second boss 321 and the first boss 131 Good contact. Specifically, the conductive layer may be plated on at least one of the two surfaces of the second boss 321 and the first boss 131, that is, the conductive layer may be plated on the second boss 321 The lower surface, and/or the upper surface of the first boss 131.

本發明實施例提供的反應腔室,其通過採用本發明上述各個實施例提供的內襯,可以避免系統產生諧振,從而可以增強製程穩定性。 The reaction chamber provided by the embodiment of the present invention can avoid the resonance of the system by using the lining provided by the foregoing embodiments of the present invention, thereby enhancing the stability of the process.

另一技術方案,本發明實施例還提供一種半導體加工設備,該半導體加工設備包括本發明上述各個實施例提供的反應腔室。 According to another technical solution, an embodiment of the present invention further provides a semiconductor processing device, and the semiconductor processing device includes the reaction chamber provided by the foregoing embodiments of the present invention.

本發明實施例提供的半導體加工設備,其通過採用本發明上述各個實施例提供的反應腔室,可以避免系統產生諧振,從而可以增強製程穩定性。 The semiconductor processing equipment provided by the embodiments of the present invention can avoid the resonance of the system by using the reaction chambers provided by the foregoing embodiments of the present invention, thereby enhancing the stability of the process.

可以理解的是,以上實施方式僅僅是為了說明本發明的原理而採用的示例性實施方式,然而本發明並不侷限於此。對於本領域內的普通技術人員而言,在不脫離本發明的精神和實質的情況下,可以做出各種變型和改進,這些變型和改進也視為本發明的保護範圍。 It can be understood that the above embodiments are only exemplary embodiments adopted to explain the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various variations and improvements can be made without departing from the spirit and essence of the present invention, and these variations and improvements are also considered to be within the protection scope of the present invention.

C1:電容 C1: capacitance

D1:間隔 D1: interval

1:基座 1: pedestal

2:內襯主體 2: lined body

6:反應腔室 6: reaction chamber

31:第二部分 31: Part Two

32:第一部分 32: Part One

Claims (12)

一種內襯,設置在一反應腔室內,其特徵在於,該內襯包括:一內襯主體,其環繞設置在該反應腔室的側壁內側,且接地;一第一部分,其環繞在設置於該反應腔室內的基座的周圍,且該第一部分的下端通過該基座接地;並且,在該第一部分的內周壁與該基座的外周壁之間環繞設置有一介電質環,以增大該第一部分與該基座產生的電容;一第二部分,其環繞設置在該內襯主體的下端與該第一部分的外周壁之間。 An inner lining is provided in a reaction chamber, characterized in that the inner lining includes: an inner lining main body, which is arranged around the inner side wall of the reaction chamber, and is grounded; a first part, which is arranged around the reaction chamber Around the pedestal in the reaction chamber, and the lower end of the first part is grounded through the pedestal; and a dielectric ring is provided between the inner peripheral wall of the first part and the outer peripheral wall of the pedestal to increase The capacitance generated by the first part and the base; a second part, which is disposed between the lower end of the liner body and the outer peripheral wall of the first part. 如申請專利範圍第1項所述之內襯,其中,該第二部分與該內襯主體連為一體。 The liner as described in item 1 of the patent application scope, wherein the second part is integral with the liner body. 如申請專利範圍第1項所述之內襯,其中,該第二部分與該第一部分連為一體。 The liner as described in item 1 of the patent application scope, wherein the second part is integral with the first part. 如申請專利範圍第1所述之內襯,其中,該內襯主體與該第二部分連為一體;該第二部分與該第一部分連為一體。 The lining as described in the first patent application, wherein the lining body is integral with the second part; the second part is integral with the first part. 如申請專利範圍第2項至第4項任一項所述之內襯,其中,該第一部分的下端相對於該第二部分的下端面垂直向下凸出。 The liner according to any one of items 2 to 4 of the patent application scope, wherein the lower end of the first part protrudes vertically downward relative to the lower end surface of the second part. 如申請專利範圍第1項至第4項任一項所述之內襯,其中,該第一部分的上端與該介電質環的上端相平齊;該第一部分的下端與該介電質環的下端相平齊。 The liner as described in any one of claims 1 to 4, wherein the upper end of the first part is flush with the upper end of the dielectric ring; the lower end of the first part is flush with the dielectric ring The lower end is flush. 一種反應腔室,在該反應腔室內設置有一基座,其特徵在於,在該反應腔室內還設置有如申請專利範圍第1項至第6項任一項所述的內襯。 A reaction chamber is provided with a pedestal in the reaction chamber, wherein the reaction chamber is further provided with an inner lining as described in any one of items 1 to 6 of the patent application. 如申請專利範圍第7項所述之反應腔室,其中,該基座包括由上而下依次設置的一基座本體、一隔離層和一金屬介面盤,其中,該金屬介面盤接地;該第一部分的下端與該金屬介面盤電導通。 The reaction chamber as described in item 7 of the patent application scope, wherein the pedestal includes a pedestal body, an isolation layer and a metal interface plate arranged in this order from top to bottom, wherein the metal interface plate is grounded; The lower end of the first part is electrically connected to the metal interface plate. 如申請專利範圍第8項所述之反應腔室,其中,該金屬介面盤包括相對於該隔離層的外周壁凸出的一第一凸臺;在該第一部分的下端設置有相對於該第一部分的外周壁凸出的一第二凸臺,該第二凸臺與該第一凸臺相互疊置,且二者通過一螺釘固定連接。 The reaction chamber as described in item 8 of the patent application scope, wherein the metal interface plate includes a first boss protruding relative to the outer peripheral wall of the isolation layer; a lower end of the first portion is provided with respect to the first A second boss protruding from a part of the outer peripheral wall, the second boss and the first boss overlap each other, and the two are fixedly connected by a screw. 如申請專利範圍第9項所述之反應腔室,其中,在該第二凸臺與該第一凸臺相接觸的二表面之間設置有一導電層。 The reaction chamber as described in item 9 of the patent application scope, wherein a conductive layer is provided between the two surfaces contacting the second boss and the first boss. 如申請專利範圍第10項所述之反應腔室,其中,該導電層採用電鍍的方式設置在該第二凸臺與該第一凸臺相接觸的二表面中的至少一表面上。 The reaction chamber of claim 10, wherein the conductive layer is disposed on at least one of the two surfaces where the second boss and the first boss are in contact by electroplating. 一種半導體加工設備,其特徵在於,包括申請專利範圍第7項至第11項任一項所述之反應腔室。 A semiconductor processing device, characterized in that it includes the reaction chamber described in any one of the patent application items 7 to 11.
TW107125039A 2017-08-17 2018-07-20 Lining, reaction chamber and semiconductor processing equipment TWI690973B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
??201710708391.6 2017-08-17
CN201710708391.6A CN107578975B (en) 2017-08-17 2017-08-17 Reaction chamber and semiconductor processing equipment
CN201710708391.6 2017-08-17

Publications (2)

Publication Number Publication Date
TW201913714A TW201913714A (en) 2019-04-01
TWI690973B true TWI690973B (en) 2020-04-11

Family

ID=61035124

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107125039A TWI690973B (en) 2017-08-17 2018-07-20 Lining, reaction chamber and semiconductor processing equipment

Country Status (2)

Country Link
CN (1) CN107578975B (en)
TW (1) TWI690973B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11202001343SA (en) * 2017-08-17 2020-03-30 Beijing Naura Microelectronics Equipment Co Ltd Liner, reaction chamber, and semiconductor processing device
CN112017933B (en) * 2019-05-31 2024-03-26 北京北方华创微电子装备有限公司 Liner, reaction chamber and semiconductor processing equipment
CN112185786B (en) * 2019-07-03 2024-04-05 中微半导体设备(上海)股份有限公司 Plasma processing apparatus and ground ring assembly for the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW420847B (en) * 1998-09-30 2001-02-01 Lam Res Corp Chamber liner for semiconductor processing chambers
TW200947172A (en) * 2008-01-28 2009-11-16 Applied Materials Inc Etching chamber having flow equalizer and lower liner
TW201334104A (en) * 2008-04-07 2013-08-16 Applied Materials Inc Lower liner with integrated flow equalizer and improved conductance
TW201336358A (en) * 2011-11-24 2013-09-01 Lam Res Corp Symmetric RF return path liner
CN103811258A (en) * 2012-11-06 2014-05-21 北京北方微电子基地设备工艺研究中心有限责任公司 Plasma reaction chamber
US20150140812A1 (en) * 2013-11-16 2015-05-21 Applied Materials, Inc. Methods for dry etching cobalt metal using fluorine radicals
CN105304519A (en) * 2014-07-11 2016-02-03 北京北方微电子基地设备工艺研究中心有限责任公司 Lining, lining preparation method and reaction chamber

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8956457B2 (en) * 2006-09-08 2015-02-17 Tokyo Electron Limited Thermal processing system for curing dielectric films
CN104746043B (en) * 2013-12-31 2017-10-13 北京北方华创微电子装备有限公司 Reaction chamber and plasma processing device
US10041868B2 (en) * 2015-01-28 2018-08-07 Lam Research Corporation Estimation of lifetime remaining for a consumable-part in a semiconductor manufacturing chamber
CN106340478A (en) * 2016-10-09 2017-01-18 无锡宏纳科技有限公司 Support bench of wafer spray apparatus
CN207183210U (en) * 2017-08-17 2018-04-03 北京北方华创微电子装备有限公司 Reaction chamber and semiconductor processing equipment

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW420847B (en) * 1998-09-30 2001-02-01 Lam Res Corp Chamber liner for semiconductor processing chambers
TW200947172A (en) * 2008-01-28 2009-11-16 Applied Materials Inc Etching chamber having flow equalizer and lower liner
TW201334104A (en) * 2008-04-07 2013-08-16 Applied Materials Inc Lower liner with integrated flow equalizer and improved conductance
TW201336358A (en) * 2011-11-24 2013-09-01 Lam Res Corp Symmetric RF return path liner
CN103811258A (en) * 2012-11-06 2014-05-21 北京北方微电子基地设备工艺研究中心有限责任公司 Plasma reaction chamber
US20150140812A1 (en) * 2013-11-16 2015-05-21 Applied Materials, Inc. Methods for dry etching cobalt metal using fluorine radicals
CN105304519A (en) * 2014-07-11 2016-02-03 北京北方微电子基地设备工艺研究中心有限责任公司 Lining, lining preparation method and reaction chamber

Also Published As

Publication number Publication date
TW201913714A (en) 2019-04-01
CN107578975B (en) 2020-06-19
CN107578975A (en) 2018-01-12

Similar Documents

Publication Publication Date Title
TWI690973B (en) Lining, reaction chamber and semiconductor processing equipment
KR102164678B1 (en) Radio frequency (rf) ground return arrangements
JP2017092448A5 (en) Edge ring assembly and system for plasma processing
JP5727281B2 (en) Inductively coupled plasma processing equipment
CN106898534B (en) Plasma confinement ring, plasma processing apparatus and processing method for substrate
WO2019243882A3 (en) Semiconductor structure enhanced for high voltage applications
US20150243483A1 (en) Tunable rf feed structure for plasma processing
JP2014017292A (en) Plasma processing apparatus, and plasma processing method
CN104746043B (en) Reaction chamber and plasma processing device
TW201913710A (en) Lower electrode assembly and process chamber
TWI681436B (en) Faraday shield and reaction chamber
CN207183210U (en) Reaction chamber and semiconductor processing equipment
CN108573847B (en) Reaction chamber and semiconductor processing equipment
JP3718093B2 (en) Semiconductor manufacturing equipment
CN105655221A (en) Semiconductor processing device
US20210193434A1 (en) Liner, reaction chamber and semiconductor processing equipment
TWI741439B (en) Plasma processing device
CN106783490A (en) Liner grounding assembly, reaction chamber and semiconductor processing equipment
TWI623962B (en) Electrode structure and ICP etching machine
CN207082507U (en) Reaction chamber
KR101253297B1 (en) Inductively coupled plasma antenna and Plasma processing apparatus using the same
CN108573845B (en) Reaction chamber and semiconductor processing equipment
CN207183209U (en) Faraday shield and reaction chamber
TW202117799A (en) Plasma processor and method for preventing arc damage to confinement ring capable of preventing the confinement ring from being broken down by arc under a low frequency radio frequency electric field
CN112017933B (en) Liner, reaction chamber and semiconductor processing equipment