TW201810548A - 電子單元 - Google Patents
電子單元 Download PDFInfo
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- TW201810548A TW201810548A TW106110296A TW106110296A TW201810548A TW 201810548 A TW201810548 A TW 201810548A TW 106110296 A TW106110296 A TW 106110296A TW 106110296 A TW106110296 A TW 106110296A TW 201810548 A TW201810548 A TW 201810548A
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- 239000000758 substrate Substances 0.000 claims abstract description 66
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- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 description 20
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- KQZLRWGGWXJPOS-NLFPWZOASA-N 1-[(1R)-1-(2,4-dichlorophenyl)ethyl]-6-[(4S,5R)-4-[(2S)-2-(hydroxymethyl)pyrrolidin-1-yl]-5-methylcyclohexen-1-yl]pyrazolo[3,4-b]pyrazine-3-carbonitrile Chemical compound ClC1=C(C=CC(=C1)Cl)[C@@H](C)N1N=C(C=2C1=NC(=CN=2)C1=CC[C@@H]([C@@H](C1)C)N1[C@@H](CCC1)CO)C#N KQZLRWGGWXJPOS-NLFPWZOASA-N 0.000 description 3
- 229940125877 compound 31 Drugs 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
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- 230000002238 attenuated effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 238000007493 shaping process Methods 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
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- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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Abstract
本發明係關於具有固定至基板的至少一個電子元件之電子單元,其中,該電子元件係配置於該基板的第一凹部內。設有尤其是導線的電性傳導接觸元件,其建立該電子元件與配置於該第二凹部的基部之接觸點之間的電性傳導連接。
Description
本發明係關於具有固定至基板的至少一個電子元件之電子單元。
一直以來,電子單元朝微型化發展的趨勢不曾中斷。電子單元應該在性能至少沒有改變或性能增進了的情況下在構成上越來越緊湊。在手攜式電腦、智慧型手機及所謂的穿戴式裝置的領域,更是日益殷切對於電子單元有越來越薄之要求。在汽車工程或其他領域的消費者也索求更加緊湊的解決方案。
藉由將電子元件配置在基板的第一凹部內達成了根據本發明提供更小型的電子單元之目的。還設有至少一個電性傳導接觸元件(contact element),此接觸元件建立起配置在第二凹部的基部之接觸點(contact point)與電子元件與之間的電性傳導連接。該接觸元件係為例如導線(wire)。該基板詳言之係為電路板,例如印刷電路板。
根據本發明,不僅將至少一個電子元件配置在凹部內,而且也將為了其接觸(contacting)連接至電子
元件之導線的連接也配置在凹部內。特別是第一及第二凹部係分開地形成。可規定在第一凹部內只配置單一個電子元件。可選地且額外地考慮只在第二凹部內設置接觸元件至接觸點之連接,亦即不在第二凹部內配置任何其他的元件。
根據本發明之電子單元一般而言,可具有任何所需數目之第一及第二凹部。
電子單元的構成高度可藉由使元件及元件的連接同時“陷入”(“sinking”)之手段而實質地減小。
電子單元最佳地形成為部件(component),尤其是SMD(Surface Mounted Device)部件,其依序安裝在例如電路的更大電子單元中。
本發明的進一步實施例係揭示於申請專利範圍、說明書及隨附的圖式中。
根據一個實施例,第一凹部的基部與第二凹部的基部大體上係配置於一個平面中。第一凹部及第二凹部可大體上一樣深。亦可組配凹部為第一及第二凹部的個別頂緣大體上係配置於一個平面中。凹部係為例如基板中的相同或不同深度的凹陷(depression)。可將上述組配變化態樣其特徵可單獨或一起實施來對於從工藝製造的面向來看有利之電子單元的緊湊構造做出貢獻。
尤其是,第一及第二凹部係形成在一個共同的、單片的基板,亦即該基板係形成為容置有凹部之連續體(當然也可具有開口或孔)。基板可例如是印刷電路板
(Printed Circuit Board:PCB)。
對於某些特定的應用而言,如果在電子元件與接觸點之間橫向存在有基板的材料的話可能很有利。例如,第一凹部及/或第二凹部具有面向各個其他的凹部之側壁(side wall)(或一個以上的側壁部)。第一凹部及/或第二凹部較佳具有從所有側面圍繞凹部的基部之側壁。
電子元件較佳固定至第一凹部的基部。該固定可為電性導通的或絕緣的。電子元件可具有連接接觸元件且配置在遠離第一凹部的基部的電子元件的一側之接觸部。電子元件係為例如半導體元件。
第一凹部及/或第二凹部可至少部分地塗覆有電性傳導材料。一般而言,如前述,第一凹部及/或第二凹部可為基板上的凹陷,亦即對應凹部的基部(視需要全部或部分地塗覆)係由基板所形成。然而,可選地第一凹部及/或第二凹部亦可由穿過基板之通道開口所形成。此開口在一側是藉由與基板的材料不同的材料(例如金屬)加以封閉,藉此形成對應凹部的基部。此製程可為塗覆製程(coating process)的一部分。若所選擇的材料為電性傳導的,則該基部本身就形成接觸點。
電子單元可具有至少兩個第一凹部,其中各個第一凹部中分別配置至少一個電子元件,其中在該至少兩個第一凹部間配置屏蔽(shielding)。該屏蔽保護兩個電子元件中的一個免於受到其他電子元件發出的不想要的零散輻射。此點對於具有發射器/接收器功能或感測器功能之
電子單元特別有利。
該屏蔽可包括從由基板所界定之平面突出或從基板的表面延伸出之***部(elevated portion)。該***部可例如形成一種凸脊(ridge)或牆。
根據一個實施例,該***部係至少一部分(較佳全部)由基板的材料所形成。尤其是,其係與基板組配為一體。
為了增進屏蔽效果,該***部可至少部份方向塗覆特別是屏蔽電磁輻射的材料。如此就可使得***部實質上對於所要屏蔽之輻射而不可滲透。屏蔽可例如基於所使用的塗覆材料的反射及/或吸收輻射之效果。電性傳導材料具有如此的屏蔽效果,但一些非金屬材料,例如反射性的矽酸鹽(silicate)或吸收有機化合物也同樣具有。
根據一個實施例,該電性傳導材料係為特別是以球銲(ball bonding)手段連接至接觸點之銲線(bonding wire)。
本發明還關於製造特別是根據前述實施例中的一個而設計的電子單元之方法。該電子單元係包括固定至基板、尤其是固定電路板之至少一個電子元件,該電子元件係配置在基板的第一凹部內且藉由至少一條銲線(bonding wire)的手段而電性傳導地連接至配置在第二凹部的基部之接觸點。
根據本發明之方法的一個實施例,首先建立接觸點與銲線之間的連接。接著建立銲線與電子元件(反
向銲接(reverse bonding))之間的連接。銲線與電子元件之間的連接較佳地設於遠離第一凹部的基部之電子元件一側。
接觸點與銲線之間的連接可藉由球銲而建立。可選地或額外地,銲線與電子元件之間的連接可藉由楔銲(wedge bonding)而建立。
特別是接觸點與銲線間的連接建立之前,可規定在電子元件的接觸部產生銲線的熔融球(molten ball)。接著,例如特別是藉由楔銲,在此球上建立銲線與電子元件間的連接(亦即進行所謂的反向“ball-stitch-on-ball”,反向BSOB)。
以下參照單純以實例表現的有利的實施例及參照隨附的圖式來說明本發明。
10、10’、10”、10a-10f‧‧‧電子單元
12‧‧‧基板
12’12”‧‧‧基板部
13‧‧‧表面
14、14’‧‧‧電子元件
16、16’、16”‧‧‧凹部
18、18’‧‧‧凹部
20‧‧‧貫通開口
21‧‧‧側壁
22、24‧‧‧基部
26、26’‧‧‧導線
28‧‧‧連接
30‧‧‧導線部
31‧‧‧灌注密封化合物
32‧‧‧接觸點
34‧‧‧牆
36、36’、36”‧‧‧塗料
S‧‧‧輻射
第1圖係根據本發明之電子單元的第一實施例之斷面圖。
第2圖係根據本發明之電子單元的第二實施例之斷面圖。
第3圖係根據本發明之電子單元的第三實施例之透視圖。
第4圖及第5圖係具有凹部之基板的不同斷面
第6圖至第10圖係根據本發明之電子單元的進一步實施例。
第11圖係第一及第二凹部的不同實施例之兩個斷面圖。
第12至14圖係產生第一及第二凹部之製造方法的一個實施例。
第15圖及第16圖係根據本發明之電子單元的又另一個實施例之平面圖及斷面圖。
第1圖顯示電子單元10包括基板12(詳言之係電路板)及電子元件14。然而,電子元件14並不是配置在基板12的表面13,而是配置在凹部16內,使電子元件14的頂緣僅略為突伸超出第1圖中的頂側、或略為超出基板12的表面13。凹部16亦可為至少如此深到完全容納電子元件14。
凹部16包括貫穿基板12之貫通開口20,且貫通開口20的一側在塗覆製程的過程中再度封閉。亦即,由塗覆層材料所形成之基部22係藉由塗覆製程以本身已知之方式所形成。凹部16的側壁及表面13的鄰近區域也在此製程中塗覆(或在獨立步驟中)。塗覆材料、塗覆厚度及/或塗覆區段的選擇可視各別的需要而改變。
電子元件14可用習用方式固定至基部22。電子元件14之接觸(contacting)可以此方式裝設。然而,亦可透過特別是黏著劑接合之方式將電子元件14固定至基部22,而不建立電性接觸。
電子元件14較佳為半導體元件。為了能夠將
電子元件14連接至電端子(electrical terminal),經設置導線(wire)16,其係電性傳導地固定至設於電子元件14的上側之接觸面。可利用例如楔銲(wedge bonding)而建立導線26與接觸點間之連接。
導線26建立起與第二凹部18的基部24之電性傳導連接28。基部24係電性傳導的且以與凹部16的基部22相似或相同之方式產生。導線26與基部24間的連接28係藉由“球銲(ball bonding)”而進行。基部24因而作為與導線26的接觸點,此接觸點可進而透過導體軌道(conductor track)或其他手段而連接至其他的端子以將電子單元10例如整合到一個電路中。
電子元件14與基部24間的連接可合宜地以下述的方式建立:
首先使導線26的一端熔融而形成一個熔融的球,並將之壓抵在對應的接觸面(此處為基部24)上。然後將導線26拉到第二接觸點(此處為電子元件14的頂側的接觸面)並以超音波、熱及/或壓力的手段使之接合於在該處。此舉例說明的方法即為“反向球銲/楔銲製程(reverse ball/wedge bonding process”)。其他的接觸方法也同樣可使用。亦可在上述的程序之前先在例如電子元件14的頂側的接觸點上形成“球”。然後將導線26切斷再接著進行“反向球銲/楔銲製程”,此時導線26並不是直接固定至電子元件14的接觸點,而是導線26固定在球所在的位置(此即反向“Bond Stitch on Ball”(reverse
BSOB))。
因為將大量的熱導入導線26來形成熔融的球,所以導線26與連接28接合的部分30會短暫地承受到高的熱負載(thermal load)。部分30因而會比導線26之受到較低的熱負載的區域更加地機械性敏感。凹部18內的連接28之陷入之構成使得受到熱負載的區域30在打線製程(bonding process)中較可能不會發生機械性變形。也就是說,可向上拉出而不會使得整體配置的構成高度具有負面影響。
為了將上述的配置固定住以保護其元件,其以適合的材料(灌注密封化合物(casting compound)31)將其密封。
第2圖顯示電子單元的替代實施例10’。其中,並沒有貫通開口,而是藉由基板12(此處為例如電路板)本身形成凹部16、18的基部22、24。凹部16、18因而為基板12的材料中的凹陷,其並未貫穿基板12。亦同樣可在電子單元中結合採用藉由貫通開口而產生之凹部及形成為凹陷之凹部(參照第11圖)。可知凹部16、18可全面地或局部地塗覆。作為示例所示的凹部18具有與第1圖所示的實施例10模擬配置中的導線26連接之局部塗覆部(接觸點32)。
為了保護電子單元10’及其元件,也使用灌注密封化合物(未圖示)將其密封。
在本揭示的框架下,“基板”一詞可做較寬
的解釋,其通常可以對應地配置為導線架(lead frane)。導線架也可具有複數個相分隔的但藉由塑膠而彼此連接之載置部(carrier section)。然而,基板12較佳為電路板。
電子單元10、10’的凹部16、18係包括在各側的個別基部22、24鄰接且因此包圍各側的基部22、24之側壁21。其通常可想像使凹部16、18的一個或多個側(局部地)開放。不過,較佳在連接28或接觸點32與電子元件14之間設置有基板部12’。亦即,對應的凹部16、18較佳地具有面對其他凹部18或16的至少一個側壁21或側壁部。基板部12’可具有與鄰近於凹部16、18的基板12之的其他部分大致相同之厚度。
第3圖顯示電子單元10”的透視圖。電子單元10”包括分別配置於凹部16及16’內的兩個電子元件14、14’。各電子元件各別透過導線26或26’而連接至凹部18或18’中的接觸點或個別基部。凹部16、16、18、18’係設計成例如第1圖中所示者。
在特別是電子元件14、14’為一個發出電磁輻射之發射元件(transmitter component)及一個對應的接收元件時,在電子元件14、14’的相鄰配置上的電子元件14、14’之間設置可靠的屏蔽是合理的。在本例中該屏蔽係藉由在電子元件14、14’間延伸之牆34而設置。其係從由基板12所界定之平面升起之***部。換言之,牆34係從基板12的表面13延伸。
牆34係為連接至基板12之一片材料或為基
板12的一部分。此具有容易製造之優點。可藉由例如材料剝離之製造方法,亦即藉由一個或多個合適的製程(例如蝕刻、銑削及/或雷射剝蝕(laser ablation)等)從基板空白處將牆34周圍的區域去除掉而成形。在此方面,凹部16、18、16’、18’或對應的貫通開口20或基板也可藉由非貫穿的凹陷而形成(參見第2及11圖)。
然而,亦可考慮藉助於MID(Molded Interconnect Device)技術來形成基板12。在此方面,其係產生模塑互連器件(molded interconnect device)之製程。這些互連器件因而係具有合適地佈設之金屬的導體軌道(conductor track)及/或塗覆部之射出成形塑膠部件。
另一種製造方法係所謂的3D印刷。亦即,基板12係藉由此類材料的手段按照希望的幾何圖案逐層地建造使得凹部16、18、16’、18’及/或牆34如所需的”建設性地”製造。因而,在理想的情況下便不再需要剝離的工序。
一種同樣地基板12的”建設性”製造變型的提供具有不同的幾何圖案之層的積層。例如,將合適的形狀(例如具有提供凹部16、18、16’、18’的開口之形狀)的纖維墊(fabric mat)相堆疊且利用樹脂使之相連結。亦可將基板12配置在特定的區域較厚,例如在該處設置較多數量的纖維墊層,舉例來說,以形成牆34。
亦可為前述製程的混合形式。例如,部分基板可用剝離法步驟製作然後將之層疊到另一部份基板(基
座,作為規則自身是一個積層元件)。
通常,所有的製造變型都得到單片基板12。
從所呈現例子可以理解,在牆34於兩側都設有塗料36(但在特定的應用中單側的塗料也可即已充分),其如有需要可連接至其他的塗覆部。在本實施例中,牆34的左側的塗料36係與凹部16的塗接觸。塗料36的材料較佳地選擇成能夠使得牆34不會為電子元件14及/或14’所發出的輻射所穿透,或至少能夠使輻射衰減。
牆34較佳地也界定灌注密封化合物31的頂緣以形成沒有突起邊緣之緊湊構造。
第4圖顯示設有牆34但沒有電子單元14、14’或導線26、26’之基板12的透視圖。其中,凹部16係部分剖視來顯示其構成大致如第1圖所說明的。
第5圖顯示完全剖視之第4圖的基板12以看清楚牆34的設計係從配置於凹部16、16’間之基板部12”延伸。基板12與牆34係形成為一體。牆34在兩側都具有塗料36,其分別連接至凹部16’(左邊)及凹部16(右邊)的個別塗覆。
利用牆來屏蔽輻射之概念可使電子元件及接觸點位於分開的凹部內之概念而獨立實施。
第6至10圖係藉由實例方式顯示根據本發明之電子單元的可能實施例所構成的變化。
電子單元10a係例如包括兩個凹部18,其各自用接觸於同時連接至電子元件14的二個導線26之一者
(比照第6圖)。
對比於此,電子單元10b係具有兩個電子單元14,其各自配置於一個獨立的凹部16內且各自連接於一個導線26。二個導線26依次連接至配置於一個共同凹部18內之分開的接觸點32(比照第7圖)。
電子單元10c係不同於二個電子單元14配置在一個共同的凹部16內的電子單元10b(比照第8圖)。
在電子單元10d中,電子元件係固然如電子單元10c一樣配置於一個共同的凹部16內。但是,卻與電子單元10a一樣設有兩個分開的凹部18(比照第9圖)。
電子單元10e具有一個電子元件14配置在一個另外的凹部16內(比照第10圖)。八個導線26經固定至電子元件14,且依次連接至配置於八個分開的凹部18之分開的接觸點32。
可輕易地將上述的實施例予以混合。可按照各別的需要而改變凹部16、18的數目及構成(例如幾何形狀、塗料...等),如同可從例如第11圖看出的。凹部16、18在此處係具有不同的深度。
以下參照第12至14圖來說明製作凹部16、18的實施例之變型。
第12圖顯示基板12的一側有塗料。此塗料36’為例如金屬膜。凹部16、18藉由材料剝離製程(material stripping process)引入基板12中。該方法較佳地為雷射剝蝕法。若塗料36’為金屬的(例如銅),則當基板12被完全
貫穿時(第13圖所示的狀態),剝離便自動結束。若使用的雷射功率太高,則入射的雷射光束入射到塗料36’面向基板的表面即反射。塗料36’可視需要而局部去除(參照第13圖)。
可選擇性地接著施加塗料36”以部份地或完全地襯在凹部16、18(參照第14圖)。當需要時,可與塗料36’之施加同時或在另外的步驟以部份地或完全地塗覆或覆蓋塗料36’。塗料36’、36”的材料可相同或不同。
第15圖顯示具有電子元件14(例如LED)之電子單元10f,其中電子元件14係配置在開放於一側的經塗覆(塗料36”)的凹部16”內。電子元件14以流暢方式朝右方放射電磁輻射S。與電子單元14連接之銲線26係連接至配置在周向封閉的凹部18內的接觸點32(參照第16圖)。電子單元10f的元件及特別是其中的電性接觸係由灌注密封化合物31加以保護。
10‧‧‧電子單元
12‧‧‧基板
12’‧‧‧基板部
13‧‧‧表面
14‧‧‧電子元件
16‧‧‧凹部
18‧‧‧凹部
20‧‧‧貫通開口
21‧‧‧側壁
22、24‧‧‧基部
26‧‧‧導線
28‧‧‧連接
30‧‧‧導線部
31‧‧‧灌注密封化合物
Claims (23)
- 一種電子單元,其具有固定至基板(12)、尤其是固定至電路板的至少一個電子元件(14、14’),其中,該電子元件(14、14’)係經配置於該基板(12)的第一凹部(16、16’、16”)內,且其中尤其是導線的電性傳導接觸元件(26、26’)係設置用來建立在該電子元件(14、14’)與配置於第二凹部(18、18’)的基部(24)之接觸點(32)間的電性傳導連接。
- 如申請專利範圍第1項所述之電子單元,其特徵在於:該第一凹部(16、16’、16”)的基部(22)與該第二凹部(18、18’)的該基部(24)基本上係配置於一個平面中。
- 如申請專利範圍第1或2項所述之電子單元,其特徵在於:該第一凹部(16、16’、16”)及該第二凹部(18、18’)係基本上相同深度。
- 如申請專利範圍第1至3項中任一項所述之電子單元,其特徵在於:該第一及該第二凹部(16、16’、16”及18、18’)的個別頂緣基本上係配置於一個平面中。
- 如申請專利範圍第1至4項中任一項所述之電子單元,其特徵在於:該第一及該第二凹部(16、16’、16”及18、18’)係形成於一個共同的、單片的基板(12)中。
- 如申請專利範圍第1至5項中任一項所述之電子單元,其特徵在於:該第一及/或該第二凹部(16、16’、16”及/或18、18’)係具有面向個別其他的凹部(18’、18及/或16、16’、16”)之側壁(21)或至少一側壁部,該第一及/或該第二凹部(16、16’及/或18、18’)尤其具有圍繞在所有側的該凹部(16、16’及/或18、18’)的基部(22、24)之側壁(21)。
- 如申請專利範圍第1至6項中任一項所述之電子單元,其特徵在於:該電子元件(14、14’)與該接觸點(32)之間橫向設有該基板(12)的材料。
- 如申請專利範圍第1至7項中任一項所述之電子單元,其特徵在於:該電子元件(14、14’)係固定至該第一凹部(16、16’、16”)的基部(22)。
- 如申請專利範圍第1至8項中任一項所述之電子單元,其特徵在於:該電子元件(14、14’)係具有連接於該接觸元件(26、26’)且配置在該電子元件(14、14’)遠離該第一凹部(16、16’、16”)的該基部(22)的一側之接觸部。
- 如申請專利範圍第1至9項中任一項所述之電子單元,其特徵在於: 該電子元件(14、14’)係半導體部件。
- 如申請專利範圍第1至10項中任一項所述之電子單元,其特徵在於:該第一凹部(16、16’、16”)及/或該第二凹部(18、18’)係至少部分地塗覆有電性傳導材料。
- 如申請專利範圍第1至11項中任一項所述之電子單元,其特徵在於:該第一及/或該第二凹部(16、16’、16”、18、18’)係包括該基板(12)的貫通開口(20),其藉由不同於該基板(12)材料的材料封閉於一側。
- 如申請專利範圍第1至12項中任一項所述之電子單元,其特徵在於:該電子單元具有至少兩個第一凹部(16、16’、16”),其中配置個別的至少一個電子元件(14、14’),屏蔽經配置在該至少二個第一凹部(16、16’)之間。
- 如申請專利範圍第13項所述之電子單元,其特徵在於:該屏蔽係包括***部(34),該***部(34)由該基板(12)所界定的平面突伸或由該基板之表面延伸。
- 如申請專利範圍第14項所述之電子單元,其特徵在於:該***部(34)係至少部分地由該基板(12)的材料所形成。
- 如申請專利範圍第14或15項所述之電子單元,其特徵在於:該***部(34)係與該基板(12)為一體所形成。
- 如申請專利範圍第14至16項中任一項所述之電子單元,其特徵在於:該***部(34)係至少區段地塗覆有尤其是至少部分地屏蔽電磁輻射之膜(36)。
- 如申請專利範圍第1至17項中任一項所述之電子單元,其特徵在於:該電性傳導接觸元件係銲線(26、26’)。
- 如申請專利範圍第1至18項中任一項所述之電子單元,其特徵在於:該接觸元件(26、26’)係以球銲方式連接至該第二凹部(18、18’)的該基部(24)的該接觸點(32)。
- 一種製造電子單元之方法,該電子單元尤其是根據申請專利範圍第1至19項中任一項所設計,其中,該電子單元係包括固定至基板(12)、尤其是固定至電路板之至少一個電子元件(14、14’),該電子元件(14、14’)係配置在該基板的第一凹部(16、16’、16”)內,且藉由銲線(26、26’)的方式電性傳導地連接至配置在第二凹部(18、18’)的基部(24)之接觸點(32)。
- 如申請專利範圍第20項所述之方法,其特徵在於:先建立該接觸點(32)與該銲線(26、26’)間的連接(28),且接著建立該銲線(26、26’)與該電子元件(14、14’)間之連接,尤其是該銲線(26、26’)與該電子元件(14、14’)之間的該連接經設置在該電子元件(14、14’)遠離第該一凹部(16、16’、16”)的該 基部(22)的一側。
- 如申請專利範圍第20或21項所述之方法,其特徵在於:該接觸點(32)與該銲線(26、26’)之間的該連接(28)係藉由球銲而建立及/或該銲線(26、26’)與該電子元件(14、14’)之間的該連接係藉由楔銲而建立。
- 如申請專利範圍第21或22項所述之方法,其特徵在於:特別是該接觸點(32)與該銲線(26、26’)之間的該連接(28)建立之前,在該電子元件(14、14’)的接觸部上產生該銲線(26、26’)的熔融球。
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DE102016106134.4A DE102016106134A1 (de) | 2016-04-04 | 2016-04-04 | Elektronische Einheit |
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JPH0444252A (ja) * | 1990-06-07 | 1992-02-14 | Fuji Electric Co Ltd | 配線基板 |
JP3506002B2 (ja) * | 1997-07-28 | 2004-03-15 | 松下電工株式会社 | プリント配線板の製造方法 |
US7985980B2 (en) * | 2007-10-31 | 2011-07-26 | Sharp Kabushiki Kaisha | Chip-type LED and method for manufacturing the same |
KR20110018777A (ko) * | 2009-08-18 | 2011-02-24 | 삼성엘이디 주식회사 | 발광 다이오드 패키지 |
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