TW201743561A - Level shifter - Google Patents

Level shifter Download PDF

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TW201743561A
TW201743561A TW105118790A TW105118790A TW201743561A TW 201743561 A TW201743561 A TW 201743561A TW 105118790 A TW105118790 A TW 105118790A TW 105118790 A TW105118790 A TW 105118790A TW 201743561 A TW201743561 A TW 201743561A
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node
transistor
gate
voltage
input signal
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TW105118790A
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Chinese (zh)
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TWI584596B (en
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張堂龍
吳政晃
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智原科技股份有限公司
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Priority to TW105118790A priority Critical patent/TWI584596B/en
Priority to CN201610648454.9A priority patent/CN107517054A/en
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Publication of TW201743561A publication Critical patent/TW201743561A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

A level shifter is capable of transferring an input signal to an output signal. When the input signal changes from a ground voltage to a first supplying voltage, a first current mirror and a first current path control circuit of the level shifter are activated to pull up an output signal to a second supplying voltage. When the input signal changes from the first supplying voltage to the ground voltage, a second current mirror and a second current path control circuit of the level shifter are activated to pull up an inverted output signal to the second supplying voltage.

Description

轉壓器 Converter

本發明係有關一種介面電路(interface circuit)，尤指介面電路中的一種轉壓器。 The present invention relates to an interface circuit, and more particularly to a voltage converter in an interface circuit.

轉壓器可接收信號範圍較小的輸入信號，並將其對應地轉換為信號範圍較大的輸出信號，是介面電路(interface circuit)中的重要構築方塊。譬如說，在IC晶片中，將特定的信號由核心電壓(core voltage)的信號範圍轉換至輸出入電壓(IO voltage)的信號範圍。基本上，核心電壓的信號範圍可以是0到1.5伏特，而輸出入電壓的信號範圍為0到3.3伏特。為了在兩種信號範圍間進行轉換，就需要使用到轉壓器，用以將0到1.5伏特的輸入信號轉換為0到3.3伏特的輸出信號。 The converter can receive an input signal with a small signal range and convert it correspondingly into an output signal with a large signal range, which is an important building block in the interface circuit. For example, in an IC chip, a specific signal is converted from a signal range of a core voltage to a signal range of an input-input voltage (IO voltage). Basically, the core voltage can range from 0 to 1.5 volts, while the input and output voltages range from 0 to 3.3 volts. In order to convert between the two signal ranges, a transducer is required to convert an input signal of 0 to 1.5 volts into an output signal of 0 to 3.3 volts.

請參考第1圖，其所繪示為習知轉壓器。此轉壓器10可將信號範圍介於電壓VDDL至GND的輸入信號IN轉為信號範圍在電壓VDDH至GND間的輸出信號OUT。其中，電源電壓VDDL可為例如1.5伏特，電源電壓VDDH可為例如3.3伏特，接地電壓GND為0伏特，其中，電源電壓VDDH大於電源電壓VDDL，且電源電壓VDDL大於接地電壓GND。 Please refer to FIG. 1 , which is a conventional pressure converter. The converter 10 can convert the input signal IN having a signal range of the voltage VDDL to GND into an output signal OUT having a signal range between the voltages VDDH and GND. The power supply voltage VDDL may be, for example, 1.5 volts, the power supply voltage VDDH may be, for example, 3.3 volts, and the ground voltage GND is 0 volts, wherein the power supply voltage VDDH is greater than the power supply voltage VDDL, and the power supply voltage VDDL is greater than the ground voltage GND.

轉壓器10包括一P型電晶體MP1、P型電晶體MP2、N型電晶體MN1與N型電晶體MN2，其中，P型電晶體MP1的源極連接至電源電壓VDDH，汲極連接至節點a，以及閘極連接至節點b。P型電晶體MP2源極連接至電源電壓VDDH，汲極連接至節點b，以及閘極連接至節點a。 The converter 10 includes a P-type transistor MP1, a P-type transistor MP2, an N-type transistor MN1, and an N-type transistor MN2, wherein the source of the P-type transistor MP1 is connected to the power supply voltage VDDH, and the drain is connected to Node a, and the gate are connected to node b. The P-type transistor MP2 source is connected to the power supply voltage VDDH, the drain is connected to the node b, and the gate is connected to the node a.

再者，N型電晶體MN1汲極連接至節點a，源極連接至接地電壓GND，以及閘極接收輸入信號IN。N型電晶體MN2汲極連接至節點b，源極連接至接地電壓GND，以及閘極接收反相的輸入信號INB。其中，節點a更做為第一輸出端，用以產生反相的輸出信號OUTB，以及節點b更做為第二輸出端，用以產生輸出信號OUT。 Furthermore, the N-type transistor MN1 is connected to the node a, the source is connected to the ground voltage GND, and the gate receives the input signal IN. The N-type transistor MN2 is connected to the node b, the source is connected to the ground voltage GND, and the gate receives the inverted input signal INB. The node a is further used as a first output terminal for generating an inverted output signal OUTB, and the node b is further configured as a second output terminal for generating an output signal OUT.

當轉壓器10的輸入信號IN為1.5伏特且反相的輸入信號INB為0伏特時，N型電晶體MN1與P型電晶體MP2為開啟(turn on)，N型電晶體MN2與P型電晶體MP1為關閉(turn off)。因此，輸出信號OUT為3.3伏特的電源電壓VDDH，反相的輸出信號OUTB為0伏特的接地電壓GND。 When the input signal IN of the converter 10 is 1.5 volts and the inverted input signal INB is 0 volts, the N-type transistor MN1 and the P-type transistor MP2 are turned on, and the N-type transistor MN2 and P-type The transistor MP1 is turned off. Therefore, the output signal OUT is a power supply voltage VDDH of 3.3 volts, and the inverted output signal OUTB is a ground voltage GND of 0 volts.

當轉壓器10的輸入信號IN為0伏特且反相的輸入信號INB為1.5伏特時，N型電晶體MN1與P型電晶體MP2為關閉(turn off)，N型電晶體MN2與P型電晶體MP1為開啟(turn on)。因此，輸出信號OUT為0伏特的接地電壓GND，以及反相的輸出信號OUTB為3.3伏特的電源電壓VDDH。 When the input signal IN of the converter 10 is 0 volts and the inverted input signal INB is 1.5 volts, the N-type transistor MN1 and the P-type transistor MP2 are turned off, and the N-type transistor MN2 and P-type The transistor MP1 is turned on. Therefore, the output signal OUT is a ground voltage GND of 0 volts, and the inverted output signal OUTB is a power supply voltage VDDH of 3.3 volts.

本發明係有關於一種轉壓器，將一輸入信號轉換為一輸出信號，包括：一第一電晶體，具有一第一汲極連接至一第一節點，一第一閘極接收該輸入信號，以及一第一源極連接至一第一電源電壓；一第二電晶體，具有一第二汲極連接至一第二節點，一第二閘極接收一反相的輸入信號，以及一第二源極連接至該第一電源電壓；一第三電晶體，具有一第三源極連接至一第二電源電壓，一第三汲極連接至該第一節點，以及一第三閘極連接至該第二節點；一第四電晶體，具有一第四源極連接至該第二電源電壓，一第四汲極連接至該第二節點，以及一第四閘極連接至該第一節點，其中該第一節點係作為一第一輸出端以產生一反相的輸出信號，且該第二節點係作為一第二輸出端以產生該輸出信號；一第一電流鏡連接至該第二電源電壓，其中該第一電流鏡具有一第一電流輸入端連接至一第三節點，以及一第一電流鏡射端連接至該第一節點；一第一電流路徑控制電路，連接至該第三節點與該第一電源電壓之間，根據該反相的輸入信號與該輸出信號來動作；一第二電流鏡連接至該第二電源電壓，其中該第二電流鏡具有一第二電流輸入端連接至一第四節點，以及一第二電流鏡射端連接至該第二節點；以及一第二電流路徑控制電路，連接至該第四節點與該第一電源電壓之間，根據該輸入信號與該反相的輸出信號來動作。 The invention relates to a voltage converter for converting an input signal into an output signal, comprising: a first transistor having a first drain connected to a first node, and a first gate receiving the input signal And a first source connected to a first power voltage; a second transistor having a second drain connected to a second node, a second gate receiving an inverted input signal, and a second The second source is connected to the first power voltage; a third transistor has a third source connected to a second power voltage, a third drain is connected to the first node, and a third gate is connected To the second node; a fourth transistor having a fourth source connected to the second supply voltage, a fourth drain connected to the second node, and a fourth gate connected to the first node The first node is used as a first output to generate an inverted output signal, and the second node is used as a second output to generate the output signal; a first current mirror is coupled to the second a power supply voltage, wherein the first current mirror has a first The current input terminal is connected to a third node, and a first current mirror is connected to the first node; a first current path control circuit is connected between the third node and the first power voltage, according to the An inverted input signal is coupled to the output signal; a second current mirror is coupled to the second supply voltage, wherein the second current mirror has a second current input coupled to a fourth node, and a second current The mirror end is connected to the second node; and a second current path control circuit is connected between the fourth node and the first power voltage, and operates according to the input signal and the inverted output signal.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10、20‧‧‧轉壓器 10, 20‧‧‧Transducer

21‧‧‧反相器 21‧‧‧Inverter

22、24‧‧‧電流鏡 22, 24‧‧‧current mirror

26、28‧‧‧電流路徑控制電路 26, 28‧‧‧ Current path control circuit

MN1~MN6‧‧‧N型電晶體 MN1~MN6‧‧‧N type transistor

MP1~MP6‧‧‧P型電晶體 MP1~MP6‧‧‧P type transistor

第1圖所繪示的是習知轉壓器。 Figure 1 shows a conventional converter.

第2圖所繪示為本發明的轉壓器。 Figure 2 is a view of the pressure converter of the present invention.

第3圖所繪示為本發明轉壓器的相關信號示意圖。 Figure 3 is a schematic diagram showing the relevant signals of the converter of the present invention.

為了讓IC晶片的運算速度更快、更省電，IC晶片中的核心電壓越來越低。而本發明提出的轉壓器以在核心電壓範圍為0到0.7伏特時仍舊能夠正常運作。 In order to make IC chips faster and more power efficient, the core voltage in IC chips is getting lower and lower. The converter of the present invention is still capable of operating normally at a core voltage range of 0 to 0.7 volts.

請參考第2圖，其所繪示為本發明轉壓器。此轉壓器20可將信號範圍介於電壓VDDL至VSS的輸入信號IN轉為信號範圍在電壓VDDH至VSS間的輸出信號OUT。其中，電源電壓VDDL可為例如0.7伏特，電源電壓VDDH可為例如3.3伏特，電源電壓VSS可為例如0伏特；亦即電源電壓VDDH大於電源電壓VDDL，且電源電壓VDDL大於電源電壓VSS。 Please refer to FIG. 2, which illustrates the converter of the present invention. The converter 20 can convert the input signal IN having a signal range of the voltages VDDL to VSS into the output signal OUT of the signal range between the voltages VDDH to VSS. The power supply voltage VDDL may be, for example, 0.7 volts, the power supply voltage VDDH may be, for example, 3.3 volts, and the power supply voltage VSS may be, for example, 0 volts; that is, the power supply voltage VDDH is greater than the power supply voltage VDDL, and the power supply voltage VDDL is greater than the power supply voltage VSS.

轉壓器20包括P型電晶體MP1、P型電晶體MP2、N型電晶體MN1、N型電晶體MN2、電流鏡22與24、以及電流路徑控制電路26與28。另外，操作於電源電壓VDDL與電源電壓VSS之間的一反相器21，其輸入端接收輸入信號IN，其輸出端產生反相的輸入信號INB。 The converter 20 includes a P-type transistor MP1, a P-type transistor MP2, an N-type transistor MN1, an N-type transistor MN2, current mirrors 22 and 24, and current path control circuits 26 and 28. In addition, an inverter 21 operating between the power supply voltage VDDL and the power supply voltage VSS receives an input signal IN at its input terminal and an inverted input signal INB at its output terminal.

轉壓器20中，P型電晶體MP1源極連接至電源電壓VDDH；汲極連接至節點a；閘極連接至節點b。P型電晶體MP2源極連接至電源電壓VDDH；汲極連接至節點b；閘極連接至節點a。 In the converter 20, the source of the P-type transistor MP1 is connected to the power supply voltage VDDH; the drain is connected to the node a; and the gate is connected to the node b. The P-type transistor MP2 source is connected to the power supply voltage VDDH; the drain is connected to the node b; and the gate is connected to the node a.

再者，N型電晶體MN1汲極連接至節點a；源極連接至電源電壓VSS；閘極接收輸入信號IN。N型電晶體MN2汲極連接至節點b；源極連接至電源電壓VSS；閘極接收反相的輸入信號INB。其中，節點a更做為第一輸出端，產生反相的輸出信號OUTB；節點b更做為第二輸出端，產生輸出信號OUT。 Furthermore, the N-type transistor MN1 is connected to the node a, the source is connected to the power supply voltage VSS, and the gate receives the input signal IN. The N-type transistor MN2 is connected to the node b; the source is connected to the power supply voltage VSS; and the gate receives the inverted input signal INB. The node a is further used as the first output terminal to generate the inverted output signal OUTB; the node b is further used as the second output terminal to generate the output signal OUT.

電流鏡22連接於電源電壓VDDH，且電流鏡22包括一電流輸入端(current inputting terminal)連接於節點c以及一電流鏡射端(current mirroring terminal)連接於節點a。另外，電流鏡24連接於電源電壓VDDH，且電流鏡24包括一電流輸入端連接於節點d以及一電流鏡射端連接於節點b。 The current mirror 22 is connected to the power supply voltage VDDH, and the current mirror 22 includes a current input terminal connected to the node c and a current mirroring terminal connected to the node a. In addition, the current mirror 24 is connected to the power supply voltage VDDH, and the current mirror 24 includes a current input terminal connected to the node d and a current mirror terminal connected to the node b.

電流路徑控制電路(current path control circuit)26包括串接於節點c與電源電壓VSS之間的二個N型電晶體MN3與MN4，N型電晶體MN3的閘極接收反相的輸入信號INB，N型電晶體MN4的閘極接收輸出信號OUT。另外，電流路徑控制電路28包括串接於節點d與電源電壓VSS之間的二個N型電晶體MN5與MN6，N型電晶體MN5的閘極接收輸入信號IN，N型電晶體MN6的閘極接收反相的輸出信號OUTB。 The current path control circuit 26 includes two N-type transistors MN3 and MN4 connected in series between the node c and the power supply voltage VSS, and the gate of the N-type transistor MN3 receives the inverted input signal INB, The gate of the N-type transistor MN4 receives the output signal OUT. In addition, the current path control circuit 28 includes two N-type transistors MN5 and MN6 connected in series between the node d and the power supply voltage VSS. The gate of the N-type transistor MN5 receives the input signal IN, and the gate of the N-type transistor MN6. The pole receives the inverted output signal OUTB.

請參照第3圖，其所繪示為本發明轉壓器的相關信號示意圖。於時間點t1，轉壓器20的輸入信號IN由0伏特變為0.7伏特，N型電晶體MN1開啟(turn on)且N型電晶體MN2關閉(turn off)。 Please refer to FIG. 3, which is a schematic diagram of related signals of the converter of the present invention. At time t1, the input signal IN of the converter 20 is changed from 0 volts to 0.7 volts, the N-type transistor MN1 is turned on and the N-type transistor MN2 is turned off.

於時間點t1至時間點t2為第一暫態期間(transient period)。於第一暫態期間的初期，輸入信號IN為0.7伏特且反相的輸出信號OUTB為3.3伏特，使得電流路徑控制電路28動作 (activate)。同時，於第一暫態期間，由於反相的輸入信號INB為0伏特，使得電流路徑控制電路26不動作。 The time period t1 to the time point t2 is a first transient period. At the beginning of the first transient period, the input signal IN is 0.7 volts and the inverted output signal OUTB is 3.3 volts, causing the current path control circuit 28 to operate. (activate). At the same time, during the first transient state, the current path control circuit 26 does not operate because the inverted input signal INB is 0 volts.

當電流路徑控制電路28動作時，節點d的電壓Vd由0伏特逐漸升高，電流路徑控制電路28產生一控制電流至電流鏡24的電流輸入端，使得節點b(意即輸出信號OUT)被上拉(pull up)至3.3伏特，並使得P型電晶體MP1關閉(turn off)，而節點a(意即反相的輸出信號OUTB)被下拉(pull down)至0伏特。 When the current path control circuit 28 operates, the voltage Vd of the node d gradually rises from 0 volts, and the current path control circuit 28 generates a control current to the current input terminal of the current mirror 24, so that the node b (meaning the output signal OUT) is Pull up to 3.3 volts and cause the P-type transistor MP1 to turn off, while node a (ie, the inverted output signal OUTB) is pulled down to 0 volts.

於時間點t2至時間點t3為第一穩態期間(steady period)，輸入信號IN為0.7伏特、反相的輸入信號INB為0伏特、輸出信號OUT為3.3伏特且反相的輸出信號OUTB為0伏特。此時，P型電晶體MP1關閉(turn off)、P型電晶體MP2開啟(turn on)、N型電晶體MN1開啟(turn on)、N型電晶體MN2關閉(turn off)、電流路徑控制電路26與28皆不動作。明顯地，於第一穩態期間，轉壓器20中並沒有任何的漏電路徑(leakage current path)，可以有效地減少轉壓器20的電源消耗(power consumption)。 The time period t2 to the time point t3 is the first steady state period, the input signal IN is 0.7 volts, the inverted input signal INB is 0 volts, the output signal OUT is 3.3 volts, and the inverted output signal OUTB is 0 volts. At this time, the P-type transistor MP1 is turned off, the P-type transistor MP2 is turned on, the N-type transistor MN1 is turned on, the N-type transistor MN2 is turned off, and the current path is controlled. Circuits 26 and 28 do not operate. Obviously, during the first steady state, there is no leakage current path in the converter 20, which can effectively reduce the power consumption of the converter 20.

於時間點t3，轉壓器20的輸入信號IN由0.7伏特變為0伏特，N型電晶體MN1關閉(turn off)且N型電晶體MN2開啟(turn on)。 At time t3, the input signal IN of the converter 20 is changed from 0.7 volts to 0 volts, the N-type transistor MN1 is turned off and the N-type transistor MN2 is turned on.

於時間點t3至時間點t4為第二暫態期間。於第二暫態期間的初期，反相輸入信號INB為0.7伏特且輸出信號OUT為3.3伏特，使得電流路徑控制電路26動作(activate)。同時，於第二暫態期間，由於輸入信號IN為0伏特，使得電流路徑控制電路28不動作。 The second transient period is from time t3 to time t4. At the beginning of the second transient period, the inverting input signal INB is 0.7 volts and the output signal OUT is 3.3 volts, causing the current path control circuit 26 to activate. At the same time, during the second transient state, the current path control circuit 28 does not operate because the input signal IN is 0 volts.

當電流路徑控制電路26動作時，節點c的電壓Vc由0伏特逐漸升高，電流路徑控制電路26產生一控制電流至電流鏡22的電流輸入端，使得節點a(意即反相的輸出信號OUTB)被上拉(pull up)至3.3伏特，並使得P型電晶體MP2關閉(turn off)，而節點b(意即輸出信號OUT)被下拉(pull down)至0伏特。 When the current path control circuit 26 operates, the voltage Vc of the node c is gradually increased by 0 volts, and the current path control circuit 26 generates a control current to the current input terminal of the current mirror 22, so that the node a (ie, the inverted output signal) OUTB) is pulled up to 3.3 volts and causes P-type transistor MP2 to turn off, while node b (meaning output signal OUT) is pulled down to 0 volts.

於時間點t4之後為第二穩態期間，輸入信號IN為0伏特、反相的輸入信號INB為0.7伏特、輸出信號OUT為0伏特且反相的輸出信號OUTB為3.3伏特。此時，P型電晶體MP1開啟(turn on)、P型電晶體MP2關閉(turn off)、N型電晶體MN1關閉(turn off)、N型電晶體MN2開啟(turn on)、電流路徑控制電路26與28皆不動作。明顯地，於第二穩態期間，轉壓器20中並沒有任何的漏電路徑，可以有效地降低轉壓器20的電源消耗。 After the time point t4 is the second steady state period, the input signal IN is 0 volts, the inverted input signal INB is 0.7 volts, the output signal OUT is 0 volts, and the inverted output signal OUTB is 3.3 volts. At this time, the P-type transistor MP1 is turned on, the P-type transistor MP2 is turned off, the N-type transistor MN1 is turned off, the N-type transistor MN2 is turned on, and the current path is controlled. Circuits 26 and 28 do not operate. Obviously, during the second steady state, there is no leakage path in the converter 20, which can effectively reduce the power consumption of the converter 20.

當輸入信號IN再次由0伏特變為0.7伏特時，其動作原理與上述時間點t1之後的動作相同，不再贅述。 When the input signal IN is changed from 0 volt to 0.7 volt again, the operation principle is the same as that after the above-mentioned time point t1, and will not be described again.

由上述的說明可知，當輸入信號IN由電源電壓VSS轉換至電源電壓VDDL時，利用電流鏡24與電流路徑控制電路28將輸出信號OUT上拉至電源電壓VDDH。當輸入信號IN由電源電壓轉VDDL換至電源電壓VSS時，利用電流鏡22與電流路徑控制電路28將反相的輸出信號INB上拉至第二電壓。 As apparent from the above description, when the input signal IN is switched from the power supply voltage VSS to the power supply voltage VDDL, the current mirror 24 and the current path control circuit 28 pull up the output signal OUT to the power supply voltage VDDH. When the input signal IN is switched from the power supply voltage VDDL to the power supply voltage VSS, the inverted output signal INB is pulled up to the second voltage by the current mirror 22 and the current path control circuit 28.

再者，本發明的優點在於提出一種轉壓器，其輸入信號IN與反相的輸入信號INB可以操作在極低的信號範圍。根據本發明的實施例，當電源電壓VDDL下降至0.4伏特時，本發明的轉壓器仍舊可以正常運作，因此非常適合運用在具有極低核心電壓的IC晶片上。 Furthermore, an advantage of the present invention is that a converter is provided in which the input signal IN and the inverted input signal INB can operate in an extremely low signal range. According to an embodiment of the present invention, the voltage converter of the present invention can still operate normally when the power supply voltage VDDL drops to 0.4 volts, and thus is well suited for use on an IC chip having a very low core voltage.

綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧轉壓器 20‧‧‧Transducer

21‧‧‧反相器 21‧‧‧Inverter

22、24‧‧‧電流鏡 22, 24‧‧‧current mirror

26、28‧‧‧電流路徑控制電路 26, 28‧‧‧ Current path control circuit

MN1~MN6‧‧‧N型電晶體 MN1~MN6‧‧‧N type transistor

MP1~MP6‧‧‧P型電晶體 MP1~MP6‧‧‧P type transistor

Claims (8)

一種轉壓器，將一輸入信號轉換為一輸出信號，包括：一第一電晶體，具有一第一汲極連接至一第一節點，一第一閘極接收該輸入信號，以及一第一源極連接至一第一電源電壓；一第二電晶體，具有一第二汲極連接至一第二節點，一第二閘極接收一反相的輸入信號，以及一第二源極連接至該第一電源電壓；一第三電晶體，具有一第三源極連接至一第二電源電壓，一第三汲極連接至該第一節點，以及一第三閘極連接至該第二節點；一第四電晶體，具有一第四源極連接至該第二電源電壓，一第四汲極連接至該第二節點，以及一第四閘極連接至該第一節點，其中該第一節點係作為一第一輸出端以產生一反相的輸出信號，且該第二節點係作為一第二輸出端以產生該輸出信號；一第一電流鏡連接至該第二電源電壓，其中該第一電流鏡具有一第一電流輸入端連接至一第三節點，以及一第一電流鏡射端連接至該第一節點；一第一電流路徑控制電路，連接至該第三節點與該第一電源電壓之間，根據該反相的輸入信號與該輸出信號來動作；一第二電流鏡連接至該第二電源電壓，其中該第二電流鏡具有一第二電流輸入端連接至一第四節點，以及一第二電流鏡射端連接至該第二節點；以及一第二電流路徑控制電路，連接至該第四節點與該第一電源電壓之間，根據該輸入信號與該反相的輸出信號來動作。 A voltage converter for converting an input signal into an output signal, comprising: a first transistor having a first drain connected to a first node, a first gate receiving the input signal, and a first The source is connected to a first power voltage; a second transistor has a second drain connected to a second node, a second gate receives an inverted input signal, and a second source is coupled to the second source The first power voltage; a third transistor having a third source connected to a second power voltage, a third drain connected to the first node, and a third gate connected to the second node a fourth transistor having a fourth source connected to the second supply voltage, a fourth drain connected to the second node, and a fourth gate connected to the first node, wherein the first The node acts as a first output to generate an inverted output signal, and the second node acts as a second output to generate the output signal; a first current mirror is coupled to the second supply voltage, wherein the The first current mirror has a first current input terminal Up to a third node, and a first current mirror end connected to the first node; a first current path control circuit connected between the third node and the first supply voltage, according to the inverted input a signal is coupled to the output signal; a second current mirror is coupled to the second supply voltage, wherein the second current mirror has a second current input coupled to a fourth node, and a second current mirror connection And the second current path control circuit is connected between the fourth node and the first power supply voltage, and operates according to the input signal and the inverted output signal. 如申請專利範圍第1項所述之轉壓器，其中該第一電晶體與該第二電晶體為N型電晶體，以及該第三電晶體與該第四電晶體為P型電晶體。 The converter of claim 1, wherein the first transistor and the second transistor are N-type transistors, and the third transistor and the fourth transistor are P-type transistors. 如申請專利範圍第1項所述之轉壓器，更包括一反相器，連接於一第三電源電壓與該第一電源電壓，該反相器接收該輸入信號產生該反相的輸入信號。 The converter of claim 1, further comprising an inverter connected to a third power voltage and the first power voltage, the inverter receiving the input signal to generate the inverted input signal . 如申請專利範圍第3項所述之轉壓器，其中該第二電源電壓大於該第三電源電壓，且該第三電源電壓大於該第一電源電壓。 The converter of claim 3, wherein the second power voltage is greater than the third power voltage, and the third power voltage is greater than the first power voltage. 如申請專利範圍第1項所述之轉壓器，其中該第一電流路徑控制電路包括串接於該第三節點與該第一電源電壓之間的一第五電晶體與一第六電晶體，該第五電晶體的一第五閘極接收該反相的輸入信號，且該第六電晶體的一第六閘極接收該輸出信號。 The voltage converter of claim 1, wherein the first current path control circuit comprises a fifth transistor and a sixth transistor connected in series between the third node and the first power voltage. A fifth gate of the fifth transistor receives the inverted input signal, and a sixth gate of the sixth transistor receives the output signal. 如申請專利範圍第5項所述之轉壓器，其中該第一電流鏡包括：一第七電晶體，具有一第七源極連接至該第二電源電壓，一第七汲極連接至該第一節點，以及一第七閘極連接至該第三節點；以及 一第八電晶體，具有一第八源極連接至該第二電源電壓，一第八汲極連接至該第三節點，以及一第八閘極連接至該第三節點。 The voltage converter of claim 5, wherein the first current mirror comprises: a seventh transistor having a seventh source connected to the second power voltage, and a seventh drain connected to the a first node, and a seventh gate connected to the third node; An eighth transistor having an eighth source coupled to the second supply voltage, an eighth drain coupled to the third node, and an eighth gate coupled to the third node. 如申請專利範圍第1項所述之轉壓器，其中該第二電流路徑控制電路包括串接於該第四節點與該第一電源電壓之間的一第九電晶體與一第十電晶體，該第九電晶體的一第九閘極接收該輸入信號，且該第十電晶體的一第十閘極接收該反相的輸出信號。 The converter of claim 1, wherein the second current path control circuit comprises a ninth transistor and a tenth transistor connected in series between the fourth node and the first power voltage A ninth gate of the ninth transistor receives the input signal, and a tenth gate of the tenth transistor receives the inverted output signal. 如申請專利範圍第7項所述之轉壓器，其中該第二電流鏡包括：一第十一電晶體，具有一第十一源極連接至該第二電源電壓，一第十一汲極連接至該第二節點，以及一第十一閘極連接至該第四節點；以及一第十二電晶體，具有一第十二源極連接至該第二電源電壓，一第十二汲極連接至該第四節點，以及一第十二閘極連接至該第四節點。 The voltage converter of claim 7, wherein the second current mirror comprises: an eleventh transistor having an eleventh source connected to the second power supply voltage, an eleventh dipole Connected to the second node, and an eleventh gate connected to the fourth node; and a twelfth transistor having a twelfth source connected to the second supply voltage, a twelfth drain Connected to the fourth node, and a twelfth gate is connected to the fourth node.
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