TW201633539A - 半導體裝置及半導體封裝體 - Google Patents

半導體裝置及半導體封裝體 Download PDF

Info

Publication number
TW201633539A
TW201633539A TW104129062A TW104129062A TW201633539A TW 201633539 A TW201633539 A TW 201633539A TW 104129062 A TW104129062 A TW 104129062A TW 104129062 A TW104129062 A TW 104129062A TW 201633539 A TW201633539 A TW 201633539A
Authority
TW
Taiwan
Prior art keywords
electrode
semiconductor
semiconductor region
region
type
Prior art date
Application number
TW104129062A
Other languages
English (en)
Inventor
Yasuhiko Akaike
Kenya Kobayashi
Yukie Nishikawa
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201633539A publication Critical patent/TW201633539A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明之實施形態提供一種可小型化之半導體裝置及半導體封裝體。 實施形態之半導體裝置包含第1導電型之第1半導體區域、第2導電型之第2半導體區域、第1電極、第2導電型之第3半導體區域、第1導電型之第4半導體區域、及導電部。第2半導體區域設置於第1半導體區域上。第1電極設置於第2半導體區域上。第3半導體區域設置於第1電極上。第4半導體區域設置於第3半導體區域上。導電部被第3半導體區域隔著絕緣部而包圍，且與第1電極電性連接。

Description

半導體裝置及半導體封裝體
[相關申請案]
本申請案享有以日本專利申請案2015-50752號(申請日：2015年3月13日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置及半導體封裝體。
包含二極體、MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金屬氧化物半導體場效電晶體)、及IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極性電晶體)等半導體元件之半導體裝置被廣泛應用於以電力控制為代表之各種用途。半導體裝置較理想為較小。
本發明所欲解決之課題在於提供一種可小型化之半導體裝置及半導體封裝體。
實施形態之半導體裝置包含第1導電型之第1半導體區域、第2導電型之第2半導體區域、第1電極、第2導電型之第3半導體區域、第1導電型之第4半導體區域、及導電部。
第2半導體區域設置於第1半導體區域上。
第1電極設置於第2半導體區域上。
第3半導體區域設置於第1電極上。
第4半導體區域設置於第3半導體區域上。
導電部被第3半導體區域隔著絕緣部而包圍，且與第1電極電性連接。
1‧‧‧半導體裝置
2‧‧‧半導體裝置
3‧‧‧半導體裝置
4‧‧‧半導體裝置
5‧‧‧半導體封裝體
6‧‧‧半導體封裝體
7‧‧‧半導體封裝體
10‧‧‧第1電極
11‧‧‧第1層
11a‧‧‧導電層
11b‧‧‧導電層
12‧‧‧第2層
12a‧‧‧導電層
13‧‧‧第3層
13a‧‧‧導電層
14‧‧‧第4層
14a‧‧‧導電層
15‧‧‧第5層
15a‧‧‧導電層
21‧‧‧第1導電部
21a‧‧‧第1端子
21b‧‧‧搭載部
22‧‧‧接合線
23‧‧‧第2導電部
23a‧‧‧第2端子
24‧‧‧接合線
25‧‧‧第3導電部
25a‧‧‧第3端子
25b‧‧‧搭載部
26‧‧‧接合線
27‧‧‧電極
28‧‧‧接合線
30‧‧‧絕緣構件
100‧‧‧半導體元件部
101‧‧‧n+半導體區域
101a‧‧‧n+型基板
101b‧‧‧n+型半導體區域
102‧‧‧n-型半導體區域
102a‧‧‧n-型半導體層
103‧‧‧p-型半導體區域
104‧‧‧p+型半導體區域
105‧‧‧p型基極區域
106‧‧‧n+型半導體區域
107‧‧‧n型半導體區域
108‧‧‧p+型集極區域
109‧‧‧p+型接觸區域
111‧‧‧陽極電極
121‧‧‧導電部
122‧‧‧絕緣部
123‧‧‧第2電極
125‧‧‧閘極電極墊
131‧‧‧絕緣層
131a‧‧‧絕緣層
141‧‧‧閘極電極
142‧‧‧閘極絕緣層
200‧‧‧半導體元件部
201‧‧‧n+半導體區域
201a‧‧‧n+型基板
201b‧‧‧n+型半導體區域
202‧‧‧n-型半導體區域
202a‧‧‧n-型半導體層
203‧‧‧p-型半導體區域
204‧‧‧p+型半導體區域
205‧‧‧p型基極區域
206‧‧‧n+型半導體區域
207‧‧‧n型半導體區域
208‧‧‧p+型集極區域
209‧‧‧p+型接觸區域
211‧‧‧陽極電極
225‧‧‧閘極電極墊
231‧‧‧絕緣層
231a‧‧‧絕緣層
241‧‧‧閘極電極
242‧‧‧閘極絕緣層
300‧‧‧半導體元件部
400‧‧‧半導體元件部
500‧‧‧半導體元件部
600‧‧‧半導體元件部
OP1‧‧‧開口
S1‧‧‧半導體層
S1a‧‧‧表面
S1b‧‧‧背面
S2‧‧‧半導體層
S2a‧‧‧表面
S2b‧‧‧背面
圖1係第1實施形態之半導體裝置之俯視圖。
圖2係第1實施形態之半導體裝置之仰視圖。
圖3係圖1之A-A'剖視圖。
圖4(a)及(b)係表示第1實施形態之半導體裝置之製造步驟之步驟剖視圖。
圖5(a)及(b)係表示第1實施形態之半導體裝置之製造步驟之步驟剖視圖。
圖6(a)及(b)係表示第1實施形態之半導體裝置之製造步驟之步驟剖視圖。
圖7(a)及(b)係表示第1實施形態之半導體裝置之製造步驟之步驟剖視圖。
圖8係表示第1實施形態之半導體裝置之製造步驟之步驟俯視圖。
圖9係表示第1實施形態之半導體裝置之製造步驟之步驟剖視圖。
圖10係第2實施形態之半導體裝置之俯視圖。
圖11係第2實施形態之半導體裝置之仰視圖。
圖12係圖10之A-A'剖視圖。
圖13係第3實施形態之半導體裝置之剖視圖。
圖14係第4實施形態之半導體裝置之剖視圖。
圖15係第5實施形態之半導體封裝體之俯視圖。
圖16係圖15之A-A'剖視圖。
圖17係第6實施形態之半導體封裝體之俯視圖。
圖18係圖17之A-A'剖視圖。
圖19係第7實施形態之半導體封裝體之俯視圖。
圖20係圖19之A-A'剖視圖。
以下，一面參照圖式一面對本發明之各實施形態進行說明。
再者，圖式為模式性或概念性之圖式，各部分之厚度與寬度之關係、部分間之大小之比率等並非必須與實際情形相同。又，即便於表示相同部分之情形時，亦存在相互之尺寸或比率根據圖式而不同地表示之情況。
又，於本案說明書與各圖中，對與在已說明之圖中敍述之要素相同之要素標註相同之符號，並適當省略詳細說明。
於各實施形態之說明中，使用XYZ正交座標系。將相對於半導體層S1或半導體層S2之主面平行之方向且相互正交之2個方向設為X方向及Y方向，且將相對於該等X方向及Y方向之兩者正交之方向設為Z方向。
於以下之說明中，n+、n、n-及p+、p、p-之表記係表示各導電型之雜質濃度之相對性的高低。即，n+表示與n相比n型雜質濃度相對性地較高，n-表示與n相比n型雜質濃度相對性地較低。又，p+表示與p相比p型雜質濃度相對性地較高，p-表示與p相比p型雜質濃度相對性地較低。
對於以下說明之各實施形態，亦可使各半導體區域之p型與n型反轉而實施各實施形態。
(第1實施形態)
圖1係第1實施形態之半導體裝置1之俯視圖。於圖1中，以虛線表示導電部121。
圖2係第1實施形態之半導體裝置1之仰視圖。
圖3係圖1之A-A'剖視圖。
如圖3所示，半導體裝置1包含半導體元件部100、半導體元件部200、及設置於該等之間之第1電極10。
半導體元件部100例如為二極體。半導體元件部100包含n+型半導體區域101、n-型(第2導電型)半導體區域102(第3半導體區域)、p-型(第1導電型)半導體區域103(第4半導體區域)、p+型半導體區域104、陽極電極111(第4電極)、導電部121、絕緣部122、第2電極123、及絕緣層131。
半導體元件部200例如為二極體。半導體元件部200包含n+型半導體區域201、n-型半導體區域202(第2半導體區域)、p-型半導體區域203(第1半導體區域)、p+型半導體區域204、陽極電極211(第3電極)、及絕緣層231。
如圖1所示，於半導體裝置1之上表面，設置有陽極電極111及第2電極123。陽極電極111與第2電極123相互隔開而設置。陽極電極111例如被第2電極123包圍。陽極電極111亦可分離為複數個而設置。同樣地，第2電極123亦可分離為複數個而設置。
如圖2所示，於半導體裝置1之下表面設置有陽極電極211。陽極電極211之面積例如大於陽極電極111之面積。再者，陽極電極211之面積亦可為陽極電極111之面積以下。陽極電極211亦可分離為複數個而設置。
如圖1所示，半導體裝置1包含複數個導電部121。再者，半導體裝置1亦可僅包含1個導電部121。第2電極123例如於自Z方向觀察時，與複數個導電部121重疊。複數個導電部121例如於自Z方向觀察時，設置於陽極電極111之周圍。
如圖3所示，陽極電極111設置於半導體層S1之表面S1a側，第1電 極10設置於半導體層S1之背面S1b側。陽極電極211設置於半導體層S2之表面S2a側，第1電極10設置於半導體層S2之背面S2b側。即，第1電極10設置於背面S1b與背面S2b之間。
陽極電極211與p+型半導體區域204電性連接。於p+型半導體區域204上，設置有p-型半導體區域203。p-型半導體區域203例如與p+型半導體區域204於Z方向上重疊，並且沿X-Y面包圍p+型半導體區域204。換言之，於p-型半導體區域203下，選擇性地設置有p+型半導體區域204。
於p-型半導體區域203上設置有n-型半導體區域202。n-型半導體區域202例如與p-型半導體區域203於Z方向上重疊，並且沿X-Y面包圍p-型半導體區域203。換言之，於n-型半導體區域202下，選擇性地設置有p-型半導體區域203。p-型半導體區域203亦可設置於n-型半導體區域202下之整個表面。
於n-型半導體區域202上設置有n+型半導體區域201。於n+型半導體區域201上設置有第1電極10。n+型半導體區域201與第1電極10電性連接。
於第1電極10上設置有n+型半導體區域101。n+型半導體區域101與第1電極10電性連接。於n+型半導體區域101上設置有n-型半導體區域102。
於n-型半導體區域102上，選擇性地設置有p-型半導體區域103。p-型半導體區域103例如藉由n-型半導體區域102之一部分而沿X-Y面包圍。p-型半導體區域103亦可設置於n-型半導體區域102上之整個表面。
於p-型半導體區域103上，選擇性地設置有p+型半導體區域104。p+型半導體區域104例如藉由n型半導體區域103之一部分而沿X-Y面包圍。p+型半導體區域104與陽極電極111電性連接。
導電部121由絕緣部122包圍。導電部121及絕緣部122例如於Z方向貫通n+型半導體區域101、n-型半導體區域102、及絕緣層131。換言之，導電部121隔著絕緣部122而藉由n+型半導體區域101及n-型半導體區域102沿X-Y面包圍。導電部121進而亦可藉由p-型半導體區域103及p+型半導體區域104而沿X-Y面包圍。
導電部121與第1電極10電性連接。導電部121例如與第1電極10接觸。導電部121亦可經由n+型半導體區域101而與第1電極10電性連接。然而，為降低第1電極10與導電部121之電阻，較理想為第1電極10與導電部121於不經由半導體區域之情況下連接。
於導電部121上設置有第2電極123。第2電極123與導電部121電性連接。導電部121與第2電極123亦可為設置成一體者。即，亦可為於導電部121與第2電極123之間無邊界而為無縫。第2電極123於X方向及Y方向上，與陽極電極111隔開而設置。
於陽極電極211之一部分與p+型半導體區域204之一部分之間、及陽極電極211之一部分與p-型半導體區域203之一部分之間設置有絕緣層231。同樣地，於陽極電極111之一部分與p+型半導體區域104之一部分之間、及陽極電極111之一部分與p-型半導體區域103之一部分之間設置有絕緣層131。
如圖3所示，第1電極10例如包含第1層11、第2層12、第3層13、第4層14、及第5層15。於n+型半導體區域201上，依序設置有第2層12、第4層14、第1層11、第5層15、及第3層13。於第5層15上設置有n+型半導體區域101。
第1層11例如包含金、錫、及銦之至少任一者。第1層11可為將2個金屬層接合而成者。即，第1層11可為將包含金、錫、及銦之至少任一者之2個層於不介置其他層之情況下接合而形成者。
第4層14及第5層15例如包含鈦、鉑、鎢、鉭、及釩之至少任一 者。第4層14中包含之材料與第5層15中包含之材料亦可互不相同。第4層14例如係用以提高第1層11與第2層12之間之密接性而設置。同樣地，第5層15可用以提高第1層11與第3層13之間之密接性而設置。
第2層12例如係具有阻隔功能之層，其可用以抑制第1層11與n+型半導體區域201之間之反應而設置。同樣地，第3層13係具有阻隔功能之層，其可用以抑制第1層11與n+型半導體區域101之間之反應而設置。
第2層12及第3層13例如包含氮化鈦。或，第2層12及第3層13包含鈦鎢。第2層12中包含之材料與第3層13中包含之材料亦可互不相同。
其次，使用圖4~圖9對第1實施形態之半導體裝置1之製造方法進行說明。
圖4~圖7及圖9係表示第1實施形態之半導體裝置1之製造步驟之步驟剖視圖。圖8係表示第1實施形態之半導體裝置1之製造步驟之步驟俯視圖。圖4~圖7(a)及圖9係對應於圖8之A-A'線之位置之步驟剖視圖。
於圖4~圖7及圖9中，左圖表示半導體元件部100之製造步驟，右圖表示半導體元件部200之製造步驟。
首先，準備n+型之半導體基板101a及半導體基板201a(以下，分別稱為n+型基板101a及n+型基板201a)。各基板之主成分為矽(Si)、砷化鎵、碳化矽、或氮化鎵等。
其次，如圖4(a)所示，於各個基板上，一面添加n型雜質一面使Si磊晶生長，藉此形成n-型半導體層102a及202a。作為n型雜質，可使用例如磷或砷。
其次，將p型雜質向各個n-型半導體層之表面之一部分進行離子注入，如圖4(b)所示，形成p-型半導體區域103及203。作為p型雜質， 可使用例如硼。
其次，於各n-型半導體層上及各p-型半導體區域上形成絕緣層。繼而，使該等絕緣層圖案化，藉此形成絕緣層131a及231a。又，此時，p-型半導體區域103之一部分及p-型半導體區域203之一部分露出。繼而，圖5(a)所示，將將p型雜質向p-型半導體區域之露出之部分進行離子注入，藉此形成p+型半導體區域104及204。
其次，於各p+型半導體區域上及各絕緣層上形成金屬層。該等金屬層例如使用CVD(Chemical Vapor Deposition，化學氣相沈積)法或PVD(Physical Vapor Deposition，物理氣相沈積)法等而形成。作為金屬層之材料，可使用例如鋁、銅、鎳、鈦、或鎢等。
其次，使該等金屬層圖案化，藉此如圖5(b)所示形成陽極電極111及211。陽極電極111之形狀及大小亦可與陽極電極211之形狀及大小不同。
其次，對n+型基板101a及201a之背面進行研磨直至n+型基板101a及201a成為特定厚度為止。藉由該步驟，如圖6(a)所示形成n+型半導體區域101b及201b。
其次，如圖6(b)所示，於n+型半導體區域101b之背面形成例如導電層11a、15a、及13a。又，於n+型半導體區域201b之背面形成例如導電層11b、14a、及12a。
其次，如圖7(a)所示，例如，於p-型半導體區域103之周圍形成複數個開口OP1。開口OP1例如貫通n+型半導體區域101b及n-型半導體區域102a。又，此時，導電層15a之上表面之一部分可通過開口OP1而露出。
其次，於開口OP1之內壁形成絕緣層。其後，如圖7(b)所示，將沈積於開口OP1之底部(導電層15a之上表面)之絕緣材料去除，藉此形成僅覆蓋開口OP1之側壁之絕緣部122。將此時之狀況示於圖8。
其次，如圖9所示，於絕緣部122之內側、絕緣部122上、及絕緣層131a之一部分上形成導電層。導電層例如包含銅，且使用鍍敷法而形成。藉由該步驟，形成圖3所示之導電部121及第2電極123。
其後，將形成於n+型半導體區域101b之背面之導電層11a、與形成於n+型半導體區域201b之背面之導電層11b加以接合。繼而，將所得之構造體分割成複數個，藉此獲得圖1~圖3所示之半導體裝置100。
再者，於圖4~圖9所示之製造方法之一例中，對在互不相同之基板上形成半導體元件部100與半導體元件部200之情形進行了說明，但該等半導體元件部亦可形成於同一基板上。該情形時，將形成有半導體元件部100及200之基板分割成複數個半導體晶片之後，將包含半導體元件部100之半導體晶片與包含半導體元件部200之半導體晶片加以接合，藉此獲得半導體裝置100。
本實施形態之半導體裝置1包含隔著第1電極10而積層之半導體元件部100及200。藉由採用此種構成，可實現半導體裝置之小型化，且可高密度地封裝半導體裝置。或，可對應於藉由將半導體元件部100與200積層而縮小之面積來擴大半導體裝置1之面積。其結果，可減小流過半導體裝置之電流之密度，從而可降低半導體裝置產生破壞之可能性。
而且，半導體裝置1還包含導電部121，其被n+型半導體區域101及n-型半導體區域102包圍，且與第1電極10電性連接。由於半導體裝置1包含導電部121，故可將與第1電極10電性連接之電極墊設置於半導體裝置1之上表面上。因此，例如，與將半導體元件部100及200設置於銅板等之互不相同之面上之情形相比，容易封裝半導體裝置1。
又，半導體裝置1係使2個半導體元件部相互對向且接合而成者，故而該等半導體元件部之翹曲相互抵消，從而可降低半導體裝置 1之翹曲。尤其於半導體元件部100之功能與半導體元件部200之功能相同之情形時，因半導體元件部100之構造而產生之應力、與因半導體元件部200之構造而產生之應力之差變小。因此，於半導體元件部100與200具有相同功能之情形時，可進一步降低半導體裝置1之翹曲。
藉由設置複數個導電部121，可減小第1電極10、與和第1電極10連接之端子之間之電阻。因此，可降低半導體裝置1之導通電阻。
進而，由於第1電極10具有包含氮化鈦或鈦鎢之第2層12及第3層13，故可抑制第1層11中包含之金屬材料與各半導體層中包含之半導體材料之反應。
又，由於第1電極10具有包含鈦之第4層14及第5層15，故可抑制第1層11與第2層12之間之剝離及第1層11與第3層13之間之剝離，從而可提高半導體裝置1之製造之良率。
(第2實施形態)
圖10係第2實施形態之半導體裝置2之俯視圖。於圖10中，以虛線表示導電部121。
圖11係第2實施形態之半導體裝置2之仰視圖。
圖12係圖10之A-A'剖視圖。
半導體裝置2包含半導體元件部300、半導體元件部400、及第1電極10。
半導體元件部300例如為MOSFET。半導體元件部300包含n+型汲極區域101、n-型半導體區域102(第3半導體區域)、p型基極區域105(第4半導體區域)、n+型源極區域106(第5半導體區域)、源極電極111(第4電極)、導電部121、絕緣部122、第2電極123、閘極電極墊125(第5電極)、絕緣層131、閘極電極141、及閘極絕緣層142。
半導體元件部400例如為MOSFET。半導體元件部400包含n+型汲 極區域201、n-型半導體區域202(第2導電型之第2半導體區域)、p型基極區域205(第1導電型之第1半導體區域)、n+型源極區域206、源極電極211(第3電極)、閘極電極墊225、絕緣層231、閘極電極241、及閘極絕緣層242。
如圖10所示，於半導體裝置2之上表面設置有源極電極111、第2電極123、閘極電極墊125、及絕緣層131。源極電極111、第2電極123、及閘極電極墊125相互隔開而設置。閘極電極墊125與複數個閘極電極141電性連接。
源極電極111之至少一部分例如於X方向上，設置於第2電極123與閘極電極墊125之間。
源極電極111亦可分離為複數個而設置。該情形時，例如，第2電極123之至少一部分設置於源極電極111彼此之間。
如圖11所示，於半導體裝置2之下表面，設置有源極電極211、閘極電極墊225、及絕緣層231。源極電極211與閘極電極墊225相互隔開而設置。閘極電極墊225與複數個閘極電極241電性連接。源極電極211亦可分離為複數個而設置。同樣地，閘極電極墊225亦可分離為複數個而設置。
如圖12所示，於n-型半導體區域202下選擇性地設置有p型基極區域205。p型基極區域205例如於X方向上設置有複數個。於p型基極區域205下例如選擇性地設置有n+型源極區域206。源極電極211與n+型源極區域206電性連接。
閘極電極241隔著閘極絕緣層242而至少與p型基極區域205對向。於圖12所示之例中，閘極絕緣層242設置於閘極電極241與n-型半導體區域202之一部分、p型基極區域205、及n+型源極區域206之至少一部分之間。
第1電極10與設置於n-型半導體區域202上之汲極區域201、及設 置於n-型半導體區域102下之n+型汲極區域101電性連接。第1電極10可作為半導體元件部300及400之汲極電極而發揮功能。
於n-型半導體區域102上選擇性地設置有p型基極區域105。p型基極區域105例如於X方向上設置有複數個。於p型基極區域105上例如選擇性地設置有n+型源極區域106。源極電極111與n+型源極區域106電性連接。
閘極電極141隔著閘極絕緣層142而至少與p型基極區域105對向。閘極絕緣層142例如設置於閘極電極141與n-型半導體區域102之一部分、p型基極區域105、及n+型源極區域106之至少一部分之間。
於相對於源極電極111及211而對第1電極10施加正電壓之狀態下，對閘極電極141及241施加閾值以上之電壓，藉此MOSFET成為導通狀態。此時，於p型基極區域105之閘極絕緣層142附近之區域及p型基極區域205之閘極絕緣層242附近之區域形成通道(反轉層)。
於本實施形態中，亦與第1實施形態同樣地，可實現半導體裝置之小型化，或可降低流過半導體裝置之電流密度。
再者，亦可將本實施形態中說明之半導體元件部300、與第1實施形態中說明之半導體元件部200組合而使用。或，亦可將本實施形態中說明之半導體元件部400、與第1實施形態中說明之半導體元件部100組合而使用。
(第3實施形態)
圖13係第3實施形態之半導體裝置3之剖視圖。
自Z方向觀察半導體裝置3之情形時之構造例如與圖10所示之俯視圖相同。自-Z方向觀察半導體裝置3之情形時之構造例如與圖2所示之仰視圖相同。
半導體裝置3包含半導體元件部500、半導體元件部200、及第1電極10。
半導體元件部500例如為IGBT。半導體元件部500包含p+型集極區域108(第6半導體區域)、n型半導體區域107、n-型半導體區域102(第3半導體區域)、p型基極區域105(第4半導體區域)、n+型源極區域106(第5半導體區域)、p+型接觸區域109、射極電極111(第4電極)、導電部121、絕緣部122、第2電極123、閘極電極墊125(第5電極)、絕緣層131、閘極電極141、及閘極絕緣層142。
半導體元件部200例如為二極體。
於第1電極10上設置有p+型集極區域108。p+型集極區域108與第1電極10電性連接。第1電極10可作為半導體元件部500之集極電極而發揮功能，並且可作為半導體元件部200之陰極電極而發揮功能。於p+型集極區域108上設置有n型半導體區域107。亦可代替n型半導體區域107，而於p+型集極區域108上設置n+型半導體區域。於n型半導體區域107上設置有n-型半導體區域102。
導電部121及絕緣部122例如被n-型半導體區域102、n型半導體區域107、及p+型集極區域108所包圍。
於n-型半導體區域102上選擇性地設置有p型基極區域105。於p型基極區域105上選擇性地設置有n+型射極區域106及p+型接觸區域109。n+型射極區域106及p+型接觸區域109與射極電極111電性連接。
於圖13所示之例中，於在X方向上相鄰之閘極絕緣層142之間設置有複數個n+型射極區域106，且於該等n+型射極區域106之間設置有p+型接觸區域109。或，亦可於在X方向上相鄰之閘極絕緣層142之間，於Y方向上交替設置有n+型射極區域106與p+型接觸區域109。
半導體元件部200與半導體元件部500例如反並聯連接，且半導體元件部200可作為回流二極體而發揮功能。即，於半導體元件部500為導通狀態時，電流自第1電極10流向射極電極111。於半導體元件部500自導通狀態切換為斷開狀態，且藉由電感成分而對半導體裝置3施 加電壓時，電流自陽極電極211流向第1電極10。
根據本實施形態，具有將具有不同功能之半導體元件部200及500積層之構造。因此，與將2個半導體元件部個別封裝之情形相比，可減小封裝所需之面積。
再者，亦可將本實施形態中說明之半導體元件部500、與第2實施形態中說明之半導體元件部400組合而使用。
(第4實施形態)
圖14係第4實施形態之半導體裝置4之剖視圖。
自Z方向觀察半導體裝置4之情形時之構造例如與圖10所示之俯視圖相同。自-Z方向觀察半導體裝置4之情形時之構造例如與圖11所示之仰視圖相同。
半導體裝置4包含半導體元件部500、半導體元件部600、及第1電極10。
半導體元件部600例如為IGBT。半導體元件部600包含n+型半導體區域201、n-型半導體區域202、p型基極區域205、n+型源極區域206、射極電極211、閘極電極墊225、絕緣層231、閘極電極241、及閘極絕緣層242。
於第1電極10下，設置有p+型集極區域208。p+型集極區域208與第1電極10電性連接。第1電極10可作為半導體元件部500及600之集極電極而發揮功能。於p+型集極區域208下設置有n型半導體區域207。亦可代替n型半導體區域207，而於p+型集極區域208下設置n+型半導體區域。於n型半導體區域207下設置有n-型半導體區域202。
於n-型半導體區域202下選擇性地設置有p型基極區域205。於p型基極區域205下選擇性地設置有n+型射極區域206及p+型接觸區域209。n+型射極區域206及p+型接觸區域209與射極電極211電性連接。
於本實施形態中，亦與第1實施形態同樣地，可實現半導體裝置 之小型化、或可降低流過半導體裝置之電流密度。
(第5實施形態)
圖15係第5實施形態之半導體封裝體5之俯視圖。於圖15中，透過絕緣構件30而表示半導體封裝體5之構造。
圖16係圖15之A-A'剖視圖。
本實施形態之半導體封裝體5係將半導體裝置1封裝化所得者。
半導體封裝體5包含半導體裝置1、第1導電部21、第2導電部23、及絕緣構件30。
如圖15所示，第1導電部21與第2導電部23相互隔開而設置。第1導電部21包含第1端子21a及搭載部21b。第2導電部23包含第2端子23a。半導體裝置1設置於搭載部21b上。
第1導電部21與半導體裝置1之陽極電極111經由接合線22而電性連接。第2導電部23與第2電極123經由接合線24而電性連接。接合線22及24之各者例如亦可設置複數個，以便降低各個導電部與各個電極之間之電阻。
作為第1導電部21及第2導電部23之材料，可使用例如銅合金。作為接合線22及24之材料，可使用例如鋁。作為絕緣構件30之材料，可使用例如聚醯亞胺等絕緣性樹脂。
如圖16所示，第1導電部21之搭載部21b與陽極電極211電性連接。即，陽極電極111及211均與第1導電部21電性連接。
半導體裝置1、第1導電部21之一部分、接合線22、第2導電部23之一部分、及接合線24藉由絕緣構件30而覆蓋。第1端子21a及第2端子23a並未被絕緣構件30覆蓋而是露出以用於與外部端子連接。搭載部21b中之未載置半導體裝置1之部分之至少一部分例如亦可露出，以用於半導體封裝體5之散熱。
根據本實施形態，使用半導體裝置1而構成半導體封裝體5，藉 此可實現半導體封裝體之小型化。
(第6實施形態)
圖17係第6實施形態之半導體封裝體6之俯視圖。於圖17中，透過絕緣構件30而表示半導體封裝體6之構造。
圖18係圖17之A-A'剖視圖。
本實施形態之半導體封裝體6係將半導體裝置2封裝化所得者。
半導體封裝體6包含半導體裝置2、第1導電部21、第2導電部23、第3導電部25、及絕緣構件30。
如圖17所示，第1導電部21、第2導電部23、及第3導電部25相互隔開而設置。第1導電部21包含第1端子21a及搭載部21b。第2導電部23包含第2端子23a。第3導電部25包含第3端子25a及搭載部25b。半導體裝置1設置於搭載部21b上及搭載部25b上。
第1導電部21經由接合線22而與陽極電極111電性連接。第2導電部23經由接合線24而與第2電極123電性連接。第3導電部25經由接合線26而與閘極電極墊125電性連接。接合線22、24、及26亦可設置複數個。
如圖18所示，半導體裝置2之源極電極211與第1導電部21電性連接。閘極電極墊225與第3導電部25電性連接。即，源極電極111及211均與第1導電部21電性連接。閘極電極墊125及225均與第3導電部25電性連接。
半導體裝置2、各引線之一部分、及各接合線藉由絕緣構件30而覆蓋。第1端子21a~第3端子25a並未被絕緣構件30覆蓋而是露出，以用於與外部端子連接。
本實施形態中亦同樣地，使用半導體裝置2而構成半導體封裝體6，藉此可實現半導體封裝體之小型化。
再者，半導體封裝體6亦可係將半導體裝置3封裝化所得者。該 情形時，半導體裝置3之射極電極111及陽極電極211與第1導電部21電性連接。又，第2電極123與第2導電部23電性連接，閘極電極墊125與第3導電部25電性連接。
(第7實施形態)
圖19係第7實施形態之半導體封裝體7之俯視圖。於圖19中，透過絕緣構件30而表示半導體封裝體7之構造。
圖20係圖19之A-A'剖視圖。
本實施形態之半導體封裝體7係將半導體裝置4封裝化所得者。
半導體封裝體7包含半導體裝置1、第1導電部21、第2導電部23、第3導電部25、電極27、及絕緣構件30。
如圖19所示，半導體封裝體7包含自第1導電部21、第2導電部23、及第3導電部25隔開而設置之電極27。半導體裝置4設置於電極27及搭載部21b上。
電極27經由接合線28而與射極電極111電性連接。第2電極123經由接合線24而與第2導電部23電性連接。閘極電極墊125經由接合線26而與第3導電部25電性連接。
如圖20所示，電極27與閘極電極墊225電性連接。即，半導體元件部600之閘極電極225與半導體元件部500之射極電極111電性連接。射極電極211與第1導電部21電性連接。因此，半導體封裝體7包含將半導體元件部500之輸出輸入至半導體元件部600之閘極之達林頓電晶體。
根據本實施形態，將構成達林頓電晶體之2個半導體元件部積層而設置。因此，可實現具有作為達林頓電晶體之功能之半導體封裝體之小型化。
對於以上說明之各實施形態中之各半導體區域之間的雜質濃度之相對性的高低，可使用例如SCM(Scanning Capacitance Microscopy，掃描式電容顯微鏡)而確認。再者，各半導體區域中之載子濃度可看作與各半導體區域中活化之雜質濃度相等者。因此，上述各實施形態之說明中之雜質濃度亦可置換為載子濃度。對於各半導體區域之間之載子濃度之相對性的高低，亦可使用SCM而確認。
又，對於各半導體區域中之雜質濃度，可使用例如SIMS(Secondary Ion Mass Spectrometry，二次離子質譜法)而測定。
以上，例示有本發明之若干實施形態，但該等實施形態係作為示例而提出者，並未意欲限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且可於不脫離發明之主旨之範圍進行各種省略、置換、變更等。該等實施形態及其變化例包含於發明之範圍或主旨，並且包含於申請專利範圍中所記載之發明及其均等之範圍。又，上述各實施形態可相互組合而實施。
1‧‧‧半導體裝置
111‧‧‧陽極電極
121‧‧‧導電部
123‧‧‧第2電極
131‧‧‧絕緣層

Claims (8)

  1. 一種半導體裝置，其包含：第1導電型之第1半導體區域；第2導電型之第2半導體區域，其設置於上述第1半導體區域上；第1電極，其設置於上述第2半導體區域上；第2導電型之第3半導體區域，其設置於上述第1電極上；第1導電型之第4半導體區域，其設置於上述第3半導體區域上；及導電部，其被上述第3半導體區域隔著絕緣部而包圍，且與上述第1電極電性連接。
  2. 如請求項1之半導體裝置，其中上述第1電極包含：第1層，其包含金、錫及銦之至少任一者；第2層，其設置於上述第1層與上述第2半導體區域之間，且包含氮化鈦或鈦鎢；及第3層，其設置於上述第1層與上述第3半導體區域之間，且包含氮化鈦或鈦鎢。
  3. 如請求項1或2之半導體裝置，其更包含：第2電極，其設置於上述導電部上，且與上述導電部電性連接；第3電極，其設置於上述第1半導體區域下，且與上述第1半導體區域電性連接；及第4電極，其與上述第2電極隔開而設置於上述第4半導體區域上，且與上述第4半導體區域電性連接。
  4. 如請求項1或2之半導體裝置，其包含： 第2導電型之第5半導體區域，其選擇性地設置於上述第4半導體區域上；閘極電極；及閘極絕緣層，其至少設置於上述閘極電極與上述第4半導體區域之間。
  5. 如請求項4之半導體裝置，其更包含：第2電極，其設置於上述導電部上，且與上述導電部電性連接；第3電極，其設置於上述第1半導體區域下，且與上述第1半導體區域電性連接；第4電極，其與上述第2電極隔開而設置於上述第4半導體區域上，且與上述第4半導體區域電性連接；及第5電極，其設置於上述第4半導體區域上，與上述閘極電極電性連接，且與上述第2電極及上述第4電極隔開而設置。
  6. 如請求項5之半導體裝置，其更包含第1導電型之第6半導體區域，其設置於上述第1電極與上述第3半導體區域之間。
  7. 一種半導體封裝體，其包含：如請求項3之半導體裝置；第1端子，其與上述第2電極電性連接；第2端子，其與上述第3電極及上述第4電極電性連接；及絕緣構件，其包圍上述半導體裝置。
  8. 一種半導體封裝體，其包含：如請求項5之半導體裝置；第1端子，其與上述第2電極電性連接；第2端子，其與上述第3電極及上述第4電極電性連接；第3端子，其與上述第5電極電性連接；及絕緣構件，其包圍上述半導體裝置。
TW104129062A 2015-03-13 2015-09-02 半導體裝置及半導體封裝體 TW201633539A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015050752A JP2016171231A (ja) 2015-03-13 2015-03-13 半導体装置および半導体パッケージ

Publications (1)

Publication Number Publication Date
TW201633539A true TW201633539A (zh) 2016-09-16

Family

ID=56888111

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104129062A TW201633539A (zh) 2015-03-13 2015-09-02 半導體裝置及半導體封裝體

Country Status (4)

Country Link
US (2) US9570439B2 (zh)
JP (1) JP2016171231A (zh)
KR (1) KR20160110011A (zh)
TW (1) TW201633539A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112242450A (zh) * 2020-12-16 2021-01-19 浙江里阳半导体有限公司 二极管器件及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022007788A (ja) * 2020-06-26 2022-01-13 富士電機株式会社 半導体装置
CN112289752B (zh) * 2020-12-01 2023-04-11 江苏捷捷微电子股份有限公司 一种倒装GaN功率器件封装结构及其制备方法
JP7509711B2 (ja) 2021-03-23 2024-07-02 株式会社東芝 半導体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821713B2 (ja) * 1987-02-26 1996-03-04 株式会社東芝 導電変調型ｍｏｓｆｅｔ
US6040599A (en) 1996-03-12 2000-03-21 Mitsubishi Denki Kabushiki Kaisha Insulated trench semiconductor device with particular layer structure
JPH10223835A (ja) * 1997-02-05 1998-08-21 Hitachi Ltd 半導体装置とその製造方法
JP2001094094A (ja) * 1999-09-21 2001-04-06 Hitachi Ltd 半導体装置およびその製造方法
JP4336205B2 (ja) 2004-01-05 2009-09-30 三菱電機株式会社 パワー半導体モジュール
JP2005302951A (ja) 2004-04-09 2005-10-27 Toshiba Corp 電力用半導体装置パッケージ
JP4153932B2 (ja) * 2004-09-24 2008-09-24 株式会社東芝 半導体装置および半導体装置の製造方法
US8263968B2 (en) * 2005-10-31 2012-09-11 The Hong Kong University Of Science And Technology Double sided emission organic light emitting diode display
JP2007184553A (ja) * 2005-12-06 2007-07-19 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2009071059A (ja) 2007-09-13 2009-04-02 Sanyo Electric Co Ltd 半導体装置
JP4600576B2 (ja) * 2008-05-08 2010-12-15 株式会社デンソー 半導体装置およびその製造方法
JP2009277944A (ja) * 2008-05-15 2009-11-26 Toyoda Gosei Co Ltd 接合体の製造方法及び発光装置の製造方法
WO2012136848A1 (en) * 2011-04-06 2012-10-11 Abb Technology Ag Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device
JP5763514B2 (ja) 2011-12-13 2015-08-12 トヨタ自動車株式会社 スイッチング素子の製造方法
JP6061181B2 (ja) * 2012-08-20 2017-01-18 ローム株式会社 半導体装置
JP6131605B2 (ja) * 2013-01-21 2017-05-24 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP6251071B2 (ja) * 2014-02-05 2017-12-20 ルネサスエレクトロニクス株式会社 半導体装置
US9741711B2 (en) * 2014-10-28 2017-08-22 Semiconductor Components Industries, Llc Cascode semiconductor device structure and method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112242450A (zh) * 2020-12-16 2021-01-19 浙江里阳半导体有限公司 二极管器件及其制造方法
CN112242450B (zh) * 2020-12-16 2021-04-06 浙江里阳半导体有限公司 二极管器件及其制造方法

Also Published As

Publication number Publication date
US20170117269A1 (en) 2017-04-27
KR20160110011A (ko) 2016-09-21
US9853023B2 (en) 2017-12-26
US9570439B2 (en) 2017-02-14
US20160268254A1 (en) 2016-09-15
JP2016171231A (ja) 2016-09-23

Similar Documents

Publication Publication Date Title
JP5319084B2 (ja) 半導体装置
US8018008B2 (en) Semiconductor device including a plurality of chips and method of manufacturing semiconductor device
US11239189B2 (en) Electronic component and semiconductor device
TWI638461B (zh) 半導體裝置及電力變換裝置
TW201633539A (zh) 半導體裝置及半導體封裝體
JP2013201413A (ja) 半導体装置および半導体装置の製造方法
US20230034806A1 (en) Semiconductor device
JP2019186309A (ja) 半導体装置
JP6617546B2 (ja) 半導体装置および半導体装置の製造方法
US10600777B1 (en) Semiconductor device
CN107078129B (zh) 半导体模块
CN102456655A (zh) 半导体模块
US9741805B2 (en) Semiconductor device and method for manufacturing the semiconductor device
US11876062B2 (en) Semiconductor device
JP6579653B2 (ja) 半導体装置および半導体装置の製造方法
JP6316221B2 (ja) 半導体装置
JP6045971B2 (ja) 半導体装置
WO2023090137A1 (ja) 半導体素子および半導体装置
US12051662B2 (en) Electronic component and semiconductor device
US20230215840A1 (en) Semiconductor device
CN112768503B (zh) Igbt芯片、其制造方法及功率模块
WO2021225120A1 (ja) 半導体装置
US10651038B2 (en) Semiconductor device
JP2023113219A (ja) 半導体装置および回路装置
JP2023113217A (ja) 半導体装置および回路装置