TW201446488A - Copper foil with carrier, printed circuit board, copper clad laminated sheet, electronic device, and printed circuit board fabrication method - Google Patents

Copper foil with carrier, printed circuit board, copper clad laminated sheet, electronic device, and printed circuit board fabrication method Download PDF

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TW201446488A
TW201446488A TW103111942A TW103111942A TW201446488A TW 201446488 A TW201446488 A TW 201446488A TW 103111942 A TW103111942 A TW 103111942A TW 103111942 A TW103111942 A TW 103111942A TW 201446488 A TW201446488 A TW 201446488A
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layer
carrier
copper foil
thin copper
ultra
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TWI526299B (en
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Michiya Kohiki
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Jx Nippon Mining & Metals Corp
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • B32B15/018—Layered products comprising a layer of metal all layers being exclusively metallic one layer being formed of a noble metal or a noble metal alloy
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/04—Wires; Strips; Foils
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/06—Wires; Strips; Foils
    • C25D7/0614—Strips or foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/50—Properties of the layers or laminate having particular mechanical properties
    • B32B2307/538—Roughness
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Laminated Bodies (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

Provided is a copper foil with a carrier, the ultrathin copper layer of which has good laser-hole-opening properties, and which is suitable for the fabrication of a high-density integrated circuit substrate. The copper foil with a carrier is provided with a carrier, an intermediate layer, and ultrathin copper layer, in that order. When the ultrathin copper layer is peeled off in accordance with JIS C 6471 after the copper foil with a carrier is heated at 200 DEG C for two hours, the surface roughness (Sz) of the ultrathin copper layer on the intermediate layer side is 1.40[mu]m to 4.05[mu]m as measured by a laser microscope.

Description

附載體銅箔、印刷配線板、覆銅積層板、電子機器及印刷配線板之製造方法 Carrier copper foil, printed wiring board, copper clad laminate, electronic device, and printed wiring board manufacturing method

本發明係關於一種附載體銅箔、印刷配線板、覆銅積層板、電子機器及印刷配線板之製造方法。 The present invention relates to a method of manufacturing a carrier-attached copper foil, a printed wiring board, a copper-clad laminate, an electronic device, and a printed wiring board.

印刷配線板通常係經過使銅箔與絕緣基板接著而製成覆銅積層板後，藉由蝕刻於銅箔面形成導體圖案之步驟而製造。伴隨近年來電子機器之小型化、高性能化需求之增大，搭載零件之高密度安裝化或訊號之高頻化得以發展，對印刷配線板要求導體圖案之微細化(微間距化)或高頻對應等。 The printed wiring board is usually produced by forming a copper-clad laminate after the copper foil and the insulating substrate are bonded to each other, and then etching the copper foil surface to form a conductor pattern. With the increase in the demand for miniaturization and high performance of electronic devices, high-density mounting of mounted components or high-frequency signals have been developed, and it has been required to miniaturize (finely pitch) or increase the conductor pattern on printed wiring boards. Frequency correspondence.

對應微間距化，最近要求厚度9μm以下、進而厚度5μm以下之銅箔，但此種極薄之銅箔之機械強度較低，於印刷配線板之製造時容易破裂或產生褶皺，因此出現了將具有厚度之金屬箔用作載體，於其上介隔剝離層電鍍極薄銅層而成之附載體銅箔。將極薄銅層之表面貼合於絕緣基板並進行熱壓接後，介隔剝離層剝離去除載體。於露出之極薄銅層上藉由抗蝕劑形成電路圖案後，而形成規定之電路。 Corresponding to the fine pitch, a copper foil having a thickness of 9 μm or less and a thickness of 5 μm or less has recently been required. However, such an extremely thin copper foil has low mechanical strength and is liable to be broken or wrinkled during the manufacture of a printed wiring board, so that A metal foil having a thickness is used as a carrier, and a copper foil with a carrier on which a very thin copper layer is plated with a release layer is interposed. After bonding the surface of the ultra-thin copper layer to the insulating substrate and thermocompression bonding, the carrier is peeled off by the release layer. A predetermined circuit is formed by forming a circuit pattern on the exposed ultra-thin copper layer by a resist.

此處，對於成為與樹脂之接著面之附載體銅箔之極薄銅層的表面，主要要求極薄銅層與樹脂基材之剝離強度充分，並且該剝離強度即便於高溫加熱、濕式處理、焊接、化學品處理等之後亦充分地保持。作為 提高極薄銅層與樹脂基材間之剝離強度之方法，通常具代表性者係使大量粗化粒子附著於經增大表面輪廓(凹凸、粗糙度)之極薄銅層上的方法。 Here, the surface of the ultra-thin copper layer which is the copper foil with a carrier which is the adhesive surface of the resin is required to have sufficient peeling strength of the ultra-thin copper layer and the resin substrate, and the peeling strength is heated even at a high temperature, and the wet treatment is performed. After welding, chemical treatment, etc., it is also fully maintained. As The method of increasing the peeling strength between the ultra-thin copper layer and the resin substrate is generally a method of attaching a large amount of roughened particles to an extremely thin copper layer having an increased surface profile (concavity and roughness).

然而，若於印刷配線板之中，特別是對需要形成微細之電路圖案之半導體封裝基板使用此種輪廓(凹凸、粗糙度)較大之極薄銅層，則於電路蝕刻時會殘留不需要之銅粒子，而產生電路圖案間之絕緣不良等問題。 However, in the printed wiring board, particularly for a semiconductor package substrate in which a fine circuit pattern needs to be formed, an extremely thin copper layer having such a large profile (concavity, roughness, roughness) is used, and it is not necessary to be left in the circuit etching. The copper particles cause problems such as poor insulation between circuit patterns.

因此，WO2004/005588號(專利文獻1)中，嘗試使用未對極薄銅層之表面實施粗化處理之附載體銅箔作為以半導體封裝基板為代表之微細電路用途的附載體銅箔。關於此種未實施粗化處理之極薄銅層與樹脂之密接性(剝離強度)，因其較低之輪廓(凹凸、粗度、粗糙度)之影響，若與通常之印刷配線板用銅箔相比則有下降之傾向。因此，對附載體銅箔要求進一步之改善。 Therefore, in WO2004/005588 (Patent Document 1), a copper foil with a carrier which is not subjected to roughening treatment on the surface of the ultra-thin copper layer is used as a carrier-attached copper foil for use as a fine circuit for a semiconductor package substrate. The adhesion (peeling strength) between the ultra-thin copper layer and the resin which are not subjected to the roughening treatment is affected by the lower profile (concavity, roughness, roughness), and the copper for the conventional printed wiring board. There is a tendency for the foil to decrease compared to the foil. Therefore, further improvement is required for the copper foil with a carrier.

因此，日本特開2007-007937號公報(專利文獻2)及日本特開2010-006071號公報(專利文獻3)中，記載有於附載體極薄銅箔之與聚醯亞胺系樹脂基板接觸(接著)之面設置Ni層或/及Ni合金層、設置鉻酸鹽層、設置Cr層或/及Cr合金層、設置Ni層與鉻酸鹽層、設置Ni層與Cr層之情況。藉由設置該等表面處理層，不實施粗化處理而獲得聚醯亞胺系樹脂基板與附載體極薄銅箔之密接強度，或即便降低粗化處理之程度(微細化)亦獲得所需之接著強度。進而，亦記載有利用矽烷偶合劑進行表面處理或實施防銹處理。 In JP-A-2007-007937 (Patent Document 2), JP-A-2010-006071 (Patent Document 3) discloses a contact with a polyimide-based resin substrate in an ultra-thin copper foil with a carrier. On the (subsequent) surface, a Ni layer or/and a Ni alloy layer, a chromate layer, a Cr layer or/and a Cr alloy layer, a Ni layer and a chromate layer, and a Ni layer and a Cr layer are provided. By providing such a surface treatment layer, the adhesion strength between the polyimide film and the carrier-attached ultra-thin copper foil is obtained without performing the roughening treatment, or the degree of the roughening treatment (reduction) is required. Then the intensity. Further, surface treatment or rust prevention treatment using a decane coupling agent is also described.

專利文獻1：WO2004/005588號 Patent Document 1: WO2004/005588

專利文獻2：日本特開2007-007937號公報 Patent Document 2: Japanese Laid-Open Patent Publication No. 2007-007937

專利文獻3：日本特開2010-006071號公報 Patent Document 3: Japanese Laid-Open Patent Publication No. 2010-006071

專利文獻4：日本專利第3261119號公報 Patent Document 4: Japanese Patent No. 3261119

附載體銅箔之開發中，迄今為止重心在於確保極薄銅層與樹脂基材之剝離強度。因此，關於適於印刷配線板之高密度安裝化之附載體銅箔，尚未進行充分之研究，而尚留有改善之餘地。 In the development of the carrier-attached copper foil, the focus has been on ensuring the peel strength of the extremely thin copper layer and the resin substrate. Therefore, there has not been sufficient research on the copper foil with a carrier suitable for high-density mounting of a printed wiring board, and there is still room for improvement.

為了使印刷配線板之積體電路密度上升，通常使用形成雷射孔，通過該孔將內層與外層連接之方法。又，關於伴隨窄間距化之微細電路形成方法，可使用於極薄銅層上形成配線電路後，藉由硫酸-過氧化氫系蝕刻劑將極薄銅層蝕刻去除之方法(MSAP(Modified-Semi-Additive-Process，改良半加成製程))，因此極薄銅層之雷射開孔性於製作高密度積體電路基板之方面為重要之項目。由於極薄銅層之雷射開孔性與孔徑精度以及雷射輸出等各條件相關，因此對積體電路之設計及生產性造成較大影響。日本專利第3261119號公報(專利文獻4)中記載有雷射開孔性良好之覆銅積層板，但根據本案發明人之研究，於蝕刻性之方面尚存在改善之餘地。 In order to increase the density of the integrated circuit of the printed wiring board, a method of forming a laser hole through which the inner layer and the outer layer are connected is generally used. Further, regarding the method of forming a fine circuit with a narrow pitch, a method of etching an extremely thin copper layer by a sulfuric acid-hydrogen peroxide-based etchant after forming a wiring circuit on an extremely thin copper layer (MSAP (Modified- Semi-Additive-Process (modified semi-additive process)), therefore, the laser opening of the ultra-thin copper layer is an important item in the production of a high-density integrated circuit substrate. Since the laser opening property of the extremely thin copper layer is related to the aperture precision and the laser output, the design and productivity of the integrated circuit are greatly affected. Japanese Laid-Open Patent Publication No. 3261119 (Patent Document 4) discloses a copper-clad laminate having excellent laser opening properties. However, according to research by the inventors of the present invention, there is still room for improvement in etchability.

因此，本發明之課題在於提供一種極薄銅層之雷射開孔性良好而適於製作高密度積體電路基板之附載體銅箔。 Accordingly, an object of the present invention is to provide a copper foil with a carrier which is excellent in laser opening properties and which is suitable for producing a high-density integrated circuit board.

為了達成上述目的，本案發明人反覆進行努力研究，結果發現，控制將極薄銅層從進行過規定之加熱處理的附載體銅箔剝離時極薄銅層剝離側利用雷射顯微鏡測量之表面粗糙度，對提高極薄銅層之雷射開孔性極有效。 In order to achieve the above object, the inventors of the present invention conducted an intensive research and found that the surface roughness of the ultra-thin copper layer peeling side measured by a laser microscope when the ultra-thin copper layer was peeled off from the copper foil with a predetermined heat treatment was controlled. Degree is extremely effective for improving the laser opening of the ultra-thin copper layer.

本發明於一態樣中，係一種附載體銅箔，依序具備有載體、中間層、及極薄銅層，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz為1.40μm以上4.05μm以下。 In one aspect of the present invention, a copper foil with a carrier is provided with a carrier, an intermediate layer, and an extremely thin copper layer, and the copper foil of the carrier is heated at 220 ° C for 2 hours, and then stripped according to JIS C 6471. In the case of the ultra-thin copper layer, the surface roughness Sz of the ultra-thin copper layer measured on the intermediate layer side by a laser microscope is 1.40 μm or more and 4.05 μm or less.

本發明之附載體銅箔於一實施形態中，於將該附載體銅箔以 220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz的標準偏差為1.30μm以下。 In one embodiment of the copper foil with carrier of the present invention, the copper foil with the carrier is After heating at 220 ° C for 2 hours, when the ultra-thin copper layer was peeled off in accordance with JIS C 6471, the standard deviation of the surface roughness Sz of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope was 1.30 μm or less.

本發明之附載體銅箔於另一實施形態中，於將該附載體銅箔 以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz的標準偏差為0.01μm以上1.20μm以下。 In another embodiment, the copper foil with carrier of the present invention is used for the copper foil with carrier After heating at 220 ° C for 2 hours, when the ultra-thin copper layer is peeled according to JIS C 6471, the standard deviation of the surface roughness Sz of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope is 0.01 μm or more and 1.20 μm. the following.

本發明之附載體銅箔於再另一實施形態中，於將該附載體銅 箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz為1.60μm以上3.70μm以下。 In still another embodiment of the copper foil with carrier of the present invention, the copper carrier is provided After the foil was heated at 220 ° C for 2 hours, the ultra-thin copper layer was peeled off according to JIS C 6471, and the surface roughness Sz of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope was 1.60 μm or more and 3.70 μm or less.

本發明於另一態樣中，係一種附載體銅箔，依序具備有載 體、中間層、及極薄銅層，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra為0.14μm以上0.35μm以下。 In another aspect of the invention, a copper foil with a carrier is provided with a load in sequence. a body, an intermediate layer, and an ultra-thin copper layer, after the copper foil with the carrier is heated at 220 ° C for 2 hours, when the ultra-thin copper layer is peeled according to JIS C 6471, the ultra-thin copper layer is measured by a laser microscope. The surface roughness Ra of the intermediate layer side is 0.14 μm or more and 0.35 μm or less.

本發明之附載體銅箔於再另一態樣中，於將該附載體銅箔以 220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra的標準偏差為0.11μm以下。 In another aspect of the copper foil with carrier of the present invention, the copper foil with the carrier is After heating at 220 ° C for 2 hours, when the ultra-thin copper layer was peeled off in accordance with JIS C 6471, the standard deviation of the surface roughness Ra of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope was 0.11 μm or less.

本發明之附載體銅箔於再另一態樣中，於將該附載體銅箔以 220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra的標準偏差為0.001μm以上0.10μm以下。 In another aspect of the copper foil with carrier of the present invention, the copper foil with the carrier is After heating at 220 ° C for 2 hours, when the ultra-thin copper layer is peeled off according to JIS C 6471, the standard deviation of the surface roughness Ra of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope is 0.001 μm or more and 0.10 μm or less. .

本發明於再另一態樣中，係一種附載體銅箔，依序具備有載 體、中間層、及極薄銅層，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz為0.62μm以上1.59μm以下，且表面粗糙度Rz之標準偏差為0.51μm以下。 In still another aspect of the present invention, a copper foil with a carrier is provided with a load in sequence. a body, an intermediate layer, and an ultra-thin copper layer, after the copper foil with the carrier is heated at 220 ° C for 2 hours, when the ultra-thin copper layer is peeled according to JIS C 6471, the ultra-thin copper layer is measured by a laser microscope. The surface roughness Rz on the intermediate layer side is 0.62 μm or more and 1.59 μm or less, and the standard deviation of the surface roughness Rz is 0.51 μm or less.

本發明之附載體銅箔於再另一態樣中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz的標準偏差為0.01μm以上0.48μm以下。 In still another aspect of the invention, the copper foil with a carrier is heated by the carrier copper foil at 220 ° C for 2 hours, and the pole is measured by a laser microscope when the ultra-thin copper layer is peeled according to JIS C 6471. The standard deviation of the surface roughness Rz of the thin copper layer on the intermediate layer side is 0.01 μm or more and 0.48 μm or less.

本發明之附載體銅箔於再另一態樣中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面高度分佈的峰度Sku為0.50以上3.70以下。 In still another aspect of the invention, the copper foil with a carrier is heated by the carrier copper foil at 220 ° C for 2 hours, and the pole is measured by a laser microscope when the ultra-thin copper layer is peeled according to JIS C 6471. The kurtosis Sku of the surface height distribution of the thin copper layer on the intermediate layer side is 0.50 or more and 3.70 or less.

本發明之附載體銅箔於再另一態樣中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面高度分佈的峰度Sku為1.00以上3.60以下。 In still another aspect of the invention, the copper foil with a carrier is heated by the carrier copper foil at 220 ° C for 2 hours, and the pole is measured by a laser microscope when the ultra-thin copper layer is peeled according to JIS C 6471. The kurtosis Sku of the surface height distribution of the thin copper layer on the intermediate layer side is 1.00 or more and 3.60 or less.

本發明之附載體銅箔於再另一態樣中，該載體之厚度為5~70μm。 In still another aspect of the copper foil with a carrier of the present invention, the carrier has a thickness of 5 to 70 μm.

本發明之附載體銅箔於再另一態樣中，於該極薄銅層表面具有粗化處理層。 In still another aspect, the copper foil with a carrier of the present invention has a roughened layer on the surface of the ultra-thin copper layer.

本發明之附載體銅箔於再另一態樣中，該粗化處理層係由選自由銅、鎳、磷、鎢、砷、鉬、鉻、鐵、釩、鈷及鋅組成之群中任一單質或含有此等單質任一種以上之合金構成的層。 In still another aspect of the present invention, the roughened layer is selected from the group consisting of copper, nickel, phosphorus, tungsten, arsenic, molybdenum, chromium, iron, vanadium, cobalt, and zinc. A single layer or a layer comprising any one or more of these elements.

本發明之附載體銅箔於再另一態樣中，於該粗化處理層之表 面具有選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層。 The copper foil with carrier of the present invention is in another aspect, in the form of the roughened layer The surface has one or more layers selected from the group consisting of a heat-resistant layer, a rust-preventive layer, a chromate-treated layer, and a decane coupling treatment layer.

本發明之附載體銅箔於再另一態樣中，於該極薄銅層之表面具有選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層。 In still another aspect, the copper foil with a carrier of the present invention has one or more selected from the group consisting of a heat-resistant layer, a rust-preventing layer, a chromate-treated layer, and a decane coupling treatment layer on the surface of the ultra-thin copper layer. Layer.

本發明之附載體銅箔於再另一態樣中，於該極薄銅層上，具備樹脂層。 In still another aspect of the copper foil with a carrier of the present invention, a resin layer is provided on the ultra-thin copper layer.

本發明之附載體銅箔於再另一態樣中，於該粗化處理層上，具備樹脂層。 In still another aspect of the copper foil with a carrier of the present invention, a resin layer is provided on the roughened layer.

本發明之附載體銅箔於再另一態樣中，於該選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層上，具備樹脂層。 In still another aspect, the copper foil with a carrier of the present invention has a resin layer on the layer selected from the group consisting of a heat-resistant layer, a rust-preventing layer, a chromate-treated layer, and a decane coupling treatment layer. .

本發明於再另一態樣中，係一種使用本發明之附載體銅箔製造之印刷配線板。 In still another aspect, the present invention is a printed wiring board manufactured using the copper foil with a carrier of the present invention.

本發明於再另一態樣中，係一種使用本發明之附載體銅箔製造之覆銅積層板。 In still another aspect, the present invention is a copper clad laminate produced using the copper foil with a carrier of the present invention.

本發明於再另一態樣中，係一種使用本發明之印刷配線板製造之電子機器。 In still another aspect, the present invention is an electronic machine manufactured using the printed wiring board of the present invention.

本發明於再另一態樣中，係一種印刷配線板之製造方法，其含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將該附載體銅箔與絕緣基板積層；及於將該附載體銅箔與絕緣基板積層後，經過剝離該附載體銅箔之載體之步驟而形成覆銅積層板，然後，藉由半加成法、減成法、部分加成法或改良半加成法中之任一方法而形成電路。 According to still another aspect of the present invention, a method of manufacturing a printed wiring board, comprising the steps of: preparing a copper foil with an insulating substrate of the present invention and an insulating substrate; laminating the copper foil with the insulating substrate; After the carrier copper foil is laminated with the insulating substrate, the copper-clad laminate is formed by peeling off the carrier with the carrier copper foil, and then, by semi-additive method, subtractive method, partial addition method or modified half-addition A circuit is formed by any of the methods.

本發明於再另一態樣中，係一種印刷配線板之製造方法，其含有如下步驟：於本發明之附載體銅箔之該極薄銅層側表面形成電路；以 埋沒該電路之方式於該附載體銅箔之該極薄銅層側表面形成樹脂層；於該樹脂層上形成電路；於該樹脂層上形成電路後，將該載體剝離；及將該載體剝離後，去除該極薄銅層，藉此使形成於該極薄銅層側表面且埋沒於該樹脂層之電路露出。 In still another aspect of the invention, a method of manufacturing a printed wiring board, comprising the steps of: forming a circuit on a side surface of the ultra-thin copper layer of the copper foil with carrier of the present invention; a method of burying the circuit to form a resin layer on a side surface of the ultra-thin copper layer of the copper foil with a carrier; forming a circuit on the resin layer; peeling off the carrier after forming a circuit on the resin layer; and stripping the carrier Thereafter, the ultra-thin copper layer is removed, whereby the circuit formed on the side surface of the ultra-thin copper layer and buried in the resin layer is exposed.

藉由本發明，可提供一種極薄銅層之雷射開孔性良好而適於製作高密度積體電路基板之附載體銅箔。 According to the present invention, it is possible to provide a copper foil with a carrier which is excellent in laser opening properties and which is suitable for producing a high-density integrated circuit substrate.

圖1係實施例中之電路圖案寬度方向之橫截面的示意圖、及使用該示意圖之蝕刻因數(EF)計算方法之概略。 Fig. 1 is a schematic view showing a cross section of a width direction of a circuit pattern in the embodiment, and an outline of a calculation method of an etching factor (EF) using the schematic diagram.

圖2A~圖2C係使用有本發明之附載體銅箔之印刷配線板其製造方法具體例的至鍍敷電路、去除抗蝕劑為止之步驟中配線板剖面的示意圖。 2A to 2C are schematic views showing a cross section of the wiring board in the step of removing the resist from the plating circuit and the specific example of the method of manufacturing the printed wiring board with the copper foil with a carrier of the present invention.

圖3D~圖3F係使用有本發明之附載體銅箔之印刷配線板其製造方法具體例的自積層樹脂及第2層附載體銅箔至雷射開孔為止之步驟中配線板剖面的示意圖。 FIG. 3D to FIG. 3F are schematic diagrams showing the cross section of the wiring board in the step from the self-laminated resin and the second-layer carrier-attached copper foil to the laser opening using the printed wiring board with the carrier-attached copper foil of the present invention. .

圖4G~圖4I係使用有本發明之附載體銅箔之印刷配線板其製造方法具體例的自形成通孔填充物至剝離第1層載體為止之步驟中配線板剖面的示意圖。 4G to 4I are schematic views showing a cross section of the wiring board in the step from the formation of the via filler to the peeling of the first carrier, in the method of manufacturing the printed wiring board with the copper foil with a carrier of the present invention.

圖5J~圖5K係使用有本發明之附載體銅箔之印刷配線板其製造方法具體例的自快速蝕刻(flash etching)至形成凸塊、銅柱為止之步驟中配線板剖面的示意圖。 5J to 5K are schematic views showing a cross section of a wiring board in a step from flash etching to formation of a bump or a copper pillar in a specific example of a method of manufacturing a printed wiring board with a copper foil with a carrier of the present invention.

<附載體銅箔> <With carrier copper foil>

本發明之附載體銅箔具備載體、積層於載體上之中間層、及積層於中間層上之極薄銅層。附載體銅箔本身之使用方法為本領域業者所周知，例如可將極薄銅層之表面貼合於紙基材酚樹脂、紙基材環氧樹脂、合成纖維布基材環氧樹脂、玻璃布-紙複合基材環氧樹脂、玻璃布-玻璃不織布複合基材環氧樹脂及玻璃布基材環氧樹脂、聚酯膜、聚醯亞胺膜等絕緣基板上，熱壓接後剝離載體，將與絕緣基板接著之極薄銅層蝕刻成目標之導體圖案，最終製造印刷配線板。 The copper foil with a carrier of the present invention comprises a carrier, an intermediate layer laminated on the carrier, and an extremely thin copper layer laminated on the intermediate layer. The method of using the carrier copper foil itself is well known in the art. For example, the surface of the ultra-thin copper layer can be bonded to the paper substrate phenol resin, paper substrate epoxy resin, synthetic fiber cloth substrate epoxy resin, glass. Cloth-paper composite substrate epoxy resin, glass cloth-glass non-woven composite substrate epoxy resin and glass cloth substrate on epoxy resin, polyester film, polyimide film, etc., and the carrier is peeled off after thermocompression bonding A very thin copper layer which is followed by an insulating substrate is etched into a target conductor pattern to finally produce a printed wiring board.

本發明之附載體銅箔於一態樣中，於將附載體銅箔以220℃ 加熱2小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Sz(表面之10點高度)被控制為1.40μm以上4.05μm以下。將附載體銅箔貼合於絕緣基板，熱壓接後剝離載體，將與絕緣基板接著之極薄銅層蝕刻成目標之導體圖案而形成電路。以上述方式使基板成為多層構造而製作印刷配線板。此處，為了使此種印刷配線板之積體電路密度上升，而形成雷射孔，通過該孔使內層與外層連接。此時，若難以於極薄銅層開出雷射孔，則當然成為問題，雷射孔過大或過小均會引起各種問題，因此必須形成為適度之大小。如此，關於極薄銅層之雷射開孔性，由於與孔徑精度以及雷射輸出等各條件相關，因此係對積體電路之設計及生產性造成較大影響之重要特性。本發明中，發現該極薄銅層之雷射開孔性藉由如下操作而變良好，即，於將附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離上述極薄銅層時，利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Sz被控制為1.40μm以上4.05μm以下。若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Sz未達1.40μm，則產生如下問題：極薄銅層表面之粗糙度不足而開孔加工時之雷射之吸收性變差，變得難以開孔，即便開了孔亦成為較小之孔。又，若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Sz超過4.05 μm，則產生如下問題：極薄銅層表面之粗糙度過大而開孔加工時之雷射之吸收性變得過剩，孔變得過大。該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Sz更佳為1.60μm以上3.70μm以下，較佳為1.80μm以上3.50μm以下，進而更佳為2.40μm以上3.70μm以下。再者，上述「以220℃加熱2小時」表示將附載體銅箔貼合於絕緣基板而進行熱壓接之情形時之典型之加熱條件。 The copper foil with carrier of the present invention is in one aspect, and the copper foil with carrier is 220 ° C After heating for 2 hours, when the ultra-thin copper layer was peeled off in accordance with JIS C 6471, the surface roughness Sz (10-point height of the surface) of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side was controlled to be 1.40 μm or more and 4.05 μm. the following. The carrier-attached copper foil is bonded to the insulating substrate, and the carrier is peeled off by thermocompression bonding, and the extremely thin copper layer next to the insulating substrate is etched into a target conductor pattern to form a circuit. The printed wiring board was produced by forming the substrate into a multilayer structure in the above manner. Here, in order to increase the density of the integrated circuit of such a printed wiring board, a laser hole is formed, and the inner layer and the outer layer are connected through the hole. At this time, if it is difficult to open the laser hole in the extremely thin copper layer, it is of course a problem, and if the laser hole is too large or too small, various problems are caused, and therefore it is necessary to form an appropriate size. As described above, the laser opening property of the ultra-thin copper layer is related to various conditions such as the aperture accuracy and the laser output, and is therefore an important characteristic that greatly affects the design and productivity of the integrated circuit. In the present invention, it was found that the laser opening property of the ultra-thin copper layer is improved by the following operation, that is, after the carrier copper foil is heated at 220 ° C for 2 hours, the ultra-thin copper layer is peeled off in accordance with JIS C 6471. In the meantime, the surface roughness Sz of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side is controlled to be 1.40 μm or more and 4.05 μm or less. If the surface roughness Sz of the ultra-thin copper layer measured by the laser microscope on the side of the intermediate layer is less than 1.40 μm, the following problem occurs: the roughness of the surface of the extremely thin copper layer is insufficient and the absorption of the laser during the hole processing is caused. The sex becomes worse and it becomes difficult to open the hole, even if the hole is opened, it becomes a smaller hole. Moreover, if the ultra-thin copper layer measured by the laser microscope has a surface roughness Sz of more than 4.05 on the side of the intermediate layer When μm, there is a problem that the roughness of the surface of the extremely thin copper layer is too large, and the absorption of the laser at the time of the opening processing becomes excessive, and the pore becomes excessive. The surface roughness Sz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is preferably 1.60 μm or more and 3.70 μm or less, preferably 1.80 μm or more and 3.50 μm or less, and more preferably 2.40 μm or more and 3.70 μm or less. . In the above, "heating at 220 ° C for 2 hours" is a typical heating condition in the case where the carrier-attached copper foil is bonded to an insulating substrate and thermocompression bonded.

又，本發明之附載體銅箔較佳為將附載體銅箔以220℃加熱 2小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Sz的標準偏差被控制為1.30μm以下。若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Sz的標準偏差超過1.30μm，則有產生雷射孔徑之不均增大(即標準偏差增大)或蝕刻因數之不均增大(即標準偏差增大)之問題之虞。又，該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Sz之標準偏差更佳為0.01μm以上1.20μm以下，再更佳為0.05μm以上1.10μm以下，尤佳為0.10μm以上1.00μm以下。 Moreover, the copper foil with carrier of the present invention preferably heats the copper foil with carrier at 220 ° C After 2 hours, when the ultra-thin copper layer was peeled off in accordance with JIS C 6471, the standard deviation of the surface roughness Sz of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side was controlled to 1.30 μm or less. If the standard deviation of the surface roughness Sz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side exceeds 1.30 μm, there is an increase in the unevenness of the laser aperture (ie, an increase in the standard deviation) or an etching factor. The problem of uneven increase (ie, increased standard deviation). Further, the standard deviation of the surface roughness Sz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is preferably 0.01 μm or more and 1.20 μm or less, more preferably 0.05 μm or more and 1.10 μm or less, and particularly preferably 0.10. Μm or more and 1.00 μm or less.

本發明之附載體銅箔於另一態樣中，於將附載體銅箔以 220℃加熱2小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Ra(算術平均粗糙度)被控制為0.14μm以上0.35μm以下。將附載體銅箔貼合於絕緣基板，熱壓接後剝離載體，將與絕緣基板接著之極薄銅層蝕刻成目標之導體圖案而形成電路。 以上述方式使基板成為多層構造而製作印刷配線板。此處，為了使此種印刷配線板之積體電路密度上升，而形成雷射孔，並通過該孔使內層與外層連接。此時，若難以於極薄銅層開出雷射孔，則當然成為問題，雷射孔過大或過小均會引起各種問題，因此必須形成為適度之大小。如此，關於極薄銅層之雷射開孔性，由於與孔徑精度以及雷射輸出等各條件相關，因此 係對積體電路之設計及生產性造成較大影響之重要特性。本發明中，發現該極薄銅層之雷射開孔性藉由如下操作而變良好，即，將附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離上述極薄銅層時，利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Ra被控制為0.14μm以上0.35μm以下。若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Ra未達0.14μm，則產生如下問題：極薄銅層表面之粗糙度不足而開孔加工時之雷射吸收性變差，變得難以開孔，即便開了孔亦成為較小之孔。又，若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Ra超過0.35μm，則產生如下問題：極薄銅層表面之粗糙度過大而開孔加工時之雷射吸收性變得過剩，孔變得過大。該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Ra較佳為0.16μm以上0.32μm以下，更佳為0.18μm以上0.32μm以下，進而更佳為0.20μm以上0.32μm以下。又，該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Ra較佳為0.14μm以上0.30μm以下。再者，上述「以220℃加熱2小時」表示將附載體銅箔貼合於絕緣基板進行熱壓接之情形時之典型加熱條件。 The copper foil with carrier of the present invention is in another aspect, After heating at 220 ° C for 2 hours, when the ultra-thin copper layer was peeled off according to JIS C 6471, the surface roughness Ra (arithmetic mean roughness) of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side was controlled to be 0.14 μm or more and 0.35. Below μm. The carrier-attached copper foil is bonded to the insulating substrate, and the carrier is peeled off by thermocompression bonding, and the extremely thin copper layer next to the insulating substrate is etched into a target conductor pattern to form a circuit. The printed wiring board was produced by forming the substrate into a multilayer structure in the above manner. Here, in order to increase the density of the integrated circuit of such a printed wiring board, a laser hole is formed, and the inner layer and the outer layer are connected through the hole. At this time, if it is difficult to open the laser hole in the extremely thin copper layer, it is of course a problem, and if the laser hole is too large or too small, various problems are caused, and therefore it is necessary to form an appropriate size. Thus, the laser opening property of the extremely thin copper layer is related to various conditions such as the aperture accuracy and the laser output. It is an important feature that has a large impact on the design and productivity of the integrated circuit. In the present invention, it has been found that the laser opening property of the ultra-thin copper layer is improved by heating the carrier-attached copper foil at 220 ° C for 2 hours and then peeling off the above-mentioned ultra-thin copper layer in accordance with JIS C 6471. The surface roughness Ra of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side is controlled to be 0.14 μm or more and 0.35 μm or less. If the surface roughness Ra of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is less than 0.14 μm, the following problem occurs: the roughness of the surface of the ultra-thin copper layer is insufficient and the laser absorption during the hole processing is performed. It becomes difficult to open the hole, and even if the hole is opened, it becomes a smaller hole. Further, if the surface roughness Ra of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side exceeds 0.35 μm, the following problem occurs: the roughness of the surface of the ultra-thin copper layer is too large and the laser absorption during the hole processing Sex becomes excessive and the hole becomes too large. The surface roughness Ra of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side is preferably 0.16 μm or more and 0.32 μm or less, more preferably 0.18 μm or more and 0.32 μm or less, and still more preferably 0.20 μm or more and 0.32 μm or less. . Moreover, the surface roughness Ra of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is preferably 0.14 μm or more and 0.30 μm or less. In addition, the above-mentioned "heating at 220 ° C for 2 hours" indicates typical heating conditions in the case where the carrier-attached copper foil is bonded to an insulating substrate and thermocompression bonded.

又，本發明之附載體銅箔較佳為將上述附載體銅箔以220℃ 加熱2小時後，依據JIS C 6471剝離上述極薄銅層時，利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Ra的標準偏差被控制為0.11μm以下。若該利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Ra的標準偏差超過0.11μm，則有產生雷射孔徑之不均增大(即標準偏差增大)或蝕刻因數之不均增大(即標準偏差增大)之問題之虞。 又，該利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Ra之標準偏差較佳為0.001μm以上0.10μm以下，更佳為0.003μm以上0.09μm以下，再更佳為0.005μm以上0.08μm以下，尤佳為0.005μm以上0.06μm以下。 Moreover, the copper foil with carrier of the present invention preferably has the above-mentioned copper foil with a carrier at 220 ° C. After the ultra-thin copper layer was peeled off in accordance with JIS C 6471, the standard deviation of the surface roughness Ra of the ultra-thin copper layer measured on the intermediate layer side by a laser microscope was controlled to be 0.11 μm or less. If the standard deviation of the surface roughness Ra of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side exceeds 0.11 μm, there is an increase in the unevenness of the laser aperture (ie, an increase in the standard deviation) or etching. The problem of an increase in the unevenness of the factor (ie, an increase in the standard deviation). Further, the standard deviation of the surface roughness Ra of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is preferably 0.001 μm or more and 0.10 μm or less, more preferably 0.003 μm or more and 0.09 μm or less, and still more preferably It is 0.005 μm or more and 0.08 μm or less, and more preferably 0.005 μm or more and 0.06 μm or less.

本發明之附載體銅箔於再另一態樣中，將附載體銅箔以 220℃加熱2小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz(十點平均粗糙度)被控制為0.62μm以上1.59μm以下。將附載體銅箔貼合於絕緣基板，熱壓接後剝離載體，將與絕緣基板接著之極薄銅層蝕刻成目標之導體圖案而形成電路。 以上述方式使基板成為多層構造而製作印刷配線板。此處，為了使此種印刷配線板之積體電路密度上升，而形成雷射孔，並通過該孔使內層與外層連接。此時，若難以於極薄銅層開出雷射孔，則當然成為問題，雷射孔過大或過小均會引起各種問題，因此必須形成為適度之大小。如此，關於極薄銅層之雷射開孔性，由於與孔徑精度以及雷射輸出等各條件相關，因此係對積體電路之設計及生產性造成較大影響之重要特性。本發明中，發現該極薄銅層之雷射開孔性藉由如下操作而變良好，即，將附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離上述極薄銅層時，利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Rz被控制為0.62μm以上1.59μm以下。若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz未達0.62μm，則產生如下問題：極薄銅層表面之粗糙度不足而開孔加工時之雷射吸收性變差，變得難以開孔，即便開了孔亦成為較小之孔。又，若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz超過1.59μm，則產生如下問題：極薄銅層表面之粗糙度過大而開孔加工時之雷射之吸收性變得過剩，孔變得過大。該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz較佳為0.70μm以上1.52μm以下，更佳為0.80μm以上1.50μm以下，進而更佳為0.90μm以上1.40μm以下。又，該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz更佳為1.10μm以上1.50μm以下。再者，上述「以220℃加熱2小時」表示將附載體銅箔貼合於絕緣基板進行熱壓接之情形時之典型加熱條件。 In another aspect of the copper foil with carrier of the present invention, the copper foil with a carrier is After heating at 220 ° C for 2 hours, when the ultra-thin copper layer was peeled off according to JIS C 6471, the surface roughness Rz (ten-point average roughness) of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side was controlled to 0.62 μm or more. 1.59 μm or less. The carrier-attached copper foil is bonded to the insulating substrate, and the carrier is peeled off by thermocompression bonding, and the extremely thin copper layer next to the insulating substrate is etched into a target conductor pattern to form a circuit. The printed wiring board was produced by forming the substrate into a multilayer structure in the above manner. Here, in order to increase the density of the integrated circuit of such a printed wiring board, a laser hole is formed, and the inner layer and the outer layer are connected through the hole. At this time, if it is difficult to open the laser hole in the extremely thin copper layer, it is of course a problem, and if the laser hole is too large or too small, various problems are caused, and therefore it is necessary to form an appropriate size. As described above, the laser opening property of the ultra-thin copper layer is related to various conditions such as the aperture accuracy and the laser output, and is therefore an important characteristic that greatly affects the design and productivity of the integrated circuit. In the present invention, it has been found that the laser opening property of the ultra-thin copper layer is improved by heating the carrier-attached copper foil at 220 ° C for 2 hours and then peeling off the above-mentioned ultra-thin copper layer in accordance with JIS C 6471. The surface roughness Rz of the ultra-thin copper layer measured by a laser microscope on the intermediate layer side is controlled to be 0.62 μm or more and 1.59 μm or less. If the surface roughness Rz of the ultra-thin copper layer measured by the laser microscope on the side of the intermediate layer is less than 0.62 μm, the following problem occurs: the roughness of the surface of the ultra-thin copper layer is insufficient and the laser absorption during the hole processing is performed. It becomes difficult to open the hole, and even if the hole is opened, it becomes a smaller hole. Further, if the surface roughness Rz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side exceeds 1.59 μm, the following problem occurs: the roughness of the surface of the ultra-thin copper layer is too large and the laser is used for the hole processing. The absorption becomes excessive and the pores become too large. The surface roughness Rz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is preferably 0.70 μm or more and 1.52 μm or less, more preferably 0.80 μm or more and 1.50 μm or less, and still more preferably 0.90 μm or more and 1.40 μm or less. . Moreover, the surface roughness Rz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is more preferably 1.10 μm or more and 1.50 μm or less. In addition, the above-mentioned "heating at 220 ° C for 2 hours" indicates typical heating conditions in the case where the carrier-attached copper foil is bonded to an insulating substrate and thermocompression bonded.

又，本發明之附載體銅箔中，將附載體銅箔以220℃加熱2 小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之上述極薄銅層於上述中間層側之表面粗糙度Rz的標準偏差被控制為0.51μm以下。 若該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz的標準偏差超過0.51μm，則產生雷射孔徑之不均增大(即標準偏差增大)或蝕刻因數之不均增大(即標準偏差增大)之問題。又，該利用雷射顯微鏡測量之極薄銅層於中間層側之表面粗糙度Rz的標準偏差較佳為0.01μm以上0.48μm以下，更佳為0.04μm以上0.40μm以下，再更佳為0.04μm以上0.35μm以下，尤佳為0.05μm以上0.20μm以下。 Further, in the copper foil with carrier of the present invention, the copper foil with a carrier is heated at 220 ° C. After the etch of the ultra-thin copper layer in accordance with JIS C 6471, the standard deviation of the surface roughness Rz of the ultra-thin copper layer measured on the intermediate layer side by a laser microscope is controlled to 0.51 μm or less. If the standard deviation of the surface roughness Rz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side exceeds 0.51 μm, the unevenness of the laser aperture (ie, the standard deviation is increased) or the etching factor is not generated. The problem of increasing (ie, increasing the standard deviation). Further, the standard deviation of the surface roughness Rz of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side is preferably 0.01 μm or more and 0.48 μm or less, more preferably 0.04 μm or more and 0.40 μm or less, and still more preferably 0.04 or less. The μm or more is 0.35 μm or less, and more preferably 0.05 μm or more and 0.20 μm or less.

又，本發明之附載體銅箔較佳為將附載體銅箔以220℃加熱 2小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之極薄銅層於中間層側之表面高度分佈的峰度Sku(Kurtosis)被控制為0.50以上3.70以下。若Sku未達0.50，則有產生如下問題之虞：由於極薄銅層表面之凸部之形狀變平坦，因此開孔加工時之雷射吸收性變差，變得難以開孔，即便開了孔亦成為較小之孔。又，於Sku大於3.70之情形時，有產生如下問題之虞：極薄銅層表面之凹凸的凸部成為陡峭之形狀，雷射之能量被局部地吸收，相對於雷射之照射徑，實際之孔之大小變大。本發明之附載體銅箔更佳為將附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離極薄銅層時，利用雷射顯微鏡測量之極薄銅層於中間層側之表面高度分佈的峰度Sku被控制為1.00以上3.60以下，再更佳為控制為1.50以上3.30以下，進而再更佳為控制為1.50以上3.20以下，再進而更佳為控制為1.50以上3.10以下，尤佳為控制為1.50以上3.00以下。 Moreover, the copper foil with carrier of the present invention preferably heats the copper foil with carrier at 220 ° C After 2 hours, when the ultra-thin copper layer was peeled off in accordance with JIS C 6471, the kurtosis Sku (Kurtosis) of the surface height distribution of the ultra-thin copper layer measured by the laser microscope on the intermediate layer side was controlled to be 0.50 or more and 3.70 or less. If Sku does not reach 0.50, there is a problem that the shape of the convex portion on the surface of the extremely thin copper layer is flat, so that the laser absorbability at the time of opening processing is deteriorated, and it becomes difficult to open the hole, even if it is opened. The hole also becomes a smaller hole. Further, when the Sku is larger than 3.70, there is a problem that the convex portion of the uneven surface of the ultra-thin copper layer has a steep shape, and the energy of the laser is locally absorbed, and the actual irradiation angle with respect to the laser is actually The size of the hole becomes larger. The copper foil with a carrier of the present invention is more preferably a surface of an extremely thin copper layer measured on a middle layer side by a laser microscope when the copper foil with a carrier is heated at 220 ° C for 2 hours, and the ultra-thin copper layer is peeled according to JIS C 6471. The height distribution kurtosis Sku is controlled to be 1.00 or more and 3.60 or less, and more preferably controlled to 1.50 or more and 3.30 or less, and more preferably controlled to 1.50 or more and 3.20 or less, and more preferably controlled to 1.50 or more and 3.10 or less. The control is preferably 1.50 or more and 3.00 or less.

<載體> <carrier>

本發明中可使用之載體典型為金屬箔或樹脂膜，例如以銅箔、銅合金箔、鎳箔、鎳合金箔、鐵箔、鐵合金箔、不鏽鋼箔、鋁箔、鋁合金箔、絕 緣樹脂膜、聚醯亞胺膜、LCD膜之形態提供。 The carrier usable in the present invention is typically a metal foil or a resin film, such as copper foil, copper alloy foil, nickel foil, nickel alloy foil, iron foil, iron alloy foil, stainless steel foil, aluminum foil, aluminum alloy foil, A resin film, a polyimide film, or an LCD film is provided.

本發明中可使用之載體典型地以壓延銅箔或電解銅箔之形態提供。通常，電解銅箔係於鈦或不鏽鋼之滾筒上由硫酸銅鍍浴電解析出銅而製造，壓延銅箔係反覆進行利用壓延輥之塑性加工與熱處理而製造。作為銅箔之材料，除精銅(JIS H3100合金編號C1100)或無氧銅(JIS H3100合金編號C1020或JIS H3510合金編號C1011)等高純度之銅以外，例如亦可使用摻Sn銅、摻Ag銅、及如添加有Cr、Zr或Mg等之銅合金、添加有Ni及Si等之卡遜系銅合金之銅合金。再者，於本說明書中，於單獨使用術語「銅箔」時，亦包括銅合金箔。 The carrier which can be used in the present invention is typically provided in the form of a rolled copper foil or an electrolytic copper foil. Usually, the electrolytic copper foil is produced by electrolyzing copper from a copper sulfate plating bath on a titanium or stainless steel drum, and the rolled copper foil is repeatedly produced by plastic working and heat treatment using a calender roll. As a material of the copper foil, in addition to high-purity copper such as refined copper (JIS H3100 alloy No. C1100) or oxygen-free copper (JIS H3100 alloy No. C1020 or JIS H3510 alloy No. C1011), for example, Sn-doped copper or Ag-doped may be used. Copper, and a copper alloy to which a Cr alloy such as Cr, Zr, or Mg is added, or a Cason copper alloy to which Ni or Si is added. Further, in the present specification, when the term "copper foil" is used alone, a copper alloy foil is also included.

對本發明中可使用之載體之厚度亦並無特別限制，只要於發 揮作為載體之作用之基礎上適當調節為適合之厚度即可，例如可設為5μm以上。其中，若過厚則生產成本增高，因此通常較佳為設為35μm以下。 因此，載體之厚度典型為8~70μm，更典型為12~70μm，再更典型為18~35μm。又，就降低原料成本之觀點而言，較佳為載體之厚度薄。因此，載體之厚度典型為5μm以上35μm以下，較佳為5μm以上18μm以下，更佳為5μm以上12μm以下，再更佳為5μm以上11μm以下，尤佳為5μm以上10μm以下。再者，於載體之厚度較薄之情形時，於載體之通箔時容易產生折痕。為了防止產生折痕，有效的是例如使附載體銅箔製造裝置之搬送輥變平滑，或縮短搬送輥與下一搬送輥之距離。 There is no particular limitation on the thickness of the carrier that can be used in the present invention, as long as it is The thickness may be appropriately adjusted to suit the thickness of the carrier, and may be, for example, 5 μm or more. However, if the production cost is increased if it is too thick, it is usually preferably 35 μm or less. Therefore, the thickness of the carrier is typically 8 to 70 μm, more typically 12 to 70 μm, and still more typically 18 to 35 μm. Further, from the viewpoint of reducing the cost of raw materials, it is preferred that the thickness of the carrier be thin. Therefore, the thickness of the carrier is typically 5 μm or more and 35 μm or less, preferably 5 μm or more and 18 μm or less, more preferably 5 μm or more and 12 μm or less, still more preferably 5 μm or more and 11 μm or less, and still more preferably 5 μm or more and 10 μm or less. Furthermore, in the case where the thickness of the carrier is thin, creases are likely to occur when the carrier is passed through the foil. In order to prevent creases, it is effective to smooth the conveyance roller of the carrier copper foil manufacturing apparatus, for example, or to shorten the distance between the conveyance roller and the next conveyance roller.

本發明之上述利用雷射顯微鏡測量之極薄銅層於中間層側 的表面粗糙度Sz、Ra、Rz及該等之標準偏差、及Sku可藉由調整載體之極薄銅層側表面形態而加以控制。以下，對本發明之載體之製作方法進行說明。 The above-mentioned ultra-thin copper layer measured by a laser microscope of the present invention is on the middle layer side The surface roughness Sz, Ra, Rz and the standard deviation of these, and Sku can be controlled by adjusting the surface morphology of the extremely thin copper layer of the carrier. Hereinafter, a method of producing the carrier of the present invention will be described.

將使用電解銅箔作為載體時之製造條件之一例示於以下。 One of the production conditions when an electrolytic copper foil is used as a carrier is exemplified below.

<電解液組成> <electrolyte composition>

銅：90~110g/L Copper: 90~110g/L

硫酸：90~110g/L Sulfuric acid: 90~110g/L

氯：50~100ppm Chlorine: 50~100ppm

調平劑1(雙(3-磺丙基)二硫化物)：10~30ppm Leveling agent 1 (bis(3-sulfopropyl) disulfide): 10~30ppm

調平劑2(胺化合物)：10~30ppm Leveling agent 2 (amine compound): 10~30ppm

上述胺化合物可使用以下之化學式之胺化合物。 As the above amine compound, an amine compound of the following chemical formula can be used.

(上述化學式中，R1及R2係選自由羥基烷基、醚基、芳基、芳香族取代烷基、不飽和烴基、烷基組成之一群中者) (In the above chemical formula, R 1 and R 2 are selected from the group consisting of a hydroxyalkyl group, an ether group, an aryl group, an aromatic substituted alkyl group, an unsaturated hydrocarbon group, and an alkyl group)

<製造條件> <Manufacturing conditions>

電流密度：70~100A/dm2 Current density: 70~100A/dm 2

電解液溫度：50~60℃ Electrolyte temperature: 50~60°C

電解液線速：3~5m/sec Electrolyte line speed: 3~5m/sec

電解時間：0.5~10分鐘 Electrolysis time: 0.5~10 minutes

極薄銅層於中間層側之表面粗糙度Sz、Ra、Rz及該等之標準偏差、及Sku係藉由調整載體之極薄銅層側表面形態而加以控制。作為該載體之極薄銅層側表面形態之調整，可列舉以下(1)~(3)之調整法。再者，如表2所述，載體之極薄銅層側表面之形態與載體側極薄銅層表面 之形態成為接近之形態。因此，藉由調整載體之極薄銅層側表面之形態，可獲得具有所需之載體側極薄銅層表面之形態之附載體極薄銅箔。 The surface roughness Sz, Ra, Rz of the ultra-thin copper layer on the intermediate layer side and the standard deviations thereof, and the Sku system are controlled by adjusting the surface morphology of the ultra-thin copper layer side of the carrier. As an adjustment of the surface form of the ultra-thin copper layer of the carrier, the following adjustment methods (1) to (3) are exemplified. Furthermore, as shown in Table 2, the shape of the side surface of the extremely thin copper layer of the carrier and the surface of the extremely thin copper layer on the side of the carrier The form is close to the form. Therefore, by adjusting the morphology of the side surface of the extremely thin copper layer of the carrier, the carrier-attached ultra-thin copper foil having the desired surface of the carrier-side ultra-thin copper layer can be obtained.

(1)對低粗度及高光澤之載體進行軟蝕刻處理或逆電解處理。 (1) A soft etching treatment or a reverse electrolytic treatment is performed on a carrier having a low thickness and a high gloss.

具體而言，對表面粗糙度Rz為0.2μm~0.6μm、或表面粗糙度Ra為0.2μm~0.6μm、或表面粗糙度Sz為0.2μm~0.6μm且60度鏡面光澤度為500%以上之載體進行軟蝕刻處理(例如藉由硫酸5~15vol%、過氧化氫0.5~5.0wt%之水溶液，於10~30℃進行0.5~10分鐘之蝕刻處理)或逆電解處理(對光澤面進行電解研磨而形成凹凸之處理)。 Specifically, the surface roughness Rz is 0.2 μm to 0.6 μm, or the surface roughness Ra is 0.2 μm to 0.6 μm, or the surface roughness Sz is 0.2 μm to 0.6 μm, and the 60-degree specular gloss is 500% or more. The carrier is subjected to a soft etching treatment (for example, an aqueous solution of 5 to 15 vol% of sulfuric acid, 0.5 to 5.0% by weight of hydrogen peroxide, an etching treatment at 10 to 30 ° C for 0.5 to 10 minutes) or a reverse electrolytic treatment (electrolysis of the shiny side) Grinding to form irregularities).

再者，上述「逆電解研磨」為電解研磨。一般電解研磨係以平滑化為目的，因此通常之見解為若對電解銅箔實施電解研磨，則與光澤面為相反側之表面(粗面)成為對象。然而，此處，由於對光澤面進行電解研磨而形成凹凸，因此成為與通常相反之見解之電解研磨處理、即逆電解研磨處理。再者，因逆電解處理產生之銅之溶解量係設為2~20g/m2。又，逆電解研磨處理之電流密度係設為0.5~50A/dm2。 Further, the above "reverse electrolytic polishing" is electrolytic polishing. In general, the electrolytic polishing is aimed at smoothing. Therefore, it is generally understood that when the electrolytic copper foil is subjected to electrolytic polishing, the surface (rough surface) opposite to the shiny surface is targeted. However, here, since the uneven surface is formed by electrolytic polishing of the shiny surface, it is an electrolytic polishing process which is the opposite of the usual, that is, a reverse electrolytic polishing process. Further, the amount of copper dissolved by the reverse electrolytic treatment is set to 2 to 20 g/m 2 . Further, the current density of the reverse electrolytic polishing treatment is set to 0.5 to 50 A/dm 2 .

(2)藉由利用經噴砂處理之壓延輥之壓延而製造載體。 (2) A carrier is produced by calendering using a calendering calendering roll.

具體而言，準備壓延銅箔作為載體，對該壓延銅箔使用藉由噴砂將表面粗化之壓延輥進行最後加工之冷壓延。此時，可設為壓延輥粗糙度Ra=0.39~0.42μm、油膜當量29000~40000。 Specifically, a rolled copper foil is prepared as a carrier, and the rolled copper foil is subjected to cold rolling by final processing using a calender roll which is roughened by sandblasting. In this case, the calender roll roughness Ra = 0.39 to 0.42 μm and the oil film equivalent of 29000 to 40,000.

此處，油膜當量係以如下之式表示。 Here, the oil film equivalent is expressed by the following formula.

油膜當量={(壓延油黏度[cSt])×(通板速度[mpm]+輥周邊速度[mpm])}/{(輥之咬入角[rad])×(材料之降伏應力[kg/mm2])} Oil film equivalent = {(calender oil viscosity [cSt]) × (passing plate speed [mpm] + roll peripheral speed [mpm])} / {(roller bite angle [rad]) × (material fall stress [kg / Mm 2 ])}

壓延油黏度[cSt]為於40℃之動黏度。 The rolling oil viscosity [cSt] is the dynamic viscosity at 40 °C.

為了將油膜當量設為29000~40000，只要利用使用高黏度之壓延油或加快通板速度等公知之方法即可。 In order to set the oil film equivalent to 29,000 to 40,000, a known method such as using a high-viscosity rolling oil or accelerating the speed of the sheet can be used.

(3)藉由規定之電解條件製造載體。 (3) The carrier is produced by the prescribed electrolytic conditions.

具體而言，使用硫酸銅電解液(銅濃度：80~120g/L，硫酸濃度70~90g/L)，並使用高濃度明膠(明膠濃度：3~10質量ppm)作為添加劑，於高電流密度(75~110A/dm2)且高線流速(3.7~5.0m/sec)條件下製作電解銅箔之載體。 Specifically, a copper sulfate electrolyte (copper concentration: 80 to 120 g/L, sulfuric acid concentration: 70 to 90 g/L) is used, and a high concentration gelatin (gelatin concentration: 3 to 10 mass ppm) is used as an additive at a high current density. (75~110A/dm 2 ) and a high-line flow rate (3.7~5.0m/sec) to produce an electrolytic copper foil carrier.

<中間層> <intermediate layer>

於載體之單面或雙面上設置中間層。載體與中間層之間亦可設置其他層。關於本發明中使用之中間層，只要為如下構成，則並無特別限定，即，於附載體銅箔向絕緣基板之積層步驟前極薄銅層不易自載體剝離，另一方面，於向絕緣基板之積層步驟後可自載體剝離極薄銅層的構成。例如，本發明之附載體銅箔之中間層亦可含有選自由Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn、該等之合金、該等之水合物、該等之氧化物、及有機物組成之群中一種或二種以上。又，中間層亦可為複數層。 An intermediate layer is provided on one or both sides of the carrier. Other layers may also be provided between the carrier and the intermediate layer. The intermediate layer used in the present invention is not particularly limited as long as it is a structure in which the ultra-thin copper layer is not easily peeled off from the carrier before the step of laminating the carrier copper foil to the insulating substrate, and the insulating layer is insulated. After the lamination step of the substrate, the ultra-thin copper layer can be peeled off from the carrier. For example, the intermediate layer of the copper foil with a carrier of the present invention may further contain a compound selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, Zn, such alloys, and the like, One or more of these oxides and organic compounds. Also, the intermediate layer may be a plurality of layers.

又，例如，中間層可藉由如下方式構成：自載體側形成由選自由Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中一種元素構成的單一金屬層、或由選自由Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中一種或二種以上之元素構成的合金層，並於其上形成由選自由Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中一種或二種以上之元素之水合物或氧化物構成的層。 Further, for example, the intermediate layer may be formed by forming an element selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn from the carrier side. a single metal layer or an alloy layer composed of one or more elements selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn, and thereon A layer composed of a hydrate or an oxide selected from one or more elements selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn is formed.

於僅於單面設置中間層之情形時，較佳為於載體之相反面設置鍍鎳層等防銹層。再者，認為於藉由鉻酸鹽處理或鋅鉻酸鹽處理或鍍敷處理設置中間層之情形時，存在鉻或鋅等附著之金屬之一部分成為水合物或氧化物之情況。 In the case where the intermediate layer is provided only on one side, it is preferable to provide a rust-proof layer such as a nickel plating layer on the opposite side of the carrier. Further, in the case where the intermediate layer is provided by chromate treatment or zinc chromate treatment or plating treatment, it is considered that a part of the metal to which the chromium or zinc adheres is a hydrate or an oxide.

又，例如，中間層可於載體上依序積層鎳、鎳-磷合金或鎳-鈷合金及鉻而構成。由於鎳與銅之接著力高於鉻與銅之接著力，因此於剝離極薄 銅層時，於極薄銅層與鉻之界面進行剝離。又，對中間層之鎳期待防止銅成分自載體向極薄銅層擴散之阻隔效果。中間層中之鎳附著量較佳為100μg/dm2以上40000μg/dm2以下，更佳為100μg/dm2以上4000μg/dm2以下，再更佳為100μg/dm2以上2500μg/dm2以下，尤佳為100μg/dm2以上未達1000μg/dm2，中間層中之鉻附著量較佳為5μg/dm2以上100μg/dm2以下。於僅於單面設置中間層之情形時，較佳為於載體之相反面設置鍍鎳層等防銹層。 Further, for example, the intermediate layer may be formed by sequentially laminating nickel, a nickel-phosphorus alloy, a nickel-cobalt alloy, and chromium on a carrier. Since the adhesion between nickel and copper is higher than the adhesion between chromium and copper, when the ultra-thin copper layer is peeled off, the interface between the ultra-thin copper layer and chromium is peeled off. Further, the nickel of the intermediate layer is expected to have a barrier effect of preventing the copper component from diffusing from the carrier to the ultra-thin copper layer. Deposited mass of nickel of the intermediate layer is preferably 100μg / dm 2 or more 40000μg / dm 2 or less, more preferably 100μg / dm 2 or more 4000μg / dm 2 or less, and still more preferably 100μg / dm 2 or more 2500μg / dm 2 or less, More preferably, it is 100 μg/dm 2 or more and less than 1000 μg/dm 2 , and the amount of chromium deposited in the intermediate layer is preferably 5 μg/dm 2 or more and 100 μg/dm 2 or less. In the case where the intermediate layer is provided only on one side, it is preferable to provide a rust-proof layer such as a nickel plating layer on the opposite side of the carrier.

<極薄銅層> <very thin copper layer>

於中間層上設置極薄銅層。中間層與極薄銅層之間亦可設置其他層。 極薄銅層可藉由利用硫酸銅、焦磷酸銅、胺基磺酸銅、氰化銅等電解浴之電鍍而形成，就可用於通常之電解銅箔並以高電流密度形成銅箔而言，較佳為硫酸銅浴。極薄銅層之厚度並無特別限制，通常薄於載體，例如為12μm以下。典型為0.5~12μm，更典型為1~5μm，再更典型為1.5~5μm，進而再典型為2~5μm。再者，亦可於載體之雙面設置極薄銅層。 An extremely thin copper layer is provided on the intermediate layer. Other layers may also be provided between the intermediate layer and the ultra-thin copper layer. The ultra-thin copper layer can be formed by electroplating using an electrolytic bath such as copper sulfate, copper pyrophosphate, copper sulfonate or copper cyanide, and can be used for a conventional electrolytic copper foil and forming a copper foil at a high current density. Preferably, it is a copper sulfate bath. The thickness of the ultra-thin copper layer is not particularly limited, and is usually thinner than the carrier, for example, 12 μm or less. Typically, it is 0.5 to 12 μm, more typically 1 to 5 μm, still more typically 1.5 to 5 μm, and further typically 2 to 5 μm. Furthermore, an extremely thin copper layer can be provided on both sides of the carrier.

<粗化處理及其他表面處理> <Coarsening and other surface treatment>

於極薄銅層之表面，亦可例如為了使與絕緣基板之密接性變良好等，而藉由實施粗化處理而設置粗化處理層。粗化處理例如可藉由利用銅或銅合金形成粗化粒子而進行。粗化處理亦可為微細者。粗化處理層亦可為由選自由銅、鎳、磷、鎢、砷、鉬、鉻、鐵、釩、鈷及鋅組成之群中任一單質或含有此等單質任一種以上之合金構成的層等。又，亦可於藉由銅或銅合金形成粗化粒子後，進而進行藉由鎳、鈷、銅、鋅之單質或合金等設置二次粒子或三次粒子之粗化處理。然後，可藉由鎳、鈷、銅、鋅之單質或合金等形成耐熱層或防銹層，進而可對其表面實施鉻酸鹽處理、矽烷偶合處理等處理。或者亦可不進行粗化處理，而藉由鎳、鈷、銅、鋅之單質或合金等形成耐熱層或防銹層，進而對其表面實施鉻酸鹽處理、矽烷偶合處 理等處理。即，可於粗化處理層之表面形成選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層，亦可於極薄銅層之表面形成選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層。再者，上述耐熱層、防銹層、鉻酸鹽處理層、矽烷偶合處理層亦可分別以複數層形成(例如2層以上、3層以上等)。 On the surface of the ultra-thin copper layer, for example, in order to improve the adhesion to the insulating substrate, the roughening treatment layer may be provided by performing the roughening treatment. The roughening treatment can be carried out, for example, by forming roughened particles using copper or a copper alloy. The roughening treatment can also be fine. The roughening treatment layer may also be composed of any element selected from the group consisting of copper, nickel, phosphorus, tungsten, arsenic, molybdenum, chromium, iron, vanadium, cobalt, and zinc, or an alloy containing any one or more of these elements. Layers, etc. Further, after the roughened particles are formed of copper or a copper alloy, the secondary particles or the tertiary particles may be subjected to roughening treatment by a simple substance such as nickel, cobalt, copper or zinc or an alloy. Then, a heat-resistant layer or a rust-preventing layer can be formed by a simple substance such as nickel, cobalt, copper or zinc, or an alloy, and the surface can be subjected to a treatment such as chromate treatment or decane coupling treatment. Alternatively, the heat-resistant layer or the rust-preventing layer may be formed by a single substance or an alloy of nickel, cobalt, copper or zinc, and the surface may be subjected to chromate treatment or decane coupling. Processing. In other words, one or more layers selected from the group consisting of a heat-resistant layer, a rust-preventive layer, a chromate-treated layer, and a decane coupling treatment layer may be formed on the surface of the roughened layer, or may be formed on the surface of the ultra-thin copper layer. One or more layers selected from the group consisting of a heat-resistant layer, a rust-preventive layer, a chromate-treated layer, and a decane coupling treatment layer are selected. Further, the heat-resistant layer, the rust-preventing layer, the chromate-treated layer, and the decane coupling treatment layer may be formed of a plurality of layers (for example, two or more layers, three or more layers, or the like).

例如，作為粗化處理之銅-鈷-鎳合金鍍敷可藉由電解鍍 敷，以形成如附著量為15~40mg/dm2之銅-100~3000μg/dm2之鈷-100~1500μg/dm2之鎳之3元系合金層的方式實施。若Co附著量未達100μg/dm2，則存在耐熱性惡化，蝕刻性變差之情況。若Co附著量超過3000μg/dm2，則存在如下情況，即，於必須考慮磁性之影響之情形時欠佳，產生蝕刻污漬，又，耐酸性及耐化學品性惡化。若Ni附著量未達100μg/dm2，則存在耐熱性變差之情況。另一方面，若Ni附著量超過1500μg/dm2，則存在蝕刻殘留增多之情況。較佳之Co附著量為1000~2500μg/dm2，較佳之鎳附著量為500~1200μg/dm2。此處，所謂蝕刻污漬，係指於利用氯化銅進行蝕刻之情形時，Co未溶解而殘留，並且，所謂蝕刻殘留，係指於利用氯化銨進行鹼蝕刻之情形時，Ni未溶解而殘留。 For example, the copper-cobalt-nickel alloy plating as the roughening treatment can be formed by electrolytic plating to form a cobalt-100-3000 μg/cobalt of 100-3000 μg/dm 2 as a deposition amount of 15 to 40 mg/dm 2 / The implementation of the ternary alloy layer of nickel of dm 2 is carried out. When the Co adhesion amount is less than 100 μg/dm 2 , the heat resistance is deteriorated and the etching property is deteriorated. When the Co adhesion amount exceeds 3000 μg/dm 2 , there is a case where the influence of the magnetic properties is considered to be unsatisfactory, etching stains are generated, and acid resistance and chemical resistance are deteriorated. If the Ni adhesion amount is less than 100 μg/dm 2 , the heat resistance may be deteriorated. On the other hand, when the Ni adhesion amount exceeds 1500 μg/dm 2 , there is a case where the etching residue increases. Preferably, the deposited mass of Co is 1000 ~ 2500μg / dm 2, preferably of the deposited mass of nickel is 500 ~ 1200μg / dm 2. Here, the term "etching stain" means that Co is not dissolved and remains in the case of etching with copper chloride, and the term "etching residue" means that when alkali etching is performed by ammonium chloride, Ni is not dissolved. Residual.

用以形成此種3元系銅-鈷-鎳合金鍍敷之通常之鍍浴及鍍敷條件之一例如下所述：鍍浴組成：Cu 10~20g/L、Co 1~10g/L、Ni 1~10g/L One of the usual plating baths and plating conditions for forming such a ternary copper-cobalt-nickel alloy plating is as follows: plating bath composition: Cu 10-20 g/L, Co 1 10 g/L, Ni 1~10g/L

pH值：1~4 pH: 1~4

溫度：30~50℃ Temperature: 30~50°C

電流密度Dk：20~30A/dm2 Current density D k : 20~30A/dm 2

鍍敷時間：1~5秒 Plating time: 1~5 seconds

以上述方式製造具備載體、積層於載體上之中間層、及積層於中間層上之極薄銅層的附載體銅箔。附載體銅箔本身之使用方法為本領 域業者所周知，例如可將極薄銅層之表面貼合於紙基材酚樹脂、紙基材環氧樹脂、合成纖維布基材環氧樹脂、玻璃布-紙複合基材環氧樹脂、玻璃布-玻璃不織布複合基材環氧樹脂及玻璃布基材環氧樹脂、聚酯膜、聚醯亞胺膜等絕緣基板上，熱壓接後剝離載體而製成覆銅積層板，將與絕緣基板接著之極薄銅層蝕刻成目標之導體圖案，最終製造印刷配線板。 A carrier-attached copper foil having a carrier, an intermediate layer laminated on the carrier, and an ultra-thin copper layer laminated on the intermediate layer was produced in the above manner. The method of using the carrier copper foil itself is As is well known in the art, for example, the surface of an extremely thin copper layer can be bonded to a paper substrate phenol resin, a paper substrate epoxy resin, a synthetic fiber cloth substrate epoxy resin, a glass cloth-paper composite substrate epoxy resin, Glass cloth-glass non-woven composite substrate epoxy resin and glass cloth substrate, such as epoxy resin, polyester film, polyimide film, etc., after hot pressing, peeling off the carrier to form a copper-clad laminate, The insulating substrate is then etched into a target conductor pattern by an extremely thin copper layer to finally produce a printed wiring board.

又，具備載體、積層於載體上之中間層、及積層於中間層上 之極薄銅層的附載體銅箔可於上述極薄銅層上具備粗化處理層，亦可於上述粗化處理層上具備一層以上之選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層構成之群中之層。 Further, it has a carrier, an intermediate layer laminated on the carrier, and a laminate on the intermediate layer The copper foil with a very thin copper layer may have a roughened layer on the ultra-thin copper layer, or may have more than one layer selected from the heat-resistant layer, the rust-proof layer, and the chromate layer on the roughened layer. The layer and the layer of the decane coupling treatment layer.

又，可於上述極薄銅層上具備粗化處理層，可於上述粗化處理層上具備耐熱層、防銹層，可於上述耐熱層、防銹層上具備鉻酸鹽處理層，可於上述鉻酸鹽處理層上具備矽烷偶合處理層。 Further, the ultra-thin copper layer may be provided with a roughened layer, and the heat-treated layer and the rust-preventing layer may be provided on the roughened layer, and the chromate-treated layer may be provided on the heat-resistant layer or the rust-preventing layer. A decane coupling treatment layer is provided on the chromate treatment layer.

又，上述附載體銅箔亦可於上述極薄銅層上、或上述粗化處理層上、或上述耐熱層、防銹層、或鉻酸鹽處理層、或矽烷偶合處理層上具備樹脂層。上述樹脂層亦可為絕緣樹脂層。 Further, the copper foil with a carrier may have a resin layer on the ultra-thin copper layer or the roughened layer or the heat-resistant layer, the rust-proof layer, the chromate-treated layer, or the decane coupling treatment layer. . The above resin layer may also be an insulating resin layer.

上述樹脂層可為接著劑，亦可為接著用之半硬化狀態(B階 段)之絕緣樹脂層。所謂半硬化狀態(B階段狀態)，包括即便以手指接觸其表面亦無黏著感，並可將該絕緣樹脂層重疊而保管，若進而受到加熱處理則產生硬化反應之狀態。 The above resin layer may be an adhesive or a semi-hardened state for subsequent use (B-stage) Section) of the insulating resin layer. In the semi-hardened state (B-stage state), even if the surface is in contact with the finger, there is no adhesive feeling, and the insulating resin layer can be stacked and stored, and if it is further subjected to heat treatment, a curing reaction occurs.

又，上述樹脂層可含有熱硬化性樹脂，亦可為熱塑性樹脂。 又，上述樹脂層亦可含有熱塑性樹脂。其種類並無特別限定，作為較佳者，例如可列舉包含環氧樹脂、聚醯亞胺樹脂、多官能性氰酸酯化合物、順丁烯二醯亞胺化合物、聚乙烯縮醛樹脂、胺酯樹脂等之樹脂。 Further, the resin layer may contain a thermosetting resin or a thermoplastic resin. Further, the resin layer may contain a thermoplastic resin. The type thereof is not particularly limited, and examples thereof include an epoxy resin, a polyimide resin, a polyfunctional cyanate compound, a maleimide compound, a polyvinyl acetal resin, and an amine. A resin such as an ester resin.

上述樹脂層可含有公知之樹脂、樹脂硬化劑、化合物、硬化促進劑、介電體(可使用含有無機化合物及/或有機化合物之介電體、含 有金屬氧化物之介電體等任何介電體)、反應觸媒、交聯劑、聚合物、預浸體、骨架材料等。又，上述樹脂層例如亦可使用國際公開編號WO2008/004399號、國際公開編號WO2008/053878、國際公開編號WO2009/084533、日本特開平11-5828號、日本特開平11-140281號、日本專利第3184485號、國際公開編號WO97/02728、日本專利第3676375號、日本特開2000-43188號、日本專利第3612594號、日本特開2002-179772號、日本特開2002-359444號、日本特開2003-304068號、日本專利第3992225號、日本特開2003-249739號、日本專利第4136509號、日本特開2004-82687號、日本專利第4025177號、日本特開2004-349654號、日本專利第4286060號、日本特開2005-262506號、日本專利第4570070號、日本特開2005-53218號、日本專利第3949676號、日本專利第4178415號、國際公開編號WO2004/005588、日本特開2006-257153號、日本特開2007-326923號、日本特開2008-111169號、日本專利第5024930號、國際公開編號WO2006/028207、日本專利第4828427號、日本特開2009-67029號、國際公開編號WO2006/134868、日本專利第5046927號、日本特開2009-173017號、國際公開編號WO2007/105635、日本專利第5180815號、國際公開編號WO2008/114858、國際公開編號WO2009/008471、日本特開2011-14727號、國際公開編號WO2009/001850、國際公開編號WO2009/145179、國際公開編號WO2011/068157、日本特開2013-19056號中記載之物質(樹脂、樹脂硬化劑、化合物、硬化促進劑、介電體、反應觸媒、交聯劑、聚合物、預浸體、骨架材料等)及/或樹脂層之形成方法、形成裝置而形成。 The resin layer may contain a known resin, a resin curing agent, a compound, a curing accelerator, and a dielectric (a dielectric containing an inorganic compound and/or an organic compound may be used, including Any dielectric body such as a metal oxide dielectric, a reaction catalyst, a crosslinking agent, a polymer, a prepreg, a skeleton material, or the like. In addition, the resin layer may be, for example, International Publication No. WO2008/004399, International Publication No. WO2008/053878, International Publication No. WO2009/084533, Japanese Patent Laid-Open No. Hei No. Hei No. Hei No. Hei. No. 3,184,485, International Publication No. WO97/02728, Japanese Patent No. 3676375, Japanese Patent Laid-Open No. 2000-43188, Japanese Patent No. 3612594, Japanese Patent Laid-Open No. 2002-179772, Japanese Patent Laid-Open No. 2002-359444, Japanese Patent Laid-Open No. 2003 -304068, Japanese Patent No. 3992225, Japanese Patent Laid-Open No. 2003-249739, Japanese Patent No. 4136509, Japanese Patent Laid-Open No. 2004-82687, Japanese Patent No. 4025177, Japanese Patent Laid-Open No. 2004-349654, Japanese Patent No. 4286060 No. 2005-262506, Japanese Patent No. 4570070, Japanese Patent Laid-Open No. 2005-53218, Japanese Patent No. 3949676, Japanese Patent No. 4178415, International Publication No. WO2004/005588, Japanese Patent Publication No. 2006-257153 Japanese Patent Laid-Open No. 2007-326923, Japanese Patent Laid-Open No. 2008-111169, Japanese Patent No. 5024930, International Publication No. WO2006/028207, Japanese Patent No. 4828427, and Japanese Special Open 2009-6 No. 7029, International Publication No. WO2006/134868, Japanese Patent No. 5046927, Japanese Patent Laid-Open No. 2009-173017, International Publication No. WO2007/105635, Japanese Patent No. 5180815, International Publication No. WO2008/114858, International Publication No. WO2009/008471 Substances (resin, resin hardener, compound, etc.) described in Japanese Laid-Open Patent Publication No. 2011-14727, International Publication No. WO2009/001850, International Publication No. WO2009/145179, International Publication No. WO2011/068157, and Japanese Patent Publication No. 2013-19056 It is formed by a hardening accelerator, a dielectric body, a reaction catalyst, a crosslinking agent, a polymer, a prepreg, a skeleton material, and the like, and/or a method of forming a resin layer, and a forming apparatus.

使該等樹脂溶解於例如甲基乙基酮(MEK)、甲苯等溶劑中 而製成樹脂液，藉由例如輥塗法等將其塗佈於上述極薄銅層上、或上述耐熱層、防銹層、或上述鉻酸鹽皮膜層、或上述矽烷偶合劑層上，繼而視需要進行加熱乾燥將溶劑去除而設為B階段狀態。乾燥例如只要使用熱風乾 燥爐即可，乾燥溫度只要為100~250℃、較佳為130~200℃即可。 Dissolving the resins in a solvent such as methyl ethyl ketone (MEK) or toluene The resin liquid is applied to the ultra-thin copper layer, the heat-resistant layer, the rust-preventive layer, the chromate film layer, or the decane coupling agent layer by, for example, a roll coating method. Then, if necessary, heat drying is carried out to remove the solvent and set it to a B-stage state. Drying, for example, by using hot air drying The drying furnace can be used, and the drying temperature is preferably 100 to 250 ° C, preferably 130 to 200 ° C.

具備上述樹脂層之附載體銅箔(附有樹脂之附載體銅箔)係 以如下態樣使用，即，於使其樹脂層與基材重疊後，將整體熱壓接而使該樹脂層熱硬化，繼而剝離載體而使極薄銅層露出(當然露出部分係該極薄銅層於中間層側之表面)，於其上形成規定之配線圖案。 A copper foil with a carrier (the carrier-attached copper foil with a resin) having the above resin layer It is used in such a manner that after the resin layer and the substrate are overlapped, the entire resin layer is thermocompression-bonded to thermally harden the resin layer, and then the carrier is peeled off to expose the ultra-thin copper layer (of course, the exposed portion is extremely thin). The copper layer is on the surface of the intermediate layer side, and a predetermined wiring pattern is formed thereon.

若使用該附有樹脂之附載體銅箔，則可減少多層印刷配線基板之製造時之預浸材料之使用片數。並且，可將樹脂層之厚度設為如可確保層間絕緣之厚度，或即便完全未使用預浸材料，亦可製造覆銅積層板。又，此時，亦可於基材之表面底塗絕緣樹脂而進一步改善表面之平滑性。 When the copper foil with a carrier with a resin is used, the number of sheets of the prepreg used in the production of the multilayer printed wiring board can be reduced. Further, the thickness of the resin layer can be set to such a thickness as to ensure interlayer insulation, or a copper clad laminate can be produced even if the prepreg material is not used at all. Further, at this time, the surface of the substrate may be primed with an insulating resin to further improve the smoothness of the surface.

再者，於不使用預浸材料之情形時，可節約預浸材料之材料成本，又積層步驟亦得以簡化，因此於經濟方面變得有利，並且存在如下優點：僅以預浸材料之厚度程度製造之多層印刷配線基板之厚度變薄，而可製造1層之厚度為100μm以下之極薄之多層印刷配線基板。 Furthermore, when the prepreg material is not used, the material cost of the prepreg material can be saved, and the lamination step can be simplified, which is economically advantageous, and has the following advantages: only the thickness of the prepreg material The thickness of the multilayer printed wiring board to be manufactured is reduced, and it is possible to manufacture a very thin multilayer printed wiring board having a thickness of 100 μm or less.

該樹脂層之厚度較佳為0.1~80μm。 The thickness of the resin layer is preferably from 0.1 to 80 μm.

若樹脂層之厚度薄於0.1μm，則接著力下降，於不介隔預浸材料而將該附有樹脂之附載體銅箔積層於具備內層材料之基材時，存在難以確保與內層材料之電路間之層間絕緣之情況。 When the thickness of the resin layer is less than 0.1 μm, the adhesion force is lowered, and when the resin-attached copper foil with a resin is laminated on the substrate having the inner layer material without interposing the prepreg, it is difficult to secure the inner layer. The case of interlayer insulation between circuits of materials.

另一方面，若使樹脂層之厚度厚於80μm，則難以藉由1次塗佈步驟而形成目標厚度之樹脂層，花費額外之材料費與步驟數，因此於經濟方面變得不利。進而，形成之樹脂層由於其可撓性較差，因此存在如下情況：操作時易於產生龜裂等，又與內層材料之熱壓接時產生過剩之樹脂流動而難以順利地進行積層。 On the other hand, when the thickness of the resin layer is made thicker than 80 μm, it is difficult to form a resin layer having a desired thickness by one application step, and an additional material cost and a number of steps are required, which is disadvantageous in terms of economy. Further, since the resin layer formed is inferior in flexibility, there is a case where cracks or the like are likely to occur during handling, and excessive resin flow occurs during thermal compression bonding with the inner layer material, and it is difficult to smoothly laminate.

進而，作為該附有樹脂之附載體銅箔之另一製品形態，亦可於上述極薄銅層上、或上述耐熱層、防銹層、或上述鉻酸鹽處理層、或上述矽烷偶合處理層上藉由樹脂層進行被覆，使之成為半硬化狀態後，繼而 剝離載體，以不存在載體之附樹脂銅箔之形態來製造。 Further, as another form of the resin-attached copper foil with a resin, the heat-resistant layer, the rust-preventing layer, the chromate-treated layer, or the decane coupling treatment may be applied to the ultra-thin copper layer. The layer is coated with a resin layer to make it semi-hardened, and then The carrier was peeled off and produced in the form of a resin-attached copper foil in the absence of a carrier.

進而，藉由在印刷配線板搭載電子零件類，而完成印刷電路 板。於本發明中，「印刷配線板」亦包括如此搭載有電子零件類之印刷配線板及印刷電路板及印刷基板。 Further, the printed circuit is completed by mounting electronic components on the printed wiring board. board. In the present invention, the "printed wiring board" also includes a printed wiring board, a printed circuit board, and a printed circuit board on which electronic components are mounted.

又，可使用該印刷配線板製作電子機器，亦可使用該搭載有電子零件類之印刷電路板製作電子機器，亦可使用該搭載有電子零件類之印刷基板製作電子機器。以下，表示若干使用有本發明之附載體銅箔之印刷配線板的製造步驟之例。 Moreover, an electronic device can be produced using the printed wiring board, and an electronic device can be produced using the printed circuit board on which the electronic component is mounted, and an electronic device can be produced using the printed circuit board on which the electronic component is mounted. Hereinafter, an example of a manufacturing procedure of a printed wiring board using the copper foil with a carrier of the present invention will be described.

於本發明之印刷配線板之製造方法之一實施形態中，含有如 下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板以極薄銅層側與絕緣基板對向之方式積層後，經過剝離上述附載體銅箔之載體之步驟而形成覆銅積層板，然後，藉由半加成法、改良半加成法、部分加成法及減成法中之任一方法而形成電路。絕緣基板亦可設為具有內層電路者。 In one embodiment of the method for producing a printed wiring board of the present invention, The following steps: preparing the copper foil and the insulating substrate with the carrier of the present invention; laminating the copper foil with the carrier and the insulating substrate; and laminating the copper foil and the insulating substrate with the ultra-thin copper layer side opposite to the insulating substrate Forming a copper-clad laminate by stripping the carrier with the carrier copper foil, and then forming a circuit by any of a semi-additive method, a modified semi-additive method, a partial addition method, and a subtractive method . The insulating substrate may also be provided as an inner layer circuit.

於本發明中，所謂半加成法，係指於絕緣基板或銅箔晶種層 上進行較薄之非電解鍍敷，於形成圖案後，使用電鍍及蝕刻而形成導體圖案之方法。 In the present invention, the so-called semi-additive method refers to an insulating substrate or a copper foil seed layer. A method in which a thin conductor is electrolessly plated and a conductor pattern is formed by plating and etching after patterning.

因此，於使用半加成法之本發明之印刷配線板之製造方法的一實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，將剝離上述載體而露出之極薄銅層全部去除；於藉由利用蝕刻去除上述極薄銅層而露出之上述樹脂設置穿孔(through hole)或/及盲孔(blind via)； 對包含上述穿孔或/及盲孔之區域進行除膠渣處理；對上述樹脂及包含上述穿孔或/及盲孔之區域設置無電解鍍敷層；於上述無電解鍍敷層上設置鍍敷阻劑；對上述鍍敷阻劑進行曝光，然後，將形成電路之區域之鍍敷阻劑去除；於去除上述鍍敷阻劑之上述形成電路之區域設置電解鍍敷層；將上述鍍敷阻劑去除；藉由快速蝕刻等將位於上述形成電路之區域以外之區域的無電解鍍敷層去除。 Therefore, in an embodiment of the method for producing a printed wiring board of the present invention using a semi-additive method, the method comprises the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; and laminating the copper foil with the carrier and the insulating substrate After laminating the carrier-attached copper foil and the insulating substrate, the carrier of the carrier-attached copper foil is peeled off; and the extremely thin copper layer exposed by peeling off the carrier is removed by etching or plasma etching using an acid or the like. Providing a through hole or/and a blind via to expose the resin by removing the ultra-thin copper layer by etching; Performing desmear treatment on the region including the perforation or/and the blind hole; providing an electroless plating layer on the resin and the region including the perforation or/and the blind hole; and providing a plating resistance on the electroless plating layer Exposing the plating resist to the above, and then removing the plating resist in the region where the circuit is formed; and providing an electrolytic plating layer in the region of the circuit forming the plating resist; and removing the plating resist Removal; the electroless plating layer located in the region outside the region where the circuit is formed is removed by rapid etching or the like.

於使用半加成法之本發明之印刷配線板之製造方法的另一 實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；於剝離上述載體而露出之極薄銅層及上述絕緣樹脂基板設置穿孔或/及盲孔；對包含上述穿孔或/及盲孔之區域進行除膠渣處理；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，將剝離上述載體而露出之極薄銅層全部去除；對藉由利用蝕刻等去除上述極薄銅層而露出之上述樹脂及包含上述穿孔或/及盲孔之區域設置無電解鍍敷層；於上述無電解鍍敷層上設置鍍敷阻劑；對上述鍍敷阻劑進行曝光，然後，將形成電路之區域之鍍敷阻劑去除；於去除上述鍍敷阻劑之上述形成電路之區域設置電解鍍敷層；將上述鍍敷阻劑去除；藉由快速蝕刻等將位於上述形成電路之區域以外之區域的無電解鍍敷層去除。 Another method for manufacturing a printed wiring board of the present invention using a semi-additive method The embodiment includes the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; laminating the copper foil with the carrier and the insulating substrate; laminating the copper foil with the carrier and the insulating substrate, and then peeling off the copper foil with the carrier a carrier; a very thin copper layer exposed to peel off the carrier; and the insulating resin substrate provided with perforations or/and blind vias; a desmear treatment of the region including the perforations or/and blind vias; etching solution by using an acid or the like Etching or plasma, etc., removing all of the ultra-thin copper layer exposed by peeling off the carrier; and removing the resin and the region including the perforation or/and blind vias by removing the ultra-thin copper layer by etching or the like An electroless plating layer is disposed; a plating resist is disposed on the electroless plating layer; the plating resist is exposed, and then the plating resist in the region where the circuit is formed is removed; and the plating resistance is removed An electrolytic plating layer is disposed in the region where the circuit is formed; the plating resist is removed; and electroless plating is performed on the region outside the region where the circuit is formed by rapid etching or the like. Layer removal.

於使用半加成法之本發明之印刷配線板之製造方法的另一 實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；於剝離上述載體而露出之極薄銅層及上述絕緣樹脂基板設置穿孔或/及盲孔；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，將剝離上述載體而露出之極薄銅層全部去除；對包含上述穿孔或/及盲孔之區域進行除膠渣處理；對藉由利用蝕刻等去除上述極薄銅層而露出之上述樹脂及包含上述穿孔或/及盲孔之區域設置無電解鍍敷層；於上述無電解鍍敷層上設置鍍敷阻劑；對上述鍍敷阻劑進行曝光，然後，將形成電路之區域之鍍敷阻劑去除；於去除上述鍍敷阻劑之上述形成電路之區域設置電解鍍敷層；將上述鍍敷阻劑去除；藉由快速蝕刻等將位於上述形成電路之區域以外之區域的無電解鍍敷層去除。 Another method for manufacturing a printed wiring board of the present invention using a semi-additive method The embodiment includes the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; laminating the copper foil with the carrier and the insulating substrate; laminating the copper foil with the carrier and the insulating substrate, and then peeling off the copper foil with the carrier a carrier; a very thin copper layer exposed to peel off the carrier; and the insulating resin substrate are provided with perforations or/and blind via holes; and the carrier is peeled off by etching or plasma etching using an acid or the like The copper layer is completely removed; the desmear treatment is performed on the region including the perforation or/and the blind via; and the resin and the region including the perforation or/and the blind via are exposed by removing the ultra-thin copper layer by etching or the like. An electroless plating layer is disposed; a plating resist is disposed on the electroless plating layer; the plating resist is exposed, and then the plating resist in the region where the circuit is formed is removed; and the plating resistance is removed An electrolytic plating layer is disposed in the region where the circuit is formed; the plating resist is removed; and electroless plating is performed on the region outside the region where the circuit is formed by rapid etching or the like. Layer removal.

於使用半加成法之本發明之印刷配線板之製造方法的另一 實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，將剝離上述載體而露出之極薄銅層全部去除；對藉由利用蝕刻去除上述極薄銅層而露出之上述樹脂之表面設置無電解鍍敷層； 於上述無電解鍍敷層上設置鍍敷阻劑；對上述鍍敷阻劑進行曝光，然後，將形成電路之區域之鍍敷阻劑去除；於去除上述鍍敷阻劑之上述形成電路之區域設置電解鍍敷層；將上述鍍敷阻劑去除；藉由快速蝕刻等將位於上述形成電路之區域以外之區域的無電解鍍敷層及極薄銅層去除。 Another method for manufacturing a printed wiring board of the present invention using a semi-additive method The embodiment includes the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; laminating the copper foil with the carrier and the insulating substrate; laminating the copper foil with the carrier and the insulating substrate, and then peeling off the copper foil with the carrier a carrier; the ultra-thin copper layer exposed by peeling off the carrier is removed by etching or plasma etching using an acid or the like; and the surface of the resin exposed by removing the ultra-thin copper layer by etching is provided Electroless plating layer; a plating resist is disposed on the electroless plating layer; the plating resist is exposed, and then the plating resist in the region where the circuit is formed is removed; and the circuit forming region is removed from the plating resist An electrolytic plating layer is provided; the plating resist is removed; and the electroless plating layer and the ultra-thin copper layer in the region outside the region where the circuit is formed are removed by rapid etching or the like.

於本發明中，所謂改良半加成法，係指如下方法：於絕緣層 上積層金屬箔，藉由鍍敷阻劑保護非電路形成部，藉由電解鍍敷增加電路形成部之銅厚後，去除抗蝕劑，藉由(快速)蝕刻去除上述電路形成部以外之金屬箔，藉此於絕緣層上形成電路。 In the present invention, the so-called modified semi-additive method refers to the following method: in the insulating layer The upper metal foil is coated with a resist to protect the non-circuit forming portion, the copper thickness of the circuit forming portion is increased by electrolytic plating, the resist is removed, and the metal other than the circuit forming portion is removed by (fast) etching. A foil is used to form an electrical circuit on the insulating layer.

因此，於使用改良半加成法之本發明之印刷配線板之製造方 法的一實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；於剝離上述載體而露出之極薄銅層與絕緣基板設置穿孔或/及盲孔；對包含上述穿孔或/及盲孔之區域進行除膠渣處理；對包含上述穿孔或/及盲孔之區域設置無電解鍍敷層；於剝離上述載體而露出之極薄銅層表面設置鍍敷阻劑；於設置上述鍍敷阻劑後，藉由電解鍍敷形成電路；將上述鍍敷阻劑去除；藉由快速蝕刻將因去除上述鍍敷阻劑而露出之極薄銅層去除。 Therefore, the manufacturer of the printed wiring board of the present invention using the modified semi-additive method In one embodiment of the present invention, the method further comprises the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; laminating the copper foil with the carrier and the insulating substrate; laminating the copper foil with the carrier and the insulating substrate, and peeling off the carrier a carrier of copper foil; a thin copper layer exposed to the carrier and a perforated or/and blind via hole; and a desmear treatment for the region including the perforation or/and the blind via; And an electroless plating layer is disposed in the region of the blind hole; a plating resist is disposed on the surface of the extremely thin copper layer exposed by peeling off the carrier; after the plating resist is disposed, the circuit is formed by electrolytic plating; The resist is removed; the extremely thin copper layer exposed by removing the plating resist is removed by rapid etching.

於使用改良半加成法之本發明之印刷配線板之製造方法的 另一實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體； 於剝離上述載體而露出之極薄銅層上設置鍍敷阻劑；對上述鍍敷阻劑進行曝光，然後，將形成電路之區域之鍍敷阻劑去除；於去除上述鍍敷阻劑之上述形成電路之區域設置電解鍍敷層；將上述鍍敷阻劑去除；藉由快速蝕刻等將位於上述形成電路之區域以外之區域的無電解鍍敷層及極薄銅層去除。 A method of manufacturing a printed wiring board of the present invention using a modified semi-additive method In another embodiment, the method further comprises the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; laminating the copper foil with the carrier and the insulating substrate; and laminating the copper foil with the carrier and the insulating substrate; Carrier of foil; Providing a plating resist on the extremely thin copper layer exposed by peeling off the carrier; exposing the plating resist, and then removing the plating resist in the region where the circuit is formed; and removing the plating resist An electrolytic plating layer is provided in a region where the circuit is formed; the plating resist is removed; and the electroless plating layer and the ultra-thin copper layer in the region outside the region where the circuit is formed are removed by rapid etching or the like.

於本發明中，所謂部分加成法，係指如下方法：於設置導體 層而成之基板(視需要開出穿孔或通孔用之孔而成之基板)上賦予觸媒核，進行蝕刻而形成導體電路，並視需要設置阻焊劑或鍍敷阻劑後，於上述導體電路上，藉由無電解鍍敷處理對穿孔或通孔等進行增厚，藉此製造印刷配線板。 In the present invention, the partial addition method refers to a method of setting a conductor The catalyst substrate is provided on the substrate (the substrate formed by the hole for the perforation or the through hole as needed), and is etched to form a conductor circuit, and if necessary, a solder resist or a plating resist is provided, On the conductor circuit, a through hole, a through hole, or the like is thickened by an electroless plating process to manufacture a printed wiring board.

因此，於使用部分加成法之本發明之印刷配線板之製造方法 的一實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；於剝離上述載體而露出之極薄銅層與絕緣基板設置穿孔或/及盲孔；對包含上述穿孔或/及盲孔之區域進行除膠渣處理；對包含上述穿孔或/及盲孔之區域賦予觸媒核；於剝離上述載體而露出之極薄銅層表面設置蝕刻阻劑；對上述蝕刻阻劑進行曝光，形成電路圖案；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，去除上述極薄銅層及上述觸媒核，而形成電路；將上述蝕刻阻劑去除；於藉由使用酸等腐蝕溶液之蝕刻或電漿等方法去除上述極薄銅層及上述觸媒核而露出之上述絕緣基板表面設置阻焊劑或鍍敷阻劑； 於未設置上述阻焊劑或鍍敷阻劑之區域設置無電解鍍敷層。 Therefore, the method of manufacturing the printed wiring board of the present invention using the partial addition method In one embodiment, the method further comprises the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; laminating the copper foil with the carrier and the insulating substrate; laminating the copper foil with the carrier and the insulating substrate, and peeling off the copper carrier a carrier for the foil; a perforated or/and blind via provided in the extremely thin copper layer and the insulating substrate exposed to peel off the carrier; and a desmear treatment on the region including the perforation or/and the blind via; a region of the blind hole is provided with a catalyst core; an etching resist is disposed on the surface of the extremely thin copper layer exposed by peeling off the carrier; and the etching resist is exposed to form a circuit pattern; etching or plasma is performed by etching the solution using an acid or the like And removing the ultra-thin copper layer and the catalyst core to form a circuit; removing the etching resist; removing the ultra-thin copper layer and the touch by etching or plasma etching using an acid or the like a solder resist or a plating resist is disposed on the surface of the insulating substrate exposed by the dielectric core; An electroless plating layer is provided in a region where the above-mentioned solder resist or plating resist is not provided.

於本發明中，所謂減成法，係指藉由蝕刻等選擇性地去除覆銅積層板上之銅箔之不需要部分，而形成導體圖案之方法。 In the present invention, the subtractive method refers to a method of forming a conductor pattern by selectively removing unnecessary portions of the copper foil on the copper clad laminate by etching or the like.

因此，於使用減成法之本發明之印刷配線板之製造方法的一實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；於剝離上述載體而露出之極薄銅層與絕緣基板設置穿孔或/及盲孔；對包含上述穿孔或/及盲孔之區域進行除膠渣處理；對包含上述穿孔或/及盲孔之區域設置無電解鍍敷層；於上述無電解鍍敷層之表面設置電解鍍敷層；於上述電解鍍敷層或/及上述極薄銅層之表面設置蝕刻阻劑；對上述蝕刻阻劑進行曝光，形成電路圖案；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，將上述極薄銅層及上述無電解鍍敷層及上述電解鍍敷層去除而形成電路；將上述蝕刻阻劑去除。 Therefore, in one embodiment of the method for producing a printed wiring board of the present invention using the subtractive method, the method includes the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; and laminating the copper foil with the carrier; After laminating the copper foil with the carrier and the insulating substrate, the carrier of the copper foil with the carrier is peeled off; the ultra-thin copper layer and the insulating substrate exposed by peeling off the carrier are provided with perforations or/and blind vias; a region of the blind hole is subjected to desmear treatment; an electroless plating layer is disposed on the region including the perforation or/and the blind hole; an electrolytic plating layer is disposed on the surface of the electroless plating layer; and the electrolytic plating layer or And an etching resistor is disposed on the surface of the ultra-thin copper layer; the etching resist is exposed to form a circuit pattern; and the ultra-thin copper layer and the above-mentioned non-existing layer are formed by etching or plasma etching using an acid or the like The electrolytic plating layer and the electrolytic plating layer are removed to form a circuit; and the etching resist is removed.

於使用減成法之本發明之印刷配線板之製造方法之另一實施形態中，含有如下步驟：準備本發明之附載體銅箔與絕緣基板；將上述附載體銅箔與絕緣基板積層；將上述附載體銅箔與絕緣基板積層後，剝離上述附載體銅箔之載體；於剝離上述載體而露出之極薄銅層與絕緣基板設置穿孔或/及盲孔；對包含上述穿孔或/及盲孔之區域進行除膠渣處理；對包含上述穿孔或/及盲孔之區域設置無電解鍍敷層；於上述無電解鍍敷層之表面形成遮罩；於未形成遮罩之上述無電解鍍敷層之表面設置電解鍍敷層； 於上述電解鍍敷層或/及上述極薄銅層之表面設置蝕刻阻劑；對上述蝕刻阻劑進行曝光，形成電路圖案；藉由使用酸等腐蝕溶液之蝕刻或電漿等方法，將上述極薄銅層及上述無電解鍍敷層去除而形成電路；將上述蝕刻阻劑去除。 Another embodiment of the method for producing a printed wiring board according to the present invention using the subtractive method comprises the steps of: preparing a copper foil with a carrier of the present invention and an insulating substrate; and laminating the copper foil with the carrier and the insulating substrate; After the copper foil with the carrier is laminated with the insulating substrate, the carrier with the carrier copper foil is peeled off; the ultra-thin copper layer and the insulating substrate exposed by peeling off the carrier are provided with perforations or/and blind holes; and the perforations or/and blinds are included The area of the hole is subjected to desmear treatment; an electroless plating layer is disposed on the region including the perforation or/and the blind hole; a mask is formed on the surface of the electroless plating layer; and the electroless plating is performed on the surface without the mask An electrolytic plating layer is disposed on the surface of the coating layer; Providing an etching resist on the surface of the electrolytic plating layer or/and the ultra-thin copper layer; exposing the etching resist to form a circuit pattern; and using etching or plasma etching using an acid or the like The ultra-thin copper layer and the electroless plating layer are removed to form a circuit; the etching resist is removed.

亦可不進行設置穿孔或/及盲孔之步驟、及其後之除膠渣步驟。 The step of providing perforations or/and blind holes, and the subsequent desmear step may also be omitted.

此處，使用圖式詳細地說明使用有本發明之附載體銅箔之印刷配線板之製造方法的具體例。再者，此處，以具有形成有粗化處理層之極薄銅層之附載體銅箔為例進行說明，但並不限定於此，即便使用具有未形成粗化處理層之極薄銅層之附載體銅箔，亦可同樣地進行下述印刷配線板之製造方法。 Here, a specific example of a method of manufacturing a printed wiring board using the copper foil with a carrier of the present invention will be described in detail using the drawings. Here, the copper foil with a carrier having an ultra-thin copper layer in which a roughened layer is formed is described as an example, but the invention is not limited thereto, and even a very thin copper layer having a roughened layer is not used. The carrier copper foil is attached, and the manufacturing method of the following printed wiring board can also be performed similarly.

首先，如圖2-A所示，準備具有於表面形成有粗化處理層之極薄銅層之附載體銅箔(第1層)。 First, as shown in Fig. 2-A, a carrier-attached copper foil (first layer) having an extremely thin copper layer having a roughened layer formed on its surface is prepared.

繼而，如圖2-B所示，於極薄銅層之粗化處理層上塗佈抗蝕劑，進行曝光、顯影，將抗蝕劑蝕刻為規定之形狀。 Then, as shown in FIG. 2-B, a resist is applied onto the roughened layer of the ultra-thin copper layer, exposed and developed, and the resist is etched into a predetermined shape.

繼而，如圖2-C所示，於形成電路用之鍍層後，將抗蝕劑去除，藉此形成規定之形狀之電路鍍敷。 Then, as shown in FIG. 2-C, after the plating for the circuit is formed, the resist is removed, thereby forming a circuit plating of a predetermined shape.

繼而，如圖3-D所示，以覆蓋電路鍍敷之方式(以埋沒電路鍍敷之方式)於極薄銅層上設置埋入樹脂而積層樹脂層，繼而自極薄銅層側接著另一附載體銅箔(第2層)。 Then, as shown in FIG. 3-D, a resin layer is laminated on the ultra-thin copper layer by coating the circuit (in the form of a buried circuit plating), and then the resin layer is laminated on the side of the ultra-thin copper layer. A carrier copper foil (layer 2).

繼而，如圖3-E所示，自第2層之附載體銅箔剝離載體。 Then, as shown in Fig. 3-E, the carrier was peeled off from the carrier copper foil of the second layer.

繼而，如圖3-F所示，於樹脂層之規定位置進行雷射開孔，使電路鍍敷露出而形成盲孔。 Then, as shown in FIG. 3-F, a laser opening is performed at a predetermined position of the resin layer to expose the circuit plating to form a blind hole.

繼而，如圖4-G所示，於盲孔中埋入銅而形成通孔填充物(via fill)。 Then, as shown in FIG. 4-G, copper is buried in the blind via to form a via fill.

繼而，如圖4-H所示，於通孔填充物上，如上述圖2-B及圖2-C般形成電路鍍敷。 Then, as shown in FIG. 4-H, circuit plating is formed on the via fill as in the above-described FIG. 2-B and FIG. 2-C.

繼而，如圖4-I所示，自第1層附載體銅箔剝離載體。 Then, as shown in Fig. 4-I, the carrier was peeled off from the first layer of the carrier-attached copper foil.

繼而，如圖5-J所示，藉由快速蝕刻將兩表面之極薄銅層去除，而使樹脂層內之電路鍍敷之表面露出。 Then, as shown in FIG. 5-J, the extremely thin copper layer on both surfaces is removed by rapid etching to expose the surface of the circuit plating in the resin layer.

繼而，如圖5-K所示，於樹脂層內之電路鍍敷上形成凸塊，於該焊料上形成銅柱。以上述方式製作使用有本發明之附載體銅箔之印刷配線板。 Then, as shown in FIG. 5-K, a bump is formed on the circuit plating in the resin layer, and a copper pillar is formed on the solder. A printed wiring board using the copper foil with a carrier of the present invention was produced in the above manner.

上述另一附載體銅箔(第2層)可使用本發明之附載體銅 箔，亦可使用習知之附載體銅箔，進而亦可使用通常之銅箔。又，於圖4-H所示之第2層之電路上，可進而形成1層或複數層電路，可藉由半加成法、減成法、部分加成法或改良半加成法中之任一方法進行該等電路形成。 The above-mentioned other carrier copper foil (the second layer) can use the copper carrier of the present invention. As the foil, a conventional copper foil may be used, and a usual copper foil may be used. Further, in the circuit of the second layer shown in FIG. 4-H, a one-layer or a plurality of layers can be further formed, which can be formed by a semi-additive method, a subtractive method, a partial addition method or a modified semi-additive method. Either method performs such circuit formation.

藉由如上所述之印刷配線板之製造方法，由於成為將電路鍍 敷埋入樹脂層中之構成，因此於例如圖5-J所示之利用快速蝕刻去除極薄銅層時，電路鍍敷經樹脂層保護，其形狀得以保持，藉此容易形成微細電路。又，由於電路鍍敷經樹脂層保護，因此耐遷移性提高，而良好地抑制電路之配線之導通。因此，容易形成微細電路。又，於如圖5-J及圖5-K所示般藉由快速蝕刻將極薄銅層去除時，電路鍍敷之露出面成為自樹脂層凹陷之形狀，因此於該電路鍍層上容易形成凸塊，進而於其上容易形成銅柱，而提高製造效率。 By the method of manufacturing a printed wiring board as described above, since the circuit is plated The composition is embedded in the resin layer. Therefore, when the ultra-thin copper layer is removed by rapid etching as shown in, for example, FIG. 5-J, the circuit plating is protected by the resin layer, and the shape thereof is maintained, whereby the fine circuit is easily formed. Further, since the circuit plating is protected by the resin layer, the migration resistance is improved, and the wiring of the circuit is favorably suppressed. Therefore, it is easy to form a fine circuit. Further, when the ultra-thin copper layer is removed by rapid etching as shown in FIGS. 5-J and 5-K, the exposed surface of the circuit plating is recessed from the resin layer, so that it is easily formed on the circuit plating layer. The bumps, on the other hand, easily form copper pillars thereon, thereby improving manufacturing efficiency.

再者，埋入樹脂(resin)可使用公知之樹脂、預浸體。例如 可使用BT(雙順丁烯二醯亞胺三)樹脂或作為含浸有BT樹脂之玻璃布之預浸體、Ajinomoto Fine-Techno股份有限公司製造之ABF膜或ABF。又，上述埋入樹脂(resin)可使用本說明書中記載之樹脂層及/或樹脂及/或預浸體。 Further, a well-known resin or prepreg can be used as the resin. For example, BT (bis-s-butylene diimide III) can be used. Resin or prepreg as a glass cloth impregnated with BT resin, ABF film or ABF manufactured by Ajinomoto Fine-Techno Co., Ltd. Further, the resin layer and/or the resin and/or the prepreg described in the present specification can be used as the resin.

又，上述第一層中使用之附載體銅箔可於該附載體銅箔之表 面具有基板或樹脂層。藉由具有該基板或樹脂層，第一層中使用之附載體銅箔受到支撐，不易形成褶皺，因此具有生產性提高之優點。再者，上述基板或樹脂層只要具有支撐上述第一層中使用之附載體銅箔之效果，則可使用所有基板或樹脂層。例如，作為上述基板或樹脂層，可使用本案說明書中記載之載體、預浸體、樹脂層或公知之載體、預浸體、樹脂層、金屬板、金屬箔、無機化合物之板、無機化合物之箔、有機化合物之板、有機化合物之箔。 Further, the copper foil with a carrier used in the first layer may be on the surface of the copper foil with the carrier The surface has a substrate or a resin layer. By having the substrate or the resin layer, the copper foil with a carrier used in the first layer is supported, and wrinkles are less likely to be formed, so that productivity is improved. Further, as long as the substrate or the resin layer has an effect of supporting the copper foil with a carrier used in the first layer, all of the substrate or the resin layer can be used. For example, as the substrate or the resin layer, a carrier, a prepreg, a resin layer, or a known carrier, a prepreg, a resin layer, a metal plate, a metal foil, a plate of an inorganic compound, or an inorganic compound described in the present specification can be used. Foil, plate of organic compound, foil of organic compound.

[實施例] [Examples]

以下，藉由本發明之實施例更詳細地說明本發明，但本發明並不受該等實施例之任何限定。 Hereinafter, the present invention will be described in more detail by way of examples of the invention, but the invention should not be construed as limited.

(實施例1~9、11、12、比較例1~5) (Examples 1 to 9, 11, 12, and Comparative Examples 1 to 5)

於電解槽中配置鈦製旋轉筒，並於筒之周圍隔開極間距離而配置電極。繼而，於電解槽中以表1中記載之載體箔製造條件進行電解，使銅析出於旋轉筒之表面，剝取析出於旋轉筒之表面之銅，連續地製造厚度18μm之電解銅箔，將其設為銅箔載體。再者，關於實施例1、2、6、8、9及12，表面處理後之銅箔載體之厚度分別為12μm、5μm、70μm、12μm、35μm、35μm。又，關於比較例3，設為厚度12μm之銅箔載體。關於實施例1、2、6、8、9及12，於表1中記載之條件對銅箔載體進行表面處理。再者，電解時間設為0.5~2分鐘，電解液溫度設為40~60℃。 A titanium rotating cylinder is disposed in the electrolytic cell, and electrodes are disposed apart from each other by a distance between the electrodes. Then, in the electrolytic cell, electrolysis was carried out under the conditions of the carrier foil described in Table 1, copper was deposited on the surface of the rotating cylinder, and copper deposited on the surface of the rotating cylinder was peeled off, and an electrolytic copper foil having a thickness of 18 μm was continuously produced. It is set as a copper foil carrier. Further, regarding Examples 1, 2, 6, 8, 9, and 12, the thickness of the surface-treated copper foil carrier was 12 μm, 5 μm, 70 μm, 12 μm, 35 μm, and 35 μm, respectively. Further, in Comparative Example 3, a copper foil carrier having a thickness of 12 μm was used. With respect to Examples 1, 2, 6, 8, 9, and 12, the copper foil carrier was subjected to surface treatment under the conditions described in Table 1. Further, the electrolysis time is set to 0.5 to 2 minutes, and the electrolyte temperature is set to 40 to 60 °C.

此處，對實施例2及8之表面處理進行說明。實施例2及8中，於形成之電解銅箔之析出面(亦稱為無光澤面或M面)側配置陰極，將銅箔作為陽極，實施直流之電解處理，藉此對銅箔之無光澤面進行逆電解研磨處理，實施例2中使銅溶解3~8g/m2，實施例8中使銅溶解8~15g/m2。再者，關於逆電解研磨處理之電流密度，實施例2中係設為5~15A/dm2，實施例8中係設為16~25A/dm2。銅箔寬度方向之60度鏡面光澤度為13~ 40，銅箔長度方向之60度鏡面光澤度為20~94。再者，60度鏡面光澤度係使用依據JIS Z8741之日本電色工業股份有限公司製造之光澤度計Handy Gloss Meter PG-1，以入射角60度進行測量。 Here, the surface treatment of Examples 2 and 8 will be described. In Examples 2 and 8, a cathode was disposed on the deposition surface (also referred to as a matte side or M surface) of the formed electrolytic copper foil, and a copper foil was used as an anode, and DC electrolysis treatment was performed to thereby obtain no copper foil. The glossy surface was subjected to a reverse electrolytic polishing treatment. In Example 2, copper was dissolved at 3 to 8 g/m 2 , and in Example 8, copper was dissolved at 8 to 15 g/m 2 . Further, the current density in the reverse electrolytic polishing treatment was 5 to 15 A/dm 2 in the second embodiment and 16 to 25 A/dm 2 in the eighth embodiment. The 60-degree specular gloss of the copper foil in the width direction is 13 to 40, and the 60-degree specular gloss of the copper foil in the longitudinal direction is 20 to 94. Further, the 60-degree specular gloss was measured at an incident angle of 60 degrees using a gloss meter Handy Gloss Meter PG-1 manufactured by Nippon Denshoku Industries Co., Ltd. according to JIS Z8741.

繼而，以如下之條件形成中間層。 Then, the intermediate layer was formed under the following conditions.

以如下條件於輥對輥(roll to roll)型之連續鍍敷線上進行電鍍，藉此形成附著量4000μg/dm2之Ni層。 Electroplating was performed on a continuous roll to roll type of plating line under the following conditions, thereby forming a Ni layer having an adhesion amount of 4000 μg/dm 2 .

‧Ni層 ‧Ni layer

硫酸鎳：250~300g/L Nickel sulfate: 250~300g/L

氯化鎳：35~45g/L Nickel chloride: 35~45g/L

乙酸鎳：10~20g/L Nickel acetate: 10~20g/L

檸檬酸三鈉：15~30g/L Trisodium citrate: 15~30g/L

光澤劑：糖精、丁二醇等 Gloss: saccharin, butylene glycol, etc.

十二烷基硫酸鈉：30~100ppm Sodium lauryl sulfate: 30~100ppm

pH值：4~6 pH: 4~6

浴溫：50~70℃ Bath temperature: 50~70°C

電流密度：3~15A/dm2 Current density: 3~15A/dm 2

水洗及酸洗後，接著於輥對輥型之連續鍍敷線上，以如下條件進行電解鉻酸鹽處理，藉此使附著量11μg/dm2之Cr層附著於Ni層上。 After washing with water and pickling, the electrolytic chromate treatment was carried out on a roll-to-roll type continuous plating line under the following conditions, whereby a Cr layer having an adhesion amount of 11 μg/dm 2 was adhered to the Ni layer.

‧電解鉻酸鹽處理 ‧ electrolytic chromate treatment

液體組成：重鉻酸鉀1~10g/L、鋅0~5g/L Liquid composition: potassium dichromate 1~10g/L, zinc 0~5g/L

pH值：3~4 pH: 3~4

液溫：50~60℃ Liquid temperature: 50~60°C

電流密度：0.1~2.6A/dm2 Current density: 0.1~2.6A/dm 2

庫倫量：0.5~30As/dm2 Coulomb amount: 0.5~30As/dm 2

於形成中間層後，以如下條件於中間層上進行電鍍，藉此形成厚度1~10μm之極薄銅層，而製成附載體銅箔。 After the intermediate layer was formed, electroplating was performed on the intermediate layer under the following conditions, thereby forming an extremely thin copper layer having a thickness of 1 to 10 μm, thereby forming a copper foil with a carrier.

‧極薄銅層 ‧ very thin copper layer

銅濃度：30~120g/L Copper concentration: 30~120g/L

H2SO4濃度：20~120g/L H 2 SO 4 concentration: 20~120g/L

電解液溫度：20~80℃ Electrolyte temperature: 20~80°C

電流密度：10~100A/dm2 Current density: 10~100A/dm 2

再者，實施例2、3中，於極薄銅層上進而設置粗化處理層、耐熱處理層、鉻酸鹽層、矽烷偶合處理層。 Further, in Examples 2 and 3, a roughening treatment layer, a heat-resistant treatment layer, a chromate layer, and a decane coupling treatment layer were further provided on the ultra-thin copper layer.

‧粗化處理 ‧ roughening

Cu：10~20g/L Cu: 10~20g/L

Co：1~10g/L Co: 1~10g/L

Ni：1~10g/L Ni: 1~10g/L

pH值：1~4 pH: 1~4

溫度：40~50℃ Temperature: 40~50°C

電流密度Dk：20~30A/dm2 Current density D k : 20~30A/dm 2

時間：1~5秒 Time: 1~5 seconds

Cu附著量：15~40mg/dm2 Cu adhesion: 15~40mg/dm 2

Co附著量：100~3000μg/dm2 Co adhesion: 100~3000μg/dm 2

Ni附著量：100~1000μg/dm2 Ni adhesion: 100~1000μg/dm 2

‧耐熱處理 ‧ heat treatment

Zn：0~20g/L Zn: 0~20g/L

Ni：0~5g/L Ni: 0~5g/L

pH值：3.5 pH: 3.5

溫度：40℃ Temperature: 40 ° C

電流密度Dk：0~1.7A/dm2 Current density D k : 0~1.7A/dm 2

時間：1秒 Time: 1 second

Zn附著量：5~250μg/dm2 Zn adhesion: 5~250μg/dm 2

Ni附著量：5~300μg/dm2 Ni adhesion: 5~300μg/dm 2

‧鉻酸鹽處理 ‧Chromate treatment

K2Cr2O7 K 2 Cr 2 O 7

(Na2Cr2O7或CrO3)：2~10g/L (Na 2 Cr 2 O 7 or CrO 3 ): 2~10g/L

NaOH或KOH：10~50g/L NaOH or KOH: 10~50g/L

ZnO或ZnSO47H2O：0.05~10g/L ZnO or ZnSO 4 7H 2 O: 0.05~10g/L

pH值：7~13 pH: 7~13

浴溫：20~80℃ Bath temperature: 20~80°C

電流密度：0.05~5A/dm2 Current density: 0.05~5A/dm 2

時間：5~30秒 Time: 5~30 seconds

Cr附著量：10~150μg/dm2 Cr adhesion: 10~150μg/dm 2

‧矽烷偶合處理 ‧decane coupling treatment

乙烯基三乙氧基矽烷水溶液 Vinyl triethoxy decane aqueous solution

(乙烯基三乙氧基矽烷濃度：0.1~1.4wt%) (Vinyl triethoxy decane concentration: 0.1~1.4wt%)

pH值：4~5 pH: 4~5

時間：5~30秒 Time: 5~30 seconds

(實施例10) (Embodiment 10)

準備壓延銅箔(精銅，JIS H3100 C1100)，對該壓延銅箔使用藉由噴砂將表面粗化之壓延輥進行最後加工之冷壓延。此時，設為壓延輥粗糙度Ra=0.39~0.42μm、油膜當量35000。藉此，獲得銅箔載體。 A rolled copper foil (fine copper, JIS H3100 C1100) was prepared, and the calendered copper foil was subjected to cold rolling for final processing by calendering the surface of the calender roll. At this time, the calender roll roughness Ra was 0.39 to 0.42 μm, and the oil film equivalent was 35,000. Thereby, a copper foil carrier was obtained.

繼而，藉由以與實施例1同樣之方式於電解銅箔之表面(無光澤面)形成中間層及極薄銅層而製作附載體銅箔。 Then, an intermediate layer and an ultra-thin copper layer were formed on the surface (matte side) of the electrodeposited copper foil in the same manner as in Example 1 to prepare a copper foil with a carrier.

對於以上述方式獲得之實施例及比較例之附載體銅箔，藉由以下之方法實施各評價。 Each of the evaluations of the copper foil with a carrier of the examples and the comparative examples obtained in the above manner was carried out by the following method.

<極薄銅層之厚度> <thickness of very thin copper layer>

製作之附載體銅箔之極薄銅層之厚度係使用FIB-SIM(Focused Ion Beam-Scanning Ion Microscope，聚焦離子束-掃描離子顯微鏡)進行觀察(倍率：10000~30000倍)。藉由觀察極薄銅層之剖面，以30μm間隔測量5處，並求出平均值。 The thickness of the extremely thin copper layer of the prepared carrier copper foil was observed using a FIB-SIM (Focused Ion Beam-Scanning Ion Microscope) (magnification: 10,000 to 30,000 times). Five spots were measured at intervals of 30 μm by observing the cross section of the extremely thin copper layer, and the average value was determined.

<極薄銅層之表面粗糙度> <Surface roughness of very thin copper layer>

對附載體極薄銅層與基材(三菱瓦斯化學股份有限公司製造，GHPL-832NX-A)進行以220℃加熱2小時之積層加壓後，依據JIS C 6471(1995，再者，剝離銅箔之方法設為8.1銅箔之剝離強度8.1.1試驗方法之種類(1)方法A(相對於銅箔去除面於90°方向上剝離銅箔之方法))將銅箔載體剝離，而使極薄銅層露出。繼而，藉由以下之順序，測量極薄銅層之露出面之各種粗糙度。 The ultra-thin copper layer with a carrier and a substrate (manufactured by Mitsubishi Gas Chemical Co., Ltd., GHPL-832NX-A) were laminated and heated at 220 ° C for 2 hours, and then peeled off according to JIS C 6471 (1995, further The method of the foil is 8.1. The peeling strength of the copper foil is 8.1.1 Type of the test method (1) Method A (method of peeling off the copper foil with respect to the copper foil removal surface in the 90° direction)) The copper foil carrier is peeled off, and An extremely thin copper layer is exposed. Then, various roughnesses of the exposed faces of the extremely thin copper layers were measured by the following procedure.

(1)極薄銅層於中間層側之表面粗糙度 (1) Surface roughness of the ultra-thin copper layer on the side of the intermediate layer

依據JIS B0601-1994，利用奧林巴斯公司製造之雷射顯微鏡OLS4000(LEXT OLS 4000)測量極薄銅層於中間層側之表面粗糙度Rz(雷射)。任意測量10處Rz(雷射)，將該Rz(雷射)之10處之平均值設為Rz(雷射)之值。又，對Rz(雷射)算出10處之值之標準偏差。 According to JIS B0601-1994, the surface roughness Rz (laser) of the ultra-thin copper layer on the intermediate layer side was measured using a laser microscope OLS4000 (LEXT OLS 4000) manufactured by Olympus Corporation. 10 Rz (laser) is arbitrarily measured, and the average value of 10 points of the Rz (laser) is set to the value of Rz (laser). Further, the standard deviation of the values of 10 points was calculated for Rz (laser).

又，依據JIS B0601-1994，利用奧林巴斯公司製造之雷射顯微鏡OLS4000測量極薄銅層於中間層側之表面粗糙度Ra(雷射)。任意測量10處Ra(雷射)，將該Ra(雷射)之10處之平均值設為Ra(雷射)之值。又，對Ra(雷射)算出10處之值之標準偏差。 Further, according to JIS B0601-1994, the surface roughness Ra (laser) of the ultra-thin copper layer on the intermediate layer side was measured using a laser microscope OLS4000 manufactured by Olympus Corporation. Ten Ra (laser) were measured arbitrarily, and the average value of the ten points of the Ra (laser) was set to the value of Ra (laser). Further, the standard deviation of the values of 10 points was calculated for Ra (laser).

又，依據ISO25178，利用奧林巴斯公司製造之雷射顯微鏡OLS4000測量極薄銅層於中間層側之表面粗糙度Sz(雷射)。任意測量10處Sz(雷射)， 將該Sz(雷射)之10處之平均值設為Sz(雷射)之值。又，對Sz(雷射)算出10處之值之標準偏差。 Further, according to ISO 25178, the surface roughness Sz (laser) of the ultra-thin copper layer on the intermediate layer side was measured using a laser microscope OLS4000 manufactured by Olympus Corporation. Measure 10 Sz (laser) arbitrarily, The average value of the 10 points of the Sz (laser) is set to the value of Sz (laser). Further, the standard deviation of the values of 10 points was calculated for Sz (laser).

進而，依據ISO25178，利用奧林巴斯公司製造之雷射顯微鏡OLS4000測量極薄銅層於中間層側之表面之Sku。 Further, according to ISO 25178, the Sku of the ultra-thin copper layer on the surface of the intermediate layer side was measured using a laser microscope OLS4000 manufactured by Olympus Corporation.

(2)形成極薄銅層之側之載體之表面粗糙度 (2) Surface roughness of the carrier forming the side of the extremely thin copper layer

依據JIS B0601-1994，利用奧林巴斯公司製造之雷射顯微鏡OLS4000(LEXT OLS 4000)測量形成極薄銅層之側之載體之表面粗糙度Rz(雷射)。任意測量10處Rz(雷射)，將該Rz(雷射)之10處之平均值設為Rz(雷射)之值。又，對Rz(雷射)算出10處之值之標準偏差。 According to JIS B0601-1994, the surface roughness Rz (laser) of the carrier forming the side of the extremely thin copper layer was measured using a laser microscope OLS4000 (LEXT OLS 4000) manufactured by Olympus Corporation. 10 Rz (laser) is arbitrarily measured, and the average value of 10 points of the Rz (laser) is set to the value of Rz (laser). Further, the standard deviation of the values of 10 points was calculated for Rz (laser).

又，依據JIS B0601-1994，利用奧林巴斯公司製造之雷射顯微鏡OLS4000測量形成極薄銅層之側之載體之表面粗糙度Ra(雷射)。任意測量10處Ra(雷射)，將該Ra(雷射)之10處之平均值設為Ra(雷射)之值。又，算出10處之Ra(雷射)之值之標準偏差。 Further, according to JIS B0601-1994, the surface roughness Ra (laser) of the carrier forming the side of the extremely thin copper layer was measured using a laser microscope OLS4000 manufactured by Olympus Corporation. Ten Ra (laser) were measured arbitrarily, and the average value of the ten points of the Ra (laser) was set to the value of Ra (laser). Further, the standard deviation of the values of Ra (laser) at 10 points was calculated.

又，依據ISO25178，利用奧林巴斯公司製造之雷射顯微鏡OLS4000測量形成極薄銅層之側之載體之表面粗糙度Sz(雷射)。任意測量10處Sz(雷射)，將該Sz(雷射)之10處之平均值設為Sz(雷射)之值。又，對Sz(雷射)算出10處之值之標準偏差。 Further, according to ISO 25178, the surface roughness Sz (laser) of the carrier forming the side of the extremely thin copper layer was measured using a laser microscope OLS4000 manufactured by Olympus Corporation. 10 Sz (laser) is arbitrarily measured, and the average value of 10 points of the Sz (laser) is set to the value of Sz (laser). Further, the standard deviation of the values of 10 points was calculated for Sz (laser).

進而，依據ISO25178，利用奧林巴斯公司製造之雷射顯微鏡OLS4000測量形成極薄銅層之側之載體之表面之Sku。 Further, according to ISO 25178, the SKU of the surface of the carrier forming the side of the extremely thin copper layer was measured using a laser microscope OLS4000 manufactured by Olympus Corporation.

再者，關於上述Rz、Ra，於極薄銅層及載體表面之觀察中，於評價長度(基準長度)257.9μm、截止值零之條件，於載體為壓延銅箔之情形時藉由與壓延方向垂直之方向(TD)之測量，或於載體為電解銅箔之情形時藉由與電解銅箔之製造裝置中之電解銅箔之行進方向垂直之方向(TD)的測量分別求出值。又，關於上述Sz及Sku，於評價面積(基準面積)66524μm2、截止值零之條件對極薄銅層及載體表面進行測量，藉此分別求出值。利用 雷射顯微鏡之表面之Sz、Rz、Ra及Sku之測量環境溫度係設為23~25℃。再者，關於實施例1、2、6、8、9及12，測量表面處理後之銅箔載體之Sz、Ra、Rz及Sku。 Further, regarding the above-mentioned Rz and Ra, in the observation of the ultra-thin copper layer and the surface of the carrier, the evaluation length (reference length) of 257.9 μm and the cutoff value of zero are used in the case where the carrier is a rolled copper foil by calendering and calendering. The direction perpendicular to the direction (TD) is measured, or when the carrier is an electrolytic copper foil, the value is obtained by measuring the direction (TD) perpendicular to the traveling direction of the electrolytic copper foil in the apparatus for manufacturing an electrolytic copper foil. Further, regarding the above-described Sz and Sku, the ultra-thin copper layer and the surface of the carrier were measured under the conditions of an evaluation area (reference area) of 66,524 μm 2 and a cutoff value of zero, thereby obtaining values. The measurement ambient temperature of the surface of the laser microscope using Sz, Rz, Ra, and Sku was set to 23 to 25 °C. Further, regarding Examples 1, 2, 6, 8, 9, and 12, Sz, Ra, Rz, and Sku of the surface-treated copper foil carrier were measured.

<雷射開孔性> <Laser hole opening>

繼而，於極薄銅層之未處理表面(極薄銅層於中間層側表面)，於下述條件下照射1發(one shot)雷射，利用顯微鏡觀察照射後之孔形狀，並實施測量。表中，作為開孔之「實際數量」，表示於12個位置嘗試開孔而實際上開出幾個(X)孔(X/12)，進而表示此時開出之孔之「比率」(%)。又，表中亦對此時產生之孔之平均徑、產生之孔之徑之標準偏差及平均徑/光束徑進行表示。再者，孔之徑係設為包圍孔之最小圓之直徑。 Then, on the untreated surface of the ultra-thin copper layer (the ultra-thin copper layer on the side surface of the intermediate layer), one shot of the laser was irradiated under the following conditions, and the shape of the hole after the irradiation was observed with a microscope, and measurement was performed. . In the table, the "actual quantity" of the opening means that the opening is attempted at 12 positions and actually several (X) holes (X/12) are opened, thereby indicating the "ratio" of the hole opened at this time ( %). Further, the table also shows the average diameter of the pores generated at this time, the standard deviation of the diameter of the generated pores, and the average diameter/beam diameter. Furthermore, the diameter of the hole is set to the diameter of the smallest circle surrounding the hole.

‧氣體種類：CO2 ‧Gas type: CO 2

‧銅箔開口徑(目標)：80μm徑 ‧ Copper foil opening diameter (target): 80μm diameter

‧光束形狀：頂帽(tophat) ‧ Beam shape: top hat

‧輸出：2.40W/10μs ‧ Output: 2.40W/10μs

‧脈衝寬度：33μs ‧ Pulse width: 33μs

‧發數：1發 ‧Number of hair: 1 round

‧開孔數：12孔/區域 ‧Number of openings: 12 holes/area

<蝕刻性> <etching property>

將附載體銅箔貼附於聚醯亞胺基板，以220℃加熱壓接2小時，然後，將極薄銅層自載體剝離。繼而，於聚醯亞胺基板上之極薄銅層表面塗佈感光性抗蝕劑後，藉由曝光步驟印刷50條L/S=5μm/5μm寬之電路，於如下之噴霧蝕刻條件下進行去除銅層之不需要部分之蝕刻處理。 The copper foil with a carrier was attached to the polyimide substrate, and was pressure-bonded at 220 ° C for 2 hours, and then the ultra-thin copper layer was peeled off from the carrier. Then, after applying a photosensitive resist on the surface of the ultra-thin copper layer on the polyimide substrate, 50 circuits of L/S=5 μm/5 μm wide were printed by an exposure step, and subjected to the following spray etching conditions. The etching process of the unnecessary portion of the copper layer is removed.

(噴霧蝕刻條件) (spray etching conditions)

蝕刻液：氯化鐵水溶液(波美度(Baume scale)：40度) Etching solution: aqueous solution of ferric chloride (Baume scale: 40 degrees)

液溫：60℃ Liquid temperature: 60 ° C

噴霧壓：2.0MPa Spray pressure: 2.0MPa

繼續蝕刻，測量電路頂部寬度成為4μm為止之時間，進而評價此時之電路底部寬度(底邊X之長度)及蝕刻因數。關於蝕刻因數，於逐漸變寬地進行蝕刻之情形時(產生塌陷之情形時)，假定電路被垂直地蝕刻時的從自銅箔上表面之垂線與樹脂基板之交點開始之塌陷之長度距離設為a時，表示該a與銅箔之厚度b之比：b/a，該數值越大，意指傾斜角越大，越不殘留蝕刻殘渣，塌陷越小。圖1表示電路圖案之寬度方向之橫截面之示意圖、及使用該示意圖之蝕刻因數之計算方法之概略。該X係藉由自電路上方之SEM觀察而進行測量，並算出蝕刻因數(EF=b/a)。再者，以a=(X(μm)-4(μm))/2進行計算。蝕刻因數表示測量電路中之12點，取平均值而得者。藉此，可簡單地判定蝕刻性之優劣。又，藉由亦算出12點之蝕刻因數之標準偏差，可判定藉由蝕刻形成之電路之直線性之優劣。 The etching was continued, and the time until the top width of the circuit became 4 μm was measured, and the width of the bottom of the circuit (the length of the bottom side X) and the etching factor were evaluated. Regarding the etching factor, when etching is gradually widened (when a collapse occurs), it is assumed that the length of the collapse from the intersection of the perpendicular line from the upper surface of the copper foil and the resin substrate when the circuit is vertically etched is set. When a is a, the ratio of the a to the thickness b of the copper foil: b/a, the larger the value, the larger the inclination angle, the less the etching residue remains, and the smaller the collapse. Fig. 1 is a view showing a schematic cross section of a circuit pattern in the width direction and an outline of a calculation method of an etching factor using the schematic diagram. The X was measured by SEM observation from above the circuit, and the etching factor (EF = b / a) was calculated. Furthermore, calculation was performed with a = (X (μm) - 4 (μm))/2. The etch factor represents 12 points in the measurement circuit and is averaged. Thereby, the merits of the etching property can be easily determined. Further, by calculating the standard deviation of the etching factor of 12 o'clock, the linearity of the circuit formed by etching can be determined.

於本發明中，將蝕刻因數為4以上評價為蝕刻性：○，將2.5以上且未達4評價為蝕刻性：△，將未達2.5或無法算出或無法形成電路評價為蝕刻性：×，將無法剝離評價為蝕刻性：-。又，可認為，蝕刻因數之標準偏差越小電路之直線性越良好。將蝕刻因數之標準偏差未達0.8判斷為直線性：○，將0.8~未達1.2判斷為直線性：△，將1.2以上判斷為直線性：×。 In the present invention, an etching factor of 4 or more is evaluated as etchability: ○, and 2.5 or more and less than 4 are evaluated as etchability: Δ, and a circuit which is less than 2.5 or cannot be calculated or cannot be formed is evaluated as etchability: ×, Will not be peeled off and evaluated as etch:-. Further, it is considered that the smaller the standard deviation of the etching factor, the better the linearity of the circuit. The standard deviation of the etching factor was less than 0.8 and it was judged as linearity: ○, 0.8 to less than 1.2 was judged to be linear: Δ, and 1.2 or more was judged to be linear: ×.

將試驗條件及試驗結果示於表1~3。 The test conditions and test results are shown in Tables 1-3.

(評價結果) (Evaluation results)

實施例1~12中，極薄銅層於中間層側之表面粗糙度Sz(雷射)均為1.40μm以上4.05μm以下，因此雷射開孔性及蝕刻性良好。 In the examples 1 to 12, since the surface roughness Sz (laser) of the ultra-thin copper layer on the intermediate layer side was 1.40 μm or more and 4.05 μm or less, the laser opening property and the etching property were good.

比較例1、5中，極薄銅層於中間層側之表面粗糙度Sz(雷射)均未達1.40μm，因此雷射開孔性不良。 In Comparative Examples 1 and 5, the surface roughness Sz (laser) of the ultra-thin copper layer on the intermediate layer side did not reach 1.40 μm, and thus the laser opening property was poor.

比較例2~4中，極薄銅層於中間層側之表面粗糙度Sz(雷射)均超過4.05μm，因此蝕刻性不良。 In Comparative Examples 2 to 4, the surface roughness Sz (laser) of the ultra-thin copper layer on the intermediate layer side exceeded 4.05 μm, and thus the etching property was poor.

又，實施例1~12中，極薄銅層於中間層側之表面粗糙度Ra(雷射)均為0.14μm以上0.35μm以下，因此雷射開孔性及蝕刻性良好。 In addition, in the examples 1 to 12, since the surface roughness Ra (laser) of the ultra-thin copper layer on the intermediate layer side is 0.14 μm or more and 0.35 μm or less, the laser opening property and the etching property are good.

比較例1、5中，極薄銅層於中間層側之表面粗糙度Ra(雷射)均未達0.14μm，因此雷射開孔性不良。 In Comparative Examples 1 and 5, the surface roughness Ra (laser) of the ultra-thin copper layer on the intermediate layer side was less than 0.14 μm, and thus the laser opening property was poor.

比較例2~4中，極薄銅層於中間層側之表面粗糙度Ra(雷射)均超過0.35μm，因此蝕刻性不良。 In Comparative Examples 2 to 4, the surface roughness Ra (laser) of the ultra-thin copper layer on the intermediate layer side exceeded 0.35 μm, and thus the etching property was poor.

又，實施例1~12中，極薄銅層於中間層側之表面粗糙度Rz(雷射)均為0.62μm以上1.59μm以下，且表面粗糙度Rz(雷射)之標準偏差均為0.51μm以下，因此雷射開孔性及蝕刻性良好。 Further, in Examples 1 to 12, the surface roughness Rz (laser) of the ultra-thin copper layer on the intermediate layer side was 0.62 μm or more and 1.59 μm or less, and the standard deviation of the surface roughness Rz (laser) was 0.51. Since it is not more than μm, the laser opening property and etching property are good.

比較例1、5中，極薄銅層於中間層側之表面粗糙度Rz(雷射)均未達0.62μm，因此雷射開孔性不良。 In Comparative Examples 1 and 5, the surface roughness Rz (laser) of the ultra-thin copper layer on the intermediate layer side was less than 0.62 μm, and thus the laser opening property was poor.

比較例2~4中，極薄銅層於中間層側之表面粗糙度Rz(雷射)均超過1.59μm，因此蝕刻性不良。 In Comparative Examples 2 to 4, the surface roughness Rz (laser) of the ultra-thin copper layer on the intermediate layer side exceeded 1.59 μm, and thus the etching property was poor.

Claims (32)

一種附載體銅箔，依序具備有載體、中間層、及極薄銅層，將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz為1.40μm以上4.05μm以下。 A carrier-attached copper foil is provided with a carrier, an intermediate layer, and an ultra-thin copper layer in this order. After the carrier copper foil is heated at 220 ° C for 2 hours, the laser is removed by peeling the ultra-thin copper layer according to JIS C 6471. The surface roughness Sz of the ultra-thin copper layer measured on the intermediate layer side measured by a microscope is 1.40 μm or more and 4.05 μm or less. 如申請專利範圍第1項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz的標準偏差為1.30μm以下。 The copper foil with a carrier according to the first aspect of the invention, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Sz of the thin copper layer on the intermediate layer side is 1.30 μm or less. 如申請專利範圍第2項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz的標準偏差為0.01μm以上1.20μm以下。 The copper foil with a carrier according to claim 2, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Sz of the thin copper layer on the intermediate layer side is 0.01 μm or more and 1.20 μm or less. 如申請專利範圍第1至3項中任一項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Sz為1.60μm以上3.70μm以下。 The copper foil with a carrier according to any one of claims 1 to 3, wherein after the copper foil of the carrier is heated at 220 ° C for 2 hours, the ultra-thin copper layer is peeled according to JIS C 6471 The surface roughness Sz of the ultra-thin copper layer measured on the intermediate layer side measured by a microscope is 1.60 μm or more and 3.70 μm or less. 如申請專利範圍第1項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra為0.14μm以上0.35μm以下。 The copper foil with a carrier according to the first aspect of the invention, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The surface roughness Ra of the thin copper layer on the intermediate layer side is 0.14 μm or more and 0.35 μm or less. 如申請專利範圍第1項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra的標準偏差為0.11μm以下。 The copper foil with a carrier according to the first aspect of the invention, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Ra of the thin copper layer on the intermediate layer side is 0.11 μm or less. 如申請專利範圍第6項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra的標準偏差為0.001μm以上0.10μm以下。 The carrier copper foil according to claim 6, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Ra of the thin copper layer on the intermediate layer side is 0.001 μm or more and 0.10 μm or less. 如申請專利範圍第1或5項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz為0.62μm以上1.59μm以下，且表面粗糙度Rz之標準偏差為0.51μm以下。 The carrier copper foil according to claim 1 or 5, wherein after the copper foil of the carrier is heated at 220 ° C for 2 hours, the ultra-thin copper layer is peeled according to JIS C 6471, and measured by a laser microscope. The surface roughness Rz of the ultra-thin copper layer on the intermediate layer side is 0.62 μm or more and 1.59 μm or less, and the standard deviation of the surface roughness Rz is 0.51 μm or less. 如申請專利範圍第8項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz的標準偏差為0.01μm以上0.48μm以下。 The copper foil with a carrier according to the eighth aspect of the invention, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Rz of the thin copper layer on the intermediate layer side is 0.01 μm or more and 0.48 μm or less. 一種附載體銅箔，係依序具備有載體、中間層、及極薄銅層，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra為0.14μm以上0.35μm以下。 A carrier-attached copper foil is provided with a carrier, an intermediate layer, and an ultra-thin copper layer in this order. After the copper foil of the carrier is heated at 220 ° C for 2 hours, the ultra-thin copper layer is peeled off according to JIS C 6471. The surface roughness Ra of the ultra-thin copper layer measured on the intermediate layer side measured by a laser microscope is 0.14 μm or more and 0.35 μm or less. 如申請專利範圍第10項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra的標準偏差為0.11μm以下。 The carrier copper foil according to claim 10, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Ra of the thin copper layer on the intermediate layer side is 0.11 μm or less. 如申請專利範圍第11項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Ra的標準偏差為0.001μm以上0.10μm以下。 The carrier-attached copper foil according to claim 11, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Ra of the thin copper layer on the intermediate layer side is 0.001 μm or more and 0.10 μm or less. 如申請專利範圍第10至12項中任一項之附載體銅箔，其中，於將該 附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz為0.62μm以上1.59μm以下，且表面粗糙度Rz之標準偏差為0.51μm以下。 The carrier copper foil according to any one of claims 10 to 12, wherein After the carrier copper foil was heated at 220 ° C for 2 hours, when the ultra-thin copper layer was peeled according to JIS C 6471, the surface roughness Rz of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope was 0.62 μm or more and 1.59. Below μm, and the standard deviation of the surface roughness Rz is 0.51 μm or less. 如申請專利範圍第13項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz的標準偏差為0.01μm以上0.48μm以下。 The carrier copper foil according to claim 13 of the invention, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Rz of the thin copper layer on the intermediate layer side is 0.01 μm or more and 0.48 μm or less. 一種附載體銅箔，依序具備有載體、中間層、及極薄銅層，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz為0.62μm以上1.59μm以下，且表面粗糙度Rz之標準偏差為0.51μm以下。 A copper foil with a carrier, which is provided with a carrier, an intermediate layer, and an ultra-thin copper layer in this order. After the copper foil of the carrier is heated at 220 ° C for 2 hours, the ultra-thin copper layer is stripped according to JIS C 6471. The surface roughness Rz of the ultra-thin copper layer measured on the intermediate layer side measured by a microscope is 0.62 μm or more and 1.59 μm or less, and the standard deviation of the surface roughness Rz is 0.51 μm or less. 如申請專利範圍第15項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面粗糙度Rz的標準偏差為0.01μm以上0.48μm以下。 The copper foil with carrier of claim 15 wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The standard deviation of the surface roughness Rz of the thin copper layer on the intermediate layer side is 0.01 μm or more and 0.48 μm or less. 如申請專利範圍第1至3、5至7、10至12、15及16項中任一項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面高度分佈的峰度Sku為0.50以上3.70以下。 The copper foil with carrier according to any one of claims 1 to 3, 5 to 7, 10 to 12, 15 and 16, wherein the copper foil of the carrier is heated at 220 ° C for 2 hours, according to JIS When C 6471 peels off the ultra-thin copper layer, the kurtosis Sku of the surface height distribution of the ultra-thin copper layer on the intermediate layer side measured by a laser microscope is 0.50 or more and 3.70 or less. 如申請專利範圍第17項之附載體銅箔，其中，於將該附載體銅箔以220℃加熱2小時後，依據JIS C 6471剝離該極薄銅層時，利用雷射顯微鏡測量之該極薄銅層於該中間層側之表面高度分佈的峰度Sku為1.00以上3.60以下。 The copper foil with a carrier according to claim 17, wherein the electrode copper foil is heated at 220 ° C for 2 hours, and the pole thin copper layer is peeled according to JIS C 6471, and the pole is measured by a laser microscope. The kurtosis Sku of the surface height distribution of the thin copper layer on the intermediate layer side is 1.00 or more and 3.60 or less. 如申請專利範圍第1至3、5至7、10至12、15及16項中任一項之附載體銅箔，其中，該載體之厚度為5~70μm。 The carrier copper foil according to any one of claims 1 to 3, 5 to 7, 10 to 12, 15 and 16, wherein the carrier has a thickness of 5 to 70 μm. 如申請專利範圍第1至3、5至7、10至12、15及16項中任一項之附載體銅箔，其中，於該極薄銅層表面具有粗化處理層。 The copper foil with a carrier according to any one of claims 1 to 3, 5 to 7, 10 to 12, 15 and 16, wherein the surface of the ultra-thin copper layer has a roughened layer. 如申請專利範圍第20項之附載體銅箔，其中，該粗化處理層係由選自由銅、鎳、磷、鎢、砷、鉬、鉻、鐵、釩、鈷及鋅組成之群中任一單質或含有此等單質任一種以上之合金構成的層。 The carrier copper foil according to claim 20, wherein the roughening layer is selected from the group consisting of copper, nickel, phosphorus, tungsten, arsenic, molybdenum, chromium, iron, vanadium, cobalt and zinc. A single layer or a layer comprising any one or more of these elements. 如申請專利範圍第20項之附載體銅箔，其中，於該粗化處理層之表面具有選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層。 The carrier-attached copper foil according to claim 20, wherein the surface of the roughened layer has one or more selected from the group consisting of a heat-resistant layer, a rust-preventing layer, a chromate-treated layer, and a decane coupling treatment layer. Layer. 如申請專利範圍第1至3、5至7、10至12、15及16項中任一項之附載體銅箔，其中，於該極薄銅層之表面具有選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層。 The carrier copper foil according to any one of claims 1 to 3, 5 to 7, 10 to 12, 15 and 16, wherein the surface of the ultra-thin copper layer has a heat-resistant layer and a rust-proof layer. One or more layers of the group consisting of a chromate treatment layer and a decane coupling treatment layer. 如申請專利範圍第1至3、5至7、10至12、15及16項中任一項之附載體銅箔，其中，於該極薄銅層上，具備樹脂層。 A copper foil with a carrier according to any one of claims 1 to 3, 5 to 7, 10 to 12, 15 and 16, wherein a resin layer is provided on the ultra-thin copper layer. 如申請專利範圍第20項之附載體銅箔，其中，於該粗化處理層上，具備樹脂層。 The carrier-attached copper foil according to claim 20, wherein a resin layer is provided on the roughened layer. 如申請專利範圍第22項之附載體銅箔，其中，於該選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層上，具備樹脂層。 The carrier-attached copper foil according to claim 22, wherein the resin layer is provided on one or more layers selected from the group consisting of a heat-resistant layer, a rust-preventing layer, a chromate-treated layer, and a decane coupling treatment layer. . 如申請專利範圍第23項之附載體銅箔，其中，於該選自由耐熱層、防銹層、鉻酸鹽處理層及矽烷偶合處理層組成之群中1種以上的層上，具備樹脂層。 The carrier-attached copper foil according to claim 23, wherein the resin layer is provided on one or more layers selected from the group consisting of a heat-resistant layer, a rust-preventing layer, a chromate-treated layer, and a decane coupling treatment layer. . 一種印刷配線板，係使用申請專利範圍第1至27項中任一項之附載體銅箔製造。 A printed wiring board manufactured by using the carrier copper foil of any one of claims 1 to 27. 一種覆銅積層板，係使用申請專利範圍第1至27項中任一項之附載體銅箔製造。 A copper clad laminate produced by using the carrier copper foil of any one of claims 1 to 27. 一種電子機器，係使用申請專利範圍第28項之印刷配線板製造。 An electronic machine manufactured using a printed wiring board of claim 28 of the patent application. 一種印刷配線板之製造方法，其含有如下步驟：準備申請專利範圍第1至27項中任一項之附載體銅箔與絕緣基板；將該附載體銅箔與絕緣基板積層；及於將該附載體銅箔與絕緣基板積層後，經過剝離該附載體銅箔之載體之步驟而形成覆銅積層板，然後，藉由半加成法、減成法、部分加成法或改良半加成法中之任一方法而形成電路。 A method of manufacturing a printed wiring board, comprising the steps of: preparing a copper foil with an insulating substrate and an insulating substrate according to any one of claims 1 to 27; laminating the copper foil with the insulating substrate; After laminating the carrier copper foil and the insulating substrate, the copper-clad laminate is formed by stripping the carrier with the carrier copper foil, and then, by semi-additive method, subtractive method, partial addition method or modified semi-additive A circuit is formed by any of the methods. 一種印刷配線板之製造方法，其含有如下步驟：於申請專利範圍第1至27項中任一項之附載體銅箔之該極薄銅層側表面形成電路；以埋沒該電路之方式於該附載體銅箔之該極薄銅層側表面形成樹脂層；於該樹脂層上形成電路；於該樹脂層上形成電路後，將該載體剝離；及將該載體剝離後，去除該極薄銅層，藉此使形成於該極薄銅層側表面且埋沒於該樹脂層之電路露出。 A manufacturing method of a printed wiring board, comprising the steps of: forming a circuit on a side surface of the ultra-thin copper layer of a copper foil with a carrier of any one of claims 1 to 27; a side surface of the ultra-thin copper layer of the carrier copper foil is formed with a resin layer; a circuit is formed on the resin layer; after the circuit is formed on the resin layer, the carrier is peeled off; and after the carrier is peeled off, the ultra-thin copper is removed The layer is thereby exposed to the circuit formed on the side surface of the ultra-thin copper layer and buried in the resin layer.
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