201026188 υ»υ/αυ^/υ806006 29048twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路基板的電鍍法，且特別是有 關於一種用以將金屬層電鍍於線路基板的接合墊上的電鍍 製程。 【先前技術】 一般而言，線路基板主要由多層線路層（patterned circuiUayer)及多層介電層（dielectriclayer)交替疊合而 成。其中，最外層線路層的接合墊上通常以錄/金層（Ni/Au layer)或其他抗氧化層加以保護，以防止接合墊因環境影 響而氧化，造成接合墊的電性品質下降。 Φ 圖1A至圖1L是習知一種線路基板電鑛方法的流程示 意圖。請先參考圖1A，首先，提供—線路基板1()，此線 路基板10已於-上表面10a形成一第一線路層咖以及一 下表面i〇b形成一第二線路層20b。請參考圖m，接著， 於上表面10a與第-線路層2〇a上形成一第一導電層術 (做為電鍍用的線路），於下表面⑽與第二線路層 上形成-第二導電層勤（做為電顧的線路） 考 =二，著’形成„第一光阻層4〇a於第—導電層‘與 第一¥電層遍上。請參考圖1D，接著，對第一光阻層 ^進行曝光與顯影，以形成—第一圖案化光阻層仏，其 J 一 ί 光阻層―暴露出部份第一導電層30a與部 第一V電層勘。請參考圖1E，接著，移除未被第一圖 201026188 υου,υ^,υ8〇6〇〇6 29048twf.doc/n 案化光阻層42a覆蓋的第一導電層3〇a與第二導電層 勘’以暴露出部份上表面1〇a、部份下表面勘、部份第 ，路層20a與第二線路層2〇b。請參考圖1F，接著，移 除第-圖案化光阻層42a，以暴露位於第一圖案化光阻層 42a下之第一導電層3〇a與第二導電層3〇匕。 請參考圖1G，接著，於第一線路層施、第二線路層 20b、第-導電層3〇a與第二導電層％上形成一第二光阻 層4〇b。喷參考圖1H，接著，對第二光阻層40b進行曝光、 顯影及光固化處理，以形成一第二圖案化光阻層42b，其 中第二圖案化光阻層42b覆蓋圖案化的第-導電層30a以 ，圖案化的第—導電層3Gb，僅顯露出第—線路層施與 $-線路層20b的欲電鑛表面（即接合墊的表面）。請參 ，圖II」接著，將上述步_線路基板放置於電鑛液 未二示）中，並經由圖案化的第一導電層以及圖案 ^第二導電層施供電，以分別形成-第-金屬層50a ，、-第二金屬層通於第_線路層施與第二線路層勘 參上^即接合墊的表面上〕，以防止線路氧化。請參考圖U， 接著，移除第二圖案化光阻層42b、第一導電層3〇a以及 f "if電層3Gt>。請同時參考圖1K與圖1L，之後’微餘 4伤第、線路層20a’以及分別形成一第一圖案化防鲜層 〇a /、第一圖案化防銲層60b於線路基板1〇的上表面 與下表面1%，其中第—圖案化防銲層60a覆蓋第-金 6 50a與第—線路層2〇a,且暴露出部份第—金屬層· 在1知線路基板的電鍍製程中，第一線路層20a以同 201026188 u6u/uu3/u806006 29048twf.doc/n 一表面上的第一導電層30a做為電鍍膜來電鍍第一金屬層 50a’但為了覆蓋圖案化的第一導電層3〇a(如圖1H所示）， 必須先去除第一圖案化光阻層42a，接著再形成第二圖案 化光阻層42b，等到完成第一金屬層5〇a之後，再去除第 一圖案化光阻層42b，因而多增加第二光阻層4〇b形成及 去除步驟（見圖1H及圖1J)。同樣，電鍍第二金屬層5〇b 於第二線路層2〇b上，與上述的製程相同，也多增加第二 ⑩ 光阻層4〇b形成及去除步驟（見圖1H及圖1;)。由於光 阻塗佈、烘烤及固化的時間長，且光罩的數量增加及光阻 曝光顯影的開口對準度必須不斷地調整、檢測，因而浪費 電鐘的時程及成本。此外’光阻在電鍍過程中若溶解於電 鍍液中’將污染電鍍液’進而縮短了電鍍液的使用壽命。 【發明内容】 本發明提供一種線路基板的表面電鑛製程。 ❹ 本發明提出一種線路基板的表面電鍍製程。首先，提 供-線路基板，其中線路基板已於—上表面形成—第一線 路層及於下表面形成一苐二線路層。接著，分別形成一 第-圖案化防_層與-第二圖案化防銲層於線路基板的上 表面與下表面’其中第—圖案化防銲層暴露出部份第一線 路層’第二圖案化麟層暴露㈣份下表面及第二線路 層。形成一第一導電層於第—圖案化防銲層上，且第一 電層覆蓋被暴露出㈣-線路層m光阻層於第 一導電層上。以第一導電層為電鍍膜，形成一第—金屬層 201026188 υου/υυ^/υ306006 29048twf.doc/n 於第-線路層上。移除第一光阻層及第一導電層，以暴露 出部份第-線路層與第—圖案化防鲜層 。形成一第二導電 層於第二圖案化防銲層與第一金屬層上，且第二導電層覆 蓋被暴露出的下表面並包覆第一金屬層。形成一第二光阻 層於第二導電層上。以第二導電層為電鍵膜，形成一第二 金屬，於被暴露出的第—線路層上。之後，移除第二光阻 層及第二導電層’以暴露出部份下表面、第一金屬層及第 ^ 二圖案化防銲層。 在本發明之-實施例中，上述之分別形成第一圖案化 防銲層與第二圖案化防鮮層於線路基板的上表面與下表面 的步驟’首先’分別形成一第一防銲層與一第二防鲜層於 線路基板，其中第一防銲層覆蓋上表面與第一線路層，第 二防銲層覆蓋下表面與第二線路層上。接著，對第一 層與第一防銲層進行曝光與顯影，以形成-第-圖案化防 銲層與一第二圖案化防銲層。 在本發明之一實施例中，上述之形成第一圖案化 響層與第二圖案化防銲層之後，更包括進行照射-紫外光於 第圖案化p方鮮層與第二圖案化防銲層上，以固化第— 案化防銲層與第二圖案化防銲層。 在本發明之一實施例中，上述之形成第一圖案化 層與第二圖案化防銲層之後，更包括進行一熱空氣供烤步 驟，以固化弟一圖案化防銲層與第二圖案化防銲層。 在本發明之-實施例中，上述之形成第一導電層 一圖案化轉層上之前，更包括對第-圖案化防銲層進二 8 201026188 U5u/uud/u806006 29048twf.doc/n 一第一粗化處理。 在本發明之一實施例中’上述之第一粗化處理包括物 理性的粗化處理或化學性的粗化處理。 在本發明之一實施例中，上述之形成第一導電層於第 一圖案化防銲層上的方法包括物理氣相沉積、化學氣相沉 積或化學液相沉積。 在本發明之一實施例中，上述之形成第一光阻層於第 一導電層上之後，更包括照射一紫外光於第一光阻層上， 以固化第一光阻層。 在本發明之一實施例中，上述之照射紫外光於第一光 阻層之後，更包括進行一熱空氣烘烤步驟，以固化第一光 阻層。 在本發明之一實施例中，上述之移除第一光阻層及第 一導電層的方法包括去膜钱刻製程。 沉 參 在本發明之一實施例中，上述之形成第二導電層於第 二圖案化防銲層與第一金屬層上的方法包括物理氣相 積、化學氣相沉積或化學液相沉積。 在本發明之一實施例中，上述之形成第二導電層於第 案化防騎上之前，更包括對第二圖案 一第二粗化處理。 叶增延仃 在本發明之—實施射，上述之第二粗化處理包 理性的粗化處理或化學性的粗化處理。 =發明之—實關巾，上叙形成第二光阻層 -導電層上之後，更包括照射—紫外光於第二光阻層上， 9 201026188 υ〇υ/υυ^,υί〇6〇〇6 29048twf.doc/n 以固化第二光阻層。 在本發明之一實施例中，上述之照射紫 ^ 阻層上之後，更包括進行一熱空氣烘烤步驟、於第二光 光阻層。 ’以固化第二 在本發明之一實施例中，上述之移除 ， 二導電層的方法包括去膜蝕刻製程。’、〜光阻層及第 在本發明之一實施例中，上述之第一 括錫、錫合金、金_金。 料層的材質包 在本發明之一實施例中，上述之 括錫、錫合金、金或鎳金。 金屬層的材質包 ^在本發明之一實施例中，上述之第―圖案化 露出的部份第-線路層為—銲罩㈣型的接^墊。、曰暴 先於砂树_祕純喊μ鍵製程是 _ 开m "形成圖案储銲層後，再於_化防銲層上 成=層’且具有多次去光阻層的步驟，以及對光阻層 罩m的步驟’因此本發明除了可減少所需之光 、里卜，尚能減少光阻層在電鍍過程中溶解量，其具 相躺成效，且為本領域巾熟知該技術者所不易聯 想的難度克服。 為讓本發明之上述和其他目的、特徵和伽能更明顯 ，下文特舉實施例’並配合所附圖式作詳細說明如下。 v>806006 29048twf.doc/n 201026188 【實施方式】 圖2Α至圖2Κ為本發明之一實施例之一種線路基板 的表面電鍍製程的流程示意圖。請先參考圖2Α，關於本實 施例的線路基板的表面電鍍製程，首先，提供一線路基板 100，其中此線路基板100已於一上表面l〇〇a形成一第一 線路層110a及於一下表面l〇0b形成一第二線路層11%。 在本實施例中’第一線路層ll〇a與第二線路層的材 質例如是銅。 請參考圖2B，接著，分別形成一第一防銲層12如與 一第二防銲層120b於線路基板1〇〇上，其中第一防銲層 120a覆蓋線路基板1〇〇的上表面i〇〇a與第一線路層 110a，第二防銲層120b覆蓋線路基板1〇〇的下表面1〇% 與第二線路層110b上。 請參考圖2C，接著，對第一防銲層12〇a與第二防銲 層120b進行曝光與顯影，以分別形成一第一圖案化防銲層 122a與一第二圖案化防銲層i22b於線路基板1〇〇的上表 面100a與下表面l〇〇b，其中第—圖案化防銲層122a暴露 出部份第一線路層110a，第二圖案化防銲層122b暴露出 部份下表面100b及第二線路層i1〇b。 在本實施例中，完成前述之第一圖案化防銲層122a與第二 圖案化防銲層122b之後’更包括進行照射一紫外光於第一 圖案化防銲層122a與第二圖案化防銲層12沘上，以固化 第一圖案化防銲層122a與第二圖案化防銲層122b。此外， 於其他實施射’在進行完照射料光後，更可以選擇性 201026188 vw/\jyj/vi06006 29048twf.doc/n 地包括進行一熱空氣烘烤步驟，以固化第一圖案化防銲層 122a與第二圖案化防銲層122b。另外，於其他未繪示實施 例中，το成則述之第一圖案化防銲層122&與第二圖案化防 銲層122b之後，更包括進行一熱空氣烘烤步驟，以固化第 一圖案化防銲層122a與第二圖案化防銲層122b。當然， 在進行完前述之熱空氣烘烤步驟後，更可以選擇性地包括 進行照射一紫外光以固化第一圖案化防鋅層122a與第二 圖案化防銲層122b。 ^ 值得一提的是，在本實施例中，第一圖案化防銲層 122a暴露出的部份第一線路層11〇a為銲罩定義型（s〇ider 1^1^6£!1^’8]^)的接合墊112&(圖2(：中繪示三個）， 用以配置至少一銲球或其他導電結構（未繪示），而線路 基板100可透過此銲球與外界作電性連接，而第二圖案化 防知層122b暴露出的第二線路層為非銲罩定義塑 (Non-Solder Mask Defined，NSMD)的接合墊 U2b (圖 2C中繪示三個），用以接合至少一晶片（未繪示），其中 瘳銲罩定義型接合墊與非銲罩定義型接合墊是依據防銲層是 否覆蓋接合墊的差異而有所區分。 接著’對第一圖案化防銲層122a進行一第一粗化處 理’以增加第一圖案化防銲層122a與後續所形成之一第一 導電層130a (請參考圖2D)之間的結合力。在本實施例 中’第一粗化處理包括物理性的粗化處理或化學性的粗化 處理，其中化學性的粗化處理例如是以—化學藥劑對第一 圖案化防銲層122a的表面做粗化’而物理性的粗化處理包 12 201026188 ν〇υ / wj/v/〇06006 29048twf.doc/n 括以研磨材研磨第一圖案化防銲層122a的表面或對第一 圖案化防銲層122a的表面進行電漿轟擊或喷砂處理。 請參考圖2D，接著，形成第一導電層130a於第一圖 案化防銲層122a上，且第一導電層130a覆蓋被暴露出的 第一線路層110a(即所謂的銲罩定義型的接合墊i12a)。 在本實施例中，形成第一導電層130a於第一圖案化防銲層 122a上的方法包括物理氣相沉積（physical vapor deposition， ❿ PVD )、化學氣相沉積（chemical vapor deposition, CVD )、 化學液相沉積（chemical liquid phase deposition，CLPD )、 電鍍法（plating)或無電電鍍法（electr〇lesspiating)，其 中物理氣相沉積例如是真空蒸鑛（vacuum evaporation )或 濺鍍（sputtering)。第一導電層130a的材質可選自於錫、 銅、鉻、鈀、鎳、鋅及其合金。 請參考圖2E ’接著，形成一第一光阻層i4〇a於第一 導電層130a上。在本實施例中，於第一導電層13〇a上形 成第一光阻層140a之後，接著對第一光阻層i40a進行光 ® 固化處理。光固化處理是於第一光阻層140a上照射一紫外 光’藉此將第一光阻層140a固體化。由於第一光阻層14如 經由光固化處理之後，其抗蝕刻性以及抗化學性相對增 加’且第一光阻層140a溶解於電鍍液中的溶解速度會因此 而變慢’故能有效避免第一光阻層14〇a溶解於電鍍液中， 因而減輕第一光阻層140a污染電鍍液的程度。值得一提的 是，在本實施例中，照射紫外光於第一光阻層14〇a之後， 更包括進行一熱空氣烘烤步驟，以提高第一光阻層14〇a 13 201026188 VOV / W-»/ ν^06006 29048twf.doc/n 固化的程度。 請參考圖2F ’接著’將上述步驟的線路基板100放置 ^電鑛液中’並以第-導電層請a為電鑛膜，電鍵形成一 第-金屬層150a於第二圖案化防鮮層i22b所暴露出的第 二線路層11Gb (即所謂的非銲罩定義型的接合墊咖） 值得注意的是’第—導電層13Qa是藉由第一線路層 UOa及線路基板刚_線路（未♦示）與第二線路層· ’與習知技術中一線路層施的同一表面形 電層30a的作法完全不同，請參考圖m。在本實 :1屬層150a的材質包括錫、錫合金、金或鎳 , '層150a用以防止第二線路層110b (即所 的接合塾112b)因環境影響而氧化，造 上霜ΐί—ϊ的是在本實施例中，由於第一導電層130a 鍍ΐ 因此當以第一導電層130a為電 」電料成第-金屬層15Ga於第二線路層110b時， 換古ί阻i勵能避免電錄金屬於第一導電層130a上。 、° ，第一光阻層140a可為一阻錢層。 電居=考圖2G ’接著，移除第—光阻層⑽a及第-導 二以暴露出部份第―、線路層110a(即所謂的銲罩 接合墊陶與第—圖案化防J === =程層⑽及第―導電層⑽的方純括去酿 接著’對第二圖案化防銲層mb進行一第二粗化處 201026188 V v806〇〇6 29048twfdoc/n 理’以增加第二圖案化防_層122b與後續所形成之一第二 導電層1働（請參考圖2H)之間的結合力。在本實施例 中，第二粗化處理實質上與第—粗化處理姻，其包括物 理性的粗化處理或化學性的粗化處理，其中化學性的粗化 處理例如是以-化學藥劑對第二圖案化防銲層咖的表 面做粗化，而物理性的粗化處理包括以研磨材研磨第二圖 案化防銲層122b的表面或對第二圖案化防鏵層咖的表 ❹ 面進行電漿轟聲或喷砂處理。 請參考® 2H’接著，形成第二導電層請㈣第二圖 案化防銲層122b上’且第二導電層隱覆蓋被暴露出的 下表面io〇b並包覆第二線路層UOb及第一金屬層15〇&。 在本實施例中’形成第二導電層13〇b於第二圖案化防銲層 122b上的方法包括物理氣相沉積、化學氣相沉積、化學^ 相沉積、電It法或無電電鑛法，纟中物理氣相沉積例如是 真空洛鍍或濺鑛。第二導電層丨娜的材質可選自於锡、 銅、鉻、纪、錄、鋅及其合金。 ft 請參考圖21’接著，形成一第二光阻層14〇b於第二 導電層130b上。在本實施例中，於第二導電層13〇b上形 成第二光阻層140b之後，接著對第二光阻層14%進行光 固化處理。光固化處理是於第二光阻層14〇b上照射一紫外 光，藉此將第二光阻層140b固體化。由於第二光阻層14此 經由光固化處理之後，其抗蝕刻性以及抗化學性相對掸 加，且第二光阻層140b溶解於電鍍液中的溶解速度會因^ 而變丨艾，故能有效避免第二光阻層14〇b溶解於電鑛液中， 15 201026188 f \J\JU! \J i$06006 29048twf.doc/n 因而減輕第二光阻層140b污染電鍍液的程度。值得一提的 是’在本實施例中，照射紫外光於第二光阻層14〇b之後， 更包括進行一熱空氣烘烤步驟，以提高第二光阻層14〇b 固化的程度。 請參考圖2J，接著，將上述步驟的線路基板1〇〇放置 =電鍍液中，並以第二導電層13〇b為電鍍膜，電鍍形成一 第一金屬層150b於第一圖案化防銲層122a所暴露出的第 一，路層110a (即所謂的銲罩定義型的接合墊U2a)上。 值传注意的是，第二導電層13〇b是藉由第二線路層u〇b 及線路基板100内的線路（未繪示）與第一線路層論 電性連接，與習知技術中在第二線路層2〇b的同一表面形 成第二導電層3Gb的作法完全不同。在本實施例卜第二 ，屬層150b的材質包括錫、錫合金、金或錄金，而第二金 層^5〇b肖以防止第一線路層u〇a (即所謂的即所謂的 β罩疋義型的接合塾112a)目環境影響而氧化 性品質下降。 $ ❹ ，得一提的是，在本實施例中，由於第二導電層13〇 j蓋第二光阻層丨働’目此#以第二導電層腿為臂 J膜丄電鍍形成第二金屬層15Gb於第—線路層11〇a時， t先阻層14%能避免電鑛金屬於第二導電層腿上。 、。之，第二光阻層14〇b可是為一阻鍵層。 電^t考圖汉，之後，移除第二光阻層祕及第二導 及i -H’以暴露出部份下表面祕、第-金屬層1灿 弟一圖案化防銲層122b，其令移除第二光阻層灘及 201026188 υου / υδ06006 29048twf.doc/n 程。至此’已完成 第二導電層13〇b的方法包括去膜蝕刻製 線路基板的表面電鍍製程。201026188 υ»υ/αυ^/υ806006 29048twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a plating method for a circuit substrate, and more particularly to a method for plating a metal layer The electroplating process on the bonding pads of the circuit substrate. [Prior Art] In general, a circuit substrate is mainly formed by alternately stacking a patterned circui Uayer and a plurality of dielectric layers. Wherein, the bonding pads of the outermost wiring layer are usually protected by a Ni/Au layer or other anti-oxidation layer to prevent the bonding pads from being oxidized due to environmental influences, resulting in a decrease in the electrical quality of the bonding pads. Φ Figures 1A to 1L are schematic flow diagrams of a conventional circuit substrate electrominening method. Referring first to FIG. 1A, first, a circuit substrate 1 is provided. The circuit substrate 10 has a first wiring layer and a lower surface ib formed on the upper surface 10a to form a second wiring layer 20b. Referring to FIG. 4, a first conductive layer (as a circuit for electroplating) is formed on the upper surface 10a and the first wiring layer 2A, and is formed on the lower surface (10) and the second wiring layer. Conductive layer diligent (as a circuit of the electric circuit) test = two, 'forming the first photoresist layer 4〇a on the first conductive layer' and the first electric layer. See Figure 1D, then, right The first photoresist layer is exposed and developed to form a first patterned photoresist layer 其, the J ί photoresist layer - exposing a portion of the first conductive layer 30a and the first V layer. Referring to FIG. 1E, first, the first conductive layer 3A and the second conductive layer not covered by the first photoresist layer 42a are replaced by the first pattern 201026188, υ^, υ8〇6〇〇6 29048 twf.doc/n. Surveying to expose part of the upper surface 1a, part of the lower surface, part of the road layer 20a and the second circuit layer 2〇b. Please refer to FIG. 1F, and then remove the first-patterned photoresist The layer 42a is configured to expose the first conductive layer 3a and the second conductive layer 3A under the first patterned photoresist layer 42a. Referring to FIG. 1G, next to the first circuit layer and the second line A second photoresist layer 4〇b is formed on the layer 20b, the first conductive layer 3〇a and the second conductive layer %. Referring to FIG. 1H, the second photoresist layer 40b is exposed, developed and photocured. a second patterned photoresist layer 42b is formed, wherein the second patterned photoresist layer 42b covers the patterned first conductive layer 30a to pattern the first conductive layer 3Gb, and only the first circuit layer is exposed. With the surface of the $-circuit layer 20b (ie, the surface of the bonding pad), please refer to Figure II. Next, the above-mentioned step-circuit substrate is placed in the electro-mineral solution (not shown), and via the patterned a conductive layer and a pattern of the second conductive layer are supplied with power to form a -th metal layer 50a, respectively, and a second metal layer is applied to the surface of the second circuit layer and the surface of the bonding pad Above] to prevent oxidation of the line. Referring to FIG. U, next, the second patterned photoresist layer 42b, the first conductive layer 3A, and the f "if electrical layer 3Gt> are removed. Please refer to FIG. 1K and FIG. 1L at the same time, and then 'micro-residual 4 damage, circuit layer 20a' and respectively form a first patterned anti-friction layer 〇a /, the first patterned solder resist layer 60b on the circuit substrate 1 〇 1% of the upper surface and the lower surface, wherein the first patterned solder resist layer 60a covers the first gold layer 60a and the first circuit layer 2〇a, and a portion of the first metal layer is exposed. The first circuit layer 20a is plated with the first conductive layer 30a on a surface of 201026188 u6u/uu3/u806006 29048 twf.doc/n as a plating film to plate the first metal layer 50a' but to cover the patterned first conductive layer. Layer 3〇a (shown in FIG. 1H), the first patterned photoresist layer 42a must be removed first, then the second patterned photoresist layer 42b is formed, and then the first metal layer 5〇a is completed, and then the first layer is removed. A patterned photoresist layer 42b is thus added to the second photoresist layer 4b forming and removing step (see FIGS. 1H and 1J). Similarly, the second metal layer 5〇b is plated on the second circuit layer 2〇b, and the second 10 photoresist layer 4〇b is formed and removed in the same manner as the above process (see FIGS. 1H and 1; ). Due to the long time of photoresist coating, baking and curing, and the increase in the number of masks and the degree of alignment of the photoresist exposure development, the timing and cost of the electric clock are wasted. In addition, if the photoresist is dissolved in the plating solution during the electroplating process, the plating solution will be contaminated, thereby shortening the service life of the plating solution. SUMMARY OF THE INVENTION The present invention provides a surface electrominening process for a circuit substrate. ❹ The present invention provides a surface plating process for a circuit substrate. First, a circuit substrate is provided in which a circuit substrate has been formed on the upper surface - a first wiring layer and a second wiring layer formed on the lower surface. Then, a first-patterned anti-layer and a second patterned solder resist layer are respectively formed on the upper surface and the lower surface of the circuit substrate, wherein the first patterned solder resist layer exposes a portion of the first circuit layer 'second The patterned lining exposes (four) portions of the lower surface and the second wiring layer. A first conductive layer is formed on the first patterned solder resist layer, and the first electrical layer covers the exposed (four)-circuit layer m photoresist layer on the first conductive layer. The first conductive layer is used as a plating film to form a first metal layer 201026188 υου/υυ^/υ306006 29048twf.doc/n on the first circuit layer. The first photoresist layer and the first conductive layer are removed to expose a portion of the first-line layer and the first-patterned anti-fresh layer. A second conductive layer is formed on the second patterned solder resist layer and the first metal layer, and the second conductive layer covers the exposed lower surface and covers the first metal layer. A second photoresist layer is formed on the second conductive layer. The second conductive layer is used as a bonding film to form a second metal on the exposed first wiring layer. Thereafter, the second photoresist layer and the second conductive layer ' are removed to expose a portion of the lower surface, the first metal layer, and the second patterned solder resist layer. In the embodiment of the present invention, the step of forming the first patterned solder resist layer and the second patterned anti-friction layer on the upper surface and the lower surface of the circuit substrate respectively to form a first solder resist layer respectively And a second anti-fresh layer on the circuit substrate, wherein the first solder resist layer covers the upper surface and the first circuit layer, and the second solder resist layer covers the lower surface and the second circuit layer. Next, the first layer and the first solder resist layer are exposed and developed to form a -first patterned solder resist layer and a second patterned solder resist layer. In an embodiment of the invention, after the forming the first patterned sounding layer and the second patterned solder resist layer, the method further comprises performing the irradiation-ultraviolet light on the first patterned p-square layer and the second patterned solder resist layer. On the layer, the cured solder mask and the second patterned solder mask are cured. In an embodiment of the invention, after the forming the first patterned layer and the second patterned solder resist layer, the method further comprises: performing a hot air baking step to cure the patterned solder mask layer and the second pattern. Welding layer. In the embodiment of the present invention, before forming the first conductive layer on the patterned transfer layer, the method further includes: forming a first-patterned solder resist layer into the second layer; 201026188 U5u/uud/u806006 29048twf.doc/n A roughening process. In an embodiment of the invention, the first roughening treatment described above includes a physical roughening treatment or a chemical roughening treatment. In one embodiment of the invention, the method of forming the first conductive layer on the first patterned solder resist layer comprises physical vapor deposition, chemical vapor deposition or chemical liquid deposition. In an embodiment of the invention, after the forming the first photoresist layer on the first conductive layer, the method further comprises irradiating an ultraviolet light on the first photoresist layer to cure the first photoresist layer. In an embodiment of the invention, after the irradiating the ultraviolet light to the first photoresist layer, the method further comprises performing a hot air baking step to cure the first photoresist layer. In an embodiment of the invention, the method for removing the first photoresist layer and the first conductive layer includes a film removing process. In one embodiment of the invention, the method of forming the second conductive layer on the second patterned solder resist layer and the first metal layer comprises physical vapor deposition, chemical vapor deposition or chemical liquid deposition. In an embodiment of the invention, the forming the second conductive layer further comprises a second roughening process on the second pattern before the forming the second conductive layer. Ye Zengyan 仃 In the present invention, the second coarsening treatment is carried out by roughening treatment or chemical roughening treatment. =Invented-the real-cut towel, after forming the second photoresist layer-on the conductive layer, it further includes illumination-ultraviolet light on the second photoresist layer, 9 201026188 υ〇υ/υυ^, υί〇6〇〇 6 29048 twf.doc/n to cure the second photoresist layer. In an embodiment of the invention, after the irradiating the photoresist layer, the step of performing a hot air baking step on the second photoresist layer is further included. In order to cure the second, in one embodiment of the invention, the method of removing the second conductive layer includes a stripping etching process. In the embodiment of the present invention, the first one is tin, tin alloy, and gold-gold. Material of the material layer In one embodiment of the invention, the above includes tin, tin alloy, gold or nickel gold. Material Package of Metal Layer In one embodiment of the present invention, the first portion of the first-line layer exposed by the first pattern is a solder mask (four) type pad.曰 先 先 先 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ And the step of the photoresist mask m. Therefore, in addition to reducing the required light and light, the present invention can reduce the amount of dissolution of the photoresist layer in the electroplating process, and has the effect of lying down, and is well known in the art. The difficulty that the technicians are not easy to associate with is overcome. The above and other objects, features and glazings of the present invention will become more apparent from the detailed description of the appended claims. v>806006 29048twf.doc/n 201026188 [Embodiment] FIG. 2A to FIG. 2B are schematic diagrams showing the flow of a surface plating process of a circuit substrate according to an embodiment of the present invention. Referring to FIG. 2A, regarding the surface plating process of the circuit substrate of the embodiment, first, a circuit substrate 100 is provided. The circuit substrate 100 has formed a first circuit layer 110a on an upper surface 10a. The surface 10b forms a second circuit layer 11%. In the present embodiment, the material of the first wiring layer 11a and the second wiring layer is, for example, copper. Referring to FIG. 2B, a first solder resist layer 12, such as a second solder resist layer 120b, is formed on the circuit substrate 1b, wherein the first solder resist layer 120a covers the upper surface of the circuit substrate 1〇〇. 〇〇a and the first wiring layer 110a, the second solder resist layer 120b covers the lower surface of the circuit substrate 1〇〇1〇 and the second wiring layer 110b. Referring to FIG. 2C, the first solder resist layer 12A and the second solder resist layer 120b are exposed and developed to form a first patterned solder resist layer 122a and a second patterned solder resist layer i22b, respectively. The upper surface 100a and the lower surface 10b of the circuit substrate 1b, wherein the first patterned solder resist 122a exposes a portion of the first wiring layer 110a, and the second patterned solder resist 122b exposes a portion The surface 100b and the second wiring layer i1〇b. In this embodiment, after the first patterned solder resist layer 122a and the second patterned solder resist layer 122b are completed, the method further includes irradiating an ultraviolet light on the first patterned solder resist layer 122a and the second patterning prevention. The solder layer 12 is patterned to cure the first patterned solder resist layer 122a and the second patterned solder resist layer 122b. In addition, in other implementations, after the irradiation of the light is completed, it is more preferable to perform a hot air baking step to cure the first patterned solder resist layer after 201026188 vw/\jyj/vi06006 29048twf.doc/n. 122a and the second patterned solder resist layer 122b. In addition, in other unillustrated embodiments, after the first patterned solder resist layer 122 & and the second patterned solder resist layer 122 b, the method further includes performing a hot air baking step to cure the first The solder resist layer 122a and the second patterned solder resist layer 122b are patterned. Of course, after the hot air baking step is performed, the ultraviolet light may be selectively irradiated to cure the first patterned zinc-proof layer 122a and the second patterned solder resist layer 122b. It is worth mentioning that, in this embodiment, a portion of the first circuit layer 11〇a exposed by the first patterned solder resist layer 122a is of a solder mask definition type (s〇ider 1^1^6£!1) ^'8]^) bonding pads 112& (Fig. 2 (three are shown)) for arranging at least one solder ball or other conductive structure (not shown) through which the circuit substrate 100 can pass The external circuit is electrically connected, and the second circuit layer exposed by the second patterned anti-knowledge layer 122b is a non-solder mask defined (NSMD) bonding pad U2b (three are shown in FIG. 2C). For bonding at least one wafer (not shown), wherein the solder mask definition type bonding pad and the non-solder mask defining type bonding pad are distinguished according to whether the solder resist layer covers the difference of the bonding pad. The patterned solder resist layer 122a performs a first roughening process to increase the bonding force between the first patterned solder resist layer 122a and one of the subsequently formed first conductive layers 130a (please refer to FIG. 2D). In the example, the first roughening treatment includes a physical roughening treatment or a chemical roughening treatment, wherein the chemical roughening treatment example The material is roughened by the chemical agent to roughen the surface of the first patterned solder resist layer 122a. The physical roughening treatment package 12 201026188 ν〇υ / wj/v/〇06006 29048twf.doc/n The surface of the first patterned solder resist layer 122a or the surface of the first patterned solder resist layer 122a is subjected to plasma bombardment or sand blasting. Referring to FIG. 2D, then, the first conductive layer 130a is formed on the first patterned layer. On the solder layer 122a, the first conductive layer 130a covers the exposed first wiring layer 110a (so-called solder mask defining type bonding pad i12a). In this embodiment, the first conductive layer 130a is formed first. The method of patterning the solder resist layer 122a includes physical vapor deposition (❿PVD), chemical vapor deposition (CVD), chemical liquid phase deposition (CLPD), electroplating (plating) or electroless plating (electr〇lesspiating), wherein physical vapor deposition is, for example, vacuum evaporation or sputtering. The material of the first conductive layer 130a may be selected from tin, copper, chromium. , Palladium, nickel, zinc and alloys thereof. Referring to FIG. 2E 'then, a first photoresist layer i4a is formed on the first conductive layer 130a. In this embodiment, the first conductive layer 13a is formed. After the first photoresist layer 140a, the first photoresist layer i40a is then photo-cured. The photocuring treatment irradiates an ultraviolet light on the first photoresist layer 140a, thereby solidifying the first photoresist layer 140a. Since the first photoresist layer 14 is relatively etch-resistant and chemically resistant after being cured by photocuring, and the dissolution rate of the first photoresist layer 140a dissolved in the plating solution is slowed down, it can be effectively avoided. The first photoresist layer 14A is dissolved in the plating solution, thereby alleviating the extent to which the first photoresist layer 140a contaminates the plating solution. It is worth mentioning that, in this embodiment, after irradiating the ultraviolet light to the first photoresist layer 14A, the method further comprises performing a hot air baking step to improve the first photoresist layer 14〇a 13 201026188 VOV / W-»/ ν^06006 29048twf.doc/n Degree of curing. Referring to FIG. 2F 'then', the circuit substrate 100 of the above step is placed in the electro-mineral solution', and the first conductive layer is used as the electric ore film, and the first metal layer 150a is formed by the electric key to form the second-patterned anti-fresh layer. The second circuit layer 11Gb exposed by i22b (so-called non-weld mask type bonding pad) is notable that the 'first conductive layer 13Qa is formed by the first wiring layer UOa and the circuit substrate just_ ♦ shows) and the second circuit layer · 'The same surface electrical layer 30a applied to a circuit layer in the prior art is completely different, please refer to the figure m. In the present embodiment, the material of the 1st layer 150a includes tin, tin alloy, gold or nickel, and the layer 150a is used to prevent the second circuit layer 110b (ie, the joint 塾 112b) from being oxidized due to environmental influences, and the frost is applied. In the present embodiment, since the first conductive layer 130a is plated, when the first conductive layer 130a is electrically charged into the first metal layer 15Ga on the second circuit layer 110b, The galvanic metal can be avoided on the first conductive layer 130a. The first photoresist layer 140a may be a hindrance layer. Electric residence = test 2G 'Next, remove the first photoresist layer (10) a and the first - lead two to expose part of the -, circuit layer 110a (the so-called solder mask bond pad ceramic and the first - patterned anti-J = == = the layer of the layer (10) and the first layer of the conductive layer (10) is purely brewed and then 'a second roughening of the second patterned solder mask mb 201026188 V v806〇〇6 29048twfdoc/n 'to increase the number The bonding force between the second patterned anti-layer 122b and one of the second conductive layers 1働 (refer to FIG. 2H) formed later. In this embodiment, the second roughening process is substantially the same as the first-roughening process. Including a physical roughening treatment or a chemical roughening treatment, wherein the chemical roughening treatment is, for example, roughening the surface of the second patterned solder mask layer with a chemical agent, and physical The roughening treatment includes grinding the surface of the second patterned solder resist layer 122b with an abrasive material or performing plasma bombing or sand blasting on the surface of the second patterned anti-corrosion layer. Please refer to ® 2H' to form The second conductive layer is provided on the (four) second patterned solder resist layer 122b and the second conductive layer is covered by the exposed surface. Io〇b and covering the second circuit layer UOb and the first metal layer 15〇& In the embodiment, the method of forming the second conductive layer 13〇b on the second patterned solder resist layer 122b includes physical gas Phase deposition, chemical vapor deposition, chemical phase deposition, electric It or electroless ore method, physical vapor deposition in the crucible is, for example, vacuum plating or sputtering. The second conductive layer can be selected from tin. Copper, chrome, chrome, cadmium, zinc, and alloys thereof. ft. Referring to FIG. 21', a second photoresist layer 14b is formed on the second conductive layer 130b. In this embodiment, the second conductive layer is formed. After the second photoresist layer 140b is formed on the layer 13〇b, the second photoresist layer 14% is then photocured. The photocuring treatment is to irradiate an ultraviolet light on the second photoresist layer 14〇b, thereby The second photoresist layer 140b is solidified. Since the second photoresist layer 14 is subjected to photocuring treatment, its etching resistance and chemical resistance are relatively increased, and the dissolution rate of the second photoresist layer 140b dissolved in the plating solution is increased. It will be changed to AI by ^, so it can effectively prevent the second photoresist layer 14〇b from being dissolved in the electric ore solution, 15 201026188 f \J\JU! \J i$06006 29048twf.doc/n thus alleviating the extent to which the second photoresist layer 140b contaminates the plating solution. It is worth mentioning that in the present embodiment, ultraviolet light is irradiated onto the second photoresist layer. After 14 〇b, a hot air baking step is further included to increase the degree of curing of the second photoresist layer 14 〇 b. Referring to FIG. 2J, the circuit substrate 1 of the above step is placed in the plating solution. And using the second conductive layer 13〇b as a plating film, electroplating to form a first metal layer 150b exposed to the first patterned solder resist layer 122a, the first layer 110a (so-called solder mask defined type Bonding pad U2a). It is noted that the second conductive layer 13b is electrically connected to the first circuit layer by a second circuit layer u〇b and a line (not shown) in the circuit substrate 100, and is known in the prior art. The formation of the second conductive layer 3Gb on the same surface of the second wiring layer 2〇b is completely different. In the second embodiment, the material of the genus layer 150b includes tin, tin alloy, gold or gold, and the second gold layer is used to prevent the first circuit layer u〇a (so-called so-called The β 疋 型 type of joint 塾 112 a) has an environmental influence and the oxidative quality is lowered. $ ❹ , it is noted that, in this embodiment, since the second conductive layer 13 〇 j covers the second photoresist layer 目 目 此 # 以 以 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二When the metal layer 15Gb is on the first circuit layer 11a, the first resist layer 14% can prevent the electric ore metal from being on the second conductive layer leg. ,. The second photoresist layer 14B may be a resistive layer. After the second photo-resist layer and the second guide and i-H' are removed to expose a portion of the lower surface secret, the first-metal layer 1 can be a patterned solder mask 122b, It removes the second photoresist layer and 201026188 υου / υδ06006 29048twf.doc/n. Heretofore, the method of completing the second conductive layer 13b includes a surface plating process for removing the wiring substrate.
朴在後續的製程中，舉例而言，本實施例之線路基板· ”線接合（wlre BGnding，WB)或覆晶接合 啊B〇nding，FC)的方式顧於晶片與封裝載板(package Γ16：)之間。詳細而言，首先，經由多條鮮線（wire)(未 4不）將晶片（未緣示）電性連接至線路基板應的非焊 罩定義型的接合墊U2b上。接著，將多_舰線路基板 100之銲罩定義型的接合墊⑽上的鮮球電性及結構性地 連接至-封裝載板（例如是―印刷電路板 使分別位於線路基板_及封裝驗之_兩介面、、兩元 =兩端點均可經由上述之銲球來達成訊號傳遞的目的。 簡言之’當線路基板100欲與其他元件（例如封裝載板、 晶片等）構成電性連接時，即可直接透過線路基板漏的 鮮罩定義㈣接合塾112a以及非銲罩定義型的接合墊 H2b與其他元件進行電性連接，如此一 |，可增加線路基 板100使用上的便利性。 此外，在本實施例中，肆然本發明的線路基板的表面 電鍍製程是應用於上表面100a與下表面100b分別具有第 一線路層110a與第二線路層11〇b的線路基板1〇〇/，、且第 一線路層ll〇a具有多個銲罩定義型的接合墊U2a，第二 線路層ii〇b具有多個非鮮罩定義型的接合墊mb，但^ 於其他實施射，亦可以僅應用於單®具有線路層的線路 基板’且亦可僅具有單健合墊，此，本發_線路基 17 201026188 / w-// V 306006 29048twf.doc/nIn the subsequent process, for example, the circuit substrate of the present embodiment, "wire bonding (WB) or flip chip bonding, FC) is considered to be a wafer and a package carrier (package Γ16). In detail, first, the wafer (not shown) is electrically connected to the non-solder mask-type bonding pad U2b of the circuit substrate via a plurality of fresh wires (not shown). Next, the fresh ball on the bonding pad (10) of the multi-ship circuit substrate 100 is electrically and structurally connected to the package carrier (for example, the "printed circuit board is placed on the circuit substrate _ and the package inspection". The two interfaces, the two elements = the two end points can achieve the purpose of signal transmission through the solder balls described above. Briefly, 'when the circuit substrate 100 is intended to be electrically connected with other components (such as package carrier, wafer, etc.) When connecting, the connection cover a 112a and the non-weld cover-defined bonding pad H2b which are directly through the line substrate are electrically connected to other components, so that the convenience of the circuit substrate 100 can be increased. In addition, in this embodiment, The surface plating process of the circuit substrate of the present invention is applied to the circuit substrate 1// having the first wiring layer 110a and the second wiring layer 11〇b on the upper surface 100a and the lower surface 100b, respectively, and the first wiring layer 11〇 a has a plurality of solder mask defining type bonding pads U2a, and the second circuit layer ii〇b has a plurality of bonding pads mb defined by the non-fringe cover type, but can be applied to only a single layer having a circuit layer. The circuit substrate 'and may also have only a single mating pad, here, the present invention_ line base 17 201026188 / w-// V 306006 29048twf.doc/n
板的表面電鍍製程所使用之線路基板1〇〇，僅為舉例 明，但並不以此為限。 D 综上所述，由於本發明的線路基板的表面電鍍製程是 先於線路層上形成圖案化防銲層後，再於圖案化防銲層2 形成導電層，且本發明之線路基板的表面電 ^The circuit substrate used in the surface plating process of the board is exemplified, but not limited thereto. In summary, since the surface plating process of the circuit substrate of the present invention is to form a patterned solder resist layer on the circuit layer, a conductive layer is formed on the patterned solder resist layer 2, and the surface of the circuit substrate of the present invention is formed. Electric ^
次去絲料轉，《域細層騎光;^理^ 驟，因此本發明除了可減少所需之光罩的數量，尚 卜 光阻層在電it過財溶解量，其具有超__成效，且 為本領域巾熟知該技術者所不㈣想雜度克服。此外， 本發明分騎第-圖案化防銲層與第二_化防銲層 粗化處理，可增加第化防銲層與 :合力，以及第二圖案化防銲層與第二導電層 f發明已以實施·露如上，然其並非用以限定 2月’任何關技術職巾具有通常知識者，在 二範圍内’當可作些許之更動與潤飾，故本 所界定者為準 X月之保濩靶圍當視後附之申請專利範圍 意圖 圖式簡單說明】 圖认至圖[是習知一種線路基板電鑛方法的流程 不 表f—猶路基板的 18 201026188„doc/n 【主要元件符號說明】 10、100 :線路基板 10a、100a :上表面 10b、100b :下表面 20a、110a :第一線路層 20b、110b :第二線路層 30a、130a :第一導電層 30b、130b ··第二導電層 ❿ 40a、140a :第一光阻層 40b、140b :第二光阻層 42a :第一圖案化光阻層 42b:第二圖案化光阻層 50a、150a :第一金屬層 50b、150b :第二金屬層 60a、122a :第一圖案化防銲層 60b、122b :第二圖案化防銲層 φ 112a :銲罩定義型的接合墊 112b :非銲罩定義型的接合墊 120a :第·一防焊層 120b :第二防銲層 19The second wire is transferred, "the fine layer rides the light; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ And those who are familiar with the technology in the field do not (4) want to overcome the complexity. In addition, in the present invention, the sub-patterned solder mask layer and the second solder mask layer are roughened, and the second solder resist layer and the resultant force are added, and the second patterned solder resist layer and the second conductive layer f are added. The invention has been implemented and disclosed above. However, it is not intended to limit February's knowledge of any technical skills. In the second range, when there are some changes and refinements, the definition of this is X. The target area of the patent application scope is intended to be a simple description of the patent application scope. The figure is recognized as a flow chart of a circuit substrate electro-minening method is not shown in the table f-Jussia substrate 18 201026188 „doc/n Main component symbol description] 10, 100: circuit substrate 10a, 100a: upper surface 10b, 100b: lower surface 20a, 110a: first wiring layer 20b, 110b: second wiring layer 30a, 130a: first conductive layer 30b, 130b · Second conductive layer ❿ 40a, 140a: first photoresist layer 40b, 140b: second photoresist layer 42a: first patterned photoresist layer 42b: second patterned photoresist layer 50a, 150a: first metal Layers 50b, 150b: second metal layers 60a, 122a: first patterned solder mask layers 60b, 122b: second Patterned solder resist layer φ 112a: joined type solder mask defined pad 112b: engagement-type non-solder-mask defined pad 120a: · a first solder mask layer 120b: second solder resist layer 19