TWI625996B

TWI625996B - Process for manufacturing wiring substrate

Info

Publication number: TWI625996B
Application number: TW103117893A
Authority: TW
Inventors: 豊田裕二; 後閑寬彥; 川合宣行; 中川邦弘
Original assignee: 三菱製紙股份有限公司
Priority date: 2013-05-22
Filing date: 2014-05-22
Publication date: 2018-06-01
Also published as: CN107969076A; JP6416323B2; CN107979919B; JP6224520B2; CN105210460B; CN107969077B; JP6514807B2; KR20160013007A; CN107969076B; WO2014188945A1; CN105210460A; CN107979919A; JP2015216332A; TW201509256A; CN107969077A; KR102076479B1; JP2018139318A; JP2017183744A

Abstract

本發明之配線基板的製造方法，其特徵為含有：於電路基板之兩表面，形成厚度不同之防焊層的製程(A)；對厚度薄於第二面之防焊層的第一面之防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；以薄膜化處理液實施使非曝光部之第一面之防焊層成為連結墊之厚度以下為止之薄膜化的製程(B)；對第一面之防焊層，實施於製程(B)被薄膜化之區域部分之曝光的製程(C3)；以及以顯影液除去第二面之非曝光部之防焊層的製程(D)。 The method for manufacturing a wiring substrate of the present invention is characterized by comprising: a process (A) of forming a solder resist layer having different thicknesses on both surfaces of a circuit substrate; The solder mask is applied to the post-processing process (B) and the process (C1) of exposing the portion other than the thinned area; the second surface solder mask is applied to the post-processing process (D) outside the developed region Partial exposure process (C2); thin filming treatment liquid (B) to make the solder mask layer on the first surface of the non-exposed part to the thickness of the bonding pad or less (B); solder mask to the first surface Layer, a process (C3) for exposing the portion of the thin filmed area in the process (B); and a process (D) for removing a solder resist layer on a non-exposed portion of the second surface with a developing solution.

Description

配線基板的製造方法 Manufacturing method of wiring board

本發明係關於配線基板的製造方法，尤其是，與具有用以連結半導體晶片及其他印刷線路板等電子構件之複數連結墊之配線基板的製造方法相關。 The present invention relates to a method for manufacturing a wiring board, and in particular, to a method for manufacturing a wiring board having a plurality of connection pads for connecting electronic components such as semiconductor wafers and other printed wiring boards.

各種電氣機器內部之配線基板，於其中一側表面或兩表面，有具備絕緣層、及形成於絕緣層表面之導體配線的電路基板。此外，於配線基板的電路基板表面，為了使焊劑不會附著於無需焊接之導體配線，而在未焊接之部分全面形成防焊層。該防焊層，發揮防止導體配線之氧化、電氣絕緣及阻隔外部環境之機能。 Wiring boards inside various electrical appliances include a circuit board having an insulating layer and conductor wiring formed on the surface of the insulating layer on one or both surfaces. In addition, on the surface of the circuit board of the wiring substrate, in order to prevent the flux from adhering to the conductor wiring that does not need to be soldered, a solder resist layer is formed on the unsoldered portion. This solder resist has the functions of preventing oxidation of conductor wiring, electrical insulation, and blocking the external environment.

此外，於配線基板上配載半導體晶片等電子構件時，於配線基板的表面，形成有用以連結半導體晶片、及其他印刷線路板等電子構件之多數連結墊。連結墊，係以使電路基板表面之導體配線的整體或一部分從防焊層露出之方式來製作。近年來，該連結墊持續朝高密度化發展，所配置之連結墊的彼此間距愈來愈狹窄，例如，也有50μm以下之窄間距。 In addition, when electronic components such as a semiconductor wafer are placed on a wiring substrate, a plurality of connection pads are formed on the surface of the wiring substrate to connect the semiconductor wafer and other electronic components such as a printed wiring board. The connection pad is produced so that the whole or a part of the conductor wiring on the surface of the circuit board is exposed from the solder resist. In recent years, the connection pads have continued to develop in high density, and the distances between the connection pads arranged have become narrower and narrower. For example, There is also a narrow pitch below 50 μm.

於高密度配置之連結墊配載電子構件的方法，有利用覆晶連結的方法。覆晶連結，係指使配設於配線基板上之電子構件連結用連結墊的一部分對應於電子構件之電極端子的配置並露出，並使該電子構件連結用連結墊之露出部與電子構件之電極端子相對，再介由焊劑凸塊進行電氣連結。 A method of placing electronic components on a connection pad arranged at a high density includes a method of using flip-chip connection. The flip-chip connection refers to exposing a part of the connection pads for connecting electronic components on the wiring board to the arrangement of the electrode terminals of the electronic components, and exposing the exposed portions of the connection pads for electronic components and the electrodes of the electronic components. The terminals are opposed to each other and electrically connected via a solder bump.

連結墊之構造上，有除去部分防焊層來使連結墊表面之整體或一部分露出的SMD(Solder Mask Defined)構造、及除去部分防焊層來使連結墊完全露出的NSMD(Non Solder Mask Defined)構造。 The structure of the bonding pad includes an SMD (Solder Mask Defined) structure in which a part of the solder resist is removed to expose the whole or a part of the surface of the bonding pad, and an NSMD (Non Solder Mask Defined) in which the solder resist is removed to partially expose the connection pad. )structure.

第1圖A係具有SMD構造之配線基板一例的概略剖面圖。在絕緣層8表面配設有導體配線7及導體配線之部分連結墊3的電路基板1表面，形成有防焊層2。連結墊3，其周邊附近為防焊層2所覆蓋。所以，有不易因為機械衝擊而發生連結墊3剝落及從連結墊3之延伸配線之頸部斷線的優點。相反地，因為電子構件之電極端子與對應其之連結墊3的電氣連結獲得確實固定，必須於形成在連結墊3露出面之接合部確保必要的焊劑量，因而導致連結墊3的大型化，故難以對應電子構件之小型化及高性能化所伴隨之連結墊3的高密度化要求。 FIG. 1 is a schematic cross-sectional view of an example of a wiring substrate having an SMD structure. On the surface of the insulating layer 8, a conductor wiring 7 and a part of the connection pad 3 of the conductor wiring of the circuit board 1 are arranged, and a solder resist layer 2 is formed. The connection pad 3 is covered by the solder resist layer 2 near its periphery. Therefore, there is an advantage that peeling of the connection pad 3 does not easily occur due to a mechanical impact and disconnection of the neck portion of the extended wiring from the connection pad 3. On the contrary, since the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad 3 is surely fixed, the necessary soldering amount must be ensured at the joint portion formed on the exposed surface of the connection pad 3, which leads to an increase in the size of the connection pad 3. Therefore, it is difficult to cope with the demand for high density of the connection pad 3 accompanying the miniaturization and high performance of electronic components.

第1圖B係具有NSMD構造之配線基板一例的概略剖面圖。在絕緣層8表面配設有導體配線7及導體配線之部分連結墊3的電路基板1表面，形成有防焊層 2。防焊層2之同一開口內，配置有複數連結墊3，該等連結墊3從防焊層2露出。NSMD構造時，連結墊3之周邊附近的防焊層2被完全除去，而使連結墊3的側面完全露出。所以，相較於SMD構造，即使較小的連結墊3，也可確保連結墊3與焊劑的接著強度。相反地，連結墊3的側面完全露出，可能降低連結墊3與絕緣層8之間的接著強度。此外，以窄間距配置之連結墊3時，在後製程的無電解鎳/金電鍍有時於連結墊3間會發生短路，或者，在連結墊3上配設焊劑凸塊的話，有時熔融之焊劑流至相鄰之連結墊3，而使連結墊3間發生短路。 FIG. 1B is a schematic cross-sectional view of an example of a wiring substrate having an NSMD structure. On the surface of the insulating layer 8, a conductor wiring 7 and a part of the conductor wiring connection pad 3 are arranged on the surface of the circuit board 1. A solder resist is formed. 2. In the same opening of the solder resist layer 2, a plurality of connection pads 3 are arranged, and the connection pads 3 are exposed from the solder resist layer 2. In the NSMD structure, the solder resist 2 near the periphery of the connection pad 3 is completely removed, and the side surfaces of the connection pad 3 are completely exposed. Therefore, compared with the SMD structure, even if the connection pad 3 is smaller, the bonding strength between the connection pad 3 and the solder can be ensured. On the contrary, the side of the connection pad 3 is completely exposed, which may reduce the bonding strength between the connection pad 3 and the insulating layer 8. In addition, when the connecting pads 3 are arranged at a narrow pitch, electroless nickel / gold plating in a later process may cause a short circuit between the connecting pads 3, or the solder pads may be melted when the connecting pads 3 are provided. The flux flows to the adjacent connection pads 3, and a short circuit occurs between the connection pads 3.

為了解決連結墊與絕緣層間的接著強度問題，有人提出以下之方法，藉由照射雷射光使配設於電路基板表面之防焊層的一部分形成深度0~15μm程度的開口部，來製造具有連結墊部分側面從防焊層露出之構造之印刷線路板的方法(例如，參照專利文獻1)。藉由採用以專利文獻1所記載之方法得到的印刷線路板，相較於使存在於防焊層下部之連結墊完全露出的印刷線路板，可能會提高連結墊與絕緣層間的接著強度。 In order to solve the problem of the bonding strength between the connection pad and the insulating layer, some people have proposed the following method. A part of the solder resist layer disposed on the surface of the circuit board is irradiated with laser light to form an opening having a depth of about 0 to 15 μm to produce a connection having a connection. A method of a printed wiring board having a structure in which a side surface of a pad portion is exposed from a solder resist (for example, refer to Patent Document 1). By using the printed wiring board obtained by the method described in Patent Document 1, it is possible to increase the bonding strength between the bonding pad and the insulating layer compared to a printed wiring board in which the bonding pads existing under the solder resist are completely exposed.

此外，為了解決窄間距配置之連結墊3的短路問題，有人提出製造於相鄰連結墊3間充填防焊層2之配線基板的方法(例如，參照專利文獻2)。依據專利文獻2之方法的話，可以形成如第2圖所示之於連結墊3間充填著防焊層2，且充填之防焊層2的厚度為連結墊3之厚度以下的NSMD構造。具體而言，於電路基板1上形成防焊層2，對防焊層2之厚度薄膜化至連結墊3之厚度以下為止的區域以外之部分進行曝光後，利用鹼性水溶液薄膜化處理液，實施使其成為連結墊3之厚度以下為止之非曝光部之防焊層2的薄膜化。藉此，形成具有包含連結墊3之厚度以下的部分及超過連結墊3之厚度的部分之多段構造的防焊層2，進而製造出做為連結墊3之部分導體配線露出的配線基板。 In addition, in order to solve the short circuit problem of the connection pads 3 arranged at a narrow pitch, a method has been proposed for manufacturing a wiring board in which the solder resist layer 2 is filled between adjacent connection pads 3 (for example, refer to Patent Document 2). According to the method of Patent Document 2, it is possible to form an NSMD structure in which the solder resist layer 2 is filled between the bonding pads 3 as shown in FIG. 2 and the thickness of the filled solder resist layer 2 is equal to or less than the thickness of the bonding pad 3. Specifically, it is formed on the circuit board 1 The solder resist layer 2 exposes a portion other than the area where the thickness of the solder resist layer 2 is reduced to a thickness below the thickness of the bonding pad 3, and then uses an alkaline aqueous solution to thin the processing solution to make it less than the thickness of the bonding pad 3. The thickness of the solder resist layer 2 in the non-exposed portions has been reduced. Thereby, the solder resist layer 2 having a multi-segment structure including a portion having a thickness less than the thickness of the connection pad 3 and a portion exceeding the thickness of the connection pad 3 is formed, and a wiring substrate with which part of the conductor wiring is exposed as the connection pad 3 is manufactured.

通常，配載著電子構件之配線基板時，於背面以高密度形成有多數之外部連結用連結墊。外部連結用連結墊，也可藉由使電路基板背面之部分導體配線從防焊層露出來製作。使該外部連結用連結墊之露出部與主機板等之外部電氣基板的導體配線相對，介由焊劑凸塊來進行電氣連結。 Generally, when a wiring substrate on which electronic components are placed, a large number of connection pads for external connection are formed on the back surface at a high density. The connection pad for external connection can also be produced by exposing part of the conductor wiring on the back surface of the circuit board from the solder resist. The exposed portion of the connection pad for external connection is opposed to the conductor wiring of an external electrical substrate such as a motherboard, and is electrically connected via a solder bump.

於電路基板兩面形成防焊層時，連結墊上之防焊層厚度，隨著包含連結墊在內之其周圍的導體配線密度而變化。例如，導體配線密度較小時，充填於導體配線間之間隙的防焊層量較多，呈現連結墊上之防焊層厚度較薄的傾向。另一方面，導體配線密度較大時，充填於導體配線間之間隙的防焊層量較少，呈現連結墊上之防焊層厚度較厚的傾向。 When a solder resist layer is formed on both sides of a circuit board, the thickness of the solder resist layer on the connection pad changes with the density of the conductor wiring around the connection pad. For example, when the density of the conductor wiring is small, the amount of the solder resist layer filled in the gap between the conductor wirings is large, and the thickness of the solder resist layer on the connection pad tends to be thin. On the other hand, when the density of the conductor wiring is high, the amount of the solder resist layer filled in the gap between the conductor wirings is small, and the thickness of the solder resist layer on the connection pad tends to be thick.

以覆晶連結來配載電子構件之配線基板時，有時包含背面之外部連結用連結墊在內之其周圍的導體配線密度大於包含表面之電子構件連結用連結墊在內之其周圍的導體配線密度。所以，有時背面之外部連結用連結墊上的防焊層厚度比表面之電子構件連結用連結墊上的防焊層厚度更厚。在利用薄膜化處理液實施防焊層薄膜化來使連結墊露出的方法時，對兩面同時實施薄膜化時，有時會發生以下之問題。 When a wiring substrate on which electronic components are mounted with a flip-chip connection, the conductor wiring density including the connection pad for external connection on the back surface may be higher than that of the conductor including the connection pad for surface electronic component connection. Wiring density. Therefore, there may be a connection pad for external connection on the back side. The thickness of the solder resist layer on the surface is thicker than the thickness of the solder resist layer on the bonding pad for connecting electronic components on the surface. When the method of thin-filming the solder resist layer using a thin-film-forming treatment solution to expose the connection pads, the following problems may occur when both surfaces are thin-filmed at the same time.

首先，以使表面之防焊層2成為電子構件連結用連結墊3之厚度以下為止的薄膜化做為基準時，背面之防焊層2也同時被實施與表面同量之薄膜化，然而，因為背面之防焊層2比表面之防焊層2更厚，背面之外部連結用連結墊4上殘留著防焊層2之殘渣，該殘渣有時會導致電氣絕緣不良的問題(第3圖)。 First, when the thickness of the solder resist layer 2 on the surface is reduced to a thickness less than the thickness of the bonding pad 3 for electronic component connection, the solder resist layer 2 on the rear surface is also thinned as much as the surface at the same time. However, Since the solder mask layer 2 on the back surface is thicker than the solder mask layer 2 on the front surface, residues of the solder mask layer 2 remain on the connection pad 4 for external connection on the rear surface, and this residue may cause a problem of poor electrical insulation (Figure 3). ).

相反地，以使背面之防焊層2成為外部連結用連結墊4之厚度以下為止的薄膜化做為基準時，表面之防焊層2也同時被實施與背面同量之薄膜化，然而，因為背面之防焊層2比表面之防焊層2更厚，充填於表面之電子構件連結用連結墊3間的防焊層2厚度比期望厚度更薄，有時會發生相鄰之電子構件連結用連結墊3間的短路問題。 On the contrary, when the thickness of the back surface solder resist layer 2 is made to be less than the thickness of the external connection pad 4 as a reference, the front surface solder mask layer 2 is also thinned as much as the back surface. However, Since the solder mask layer 2 on the back surface is thicker than the solder mask layer 2 on the surface, the thickness of the solder mask layer 2 between the bonding pads 3 for electronic component connection filled on the surface is thinner than desired, and adjacent electronic components may occur. A short circuit between the connection pads 3 for connection.

但是，於電路基板上實施電子構件之覆晶連結的印刷線路板時，為了確保電子構件與電路基板之連結信賴性，以填膠(密封樹脂)充填電子構件與電路基板之空隙來進行補強。為了確保補強效果，必須對電子構件與電路基板之空隙進行充分量之填膠的充填。然而，使用專利文獻1所得到之印刷線路板來實施覆晶連結時，為了確保補強效果而實施充分填膠之充填時，填膠從電子構件與電路基板之空隙溢至周圍，有時會對電氣作動產生不良影響。所以，為了防止填膠溢至周圍，有人提出具有堤壩構造的印刷線路板(例如，參照專利文獻3~5)。 However, in order to ensure the reliability of the connection between the electronic component and the circuit substrate when a flip-chip-connected printed wiring board is used to attach the electronic component to the circuit substrate, the gap between the electronic component and the circuit substrate is reinforced by a filler (sealing resin). In order to ensure the reinforcing effect, a sufficient amount of glue must be filled in the gap between the electronic component and the circuit board. However, when the chip-on-chip connection is performed using the printed wiring board obtained in Patent Document 1, in order to ensure a reinforcing effect and a sufficient filling is performed, the filling is performed from the electronic component and the electronic component. The space on the circuit board overflows to the surroundings, which may adversely affect the electrical operation. Therefore, in order to prevent the adhesive from overflowing to the surroundings, a printed wiring board having a dam structure has been proposed (for example, refer to Patent Documents 3 to 5).

專利文獻3提出之方法，係在具有導體電路之電路基板上形成防焊層後，實施部分曝光，其後，對未曝光部實施顯影處理，形成使部分連結墊上部從防焊層露出的開口部，其次，實施第2次部分曝光，其後，以除膠渣處理來實施第2次部分曝光之未曝光部的薄膜化，進而形成堤壩形狀的方法。利用此方法之防焊層的開口部，因為係SMD構造，難以確實固定電子構件之電極端子與對應於其之連結墊的電氣連結，有時連結墊與焊球之電氣連結會不充分。此外，利用此方法之堤壩構造的形成，因為係利用除膠渣處理來實施，有時，防焊層會粗面化而導致防焊層強度降低，進而無法充分確保印刷線路板之信賴性。 The method proposed in Patent Document 3 is to perform partial exposure after forming a solder resist layer on a circuit substrate having a conductor circuit, and then develop the unexposed portion to form an opening that exposes the upper part of the connection pad from the solder resist layer. Then, a method of performing a second partial exposure, and thereafter performing a thinning of the unexposed portion of the second partial exposure by a desmearing treatment to form a bank shape. Since the opening of the solder resist layer using this method has an SMD structure, it is difficult to reliably fix the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad, and the electrical connection between the connection pad and the solder ball may be insufficient. In addition, the formation of a dam structure using this method is implemented by using a slag removal treatment. In some cases, the solder resist may be roughened and the strength of the solder resist may be reduced, and the reliability of the printed wiring board may not be sufficiently ensured.

專利文獻4所提出之方法，係在具有導體電路之電路基板上形成防焊層後，實施部分曝光，其後，對未曝光部實施顯影處理，來形成使連結墊完全從防焊層之露出的開口部，其次，形成第2次防焊後，實施未曝光部遠大於第1次部分曝光區域之第2次部分曝光，其後，以未曝光部之顯影來形成堤壩形狀的方法。利用此方法之防焊層的開口部，係NSMD構造，連結墊之周邊附近的防焊層被完全除去，連結墊之側面完全露出，可能導致連結墊與絕緣層間的接著強度降低。 The method proposed in Patent Document 4 is to form a partial exposure after forming a solder resist layer on a circuit substrate having a conductor circuit, and then develop the unexposed portion to form the bonding pad completely exposed from the solder resist layer. Secondly, after the second solder mask is formed, a second partial exposure in which the unexposed portion is much larger than the first partially exposed region is performed, and then a method of forming a bank shape by developing the unexposed portion is performed. The opening of the solder resist layer using this method is of NSMD structure. The solder resist layer near the periphery of the connection pad is completely removed, and the side of the connection pad is completely exposed, which may cause the bonding strength between the connection pad and the insulation layer to decrease.

專利文獻5提出之方法，係在具有導體電路之電路基板上形成防焊層後，實施部分曝光製程，其後，實施未曝光部之防焊層的薄膜化，而於防焊層形成開口部及堤壩形狀的方法。利用此方法之防焊層的開口部，係SMD構造，因為連結墊之周邊附近為防焊層所覆蓋，難以使電子構件之電極端子與對應其之連結墊的電氣連結獲得確實固定，有時會有連結墊與焊球之電氣連結不充分的情形。 The method proposed in Patent Document 5 is to perform a partial exposure process after forming a solder resist layer on a circuit substrate having a conductor circuit, and thereafter, thinning the solder resist layer of the unexposed portion to form an opening portion in the solder resist layer. And dam shape methods. The opening of the solder resist layer using this method has an SMD structure. Because the vicinity of the connection pad is covered by the solder resist layer, it is difficult to secure the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad. The electrical connection between the connection pad and the solder ball may be insufficient.

[專利文獻] [Patent Literature]

[專利文獻1]日本特許3346263號公報 [Patent Document 1] Japanese Patent No. 3346263

[專利文獻2]國際公開第2012/043201號小冊子 [Patent Document 2] International Publication No. 2012/043201

[專利文獻3]日本特開2012-238668號公報 [Patent Document 3] Japanese Patent Laid-Open No. 2012-238668

[專利文獻4]日本特開平05-226505號公報 [Patent Document 4] Japanese Patent Laid-Open No. 05-226505

[專利文獻5]日本特開2011-77191號公報 [Patent Document 5] Japanese Patent Laid-Open No. 2011-77191

本發明之課題，係在提供一種於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，且電路基板之兩表面具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，在配線基板的兩表面，從防焊層露出之連結墊間不會發生電氣短路，且露出之連結墊上不殘留防焊層之殘渣的配線基板的製造方法。此外，本發明之其他課題，係在提供一種印刷線路板的製造方法，可以得到連結墊與絕緣層及連結墊與焊劑之接著強度高，無填膠流出所致之電性作動不良，防焊層強度高的印刷線路板。 The problem of the present invention is to provide a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer, and the two surfaces of the circuit substrate have a solder resist layer, so that a part of the connecting pad is exposed from the solder resist layer. A method of manufacturing a wiring board is a method of manufacturing a wiring board on both surfaces of the wiring board, where no electrical short circuit occurs between the bonding pads exposed from the solder resist, and the residue of the solder resist does not remain on the exposed bonding pads. In addition, another object of the present invention is to provide a method for manufacturing a printed wiring board. A printed wiring board with high bonding strength between the connection pad and the insulating layer, and the connection pad and the flux, without electrical failure caused by the outflow of the filler, and high strength of the solder resist layer can be obtained.

本發明者們，為了解決上述課題，經過審慎檢討的結果，發現以下述發明可以解決上述課題。 In order to solve the above-mentioned problems, the present inventors have found that the above-mentioned problems can be solved by the following inventions as a result of careful review.

(1)之配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之防焊層的製程(A)；對厚度薄於第二面之防焊層的第一面之防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之防焊層，實施於製程(B)被薄膜化之區域部分之曝光的製程(C3)；以及以顯影液除去第二面之非曝光部之防焊層的製程 (D)。 (1) A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer, and a solder resist layer is provided on both surfaces of the circuit substrate, so that a part of the connecting pad is separated from A method for manufacturing a wiring substrate with exposed solder resist layer, comprising a process of forming solder resist layers with different thicknesses on both surfaces of a circuit substrate having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer ( A); For the solder mask layer on the first side, which is thinner than the solder mask layer on the second side, the process (C1) for exposing the part other than the thinned area in the post-process (B1); for the second side The solder resist layer is implemented in the process (C2) of exposing the part other than the developed area in the post-process (D); on the first side, a thin film treatment liquid is used to make the solder resist layer of the non-exposed part into a bonding pad. A process (B) of exposing a part of the bonding pad to a thin film to a thickness of less than or equal to the thickness; and a process (C3) of exposing the solder resist layer on the first surface to the area where the process (B) is thinned; And removing the non-exposed part of the second surface with a developer Welding process layer (D).

(2)之配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之防焊層的製程(A)；對厚度薄於第二面之防焊層的第一面之防焊層，實施後製程之製程(B1)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；對第一面，在連結墊未露出之範圍，以薄膜化處理液，實施非曝光部之防焊層之薄膜化的製程(B1)；於第一面之防焊層，實施於後製程之製程(B2)被薄膜化區域以外部分之曝光的製程(C4)；於第一面，以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B2)；對第一面之防焊層，實施於製程(B2)被薄膜化之區域部分之曝光的製程(C5)；以及以顯影液除去第二面之非曝光部之防焊層的製程 (D)。 (2) A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer, and a solder resist layer is provided on both surfaces of the circuit substrate, so that a part of the connecting pad is separated from A method for manufacturing a wiring substrate with exposed solder resist layer, comprising a process of forming solder resist layers with different thicknesses on both surfaces of a circuit substrate having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer ( A); For the solder mask layer on the first side that is thinner than the solder mask layer on the second side, the process (B1) after the post-process is performed is the process (C1) of exposing parts other than the thin film area; for the second side, Solder mask is applied to the process (C2) of exposing the part other than the developed area of the post-process (D); on the first side, a non-exposed part is treated with a thin film in a range where the bonding pad is not exposed. The process of thinning the solder mask layer (B1); the solder mask on the first side is implemented in the process of the later process (B2), the process of exposing the part other than the thin film area (C4); on the first side, Implementing a thin film treatment solution A process (B2) where the thickness of the junction pad is less than the thickness to expose a part of the bonding pad (B2); the first side of the solder mask is implemented in the process (B2) where the area where the film is thinned is exposed (C5) ); And a process for removing a solder resist layer of a non-exposed part of the second surface with a developing solution (D).

(3)之配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之第一防焊層的製程(A1)；對厚度薄於第二面之第一防焊層的第一面之第一防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之第一防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之第一防焊層，實施於製程(B)被薄膜化區域部分之曝光的製程(C3)；於完成至(C3)製程為止之電路基板之第一面的第一防焊層上，形成第二防焊層之製程(A2)；對第一面之第二防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C6)；以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。 (3) A method for manufacturing a wiring board is a circuit board having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer, and a solder resist layer on both surfaces of the circuit board, so that a part of the connecting pad is removed. A method for manufacturing a wiring substrate with a solder mask exposed, comprising: forming a first solder mask with different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer; Process (A1); for the first solder mask having a thickness thinner than the second solder mask on the first side, the process (B) of the first process in which the post-process is carried out (B) is exposed outside the thinned area (C1) ); For the first solder resist layer on the second side, the process (C2) of exposing the portion other than the developed area in the post-process (D1) is performed; on the first side, the non-exposed portion is implemented with a thin film treatment liquid. The process (B) of forming the first solder resist layer to a thickness less than the thickness of the bonding pad to expose a part of the bonding pad; the first solder resist layer on the first side is thinned into the process (B). Regional part exposure process (C3); after completion to (C3) process The process (A2) of forming a second solder resist layer on the first solder resist layer on the first side of the circuit board so far; the second solder resist layer on the first face is developed in a process (D1) implemented in a later process Process (C6) for exposing parts other than the area; and removing the second solder resist layer and the second non-exposed part of the first surface with a developing solution Process (D1) of the first solder resist layer on the non-exposed part of the surface.

(4)之配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之第一防焊層的製程(A1)；對厚度薄於第二面之第一防焊層的第一面之第一防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之第一防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之第一防焊層，實施於製程(B)被薄膜化區域部分之曝光的製程(C3)；以顯影液除去第二面之非曝光部之第一防焊層的製程(D)；於完成至(D)製程為止之電路基板之第一面的第一防焊層上，形成第二防焊層之製程(A2)；對第一面之第二防焊層，實施於後製程之製程(D2) 被顯影區域以外部分之曝光的製程(C6)；以及以顯影液除去第一面之非曝光部之第二防焊層的製程(D2)。 (4) A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer, and a solder resist layer is provided on both surfaces of the circuit substrate, so that a part of the connecting pad is separated from A method for manufacturing a wiring substrate with a solder mask exposed, comprising: forming a first solder mask with different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer; Process (A1); for the first solder mask having a thickness thinner than the second solder mask on the first side, the process (B) of the first process in which the post-process is carried out (B) is exposed outside the thinned area (C1) ); For the first solder mask layer on the second side, the process (C2) of exposing the part other than the developed area in the post-process (D) is performed; on the first side, a non-exposure is performed with a thin film treatment liquid The first solder resist layer is thinned to a thickness of the bonding pad or less, and a part of the bonding pad is exposed (B). The first solder resist layer on the first surface is applied to the process (B). Process (C3) for exposing a portion of a region; removing with a developer Manufacturing process (D) of the first solder resist layer of the non-exposed part on the second side; forming the second solder resist layer on the first solder resist layer on the first side of the circuit substrate until completion of the (D) process (A2); For the second solder mask on the first side, the process (D2) is implemented in the post-process A process (C6) for exposing a portion other than the developed area; and a process (D2) for removing a second solder resist layer of a non-exposed part of the first surface with a developing solution.

(5)之配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之第一防焊層的製程(A1)；對第二面之第一防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之第一防焊層，實施於製程(B)被薄膜化區域部分之曝光的製程(C3)；於完成至(C3)製程為止之電路基板之第一面的第一防焊層上，形成第二防焊層之製程(A2)；對第一面之第二防焊層，實施於後製程之製程(B3)被薄膜化區域以外部分之曝光的製程(C6)；於第一面，在連結墊未露出之範圍，以薄膜化處理液實施非曝光部之第二防焊層之薄膜化的製程(B3)；對第一面之第二防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C7)；以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。 (5) A method for manufacturing a wiring board is a circuit board having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer, and a solder resist layer on both surfaces of the circuit board, so that a part of the connecting pad is A method for manufacturing a wiring substrate with a solder mask exposed, comprising: forming a first solder mask with different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer; Process (A1); for the first solder resist layer on the second side, the process (C2) of exposing the part outside the developed area in the process (D1) of the post-process; on the first side, a thin film treatment solution is used to implement The process (B) of forming the first solder resist layer of the non-exposed portion to a thickness less than the thickness of the bonding pad to expose a part of the bonding pad; the first solder resist layer on the first side is implemented in the manufacturing process (B) Process (C3) for exposing part of the filmed area; process (A2) for forming a second solder resist layer on the first solder resist layer on the first side of the circuit substrate until the process (C3) is completed; The second solder mask on one side is implemented in the post-process (B3) Process (C6) for exposing parts other than the thinned area; on the first side, in a range where the bonding pad is not exposed, a process for thinning the second solder resist layer of the non-exposed part with a thinning treatment liquid (B3) ; For the second solder mask layer on the first side, a process (C7) of exposing the portion other than the developed area in the post-process (D1); and a second solder mask for removing the non-exposed part of the first side with a developing solution Process (D1) of the first solder resist layer of the second layer and the non-exposed portion on the second surface.

(6)之配線基板的製造方法，係在製程(C1)之前，實施製程(C2)之上述(1)~(4)項之其中任一項所記載之配線基板的製造方法。 (6) The manufacturing method of the wiring board is a manufacturing method of the wiring board described in any one of the items (1) to (4) of the manufacturing process (C2) before the manufacturing process (C1).

(7)配線基板的製造方法，係同時實施製程(C1)及製程(C2)之上述(1)~(4)項之其中任一項所記載之配線基板的製造方法。 (7) A method for manufacturing a wiring board is a method for manufacturing a wiring board according to any one of the above (1) to (4) in which the process (C1) and the process (C2) are performed simultaneously.

(8)之配線基板的製造方法，係以氧環境下之非接觸曝光方式來實施製程(C3)之曝光之上述(1)、(3)、(4)項之其中任一項所記載之配線基板的製造方法。 (8) The method for manufacturing a wiring board is the method described in any one of the items (1), (3), and (4) described above in which the exposure of the process (C3) is performed by a non-contact exposure method in an oxygen environment. Manufacturing method of wiring board.

(9)之配線基板的製造方法，係以氧環境下之非接觸曝光方式來實施製程(C3)及製程(C7)之曝光之上述(5)所記載之配線基板的製造方法。 (9) The method for manufacturing a wiring board is a method for manufacturing a wiring board according to (5) above, in which the exposure in the process (C3) and the process (C7) is performed by a non-contact exposure method in an oxygen environment.

(10)之配線基板的製造方法，係以氧環境下之非接觸曝光方式來實施製程(C4)及製程(C5)之曝光之上述(2)所記載之配線基板的製造方法。 (10) The method for manufacturing a wiring board is the method for manufacturing a wiring board described in (2) above in which the exposure in the process (C4) and the process (C5) is performed by a non-contact exposure method in an oxygen environment.

(11)之配線基板的製造方法，係製程(C3)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下之上述(1)、(3)、(4)、(8)項之其中任一項所記載之配線基板的製造方法。 (11) A method for manufacturing a wiring board, in which the exposure amount in the process (C3) is 1 to 5 times the exposure amount in the process (C1), and the above (1), (3), (4), (8) The method of manufacturing a wiring board according to any one of the items).

(12)之配線基板的製造方法，係製程(C3)及製程(C7)之曝光量為製程(C6)之曝光量之1倍以上、5倍以下之上述(5)或(9)所記載之配線基板的製造方法。 (12) The manufacturing method of the wiring board is such that the exposure amount of the process (C3) and the process (C7) is more than 1 to 5 times the exposure amount of the process (C6), as described in (5) or (9) above. Manufacturing method of wiring board.

(13)之配線基板的製造方法，係製程(C4)及製程(C5)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下之上述(2)或(10)所記載之配線基板的製造方法。 (13) The manufacturing method of the wiring board is such that the exposure amount of the process (C4) and the process (C5) is 1 to 5 times the exposure amount of the process (C1), as described in (2) or (10) above. Manufacturing method of wiring board.

(14)之配線基板的製造方法，係製程(B)之防焊層的薄膜化處理以薄膜化處理面朝上來實施之上述(1)、(3)、(4)、(8)、(11)項之其中任一項所記載之配線基板的製造方法。 (14) The method for manufacturing a wiring substrate is the thinning treatment of the solder resist layer in the process (B), and the thinning treatment is performed with the thinning treatment surface facing upwards (1), (3), (4), (8), ( The manufacturing method of the wiring board as described in any one of 11).

(15)之配線基板的製造方法，係製程(B)及製程(B3)之防焊層的薄膜化處理以薄膜化處理面朝上來實施之上述(5)、(9)、(12)項之其中任一項所記載之配線基板的製造方法。 (15) A method for manufacturing a wiring board, which is carried out in (5), (9), and (12) of the above steps (5), (9), and (12) in which the thinning treatment of the solder resist layer in the process (B) and the process (B3) The manufacturing method of the wiring board as described in any one of them.

(16)之配線基板的製造方法，係製程(B1)及製程(B2)之防焊層的薄膜化處理以薄膜化處理面朝上來實施之上述(2)、(10)、(13)項之其中任一項所記載之配線基板的製造方法。 (16) A method for manufacturing a wiring board, which is carried out in (2), (10), and (13) of the above-mentioned (2), (10), and (13) in which the thinning treatment of the solder resist layer in the manufacturing process (B1) and the manufacturing process (B2) is performed with the film-forming process facing upward. The manufacturing method of the wiring board as described in any one of them.

依據本發明，可以提供一種配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，在配線基板的兩表面，從防焊層露出之連結墊間不會發生電氣短路，此外，防焊層之殘渣不會殘留於露出之連結墊上。此外，依據本發明，可以提供一種印刷線路板之製造方法，可以得到連結墊與絕緣層及連結墊與焊劑之高接著強度，無填膠流出所導致的電氣作動不良，且防焊層強度高的印刷線路板。 According to the present invention, it is possible to provide a method for manufacturing a wiring substrate, which is a circuit substrate having an insulating layer on both surfaces and a connection pad formed on the surface of the insulation layer, and a solder resist layer on both surfaces of the circuit substrate, so that the connection pad A method for manufacturing a wiring board whose part is exposed from the solder resist layer does not prevent the connection pads exposed from the solder resist layer on both surfaces of the wiring substrate. An electrical short circuit occurs, and in addition, the residue of the solder resist does not remain on the exposed bonding pad. In addition, according to the present invention, a method for manufacturing a printed circuit board can be provided, which can obtain high bonding strength between the connection pad and the insulating layer, and the connection pad and the solder, without electrical failure caused by the outflow of the filler, and high strength of the solder resist. Printed circuit board.

1‧‧‧電路基板 1‧‧‧circuit board

2‧‧‧防焊層 2‧‧‧ solder mask

2-1‧‧‧第一防焊層 2-1‧‧‧First solder resist

2-2‧‧‧第二防焊層 2-2‧‧‧Second solder mask

3‧‧‧電子構件連結用連結墊、第一面之連結墊 3‧‧‧ Connection pad for electronic component connection, first connection pad

4‧‧‧外部連結用連結墊、第二面之連結墊 4‧‧‧ Link pad for external connection, link pad on the second side

5‧‧‧光罩 5‧‧‧Mask

6‧‧‧活性光線 6‧‧‧ Active light

7‧‧‧導體配線 7‧‧‧Conductor wiring

8‧‧‧絕緣層 8‧‧‧ Insulation

第1圖係配線基板一例之概略剖面圖。 FIG. 1 is a schematic cross-sectional view of an example of a wiring board.

第2圖係配線基板一例之概略剖面圖。 Fig. 2 is a schematic cross-sectional view of an example of a wiring substrate.

第3圖係配線基板一例之概略剖面圖。 Fig. 3 is a schematic cross-sectional view of an example of a wiring substrate.

第4圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 4 is a cross-sectional process drawing showing an example of a method for manufacturing a wiring substrate according to the present invention.

第5圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 5 is a cross-sectional process drawing showing an example of a method for manufacturing a wiring substrate according to the present invention.

第6圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 6 is a cross-sectional process drawing showing an example of a method for manufacturing a wiring substrate according to the present invention.

第7圖係本發明之配線基板的製造方法一例之剖面製程圖。 FIG. 7 is a cross-sectional process drawing showing an example of a method for manufacturing a wiring substrate according to the present invention.

第8圖係本發明之配線基板的製造方法一例之剖面製程圖。 FIG. 8 is a cross-sectional process drawing of an example of a method for manufacturing a wiring substrate of the present invention.

第9圖係本發明所製造之配線基板一例的概略剖面圖。 Fig. 9 is a schematic cross-sectional view of an example of a wiring substrate manufactured by the present invention.

第10圖係本發明所製造之配線基板一例的概略剖面圖。 FIG. 10 is a schematic cross-section of an example of a wiring board manufactured by the present invention Illustration.

第11圖係本發明所製造之配線基板一例的概略剖面圖。 Fig. 11 is a schematic cross-sectional view of an example of a wiring substrate manufactured by the present invention.

第12圖係本發明所製造之配線基板一例的概略剖面圖。 Fig. 12 is a schematic cross-sectional view of an example of a wiring substrate manufactured by the present invention.

第13圖係多層電路基板一例之概略剖面圖。 FIG. 13 is a schematic cross-sectional view of an example of a multilayer circuit board.

以下，針對本發明之配線基板的製造方法進行詳細說明。 Hereinafter, the manufacturing method of the wiring board of this invention is demonstrated in detail.

第4-1圖及第4-2圖係配線基板的製造方法(1)一例之剖面製程圖。準備兩表面具有絕緣層8、及形成於絕緣層8表面之導體配線7的電路基板。導體配線7之一部分係連結墊3及4。製程(A)時，於電路基板1之兩表面，以覆蓋全面之方式形成著防焊層2。第一面及第二面之防焊層2的形成上，可以兩表面同時實施，也可以逐面實施，然而，必須對應形成之防焊層厚度，設定不會過度熱硬化之加熱條件。兩表面之防焊層2的厚度不同，厚度較薄之一方為「第一面」，厚度較厚之一方為「第二面」。在兩表面，以相同條件形成防焊層2時，防焊層2之厚度，隨著包含各面之連結墊3及4在內的導體配線7密度而產生變化。第4-1圖時，下側之第二面之導體配線7密度大於上側之第一面，故第二面之導體配線7上的防焊層2厚度也大於第一面之導體配線7上的防焊層 2厚度。而且，配載電子構件之配線基板時，有時包含背面之外部連結用連結墊4在內之周圍導體配線7的密度大於包含表面之電子構件連結用連結墊3在內之周圍導體配線7密度，故表面為第一面，背面則為第二面。 Figures 4-1 and 4-2 are cross-sectional process drawings of an example of the method (1) of manufacturing a wiring board. A circuit board having an insulating layer 8 on both surfaces and a conductor wiring 7 formed on the surface of the insulating layer 8 is prepared. Part of the conductor wiring 7 is the connection pads 3 and 4. During the process (A), a solder resist layer 2 is formed on both surfaces of the circuit substrate 1 so as to cover the entire surface. The formation of the solder resist layer 2 on the first surface and the second surface can be implemented on both surfaces simultaneously or one by one. However, the heating conditions must be set according to the thickness of the solder resist layer to be formed without excessive thermal hardening. The thicknesses of the solder resists 2 on the two surfaces are different. The one with the thinner thickness is the "first side", and the one with the thicker thickness is the "second side." When the solder resist layer 2 is formed on both surfaces under the same conditions, the thickness of the solder resist layer 2 changes with the density of the conductor wiring 7 including the connection pads 3 and 4 on each side. In Fig. 4-1, the density of the conductor wiring 7 on the second side of the lower side is larger than that of the first side on the upper side. Therefore, the thickness of the solder resist 2 on the conductor wiring 7 on the second side is also larger than that on the conductor wiring 7 on the first side. Solder mask 2 thickness. Furthermore, when a wiring board on which electronic components are placed, the density of the peripheral conductor wirings 7 including the back-side external connection connecting pads 4 may be higher than the density of the peripheral conductor wirings 7 including the front-side electronic component connection connecting pads 3. Therefore, the surface is the first surface and the back surface is the second surface.

製程(C1)時，對第一面之防焊層2，實施於後製程之製程(B)被薄膜化區域以外部分之曝光。製程(C2)時，對第二面之防焊層2，實施於後製程之製程(D)被顯影之區域以外部分的曝光。在防焊層2之經過曝光的部分，防焊劑產生光聚合，而對薄膜化製程及顯影製程具有耐性。 In the manufacturing process (C1), the solder mask layer 2 on the first side is exposed to a part other than the thinned area in the manufacturing process (B) of the post-processing. During the manufacturing process (C2), the second side of the solder resist layer 2 is exposed to a part other than the area where the manufacturing process (D) of the subsequent manufacturing process is developed. In the exposed portion of the solder resist layer 2, the solder resist generates photopolymerization, and has resistance to a thin film formation process and a development process.

製程(B)時，於第一面，以薄膜化處理液實施使非曝光部之防焊層2成為連結墊3之厚度以下為止的薄膜化，來使連結墊3之一部分露出。配載電子構件之配線基板時，於該製程(B)，將露出之連結墊3當做電子構件連結用連結墊3來使用。製程(B)時，也同時實施第二面之非曝光部之防焊層2的薄膜化，然而，因為第二面之連結墊4上的防焊層2比第一面之連結墊3上的防焊層2更厚，防焊層2之殘渣殘留於連結墊4上。 In the process (B), a thin film is used on the first surface to thin the non-exposed portion of the solder resist layer 2 to a thickness of the connection pad 3 or less to expose a part of the connection pad 3. When a wiring board on which electronic components are placed, in this process (B), the exposed bonding pad 3 is used as the bonding pad 3 for connecting electronic components. In the process (B), the thinning of the solder resist layer 2 of the non-exposed part on the second side is also performed at the same time. However, the solder resist layer 2 on the bonding pad 4 on the second side is higher than the bonding pad 3 on the first side. The solder resist layer 2 is thicker, and the residue of the solder resist layer 2 remains on the connection pad 4.

製程(C3)時，對第一面之防焊層2，實施在製程(B)被薄膜化之區域部分的曝光。防焊層2之經過曝光的部分，防焊劑產生光聚合，而對顯影製程具有耐性。 During the manufacturing process (C3), the solder resist layer 2 on the first side is exposed to a part of the area where the manufacturing process (B) is thinned. In the exposed portion of the solder resist layer 2, the solder resist generates photopolymerization and is resistant to the development process.

製程(D)時，於第二面，以顯影液除去非曝光部之防焊層2，來使連結墊4之一部分露出。藉由製程 (D)，殘留於連結墊4上之防焊層2殘渣被除去。配載電子構件之配線基板時，將於該製程(D)露出之連結墊4當做外部連結用連結墊4來使用。在第一面之防焊層2，於製程(B)被薄膜化之區域部分，在製程(D)之前所實施的製程(C3)被曝光，對顯影製程具有耐性，而未被顯影液除去。 During the manufacturing process (D), a part of the connection pad 4 is exposed by removing the solder resist layer 2 of the non-exposed portion with a developing solution on the second surface. By process (D) The residue of the solder resist 2 remaining on the connection pad 4 is removed. When a wiring board on which electronic components are placed, the connection pad 4 exposed in the process (D) is used as the connection pad 4 for external connection. The solder resist layer 2 on the first side is exposed to the process (C3) performed before the process (D) in the area where the process (B) is thinned, and has resistance to the development process without being removed by the developer. .

配線基板的製造方法(1)時，可以將製程(C1)之曝光區域變化成任意形狀，藉由曝光區域之變更，例如，可以製作如第9圖所示之剖面形狀的配線基板。第9之a圖時，於第一面之連結墊3間形成有防焊層2之凸部。第9之b圖時，於第一面，交互並列著為從防焊層2露出之連結墊3及防焊層2所覆蓋的導體配線7。 In the method (1) for manufacturing a wiring board, the exposed area in the process (C1) can be changed to an arbitrary shape. By changing the exposed area, for example, a wiring board with a cross-sectional shape as shown in FIG. 9 can be produced. In FIG. 9A, a convex portion of the solder resist layer 2 is formed between the connection pads 3 on the first surface. In Fig. 9b, on the first side, the conductor wiring 7 covered by the connection pad 3 exposed from the solder resist layer 2 and the solder resist layer 2 are alternately arranged in parallel.

第5-1圖、第5-2圖及第5-3圖，係配線基板的製造方法(2)一例之剖面製程圖。配線基板的製造方法(1)的不同，係於第一面，分別追加一次防焊層2之曝光製程及薄膜化製程。藉由覆晶連結將電子構件配載於配線基板時，因為電子構件與配線基板之熱膨漲係數差而承受到熱衝擊時，應力集中於連結部，而使連結部發生變形或被破壞。為了防止應力集中於連結部並提高連結信賴性，一般，以被稱為填膠之樹脂組成物來密封電子構件與配線基板之間。依據配線基板的製造方法(2)，可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 Fig. 5-1, Fig. 5-2, and Fig. 5-3 are cross-sectional process drawings of an example of a method (2) of manufacturing a wiring board. The difference in the manufacturing method (1) of the wiring board is based on the first side, and an additional exposure process and a thin film formation process of the solder resist layer 2 are added respectively. When an electronic component is mounted on a wiring substrate by a flip-chip connection, when a thermal shock is applied due to a difference in thermal expansion coefficient between the electronic component and the wiring substrate, stress is concentrated on the connecting portion, and the connecting portion is deformed or broken. In order to prevent stress from being concentrated on the connection portion and improve connection reliability, a resin composition called a filler is generally used to seal the gap between the electronic component and the wiring board. According to the manufacturing method (2) of the wiring board, a solder mask having a two-stage structure having a dam structure for the purpose of filling the gap between the electronic component and the wiring board with a dam can be formed.

製程(A)時，於電路基板1之兩表面，以覆蓋全面之方式來形成防焊層2。製程(C1)時，對第一面之防焊層2，實施於後製程之製程(B1)被薄膜化區域以外部分之曝光。製程(C2)時，對第二面之防焊層2，實施於後製程之製程(D)被顯影之區域以外部分的曝光。 During the process (A), the two surfaces of the circuit substrate 1 are covered with Cover the whole way to form the solder mask 2. During the manufacturing process (C1), the solder mask layer 2 on the first side is exposed to a part other than the thinned area in the manufacturing process (B1) of the post-processing. During the manufacturing process (C2), the second side of the solder resist layer 2 is exposed to a part other than the area where the manufacturing process (D) of the subsequent manufacturing process is developed.

製程(B1)時，於第一面，在連結墊3未露出之範圍，以薄膜化處理液實施非曝光部之防焊層2的薄膜化。製程(B1)時，也同時對第二面之非曝光部的防焊層2實施薄膜化。 In the manufacturing process (B1), on the first surface, the thickness of the solder resist layer 2 of the non-exposed portion is thinned with a thinning treatment liquid in a range where the connection pad 3 is not exposed. In the manufacturing process (B1), the thickness of the solder resist layer 2 of the non-exposed portion on the second surface is also reduced.

製程(C4)時，對第一面之防焊層2，實施於後製程之製程(B2)被薄膜化之區域以外部分的曝光。 During the manufacturing process (C4), the first side of the solder resist layer 2 is exposed to a part other than the area where the manufacturing process (B2) of the post-processing is thinned.

製程(B2)時，於第一面，以薄膜化處理液實施使非曝光部之防焊層2成為連結墊3之厚度以下為止的薄膜化，來使連結墊3之一部分露出。配載電子構件之配線基板時，於該製程(B2)，將露出之連結墊3當做電子構件連結用連結墊3來使用。製程(B2)時，也同時實施第二面之非曝光部之防焊層2的薄膜化，因為第二面之連結墊4上的防焊層2比第一面之連結墊3上的防焊層2更厚，防焊層2之殘渣殘留於連結墊4上。 In the manufacturing process (B2), a thin film is used on the first surface to thin the non-exposed portion of the solder resist layer 2 to a thickness of the connection pad 3 or less to expose a part of the connection pad 3. When the wiring board for electronic components is placed, in this process (B2), the exposed connection pad 3 is used as the connection pad 3 for electronic component connection. In the manufacturing process (B2), the thinning of the solder resist layer 2 on the non-exposed part of the second side is also performed at the same time, because the solder resist layer 2 on the bonding pad 4 on the second side is lower than the solder resist on the bonding pad 3 on the first side. The solder layer 2 is thicker, and the residue of the solder resist layer 2 remains on the connection pad 4.

製程(C5)時，對第一面之防焊層2，實施在製程(B2)被薄膜化之區域部分的曝光。 During the manufacturing process (C5), the first side of the solder resist layer 2 is exposed to the area where the manufacturing process (B2) is thinned.

製程(D)時，於第二面，以顯影液除去非曝光部之防焊層2，來使連結墊4之一部分露出。藉由製程(D)，殘留於連結墊4上之防焊層2殘渣被除去。配載電子構件之配線基板時，將於該製程(D)露出之連結墊 4當做外部連結用連結墊4來使用。 During the manufacturing process (D), a part of the connection pad 4 is exposed by removing the solder resist layer 2 of the non-exposed portion with a developing solution on the second surface. By the process (D), the residue of the solder resist 2 remaining on the connection pad 4 is removed. When the wiring board for electronic components is placed, the bonding pads exposed in this process (D) 4 is used as a connection pad 4 for external connection.

配線基板的製造方法(2)時，可以將製程(C4)之曝光區域變化成任意形狀，藉由曝光區域之變更，例如，可以製作第10圖所示之剖面形狀的配線基板。第10之c圖時，於第一面之連結墊3間形成有防焊層2之凸部。第10圖之d時，於第一面，交互並列著從防焊層2露出之連結墊3及被防焊層2覆蓋之導體配線7。 In the method (2) of manufacturing a wiring board, the exposed area in the process (C4) can be changed to an arbitrary shape. By changing the exposed area, for example, a wiring board with a cross-sectional shape as shown in FIG. 10 can be produced. In FIG. 10C, a convex portion of the solder resist layer 2 is formed between the connection pads 3 on the first surface. At d of FIG. 10, the connection pads 3 exposed from the solder resist layer 2 and the conductor wirings 7 covered by the solder resist layer 2 are alternately juxtaposed on the first surface.

第6-1圖、第6-2圖及第6-3圖，係配線基板的製造方法(3)一例之剖面製程圖。與配線基板的製造方法(2)不同之點，係第一面之防焊層由第一防焊層2-1及第二防焊層2-2所構成。配線基板的製造方法(3)時，係進行使第一面之非曝光部的第一防焊層2-1之厚度成為連結墊3之厚度以下為止的薄膜化後，於第一防焊層2-1之表面上形成第二防焊層2-2，進行曝光後，進行非曝光部之第二防焊層2-2的顯影處理。藉此，與使用配線基板的製造方法(2)時相同，可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 Fig. 6-1, Fig. 6-2 and Fig. 6-3 are cross-sectional process drawings of an example of a method (3) of manufacturing a wiring board. The difference from the manufacturing method (2) of the wiring board is that the first solder mask layer is composed of the first solder mask layer 2-1 and the second solder mask layer 2-2. In the method (3) for manufacturing a wiring board, the thickness of the first solder resist layer 2-1 of the non-exposed portion of the first surface is reduced to a thickness of the connection pad 3 or less, and then the first solder resist layer is formed. A second solder resist layer 2-2 is formed on the surface of 2-1, and after exposure, a development treatment of the second solder resist layer 2-2 in the non-exposed portion is performed. Thereby, as in the case of the manufacturing method (2) using the wiring substrate, a solder mask having a two-stage structure having a dam structure for the purpose of filling the gap between the electronic component and the wiring substrate can be formed.

製程(A1)時，於電路基板1之第一面與第二面，形成有厚度不同之第一防焊層2-1。第一面與第二面之第一防焊層2-1的形成，可以兩表面同時也可逐片實施，但必須對應所形成之防焊層的厚度，來設定不會過度熱硬化之加熱條件。 During the manufacturing process (A1), a first solder resist layer 2-1 having a different thickness is formed on the first surface and the second surface of the circuit substrate 1. The formation of the first solder resist layer 2-1 on the first surface and the second surface can be implemented on both surfaces at the same time, but can be implemented piece by piece, but the thickness of the solder resist layer to be formed must be set to prevent excessive heat hardening. condition.

製程(C1)時，對厚度比第二面之第一防焊層2-1更薄之第一面的第一防焊層2-1，實施於後製程之製程(B)被薄膜化區域以外部分之曝光。製程(C2)時，對第二面之第一防焊層2-1，實施於後製程之製程(D1)被顯影之區域以外部分的曝光。 During the process (C1), the first solder mask layer 2-1 on the first side, which is thinner than the first solder mask layer 2-1 on the second side, is applied to the thinned area of the later process (B). Exposure of other parts. During the manufacturing process (C2), the first solder resist layer 2-1 on the second side is exposed to a portion other than the area where the manufacturing process (D1) of the subsequent manufacturing process is developed.

製程(B)時，於第一面，以薄膜化處理液實施使非曝光部之第一防焊層2-1成為連結墊3之厚度以下為止的薄膜化，來使連結墊3之一部分露出。製程(B)時，第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而，因為第二面之連結墊4上之第一防焊層2-1比第一面之連結墊3上之第一防焊層2-1更厚，於連結墊4上，殘留著第一防焊層2-1之殘渣。 In the process (B), a thin film is used on the first surface to thin the first solder resist layer 2-1 of the non-exposed portion to a thickness of the bonding pad 3 or less to expose a part of the bonding pad 3 . In the process (B), the first solder resist 2-1 of the non-exposed portion on the second surface is also thinned. However, because the first solder resist layer 2-1 on the second side bonding pad 4 is thicker than the first solder resist layer 2-1 on the first side bonding pad 3, the first A residue of solder mask 2-1.

製程(C3)時，對第一面之第一防焊層2-1，實施於製程(B)被薄膜化之區域部分的曝光。 During the manufacturing process (C3), the first solder resist layer 2-1 on the first surface is exposed to the area where the manufacturing process (B) is thinned.

製程(A2)時，於完成至製程(C3)為止之電路基板之第一面的第一防焊層2-1，形成第二防焊層2-2。此時，調整第一面之第二防焊層2-2的相關加熱條件，來使第二面之第一防焊層2-1的非曝光部不會發生過度熱硬化。 During the manufacturing process (A2), the second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit substrate up to the process (C3). At this time, the relevant heating conditions of the second solder resist layer 2-2 on the first side are adjusted so that the non-exposed portion of the first solder resist layer 2-1 on the second side does not undergo excessive thermal hardening.

製程(C6)時，對第一面之第二防焊層2-2，實施於後製程之製程(D1)被顯影區域以外部分之曝光。 During the manufacturing process (C6), the second solder resist layer 2-2 on the first side is exposed to a part other than the developed area in the manufacturing process (D1) of the subsequent manufacturing process.

製程(D1)時，以顯影液除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1，來使連結墊3及4之一部分露出。以製程(D1)，除去殘留於連結墊4上之第一防焊層2-1的殘渣。配載電子構件之配線基板時，於該製程(D1)露出之連結墊3被當做電子構件連結用連結墊3來使用，連結墊4則被當做外部連結用連結墊4來使用。 During the manufacturing process (D1), the developing pad is used to remove the second solder resist layer 2-2 of the non-exposed portion on the first surface and the first solder resist layer 2-1 of the non-exposed portion on the second surface to make the connection pads 3 and One part of 4 is exposed. With the process (D1), The residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. When the wiring board for mounting electronic components is placed, the bonding pad 3 exposed in this process (D1) is used as the bonding pad 3 for connecting electronic components, and the bonding pad 4 is used as the bonding pad 4 for external connections.

第7-1圖、第7-2圖及第7-3圖，係配線基板的製造方法(4)一例之剖面製程圖。與配線基板的製造方法(3)不同之點，係在形成第一面之第二防焊層2-2前，以顯影液除去第二面之第一防焊層2-1。首先，在以顯影液除去第二面之非曝光部的第一防焊層2-1來形成第一面之第二防焊層2-2時，無需實施同時對第二面之非曝光部的第一防焊層2-1進行加熱來避免過度熱硬化之加熱條件調整。配線基板的製造方法(4)時，與使用配線基板的製造方法(2)及(3)時相同，可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 FIG. 7-1, FIG. 7-2, and FIG. 7-3 are cross-sectional process drawings of an example of a method (4) of manufacturing a wiring board. The difference from the manufacturing method (3) of the wiring substrate is that the first solder resist layer 2-1 on the second surface is removed with a developing solution before the second solder resist layer 2-2 on the first surface is formed. First, when the first solder resist layer 2-1 of the non-exposed portion on the second surface is removed with a developing solution to form the second solder resist layer 2-2 of the first surface, it is not necessary to simultaneously perform the non-exposed portion on the second surface. The first solder resist layer 2-1 is heated to avoid excessive thermal hardening adjustment of the heating conditions. In the method (4) of manufacturing a wiring board, the same as when manufacturing methods (2) and (3) using a wiring board, it is possible to form a dam structure with the purpose of filling the gap between the electronic component and the wiring board with a dam. Two-stage construction of solder mask.

製程(A1)時，於電路基板1之第一面與第二面，形成有厚度不同之第一防焊層2-1。製程(C1)，對厚度比第二面之第一防焊層2-1更薄之第一面之第一防焊層2-1，實施於後製程之製程(B)被薄膜化區域以外部分之曝光。製程(C2)時，對第二面之第一防焊層2-1，實施於後製程之製程(D)被顯影之區域以外部分的曝光。 During the manufacturing process (A1), a first solder resist layer 2-1 having a different thickness is formed on the first surface and the second surface of the circuit substrate 1. Process (C1), the first solder mask layer 2-1 on the first side, which is thinner than the first solder mask layer 2-1 on the second side, is performed outside the thinned area of the later process (B) Partial exposure. During the manufacturing process (C2), the first solder resist layer 2-1 on the second side is exposed to a portion other than the area where the manufacturing process (D) of the subsequent manufacturing process is developed.

製程(B)時，於第一面，以薄膜化處理液實施使非曝光部之第一防焊層2-1成為連結墊3之厚度以下為止之薄膜化，來使連結墊3之一部分露出。製程(B)時，第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而，因為第二面之連結墊4上的第一防焊層2-1比第一面之連結墊3上的第一防焊層2-1更厚，連結墊4上殘留著第一防焊層2-1之殘渣。 During the manufacturing process (B), the first surface is treated with a thin film treatment solution so that the first solder resist layer 2-1 of the non-exposed portion becomes the thickness of the connection pad 3 or less. The thin film has been formed so as to expose a part of the connection pad 3. In the process (B), the first solder resist 2-1 of the non-exposed portion on the second surface is also thinned. However, because the first solder resist layer 2-1 on the second side bonding pad 4 is thicker than the first solder resist layer 2-1 on the first side bonding pad 3, the first solder resist remains on the bonding pad 4. Residue of solder layer 2-1.

製程(D)時，以顯影液除去第二面之非曝光部的第一防焊層2-1，來使連結墊4之一部分露出。藉由製程(D)，殘留於連結墊4上之第一防焊層2-1的殘渣被除去。配載電子構件之配線基板時，將於該製程(D)露出之連結墊4當做外部連結用連結墊4來使用。 In the process (D), a part of the connection pad 4 is exposed by removing the first solder resist 2-1 of the non-exposed portion on the second surface with a developing solution. By the process (D), the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. When a wiring board on which electronic components are placed, the connection pad 4 exposed in the process (D) is used as the connection pad 4 for external connection.

製程(A2)時，於完成至製程(D)為止之電路基板之第一面的第一防焊層2-1上，形成第二防焊層2-2。 In the process (A2), a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit substrate up to the process (D).

製程(C6)時，對第一面之第二防焊層2-2，實施於後製程之製程(D2)被顯影區域以外部分之曝光。 During the manufacturing process (C6), the second solder resist layer 2-2 on the first side is exposed to a portion other than the developed area in the manufacturing process (D2) of the subsequent manufacturing process.

製程(D2)時，以顯影液除去第一面之非曝光部的第二防焊層2-2，來使連結墊3之一部分露出。配載電子構件之配線基板時，將於製程(D2)被露出之連結墊3當做電子構件連結用連結墊3來使用。 In the manufacturing process (D2), the second solder resist 2-2 of the non-exposed part of the first surface is removed with a developing solution to expose a part of the connection pad 3. When the wiring board on which the electronic component is placed is placed, the connection pad 3 exposed in the manufacturing process (D2) is used as the connection pad 3 for electronic component connection.

配線基板的製造方法(3)及(4)時，可以將製程(C1)之曝光區域變化成任意形狀，藉由曝光區域之變更，例如，可以製作第11圖所示之剖面形狀的配線基板。第11之e圖時，於第一面之連結墊3之間，形成有第一防焊層2-1之凸部。第11之f圖時，交互並列著從第一防焊層2-1露出之連結墊3及為第一防焊層2-1所覆蓋之導體配線7。 In the manufacturing methods (3) and (4) of the wiring board, the exposure area in the process (C1) can be changed to an arbitrary shape, and by changing the exposure area, for example, a cross-sectional wiring as shown in FIG. 11 can be produced. Substrate. In FIG. 11e, a convex portion of the first solder resist layer 2-1 is formed between the connection pads 3 on the first surface. In FIG. 11f, the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered by the first solder resist layer 2-1 are alternately arranged in parallel.

第8-1圖、第8-2圖及第8-3圖，係配線基板的製造方法(5)一例之剖面製程圖。配線基板的製造方法(5)時，係於第一面，在對第一防焊層2-1實施曝光前，實施使第一防焊層2-1之厚度成為連結墊3之厚度以下為止之薄膜化處理。其後，於第一防焊層2-1之表面上形成第二防焊層2-2並曝光後，實施非曝光部之第二防焊層2-2的薄膜化處理，其後，再度執行曝光，執行殘餘之非曝光部之第二防焊層2-2的顯影處理。配線基板的製造方法(5)時，與使用配線基板的製造方法(2)~(4)時相同，可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 Fig. 8-1, Fig. 8-2 and Fig. 8-3 are cross-sectional process drawings of an example of a method (5) of manufacturing a wiring board. In the method (5) for manufacturing a wiring board, the first solder resist layer 2-1 is attached to the first surface, and the thickness of the first solder resist layer 2-1 is made to be equal to or less than the thickness of the connection pad 3 before the first solder resist layer 2-1 is exposed. Thin film processing. Thereafter, a second solder resist layer 2-2 is formed on the surface of the first solder resist layer 2-1 and exposed, and then a thin film treatment of the second solder resist layer 2-2 of the non-exposed portion is performed, and thereafter, again The exposure is performed, and the development processing of the second solder resist 2-2 of the remaining non-exposed portion is performed. In the manufacturing method (5) of the wiring board, the same as the manufacturing methods (2) to (4) of the wiring board, it is possible to form a dam structure with the purpose of filling the gap between the electronic component and the wiring board with a dam. Two-stage construction of solder mask.

製程(A1)時，於電路基板1之第一面與第二面，形成有厚度不同之第一防焊層2-1。製程(C2)時，對第二面之第一防焊層2-1，實施於後製程之製程(D1)被顯影區域以外部分之曝光。 During the manufacturing process (A1), a first solder resist layer 2-1 having a different thickness is formed on the first surface and the second surface of the circuit substrate 1. During the manufacturing process (C2), the first solder resist layer 2-1 on the second side is exposed to a portion other than the developed area in the manufacturing process (D1) of the subsequent manufacturing process.

製程(B)時，於第一面，以薄膜化處理液實施使非曝光部之第一防焊層2-1成為連結墊3之厚度以下為止之薄膜化，來使所有的連結墊3之一部分露出。製程(B)時，第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而，因為第二面之連結墊4上的第一防焊層2- 1比第一面之連結墊3上的第一防焊層2-1更厚，連結墊4上殘留著第一防焊層2-1之殘渣。 During the manufacturing process (B), a thin film is used to thin the first solder resist layer 2-1 of the non-exposed part to a thickness of the bonding pad 3 or less on the first surface to make all the bonding pads 3 thin. Part of it is exposed. In the process (B), the first solder resist 2-1 of the non-exposed portion on the second surface is also thinned. However, because the first solder resist layer 2 on the bonding pad 4 on the second side is 2- 1 is thicker than the first solder resist 2-1 on the connection pad 3 on the first side, and the residue of the first solder resist 2-1 remains on the connection pad 4.

製程(A2)時，於完成至製程(C3)為止之電路基板之第一面的第一防焊層2-1上，形成第二防焊層2-2。 In the process (A2), a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit substrate up to the process (C3).

製程(C6)時，對第一面之第二防焊層2-2，實施於後製程之製程(B3)被薄膜化區域以外部分之曝光。 During the manufacturing process (C6), the second solder resist layer 2-2 on the first side is exposed to a part other than the thinned area in the manufacturing process (B3) of the subsequent manufacturing process.

製程(B3)時，於第一面，在連結墊3未露出之範圍，以薄膜化處理液實施非曝光部之第二防焊層2-2的薄膜化。製程(B3)時，第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而，有時連結墊4上殘留著第一防焊層2-1之殘渣。 During the manufacturing process (B3), on the first surface, the second solder resist layer 2-2 of the non-exposed portion is formed into a thin film by a thin film treatment liquid in a range where the connection pad 3 is not exposed. In the process (B3), the first solder resist layer 2-1 of the non-exposed portion on the second surface is also thinned. However, the residue of the first solder resist 2-1 may remain on the connection pad 4 in some cases.

製程(C7)時，對第一面之第二防焊層2-2，實施於後製程之製程(D1)被顯影區域以外部分之曝光。 During the manufacturing process (C7), the second solder resist layer 2-2 on the first side is exposed to a part other than the developed area in the manufacturing process (D1) of the subsequent manufacturing process.

製程(D1)時，以顯影液除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1，使連結墊3之一部分再度露出，同時，使連結墊4之一部分露出。藉由製程(D1)，殘留於連結墊4上之第一防焊層2-1的殘渣被除去。配載電子構件之配線基板時，將該製程(D1)所露出之連結墊3當做電子構件連結用連結墊3來使用，將連結墊4當做外部連結用連結墊4 來使用。 During the manufacturing process (D1), the second solder resist layer 2-2 of the non-exposed part on the first surface and the first solder resist layer 2-1 of the non-exposed part on the second surface are removed with a developing solution to make a part of the connection pad 3 When exposed again, a part of the connection pad 4 is exposed. By the process (D1), the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. When placing a wiring board for electronic components, use the bonding pad 3 exposed in this process (D1) as the bonding pad 3 for the connection of electronic components, and use the bonding pad 4 as the bonding pad 4 for external connection. To use.

配線基板的製造方法(5)時，可以將製程(C7)之曝光區域變化成任意形狀，藉由曝光區域之變更，例如，可以製作第12圖所示之剖面形狀的配線基板。第12之g圖時，於第一面之連結墊3間，形成有第二防焊層2-2之凸部。第12之h圖時，交互並列著從第一防焊層2-1露出之連結墊3、及為第一防焊層2-1及第二防焊層2-2所覆蓋之導體配線7。 In the method (5) for manufacturing a wiring board, the exposed area in the process (C7) can be changed to an arbitrary shape. By changing the exposed area, for example, a wiring board with a cross-sectional shape as shown in FIG. 12 can be produced. In FIG. 12g, a convex portion of the second solder resist layer 2-2 is formed between the connection pads 3 on the first surface. In FIG. 12 h, the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 are alternately arranged in parallel. .

本發明之電路基板1，具有絕緣層8、及形成於絕緣層8表面之連結墊3、4。於絕緣層8表面，形成有導體配線7，連結墊3、4係導體配線7之一部分。本發明之配線基板，於電路基板1之兩表面具有防焊層2，連結墊3、4之一部分從防焊層2露出。配載電子構件之配線基板時，於表面具有電子構件連結用連結墊3，於背面具有外部連結用連結墊4。表面之電子構件連結用連結墊3用以接合電子構件，背面之外部連結用連結墊4則用以接合外部電氣基板之導體配線。 The circuit board 1 of the present invention includes an insulating layer 8 and connecting pads 3 and 4 formed on a surface of the insulating layer 8. On the surface of the insulating layer 8, a conductor wiring 7 is formed, and a part of the connection pads 3 and 4 based on the conductor wiring 7 is formed. The wiring substrate of the present invention has a solder resist layer 2 on both surfaces of the circuit substrate 1, and a part of the connection pads 3 and 4 is exposed from the solder resist layer 2. When the wiring board on which the electronic component is placed is provided, the connecting pad 3 for connecting electronic components is provided on the front surface, and the connecting pad 4 for external connection is provided on the rear surface. The connection pads 3 for connecting electronic components on the front surface are used for bonding electronic components, and the connection pads 4 for external connection on the rear surface are used for bonding conductor wiring of external electrical substrates.

本發明之電路基板，例如，係於配設著導體配線之絕緣基板，交互疊層增建用絕緣層及導體配線來製作。第13A、B圖，係於配設著導體配線之絕緣基板交互疊層著增建用絕緣層及導體配線所製作之電路基板一例的概略剖面圖。第4~8圖係本發明之配線基板的製造方法一例的剖面製程圖，在依據本發明所製造之配線基板一例之概略剖面圖的第9~12圖中，記載著具有一層之絕緣層 8且具有形成於絕緣層8之兩表面之導體配線7的電路基板1，然而，使用於本發明之配線基板的製造方法之電路基板1，如第13A、B圖所示，係於配設有導體配線之絕緣基板交互疊層著增建用絕緣層及導體配線來製作，包含於兩表面具有絕緣層8、及形成於絕緣層8表面之導體配線7的電路基板1在內。絕緣基板，例如，由使玻璃布含浸有雙馬來醯亞胺-三氮雜苯樹脂或環氧樹脂等之熱硬化性樹脂的電氣絕緣材料等所構成之樹脂製基板。增建用絕緣層，例如，與絕緣基板相同之使玻璃布含浸有熱硬化性樹脂之電氣絕緣材料、或使氧化矽等無機填料分散於環氧樹脂等熱硬化性樹脂之電氣絕緣材料等。導體配線，例如，係以消去法、半加法、加法等來形成。消去法時，例如，於絕緣層上形成銅層後，形成抗蝕層，實施曝光、顯影、蝕刻、去除光阻，來形成導體配線。半加法時，於絕緣層表面，以無電解銅電鍍來配設電解銅電鍍用之基底金屬層。其次，形成具有對應導體配線之開口的電鍍抗蝕層，而於因電解銅電鍍而露出之基底金屬層的表面，形成電解銅電鍍層。其後，剝離電鍍抗蝕層，以閃蝕除去露出之基底金屬層，即可形成導體配線。 The circuit board of the present invention is produced by, for example, an insulating substrate provided with a conductor wiring, and alternately stacking additional insulation layers and conductor wiring. Figures 13A and B are schematic cross-sectional views of an example of a circuit board produced by alternately stacking an extension insulating layer and a conductor wiring on an insulating substrate provided with conductor wiring. Figures 4 to 8 are cross-sectional process drawings showing an example of a method for manufacturing a wiring substrate according to the present invention. Figures 9 to 12 of a schematic cross-sectional view of an example of a wiring substrate manufactured according to the present invention include an insulating layer. 8 and a circuit board 1 having conductor wirings 7 formed on both surfaces of the insulating layer 8. However, as shown in FIGS. 13A and B, the circuit board 1 used in the manufacturing method of the wiring board of the present invention is arranged The insulating substrate with conductor wiring is produced by alternately stacking additional insulation layers and conductor wiring, and includes a circuit substrate 1 having an insulating layer 8 on both surfaces and a conductor wiring 7 formed on the surface of the insulating layer 8. The insulating substrate is, for example, a resin substrate made of an electrical insulating material in which a glass cloth is impregnated with a thermosetting resin such as bismaleimide-triazine resin or epoxy resin. The insulating layer for the extension is, for example, an electric insulating material in which a glass cloth is impregnated with a thermosetting resin, or an electric insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin, as in an insulating substrate. The conductor wiring is formed by, for example, an elimination method, a semi-addition method, an addition method, or the like. In the erasing method, for example, a copper layer is formed on an insulating layer, a resist layer is formed, and then exposed, developed, etched, and photoresist is removed to form a conductor wiring. In the semi-additive process, a base metal layer for electrolytic copper plating is provided on the surface of the insulating layer by electroless copper plating. Next, a plating resist having an opening corresponding to the conductor wiring is formed, and an electrolytic copper plating layer is formed on the surface of the base metal layer exposed by electrolytic copper plating. Thereafter, the plating resist is peeled off, and the exposed base metal layer is removed by flash etching to form a conductor wiring.

配載電子構件之配線基板時，配線基板表面之連結墊，係用以連結電子構件之連結用墊。電子構件，介由該連結墊與焊劑凸塊來電氣連結，被覆晶組裝於配線基板。為了提高防焊層之黏著性，也可進行連結墊表面之粗面化處理、或耦合劑處理。配線基板背面之連結墊，係以外部連結為目的的連結用墊。介由焊劑凸塊，將該連結墊與主機板等外部電氣基板之導體配線進行電氣連結，來覆晶組裝於主機板。 When a wiring board on which an electronic component is placed is placed, the connection pad on the surface of the wiring substrate is a connection pad for connecting the electronic component. The electronic component is electrically connected to the solder bump via the connection pad, and the cover wafer is assembled on the wiring substrate. In order to improve the adhesion of the solder resist layer, a roughening treatment on the surface of the connection pad or a coupling agent treatment may be performed. Connection pads on the back of the wiring board Linking pad for external linking purposes. This connection pad is electrically connected to the conductor wiring of an external electrical substrate such as a main board via a solder bump to be flip-chip assembled on the main board.

本發明之防焊劑，可以使用鹼性顯影型防焊劑。此外，1液性、2液性的任一液狀防焊劑皆可，也可以為乾膜光阻。防焊劑，例如，含有鹼溶性樹脂、單官能壓克力單體、多官能壓克力單體、光起始劑、環氧樹脂、無機填料等。 As the solder resist of the present invention, an alkaline developing type solder resist can be used. In addition, either one-liquid or two-liquid solder resist may be used, and a dry film photoresist may be used. The solder resist contains, for example, an alkali-soluble resin, a monofunctional acrylic monomer, a polyfunctional acrylic monomer, a photoinitiator, an epoxy resin, an inorganic filler, and the like.

鹼溶性樹脂，例如，具有光硬化性及熱硬化性之兩方特性的鹼溶性樹脂，例如，對附加有丙烯酸之酚醛型環氧樹脂而環氧壓克力化樹脂的2級羥基附加酸酐的樹脂。多官能壓克力單體，例如，三羥甲基丙烷三丙烯酸酯(Trimethylol Propane Triacrylate)、二新戊四醇聚丙烯酸酯(Di-pentaerythritol Polyacrylate)、季戊四醇三丙烯酸酯(Pentaerythritol Triacrylate)等。光起始劑，例如，2-甲基-1-(4-甲基苯硫基)-2-瑪啉基正丙醇-1-酮(2-Methyl-1-(4-Methylthiophenyl)-2-Morpholinopropan-1-one)等。環氧樹脂，當做硬化劑來使用。以使其與鹼溶性樹脂之羧酸產生反應來進行架橋，謀求提高耐熱性及耐藥性之特性，然而，因為羧酸與環氧基在常溫也會產生反應，保存安定性差，鹼性顯影型防焊劑，一般都採用在使用前進行混合之2液性形態。無機填料，例如，滑石、矽石、硫酸鋇、氧化鈦、氧化鋅等。 Alkali-soluble resins, for example, alkali-soluble resins having both photo-hardening properties and thermo-hardening properties, for example, the addition of acid anhydride to the secondary hydroxyl groups of epoxy acrylic resins and phenolic epoxy resins Resin. Polyfunctional acrylic monomers, such as Trimethylol Propane Triacrylate, Di-pentaerythritol Polyacrylate, Pentaerythritol Triacrylate, and the like. Photoinitiators, for example, 2-Methyl-1- (4-methylphenylthio) -2-maolinyl-n-propanol-1-one (2-Methyl-1- (4-Methylthiophenyl) -2 -Morpholinopropan-1-one) and so on. Epoxy resin is used as a hardener. It is bridged by reacting with the carboxylic acid of alkali-soluble resin to improve heat resistance and chemical resistance. However, because carboxylic acid and epoxy group also react at normal temperature, it has poor storage stability and alkaline development. Type solder resist generally adopts a two-liquid form that is mixed before use. Inorganic fillers, for example, talc, silica, barium sulfate, titanium oxide, zinc oxide, and the like.

防焊層，在電路基板之兩表面，係以覆蓋全面之方式來形成。防焊層之形成上，例如，液狀防焊劑的話，可以使用網版印刷法、輥塗法、噴霧法、浸漬法、幕塗法、棒塗法、氣刀法、熱熔法、凹版塗佈法、毛刷塗佈法、套版印刷法。此外，膜狀防焊劑的話，使用疊合法及真空疊合法。 Solder mask on both surfaces of the circuit board Surface way to form. For the formation of the solder resist layer, for example, the liquid solder resist can be screen printing method, roll coating method, spray method, dipping method, curtain coating method, bar coating method, air knife method, hot melt method, gravure coating. Cloth method, brush coating method, offset printing method. In the case of a film-like solder resist, a stacking method and a vacuum stacking method are used.

以配線基板的製造方法(1)及(2)之製程(A)所形成的防焊層2、及以配線基板的製造方法(3)~(5)之製程(A1)所形成的第一防焊層2-1，在電路基板之兩表面的厚度不同，厚度較薄之一方為「第一面」，厚度較厚之一方為「第二面」。於電路基板之兩表面形成防焊層時，一般係對兩表面設定相同條件。其係因為防焊劑具有熱硬化性。液狀防焊劑時，因為在塗佈後必須實施以去溶劑為目的的加熱乾燥，各表面之塗佈量不同的話，就必須依各表面變更乾燥條件，然而，其時，又必須設定不會過度熱硬化之條件。此外，乾膜光阻時，因為疊合時必須加熱，各表面若使用厚度不同之乾膜光阻的話，就必須依各表面變更疊合時的加熱條件，然而，其時，又必須設定不會過度熱硬化之條件。如上所示，不改變各表面之防焊層厚度、加熱乾燥條件等，而採用兩表面之防焊層種類、厚度、加熱乾燥條件等相同之條件，可以使作業製程較為簡單而較佳。 The solder resist layer 2 formed by the manufacturing process (A) of the wiring substrate manufacturing methods (1) and (2), and the first formed by the manufacturing process (A1) of the wiring substrate manufacturing methods (3) to (5). The thickness of the solder mask layer 2-1 on the two surfaces of the circuit board is different. The thinner one is the “first side”, and the thicker one is the “second side”. When a solder resist layer is formed on both surfaces of a circuit substrate, the same conditions are generally set on both surfaces. This is because the solder resist is thermosetting. In the case of a liquid solder resist, it is necessary to perform heating and drying for the purpose of removing the solvent after coating. If the coating amount of each surface is different, the drying conditions must be changed for each surface. However, at this time, it is necessary to set Conditions for excessive thermal hardening. In addition, in the case of dry film photoresist, because the film must be heated during lamination, if the dry film photoresist with different thickness is used on each surface, the heating conditions during lamination must be changed according to each surface. Conditions that can cause excessive thermal hardening. As shown above, without changing the thickness, heat-drying conditions, etc. of the solder mask on each surface, using the same conditions, such as the type, thickness, and heat-drying conditions of the solder mask on both surfaces, can make the working process simpler and better.

於電路基板之兩表面，以相同條件形成防焊層時，防焊層之厚度，隨著包含各面之連結墊在內之周圍的導體配線密度而變化。例如，於配載電子構件之配線基板，背面之外部連結用連結墊配列成區域陣列型時，相較於表面之包含電子構件連結用連結墊在內之周圍的導體配線密度，背面之包含外部連結用連結墊在內之周圍的導體配線密度較大。結果，背面之外部連結用連結墊上的防焊層厚度，比表面之電子構件連結用連結墊上的防焊層厚度更厚。此時，表面為第一面，背面為第二面。 When a solder resist layer is formed on both surfaces of a circuit board under the same conditions, the thickness of the solder resist layer varies with the density of the conductor wiring around the connection pads on each side. For example, in the wiring base for electronic components When the external connection pads on the board and the rear side are arranged in the area array type, compared with the conductor wiring density around the surface including the connection pads for electronic component connection, The conductor wiring density is high. As a result, the thickness of the solder resist layer on the back connection pad for external connection is thicker than the thickness of the solder resist layer on the front connection pad for electronic component connection. At this time, the front surface is the first surface and the rear surface is the second surface.

本發明之防焊層被薄膜化的製程，係包含：以薄膜化處理液進行非曝光部之防焊層成份之膠束化的膠束化處理(薄膜化處理)、及以膠束除去液除去膠束之膠束除去處理在內的製程。此外，也可以包含：以水洗來清洗未除去之膠束、殘存薄膜化處理液、及膠束除去液的水洗處理、及除去水洗水之乾燥處理在內。 The process for thinning the solder resist layer of the present invention includes a micellization process (thinning process) for micellizing the components of the solder resist layer of the non-exposed portion with a thin film treatment liquid, and a micellar removal liquid. A process that includes micellar removal, including micellar removal. In addition, washing with water to wash the unremoved micelles, the remaining thin film-forming treatment solution, the washing treatment with the micelle removal solution, and the drying treatment with the washing water removed may be included.

薄膜化處理(膠束化處理)，係指以薄膜化處理液實施非曝光部之防焊層成份的膠束化，來使該膠束不溶於薄膜化處理液的處理。 The thin film treatment (micellarization treatment) refers to a treatment in which a soldering layer component of a non-exposed portion is micellized with a thinning treatment liquid to make the micelle insoluble in the thinning treatment liquid.

本發明之薄膜化處理液，可以使用鹼性水溶液。可以做為薄膜化處理液使用之鹼性水溶液，例如，鹼金屬矽酸鹽(Alkali Metal Silicate)、鹼金屬氫氧化物(Alkali Metal Hydroxide)、鹼金屬磷酸鹽(Alkali Metal Phosphate)、鹼金屬碳酸鹽(Alkali Metal Carbonate)、銨磷酸鹽、銨碳酸鹽等之無機鹼性化合物的水溶液；單乙醇胺、二乙醇胺、三乙醇胺、甲胺、二甲胺、乙胺、二乙胺、三乙胺、環己胺、四甲基氫氧化銨(Tetramethylammonium Hydroxide、TMAH)、四乙基氫氧化銨、三甲基-2-羥乙基氫氧化氨(膽鹼、Choline)等之有機鹼性化合物的水溶液。鹼金屬，例如，鋰、鈉、鉀等。上述無機鹼性化合物及有機鹼性化合物，可以單獨使用，也可以複數組合來使用。也可以使用無機鹼性化合物與有機鹼性化合物之組合。 As the film-forming treatment liquid of the present invention, an alkaline aqueous solution can be used. Can be used as an alkaline aqueous solution for thin film treatment liquids, for example, Alkali Metal Silicate, Alkali Metal Hydroxide, Alkali Metal Phosphate, Alkali Metal Carbonate Aqueous solutions of inorganic alkaline compounds such as salts (Alkali Metal Carbonate), ammonium phosphate, ammonium carbonate, etc .; monoethanolamine, diethanolamine, triethanolamine, methylamine, dimethylamine, ethylamine, diethylamine, triethylamine, Cyclohexylamine, Tetramethylammonium Hydroxide (TMAH), Tetraethylhydrogen An aqueous solution of organic basic compounds such as ammonium oxide, trimethyl-2-hydroxyethyl ammonium hydroxide (choline, Choline) and the like. Alkali metals, for example, lithium, sodium, potassium, and the like. These inorganic basic compounds and organic basic compounds may be used alone or in combination. A combination of an inorganic basic compound and an organic basic compound can also be used.

此外，為了使防焊層表面更均一地薄膜化，也可以於薄膜化處理液添加硫酸鹽、亞硫酸鹽。硫酸鹽或亞硫酸鹽，例如，鋰、鈉或鉀等之鹼金屬硫酸鹽或亞硫酸鹽、鎂、鈣等之鹼土類金屬硫酸鹽或亞硫酸鹽。 In addition, in order to make the surface of the solder resist layer thinner, a sulfate or a sulfite may be added to the thinning treatment liquid. Sulfates or sulfites, for example, alkali metal sulfates such as lithium, sodium, or potassium, or alkaline earth metal sulfates or sulfites, such as sulfite, magnesium, and calcium.

薄膜化處理液，於該等中，又以含有從鹼金屬碳酸鹽、鹼金屬磷酸鹽、鹼金屬氫氧化物、鹼金屬矽酸鹽所選取之無機鹼性化合物、及從TMAH(四甲基氫氧化銨)、膽鹼所選取之有機鹼性化合物當中之任1種，且該無機鹼性化合物及有機鹼性化合物之含有量為3~25質量%的薄膜化處理液，因為可以使表面更均一地薄膜化而更適合使用。未滿3質量%時，有時薄膜化處理容易發生不均。此外，超過25質量%的話，有時容易發生無機鹼性化合物析出，而使液之時效安定性、作業性變差。鹼性化合物之含有量為5~20質量%更佳，7~15質量%最好。薄膜化處理液之pH，以10以上為佳。此外，也可以適度添加界面活性劑、消泡劑、溶劑等。 The thin film-forming treatment liquid contains inorganic basic compounds selected from alkali metal carbonates, alkali metal phosphates, alkali metal hydroxides, and alkali metal silicates, and from TMAH (tetramethyl) Ammonium hydroxide), any of the organic basic compounds selected from choline, and the inorganic alkaline compound and the organic basic compound contain 3 to 25% by mass of the thin film treatment liquid, because the surface can be made The film is more uniform and more suitable for use. If it is less than 3% by mass, unevenness may easily occur in the thin film formation process. In addition, if it exceeds 25% by mass, precipitation of an inorganic basic compound is likely to occur, which may deteriorate the stability and workability of the liquid. The content of the basic compound is more preferably 5 to 20% by mass, and most preferably 7 to 15% by mass. The pH of the film-forming treatment liquid is preferably 10 or more. In addition, a surfactant, a defoaming agent, a solvent, and the like may be appropriately added.

防焊層之薄膜化時，不溶於防焊層中所含有之薄膜化處理液之無機填料的存在不能忽視。無機填料之尺寸隨著其種類而不同，具有從被稱為奈米填料之超微米級至較大之數十微米為止之某種程度的粒度分布，以30~70質量%之含有量存在於層中。薄膜化，在鹼性化合物浸透至防焊層後，於膠束除去過程進行防焊層成份之膠束化，然而，因為不溶性無機填料的存在，鹼性化合物之浸透獲得抑制，而使薄膜化速度變慢。 When the solder resist is formed into a thin film, the presence of an inorganic filler which is insoluble in the thin film-forming treatment solution contained in the solder resist cannot be ignored. The size of the inorganic filler varies with its type, from ultra-micron A degree of particle size distribution up to a few tens of micrometers exists in the layer with a content of 30 to 70% by mass. Thin film formation. After the basic compound penetrates into the solder resist layer, the micellization of the solder resist component is performed during the micelle removal process. However, the penetration of the alkaline compound is suppressed due to the presence of the insoluble inorganic filler, and the thin film is formed. Slower.

針對此種無機填料所導致之鹼性化合物的浸透阻礙，只要使薄膜化處理液之pH成為12.5以上即可，13.0以上更佳。薄膜化處理液之pH愈高，則鹼性化合物浸透時之防焊層的膨潤愈大，而不易受到無機填料所導致之浸透阻礙的影響。 In order to prevent the permeation of the basic compound caused by such an inorganic filler, the pH of the thin film-forming treatment liquid may be 12.5 or more, and more preferably 13.0 or more. The higher the pH of the thin film-forming treatment solution, the larger the swelling of the solder resist layer when the alkaline compound penetrates, and it is less likely to be affected by the impediment of penetration caused by the inorganic filler.

於本發明，以薄膜化使第一面之連結墊的一部分露出時，該露出之連結墊，可以當做電子構件連結用連結墊來使用。通常，連結墊表面被粗面化，利用其錨定效果來提高連結墊與防焊層之黏著性，而可維持長時間之高絕緣信賴性。傳統之防焊圖案形成上，除去防焊層來使連結墊表面露出時，一般係將分散能力優良之低濃度碳酸鈉水溶液當做顯影液來使用，於連結墊表面幾乎不會發生防焊層之殘渣。然而，使用低濃度之碳酸鈉水溶液來實施防焊層之薄膜化的話，無法得到面內均一之薄膜化，而發生面內不均。 In the present invention, when a part of the connection pad on the first surface is exposed in a thin film, the exposed connection pad can be used as a connection pad for connecting electronic components. Generally, the surface of the connection pad is roughened, and the anchoring effect is used to improve the adhesion between the connection pad and the solder resist, and it can maintain high insulation reliability for a long time. In the traditional solder resist pattern formation, when the solder resist layer is removed to expose the surface of the bonding pad, a low-concentration sodium carbonate aqueous solution with excellent dispersion ability is generally used as a developing solution, and the solder resist layer hardly occurs on the surface of the bonding pad Residue. However, when the thickness of the solder resist is reduced by using a low-concentration sodium carbonate aqueous solution, uniform in-plane thinning cannot be obtained, and in-plane unevenness occurs.

薄膜化處理液之溫度，以15~35℃為佳，最好為20~30℃。溫度太低的話，有時鹼性化合物對防焊層之浸透速度變慢，進行期望厚度之薄膜化需要較長的時間。另一方面，溫度太高的話，因為膠束除去過程與防焊層成份之膠束化同時進行，有時容易於面內發生膜厚不均，而應避免。 The temperature of the thin film treatment liquid is preferably 15 to 35 ° C, and most preferably 20 to 30 ° C. If the temperature is too low, the penetration rate of the alkaline compound into the solder resist layer may be slow, and it may take a long time to make the desired thickness into a thin film. On the other hand, if the temperature is too high, the micelle removal process and solder mask The micellization of the layer components proceeds at the same time, and it is easy to cause uneven film thickness in the surface, which should be avoided.

在利用薄膜化處理液之薄膜化處理時，可以採用浸漬處理、漿攪拌處理、噴霧處理、塗刷、刮削等方法，然而，以浸漬處理為佳。浸漬處理以外之處理方法，薄膜化處理液中容易發生氣泡，發生之氣泡在薄膜化中附著於防焊層表面，有時會有膜厚不均一的情形。使用噴霧處理等時，以不會發生氣泡之方式來儘量縮小噴霧壓為佳。 In the thinning treatment using the thinning treatment liquid, methods such as immersion treatment, slurry stirring treatment, spray treatment, painting, and scraping can be used. However, dipping treatment is preferred. In the treatment methods other than the dipping treatment, bubbles are liable to occur in the thinning treatment solution, and the generated bubbles may adhere to the surface of the solder resist layer during the thinning, and the thickness may be uneven. When using a spray treatment or the like, it is preferable to minimize the spray pressure so that air bubbles do not occur.

在以薄膜化處理液實施薄膜化處理後，實施除去不溶於薄膜化處理液之防焊層成份之膠束的膠束除去處理時，以膠束除去液之噴霧來一舉溶解除去膠束。 After performing the thinning treatment with the thinning treatment liquid, the micelle removal treatment for removing the micelles that are insoluble in the solder resist component of the thinning treatment liquid is performed by dissolving and removing the micelles with a spray of the micelle removal liquid.

膠束除去液，可以使用自來水、工業用水、純水等。此外，將含有從鹼金屬碳酸鹽、鹼金屬磷酸鹽、鹼金屬矽酸鹽所選取之無機鹼性化合物當中之任1種之pH5~10的水溶液當做膠束除去液來使用，容易使不溶於薄膜化處理液之防焊層成份再分散。膠束除去液之Ph為未滿5時，防焊層成份可能聚集而成為不溶性之泥渣，並附著於薄膜化之防焊層表面。另一方面，膠束除去液之pH超過10時，同時促進防焊層成份之膠束化與膠束除去過程，面內容易發生膜厚不均。此外，膠束除去液，可以使硫酸、磷酸、鹽酸等來調整pH。 As the micelle removal liquid, tap water, industrial water, and pure water can be used. In addition, an aqueous solution having a pH of 5 to 10 containing any one of the inorganic basic compounds selected from alkali metal carbonates, alkali metal phosphates, and alkali metal silicates is used as a micelle removal solution, which is easy to make insoluble The components of the solder mask layer of the thin film treatment liquid are re-dispersed. When the pH of the micelle removal solution is less than 5, the components of the solder resist layer may aggregate and become insoluble sludge, and adhere to the surface of the thinned solder resist layer. On the other hand, when the pH of the micelle removal liquid exceeds 10, the process of micellization and the removal of micelles of the solder resist component is promoted at the same time, and uneven film thickness is liable to occur in the plane. In addition, the micelle removal solution can adjust the pH by using sulfuric acid, phosphoric acid, hydrochloric acid, or the like.

針對膠束除去處理之噴霧條件來進行說明。噴霧條件(溫度、時間、噴霧壓)，係配合薄膜化處理之防焊層的溶解速度來進行適度調整。具體而言，處理溫度以10~50℃為佳，22~50℃更佳。水溶液之溫度為未滿10℃時，有時會發生防焊層成份的溶解不良，而容易使防焊層之殘渣殘留於粗面化之連結墊表面。另一方面，超過50℃的話，可能發生水溶液的蒸發或連續運轉之溫度管理的問題，而使裝置設計上受到限制，應避免。此外，噴霧壓以0.01~0.5MPa為佳，0.1~0.3MPa更佳。膠束除去液之供給流量，以防焊層每1cm²為0.030~1.0L/min為佳，0.050~1.0L/min更佳，最好為0.10~1.0L/min。供給流量在該範圍內的話，不溶解成份不會殘留於薄膜化後之防焊層表面，而可以在面內大致均一地除去膠束。防焊層每1cm²的供給流量為未滿0.030L/min時，有時防焊層之不溶解成份會殘留。另一方面，供給流量超過1.0L/min的話，供給所需要的泵等構件較為龐大，有時還要大規模的裝置。此外，超過1.0L/min之供給量時，防焊層成份之溶解除去效果沒有改變。 The spray conditions of the micelle removal process will be described. Spray conditions (temperature, time, spray pressure) are appropriately adjusted in accordance with the dissolution rate of the solder resist layer in a thin film process. Specifically, the processing temperature is preferably 10 to 50 ° C, and more preferably 22 to 50 ° C. When the temperature of the aqueous solution is less than 10 ° C, poor dissolution of the components of the solder resist layer may occur, and residues of the solder resist layer may easily remain on the surface of the roughened bonding pad. On the other hand, if it exceeds 50 ° C, the evaporation of the aqueous solution or the problem of temperature management during continuous operation may occur, which limits the design of the device and should be avoided. In addition, the spray pressure is preferably 0.01 to 0.5 MPa, and more preferably 0.1 to 0.3 MPa. The supply flow rate of the micelle removal liquid is preferably 0.030 to 1.0 L / min per 1 cm ² of the solder resist, more preferably 0.050 to 1.0 L / min, and most preferably 0.10 to 1.0 L / min. When the supply flow rate is within this range, insoluble components will not remain on the surface of the solder resist layer after being thinned, and micelles can be removed substantially uniformly within the surface. When the supply flow rate of the solder resist per 1 cm ² is less than 0.030 L / min, insoluble components of the solder resist may remain. On the other hand, if the supply flow rate exceeds 1.0 L / min, components such as a pump required for supply are relatively large, and sometimes a large-scale device is required. In addition, when the supply amount exceeds 1.0 L / min, the effect of dissolving and removing the solder resist component remains unchanged.

第一面所露出之連結墊3周圍之防焊層2與第一防焊層2-1的厚度、以及做為填膠堰塞用堤壩之一部分之防焊層2、第一防焊層2-1與第二防焊層2-2的厚度，由配線基板的製造方法(1)與(2)之製程(A)、及配線基板的製造方法(3)~(5)之製程(A1)與(A2)之形成於第一面的防焊層2、第一防焊層2-1與第二防焊層2-2之厚度、及配線基板的製造方法(1)、(3)~(5)之製程(B)、配線基板的製造方法(2)之製程(B1)與(B2)、配線基板的製造方法(5)之製程(B3)之第一面非曝光部之防焊層2、第一防焊層2-1與第二防焊層2-2的薄膜化量所決定。此外，本發明時，可以在0.01~500μm之範圍內，適度自由地實施薄膜化量調整。被薄膜化至連結墊之厚度以下為止之防焊層2、至從第一防焊層2-1表面所露出之連結墊3表面為止的高度，其後，可以對應必要之焊劑量來進行適度調整。此外，做為填膠堰塞用堤壩之一部分的防焊層2、第一防焊層2-1、及第二防焊層2-2之厚度，可以對應電子構件之大小、電子構件之連結端子的大小、以及充填於電子構件與配線基板之間的填膠量來進行適度調整。 The thickness of the solder mask layer 2 and the first solder mask layer 2-1 around the connection pad 3 exposed on the first surface, and the solder mask layer 2 and the first solder mask layer 2 as a part of the dam for filling the dam. -1 and the thickness of the second solder resist layer 2-2 are determined by the manufacturing process (A) of the wiring board (1) and (2), and the manufacturing process (3) to (5) of the wiring board (A1). ) And (A2), the thickness of the solder resist layer 2 formed on the first surface, the thickness of the first solder resist layer 2-1 and the second solder resist layer 2-2, and the manufacturing method of the wiring board (1), (3) ~ (5) of process (B), wiring board manufacturing method (2) Processes (B1) and (B2), the process (B3) of the manufacturing method (5) of the wiring board, the first surface of the non-exposed portion, the solder mask layer 2, the first solder mask layer 2-1, and the second solder mask layer 2 -2 film thickness. In addition, in the present invention, the amount of thinning can be adjusted appropriately and freely within a range of 0.01 to 500 μm. The thickness of the solder resist layer 2 until the thickness of the bonding pad is less than the thickness of the bonding pad. The height up to the surface of the bonding pad 3 exposed from the surface of the first solder resist layer 2-1 can be appropriately adjusted according to the necessary amount of solder. Adjustment. In addition, the thickness of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2, which are part of the dam for filling the dam, can correspond to the size of the electronic component and the connection of the electronic component. The size of the terminals and the amount of adhesive filled between the electronic component and the wiring board are appropriately adjusted.

配線基板的製造方法(6)，在配線基板的製造方法(1)~(4)之製程(C1)前，實施製程(C2)。此外，配線基板的製造方法(7)，係同時實施配線基板的製造方法(1)~(4)的製程(C1)及製程(C2)。如上所示，配線基板的製造方法(1)~(4)時，可以更替製程(C1)與製程(C2)之順序，也可以同時實施製程(C1)及製程(C2)。 The manufacturing method (6) of the wiring board is carried out before the manufacturing process (C1) of the manufacturing methods (1) to (4) of the wiring board. In addition, the manufacturing method (7) of the wiring board is a process (C1) and a manufacturing process (C2) that simultaneously implement the manufacturing methods (1) to (4) of the wiring board. As shown above, in the manufacturing methods (1) to (4) of the wiring board, the order of the process (C1) and the process (C2) may be changed, or the process (C1) and the process (C2) may be performed simultaneously.

配線基板的製造方法(1)之製程(C1)時，係對第一面之防焊層2，選擇性地實施後製程之製程(B)所薄膜化之區域以外部分的曝光。配線基板的製造方法(2)之製程(C1)時，係對第一面之防焊層2，選擇性地實施後製程之製程(B1)所薄膜化之區域以外部分的曝光。配線基板的製造方法(3)及(4)之製程(C1) 時，係對第一面之第一防焊層2-1，選擇性地實施後製程之製程(B)所薄膜化之區域以外部分的曝光。配線基板的製造方法(2)之製程(C4)時，係對第一面之防焊層2，選擇性地實施後製程之製程(B2)所薄膜化之區域以外部分的曝光。配線基板的製造方法(3)之製程(C6)及配線基板的製造方法(5)之製程(C7)時，係對第一面之第二防焊層2-2，選擇性地實施後製程之製程(D1)所顯影之區域以外部分的曝光。配線基板的製造方法(4)之製程(C6)時，係對第一面之第二防焊層2-2，選擇性地實施後製程之製程(D2)所顯影之區域以外部分的曝光。配線基板的製造方法(5)之製程(C6)時，係對第一面之第二防焊層2-2，實施於後製程之製程(B3)被薄膜化區域以外部分之曝光。被曝光之防焊劑，產生光聚合，防焊層2、第一防焊層2-1、及第二防焊層2-2產生硬化。在第4-1圖~第8-3圖中，係介由光罩5進行活性光線6之曝光，然而，也可以直接描繪方式來實施。曝光方式，例如，可以為以氙燈、高壓水銀燈、低壓水銀燈、超高壓水銀燈、UV螢光燈做為光源之反射影像曝光方式、及採用光罩之接觸曝光方式、近接方式、投射方式及雷射掃描曝光方式等。第一面之「被薄膜化區域」，例如，係連結墊上或包含連結墊之間在內之連結墊的周圍區域。更具體而言，係以配載電子構件為目的之安裝區域及其周圍。 In the manufacturing process (C1) of the manufacturing method (1) of the wiring board, exposure to a portion other than the area thinned by the manufacturing process (B) of the post-process is performed on the first surface of the solder resist layer 2. In the manufacturing process (C1) of the manufacturing method (2) of the wiring board, the first part of the solder resist layer 2 is selectively exposed to a portion other than the area thinned by the post-process (B1). Process (C1) for manufacturing method (3) and (4) of wiring board At this time, the first solder resist 2-1 on the first side is selectively exposed to a portion other than the area thinned by the post-process (B). In the process (C4) of the manufacturing method (2) of the wiring substrate, the exposure of the portion other than the area thinned by the post-process (B2) to the solder mask layer 2 on the first side is selectively performed. When the manufacturing process (C6) of the wiring substrate manufacturing method (3) and the manufacturing process (C7) of the wiring substrate manufacturing method (5) are performed, the second solder resist layer 2-2 on the first side is selectively subjected to a post-process Exposure of parts other than the area developed by the manufacturing process (D1). In the process (C6) of the manufacturing method (4) of the wiring substrate, the second solder resist layer 2-2 on the first side is selectively exposed to a portion other than the area developed by the post-process (D2). In the process (C6) of the manufacturing method (5) of the wiring substrate, the second solder resist layer 2-2 on the first surface is exposed to a portion other than the thinned area in the process (B3) of the post-process. The exposed solder resist generates photopolymerization, and the solder resist 2, the first solder resist 2-1, and the second solder resist 2-2 are hardened. In FIGS. 4-1 to 8-3, the exposure of the active light 6 is performed through the mask 5. However, it can also be implemented by drawing directly. The exposure method can be, for example, a reflection image exposure method using a xenon lamp, a high-pressure mercury lamp, a low-pressure mercury lamp, an ultra-high pressure mercury lamp, or a UV fluorescent lamp as a light source, and a contact exposure method, a proximity method, a projection method, and a laser using a photomask. Scanning exposure method, etc. The "thin filmed area" on the first side is, for example, the area on the connection pad or the surrounding area of the connection pad including the connection pads. More specifically, it refers to the mounting area and its surroundings for the purpose of placing electronic components.

配線基板的製造方法(1)與(2)之製程 (C2)時，係對第二面之防焊層2，選擇性地實施後製程之製程(D)所顯影之區域以外部分的曝光。配線基板的製造方法(4)之製程(C2)時，係對第二面之第一防焊層2-1，選擇性地實施後製程之製程(D)所顯影之區域以外部分的曝光。配線基板的製造方法(3)與(5)之製程(C2)時，係對第二面之第一防焊層2-1，選擇性地實施後製程之製程(D1)所顯影之區域以外部分的曝光。被曝光之防焊劑，產生光聚合，防焊層2及第一防焊層2-1產生硬化。曝光方式，可以使用與上述配線基板的製造方法(1)之製程(C1)等相同的方式。第二面之「被顯影區域」，例如，係連結墊上或包含連結墊之間在內之連結墊的周圍區域。更具體而言，係以安裝外部電氣基板之導體配線為目的而使配置成區域陣列(Area array)型之連結墊的一部分露出之圓形開口部區域。 Manufacturing method of wiring board (1) and (2) In the case of (C2), the second side of the solder resist layer 2 is selectively exposed to a portion other than the area developed by the post-process (D). In the process (C2) of the manufacturing method (4) of the wiring substrate, the first solder resist layer 2-1 on the second side is selectively exposed to a portion other than the area developed by the post-process (D). In the process (C2) of the manufacturing method (3) and (5) of the wiring substrate, the first solder resist layer 2-1 on the second side is selectively implemented outside the area developed by the post-process (D1) Partial exposure. The exposed solder resist generates photopolymerization, and the solder resist 2 and the first solder resist 2-1 harden. For the exposure method, the same method as the manufacturing process (C1) of the manufacturing method (1) of the wiring board can be used. The "developed area" on the second side is, for example, the area on the connection pad or the surrounding area of the connection pad including the connection pads. More specifically, it is a circular opening area where a part of the connection pads arranged in an area array are exposed for the purpose of mounting the conductor wiring of an external electrical substrate.

配線基板的製造方法(1)之製程(C3)時，係對第一面之防焊層2，實施於製程(B)被薄膜化之區域部分的曝光。配線基板的製造方法(3)~(5)之製程(C3)時，係對第一面之第一防焊層2-1，實施於製程(B)被薄膜化之區域部分的曝光。配線基板的製造方法(2)之製程(C5)時，係對第一面之防焊層2，實施於製程(B2)被薄膜化之區域部分的曝光。曝光方式，可以使用與上述配線基板的製造方法(1)之製程(C1)等相同的方式。配線基板的製造方法(1)、(3)~(5)之製程(C3)及配線基板的製造方法(2)之製程(C5) 後，因為有非曝光部之防焊層2、第一防焊層2-1、第二防焊層2-2被顯影除去之製程(配線基板的製造方法(1)、(2)及(4)之製程(D)、配線基板的製造方法(3)及(5)之製程(D1)、以及配線基板的製造方法(4)之製程(D2))，而必須實施形成最終防焊層之區域的曝光，來使防焊劑產生光聚合。配線基板的製造方法(1)、(3)、(4)之製程(C3)之曝光部分，至少包含於製程(B)被薄膜化之區域在內，以包含製程(C1)所曝光之部分及製程(B)所薄膜化之區域的境界部在內為佳。此外，配線基板的製造方法(2)之製程(C5)的曝光部分，至少包含於製程(B2)被薄膜化之區域在內，以包含製程(C4)所曝光之部分及製程(B2)所薄膜化之區域的境界部在內為佳。 In the manufacturing process (C3) of the manufacturing method (1) of the wiring board, the solder mask layer 2 on the first surface is exposed to a part of the area where the manufacturing process (B) is thinned. In the process (C3) of the manufacturing method (3) to (5) of the wiring board, the first solder resist layer 2-1 on the first surface is exposed to the area where the process (B) is thinned. In the manufacturing process (C5) of the manufacturing method (2) of the wiring board, the first part of the solder resist layer 2 is exposed to the area where the manufacturing process (B2) is thinned. For the exposure method, the same method as the manufacturing process (C1) of the manufacturing method (1) of the wiring board can be used. Manufacturing process of wiring board (1), (3) to (5) (C3) and manufacturing process of wiring board (2) (C5) After that, there are processes in which the solder resist layer 2 of the non-exposed portion, the first solder resist layer 2-1, and the second solder resist layer 2-2 are developed and removed (the manufacturing method of the wiring board (1), (2), and ( 4) (D), wiring board manufacturing method (3) and (5) manufacturing process (D1), and wiring board manufacturing method (4) manufacturing process (D2)), and the final solder resist must be formed The exposed areas are exposed to photopolymerize the solder resist. The exposure part of the process (C3) of the manufacturing method (1), (3), and (4) of the wiring substrate is at least included in the area where the process (B) is thinned, and includes the part exposed by the process (C1) And the boundary part of the area thinned by the process (B) is preferable. In addition, the exposed part of the manufacturing process (C5) of the manufacturing method (2) of the wiring substrate is included at least in the area where the manufacturing process (B2) is thinned, and includes the exposed part of the manufacturing process (C4) and The boundary part of the thin film area is preferable.

配線基板的製造方法(1)~(4)之製程(C1)、配線基板的製造方法(1)、(3)~(5)之製程(C3)、配線基板的製造方法(1)~(5)之製程(C2)、配線基板的製造方法(2)之製程(C4)及(C5)、配線基板的製造方法(3)~(5)之製程(C6)、以及配線基板的製造方法(5)之製程(C7)的曝光量，可以對應防焊劑之感光度來適度決定。具體而言，配線基板的製造方法(1)、(3)~(5)之製程(B)、配線基板的製造方法(2)之製程(B1)與(B2)、以及配線基板的製造方法(5)之製程(B3)時，所使用之薄膜化處理液，或者，配線基板的製造方法 (1)、(2)、(4)之製程(D)、配線基板的製造方法(3)及(5)之製程(D1)、以及配線基板的製造方法(4)之製程(D2)時，只要對所使用之顯影液，防焊劑不會溶解或膨潤之程度，使防焊劑產生光聚合並硬化即可，通常為100~600mJ/cm²。 Manufacturing method (1) to (4) of the wiring board (C1), manufacturing method (1), (3) to (5) of the wiring board (C3), manufacturing method (1) to (1) of the wiring board 5) Process (C2), manufacturing method of wiring board (2) Manufacturing process (C4) and (C5), manufacturing method of wiring board (3) to (5) manufacturing process (C6), and manufacturing method of wiring board The exposure amount in the process (C7) of (5) can be appropriately determined according to the sensitivity of the solder resist. Specifically, the manufacturing method (1), (3) to (5) of the wiring board manufacturing process (B), the manufacturing processes (B1) and (B2) of the wiring board manufacturing method (2), and the manufacturing method of the wiring board (5) In the manufacturing process (B3), the thin-film processing solution used, or the manufacturing method (1), (2), (4) of the wiring board (D), the manufacturing method of the wiring board (3) In the process (D1) of (5) and the process (D2) of the manufacturing method of the wiring board (4), as long as the developer is used, the solder resist does not dissolve or swell, so that the solder resist is photopolymerized. It can be hardened, usually 100 ~ 600mJ / cm ² .

配線基板的製造方法(1)、(3)、(4)之製程(C3)、配線基板的製造方法(2)之製程(C4)與(C5)、配線基板的製造方法(5)之製程(C3)與製程(C7)的曝光，以在氧環境下之非接觸曝光方式來實施為佳。非接觸曝光方式，例如，於光罩與配線基板之間配設間隙而以非接觸方式來實施曝光之近接方式、投射方式、以及未使用光罩之直接描繪方式。在防焊層2、第一防焊層2-1、以及第二防焊層2-2上沒有支撐層膜的狀態下，實施氧環境下之非接觸曝光，各防焊層之表層附近(從防焊層表面之深度0~0.5μm程度)的光聚合，在氧的影響下受到妨礙而成為未硬化部分，只有離開表層之部位才會硬化。所以，藉由配線基板的製造方法(1)之製程(D)、配線基板的製造方法(2)之製程(B2)與(D)、配線基板的製造方法(3)之製程(D1)、配線基板的製造方法(4)之製程(D)與(D2)、配線基板的製造方法(5)之製程(D1)，除去表層附近之未硬化部分，而使防焊層2、第一防焊層2-1、以及第二防焊層2-2的表面被粗面化。位於配線基板表面之電子構件連結用連結墊周圍的防焊層表面被粗面化時，相較於平滑時，填膠之黏著性更為強固，結果，可以防止熱衝擊所導致之應力集中於電子構件與配線基板的連結部，而進一步提高連結信賴性。藉由氧環境下之非接觸方式曝光來實施防焊層2、第一防焊層2-1、以及第二防焊層2-2之表面的粗面化，可以提高填膠之黏著性，而得到高連結信賴性。提高填膠之黏著性上，防焊層之表面粗細度Ra以0.30μm以上、0.50μm以下為佳。表面粗細度Ra超過0.50μm的話，防焊強度降低，有時無法得到絕緣信賴性。表面粗細度Ra為算術平均表面粗細度。 Manufacturing process (1), (3), (4) of the wiring substrate manufacturing process (C3), manufacturing process (2) of the wiring substrate manufacturing process (C4) and (C5), manufacturing process of the wiring substrate manufacturing method (5) The exposure of (C3) and process (C7) is preferably performed by a non-contact exposure method in an oxygen environment. The non-contact exposure method includes, for example, a proximity method, a projection method, and a direct drawing method in which a gap is provided between the photomask and the wiring substrate to perform exposure in a non-contact manner. In the state where there is no support layer film on the solder mask layer 2, the first solder mask layer 2-1, and the second solder mask layer 2-2, a non-contact exposure under an oxygen environment is performed, and the vicinity of the surface layer of each solder mask layer ( The photopolymerization from the depth of the solder mask surface (about 0 to 0.5 μm) is hindered under the influence of oxygen and becomes an unhardened part, and only the part leaving the surface layer will harden. Therefore, by the manufacturing process (D) of the wiring substrate manufacturing method (1), the manufacturing process (B2) and (D) of the wiring substrate manufacturing method (2), the manufacturing process (D1) of the wiring substrate manufacturing method (3), The manufacturing process (D) and (D2) of the wiring substrate manufacturing method (4) and the manufacturing process (D1) of the wiring substrate manufacturing method (5) remove the unhardened portion near the surface layer, so that the solder resist 2 and the first resist The surfaces of the solder layer 2-1 and the second solder resist layer 2-2 are roughened. When the surface of the solder resist layer around the connection pad for connecting electronic components on the surface of the wiring board is roughened, compared with when smooth, The adhesiveness of the filler is stronger. As a result, it is possible to prevent stress caused by thermal shock from being concentrated on the connection portion between the electronic component and the wiring substrate, and further improve the connection reliability. Roughening the surface of the solder mask layer 2, the first solder mask layer 2-1, and the second solder mask layer 2-2 by non-contact exposure in an oxygen environment can improve the adhesiveness of the filler. And get high link reliability. In order to improve the adhesiveness of the filler, the surface roughness Ra of the solder resist is preferably 0.30 μm or more and 0.50 μm or less. When the surface roughness Ra exceeds 0.50 μm, the solder resist strength decreases, and insulation reliability may not be obtained in some cases. The surface roughness Ra is an arithmetic average surface roughness.

配線基板的製造方法(1)、(3)、(4)之製程(C3)、及配線基板的製造方法(2)之製程(C4)與(C5)的曝光量，以製程(C1)之曝光量的1倍以上、5倍以下為佳，最好為1.5倍以上、3倍以下。同樣的，配線基板的製造方法(5)之製程(C3)與製程(C7)的曝光量，以製程(C6)之曝光量的1倍以上、5倍以下為佳，最好為1.5倍以上、3倍以下。氧環境下之非接觸曝光時，藉由提供比防焊劑不會被溶解或膨潤之程度而可硬化之必要曝光量更多的曝光量，可以將防焊層表面之氧所導致之聚合妨礙抑制於最小。曝光量愈多，對聚合妨礙之抑制有其效果，然而，另一方面，曝光量太多的話，不但防焊劑之解析度惡化，曝光時間也會過長，故應避免。 The manufacturing process (C3) of the wiring board manufacturing method (1), (3), and (4), and the exposure amount of the manufacturing processes (C4) and (C5) of the wiring board manufacturing method (2). The exposure amount is preferably 1 time or more and 5 times or less, and more preferably 1.5 times or more and 3 times or less. Similarly, the exposure amount of the process (C3) and the process (C7) of the manufacturing method (5) of the wiring substrate is preferably 1 time or more and 5 times or less, and more preferably 1.5 times or more. 3 times or less. In non-contact exposure in an oxygen environment, by providing more exposure than necessary to prevent the solder resist from being dissolved or swelled, it is possible to suppress the polymerization hindered by oxygen on the surface of the solder resist. To the smallest. The larger the exposure amount, the more effective it is to suppress the inhibition of polymerization. On the other hand, if the exposure amount is too large, not only the resolution of the solder resist will deteriorate, but the exposure time will be too long, so it should be avoided.

配線基板的製造方法(1)、(3)~(5)之製程(B)、及配線基板的製造方法(2)之製程(B2) 時，於第一面，以薄膜化處理液實施使非曝光部之防焊層2、及第一防焊層2-1成為連結墊3之厚度以下為止的薄膜化，來使連結墊3之一部分露出。配線基板的製造方法(2)之製程(B1)、及配線基板的製造方法(5)之製程(B3)時，於第一面，在連結墊3未露出之範圍，以薄膜化處理液實施非曝光部之防焊層2、第二防焊層2-2的薄膜化。使用膜狀防焊劑來配設支撐層膜時，剝離支撐層膜後再執行薄膜化。 Manufacturing process of wiring board (1), manufacturing process (3) to (5) (B), manufacturing process of wiring board (2), manufacturing process (B2) At this time, on the first surface, a thin film is used to thin the solder resist layer 2 and the first solder resist layer 2-1 of the non-exposed portion to a thickness of the bonding pad 3 or less to make the bonding pad 3 thin. Part of it is exposed. In the process (B1) of the manufacturing method (2) of the wiring substrate and the process (B3) of the manufacturing method (5) of the wiring substrate, the first surface and the area not exposed by the connection pad 3 are implemented with a thin film treatment liquid. The thickness of the non-exposed portion of the solder resist layer 2 and the second solder resist layer 2-2 is reduced. When a support film is provided using a film-like solder resist, the support film is peeled and then thinned.

配線基板的製造方法(1)、(3)~(5)之製程(B)、及配線基板的製造方法(2)之製程(B2)時，以薄膜化後之防焊層2、及第一防焊層2-1的厚度成為與第一面所露出之連結墊3的厚度相同、或更薄為止來實施薄膜化。薄膜化後之防焊層2、及第一防焊層2-1的厚度太薄的話，露出之連結墊3之間的電氣絕緣不足，有時會發生無電解鎳/金電鍍之短路，或者，有時連結墊3之間會發生焊劑所導致的短路。所以、薄膜化後之防焊層2、及第一防焊層2-1的厚度，以連結墊3之厚度的3分之1以上為佳，3分之2以上更佳。 In the manufacturing method (1) of the wiring board, the manufacturing process (B) of (3) to (5), and the manufacturing process (B2) of the manufacturing method (2) of the wiring board, a thin film of the solder resist layer 2 and the first The thickness of one solder resist 2-1 is the same as or less than the thickness of the bonding pad 3 exposed on the first surface, and the thickness is reduced. If the thickness of the thinned solder resist layer 2 and the first solder resist layer 2-1 is too thin, the electrical insulation between the exposed bonding pads 3 is insufficient, and a short circuit of electroless nickel / gold plating may occur, or In some cases, a short circuit caused by solder may occur between the connection pads 3. Therefore, the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after being thinned is preferably more than one-third of the thickness of the connection pad 3, and more preferably two-thirds or more.

配線基板的製造方法(1)之製程(B)、及配線基板的製造方法(2)之製程(B1)與(B2)時，第一面之非曝光部的防焊層2被薄膜化，第二面之非曝光部的防焊層2也同時被薄膜化。在配線基板的製造方法(3)~(5)之製程(B)時，第一面之非曝光部的第一防焊層2-1被薄膜化，第二面之非曝光部的第一防焊層2- 1也同時被薄膜化。配線基板的製造方法(5)之製程(B3)時，第一面之非曝光部的第二防焊層2-2被薄膜化，第二面之非曝光部的第一防焊層2-1也同時被薄膜化。第二面之薄膜化量，因為第二面之非曝光部之防焊層2、及第一防焊層2-1的熱硬化狀態而有所不同，然而，於兩表面，以相同加熱條件來形成防焊層2、及第一防焊層2-1時，通常，第一面與第二面之非曝光部的防焊層2、及第一防焊層2-1，會同時被同量薄膜化。 In the manufacturing process (B) of the wiring substrate manufacturing method (1), and the manufacturing processes (B1) and (B2) of the wiring substrate manufacturing method (2), the solder resist layer 2 on the non-exposed part of the first surface is thinned. At the same time, the solder resist layer 2 of the non-exposed portion on the second surface is also thinned. In the manufacturing process (B) of the wiring substrate manufacturing method (3) to (5), the first solder resist layer 2-1 of the non-exposed portion on the first surface is thinned, and the first Solder mask 2- 1 is also thinned at the same time. In the process (B3) of the manufacturing method (5) of the wiring substrate, the second solder resist layer 2-2 of the non-exposed portion on the first surface is thinned, and the first solder resist layer 2- of the non-exposed portion on the second surface is thinned. 1 is also thinned at the same time. The amount of film formation on the second surface differs depending on the thermal hardening state of the solder mask layer 2 of the non-exposed portion of the second surface and the first solder mask layer 2-1. However, the same heating conditions are used on both surfaces. When the solder resist layer 2 and the first solder resist layer 2-1 are formed, generally, the solder resist layer 2 and the first solder resist layer 2-1 of the non-exposed portions of the first and second faces are simultaneously Same amount of film.

配線基板的製造方法(1)、(3)~(5)之製程(B)、配線基板的製造方法(2)之製程(B1)與(B2)、以及配線基板的製造方法(5)之製程(B3)時，薄膜化處理，以第一面朝上來實施為佳。薄膜化處理之處理方式，為了使薄膜化處理液中不易發生氣泡，浸漬處理係有效的方法。萬一，薄膜化處理液中發生氣泡時，氣泡在薄膜化處理液中浮上而附著於下面(第二面)之防焊層2、及第一防焊層2-1的表面。該氣泡的附著，有時會使第二面之薄膜化後的膜厚不均一。然而，在後製程之配線基板的製造方法(1)、(2)、(4)之製程(D)、配線基板的製造方法(3)及(5)之製程(D1)、以及配線基板的製造方法(4)之製程(D2)時，因為第二面之非曝光部的防焊層2、及第一防焊層2-1被顯影除去，最終不會出現膜厚不均的問題。 Wiring board manufacturing method (1), (3) to (5) manufacturing process (B), wiring board manufacturing method (2) manufacturing process (B1) and (B2), and wiring board manufacturing method (5) In the manufacturing process (B3), it is preferable that the thinning process is performed with the first side facing upward. The thinning treatment method is an effective method to prevent bubbles from forming in the thinning treatment liquid. In case of occurrence of air bubbles in the thin film-forming treatment liquid, the air bubbles float on the thin film-forming treatment liquid and adhere to the surface of the solder mask layer 2 (the second surface) and the first solder mask layer 2-1. The adhesion of the bubbles may cause the thickness of the second surface to become non-uniform. However, the manufacturing method (1), (2), (4) of the wiring substrate in the post-process (D), the manufacturing method (3) and (5) of the wiring substrate (D1), and the manufacturing method of the wiring substrate In the manufacturing process (D2) of the manufacturing method (4), since the solder resist layer 2 of the non-exposed portion on the second surface and the first solder resist layer 2-1 are developed and removed, the problem of uneven film thickness does not occur in the end.

配線基板的製造方法(1)及(2)之製程(D)時，以顯影來除去第二面之非曝光部的防焊層2。配線基板的製造方法(4)之製程(D)時，以顯影來除去第二面之非曝光部的第一防焊層2-1。配線基板的製造方法(3)及(5)之製程(D1)時，以顯影來除去第一面之非曝光部的第二防焊層2-2、及第二面之非曝光部的第一防焊層2-1。配線基板的製造方法(4)之製程(D2)時，以顯影來除去第一面之非曝光部的第二防焊層2-2。顯影方法，採用符合使用之防焊劑的顯影液，對電路基板之兩表面進行噴霧，除去各防焊層之不需要部分。顯影液，係使用稀薄之鹼性水溶液，一般而言，係使用0.3~3質量%之碳酸鈉水溶液或碳酸鉀水溶液。 In the process (D) of the manufacturing methods (1) and (2) of the wiring board, the solder resist layer 2 of the non-exposed portion on the second surface is removed by development. In the process (D) of the manufacturing method (4) of the wiring substrate, the first solder resist 2-1 of the non-exposed portion on the second surface is removed by development. In the process (D1) of the manufacturing method (3) and (5) of the wiring substrate, the second solder resist layer 2-2 of the non-exposed portion on the first surface and the second portion of the non-exposed portion on the second surface are removed by development. A solder mask 2-1. In the manufacturing process (D2) of the manufacturing method (4) of the wiring board, the second solder resist 2-2 of the non-exposed part of the first surface is removed by development. For the developing method, a developing solution conforming to the used solder resist is used to spray both surfaces of the circuit substrate to remove unnecessary portions of each solder resist layer. As the developing solution, a thin alkaline aqueous solution is used, and in general, a sodium carbonate aqueous solution or a potassium carbonate aqueous solution of 0.3 to 3% by mass is used.

[實施例] [Example]

以下，利用實施例來針對本發明進行更詳細的說明，然而，本發明並未受限於該實施例。 Hereinafter, the present invention will be described in more detail using an embodiment. However, the present invention is not limited to the embodiment.

實施例1~6，係第4-1圖及第4-2圖所示之配線基板的製造方法(1)的相關例。 Examples 1 to 6 are related examples of the manufacturing method (1) of the wiring substrate shown in FIGS. 4-1 and 4-2.

(實施例1) (Example 1) <製程(A)> <Process (A)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)側，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)側，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此，形成防焊層2。第一面之防焊層2時，從絕緣層8表面之厚度為30μm，電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面，相較於導體配線密度較大之第二面，防焊層2之厚度為較薄之8μm。 A circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm) with a conductor wiring 7 formed on both surfaces was produced by a semi-additive method. On the surface (first surface) side, there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back (second surface) side, a connection pad 4 serving as an external connection is formed. Use a circular conductor wiring with a diameter of 600 μm. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 25 μm was vacuum thermocompression bonded (lamination temperature 75 ° C, suction time 30 seconds) (Pressurizing time: 10 seconds) on both surfaces of the circuit board 1. Thereby, the solder resist layer 2 is formed. In the case of the solder resist layer 2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm, and the thickness on the connection pad 3 for electronic component connection is 15 μm. In the case of the solder resist layer 2 on the second side, the thickness from the surface of the insulating layer 8 is 38 μm, and the thickness on the external connection pad 4 is 23 μm. The thickness of the solder resist layer 2 is 8 μm thinner on the first surface where the conductor wiring density is smaller than the second surface where the conductor wiring density is larger.

<製程(C1)> <Process (C1)>

對第一面之防焊層2，使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 For the solder mask layer 2 on the first side, a photomask 5 irradiated with a pattern of active light 6 is used at a distance of 200 μm from the outer edge of the connection pad 3 of the plurality of electronic component connection pads with a contrast distance of 200 mJ / cm. ² Implement contact exposure.

<製程(C2)> <Process (C2)>

對第二面之防焊層2，於外部連結用連結墊4上配設直徑500μm之圓形開口部區域，利用對圓形開口部區域以外照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 A circular opening area with a diameter of 500 μm is arranged on the second-side solder resist layer 2 on the connection pad 4 for external connection, and a photomask 5 irradiated with a pattern of active light 6 outside the circular opening area is used for exposure. An amount of 200 mJ / cm ^{2 was used} for contact exposure.

<製程(B)> <Process (B)>

剝離第一面及第二面之防焊層2上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液50秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3之表面下5.0μm為止，實施平均20μm之防焊層2的薄膜化。以光學顯微鏡進行觀察，第一面之防焊層2表面沒有處理不均，而得到良好的面內均一性。另一方面，於第二面，平均20μm之防焊層2也被薄膜化，薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約3μm之防焊層2的殘渣。 After peeling off the supporting layer film on the solder resist layer 2 on the first and second sides, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as a thin film treatment solution with the first side facing upward, and The circuit board 1 is immersed in a thin film-forming treatment liquid for 50 seconds, and is then subjected to a micellization process (thinning process). Thereafter, a micellar removal treatment using a micellar removal solution (liquid temperature 25 ° C) is sprayed, a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed to make the solder resist 2 on the non-exposed part of the first surface The thickness of the solder resist layer 2 is reduced to an average of 20 μm until the thickness is 5.0 μm below the surface of the connection pad 3 for electronic component connection. Observation with an optical microscope showed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, on the second surface, the solder resist layer 2 with an average thickness of 20 μm is also thinned. Bubbles in the thin film treatment liquid adhere to the solder resist layer 2 on the non-exposed part of the second surface, and the film thickness is uneven . In addition, residues of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.

<製程(C3)> <Process (C3)>

對第一面之防焊層2，利用使活性光線6照射製程(B)所薄膜化之區域部分及從該薄膜化之區域境界部的200μm外側為止之區域之圖案的光罩5，以曝光量400mJ/cm²之氧環境下的非接觸曝光來實施曝光。 For the solder mask layer 2 on the first side, a photomask 5 with a pattern in which the active light 6 is irradiated to the portion of the filmed area in the process (B) and the area from 200 μm outside the boundary portion of the filmed area is exposed. Exposure was performed by non-contact exposure under an oxygen environment at an amount of 400 mJ / cm ² .

<製程(D)> <Process (D)>

利用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘之顯影，除去第二面之非曝光部的防焊層2。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.5μm為止，防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光，電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。 1% by mass sodium carbonate aqueous solution (liquid temperature 30 ° C, spray 0.15 MPa), development was performed for 30 seconds, and the solder resist 2 on the non-exposed portion of the second surface was removed. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the connection pads 3 for connecting electronic components on the first surface up to 5.5 μm below the surface of the connection pads 3 for connecting electronic components. By the non-contact exposure under the oxygen environment of the process (C3), the photopolymerization of the surface of the solder resist layer 2 between the bonding pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.5μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and the connection for adjacent electronic component connection was performed. Between the pads 3, a solder resist layer 2 having a thickness of 9.5 μm is filled. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度。使用超深度形狀測定顯微鏡(KEYENCE CORPORATION製、商品編號「VK-8500」)測定表面粗細度時，表面粗細度Ra為0.40μm。 Next, the surface roughness of the solder resist layer 2 between the connection pads 3 for connecting adjacent electronic components was measured. When the surface roughness was measured using an ultra-depth shape measuring microscope (manufactured by Keyence Corporation, product number "VK-8500"), the surface roughness Ra was 0.40 μm.

利用超深度形狀測定顯微鏡(KEYENCE CORPORATION製、商品編號「VK-8500」)之算術平均表面粗細度Ra，係採用以JIS B0601-1994表面粗細度-定義為基準的計算式。而且，測定區域為900μm²，基準長度為40μm。 The arithmetic average surface roughness Ra using a super depth shape measuring microscope (manufactured by KEYENCE CORPORATION, product number "VK-8500") is a calculation formula based on JIS B0601-1994 surface roughness-definition. The measurement area was 900 μm ² and the reference length was 40 μm.

(實施例2) (Example 2)

除了更替製程(C1)與製程(C2)之順序以外，以與實施例1相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.5μm為止，防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光，電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。 A process (A) to a process (D) were carried out in the same manner as in Example 1 except that the order of the process (C1) and the process (C2) was changed. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the connection pads 3 for connecting electronic components on the first surface up to 5.5 μm below the surface of the connection pads 3 for connecting electronic components. By the non-contact exposure under the oxygen environment of the process (C3), the photopolymerization of the surface of the solder resist layer 2 between the bonding pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.5μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and the connection for adjacent electronic component connection was performed. Between the pads 3, a solder resist layer 2 having a thickness of 9.5 μm is filled. Further, on the second surface, a circular opening portion having a solder resist layer having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection connection pad 4.

其次，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.40μm。 Next, the surface roughness of the solder resist layer 2 between the connection pads 3 for connecting adjacent electronic components was measured, and the surface roughness Ra was 0.40 μm.

(實施例3) (Example 3)

除了製程(C3)之曝光量為200mJ/cm²以外，以與實施例1相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。在第一面，至電子構件連結用連結墊3之表面下6.0μm為止，防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光，電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少1.0μm。 A process (A) to a process (D) were carried out in the same manner as in Example 1 except that the exposure amount of the process (C3) was 200 mJ / cm ² . As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. On the first side, the solder resist layer 2 is filled between the bonding pads 3 for electronic component connection up to 6.0 μm below the surface of the bonding pads 3 for electronic component connection. By the non-contact exposure under the oxygen environment of the process (C3), the photopolymerization of the surface of the solder resist layer 2 between the bonding pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 1.0 μm.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.0μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and the connection for adjacent electronic component connection was performed. Between the pads 3, a solder resist layer 2 having a thickness of 9.0 μm is filled. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.50μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.50 μm.

(實施例4) (Example 4)

除了製程(C3)之曝光量為1000mJ/cm²以外，以與實施例1相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.0μm為止，防焊層2充填於電子構件連結用連結墊3之間。未確認到製程(C3)之氧聚合妨礙所導致之第一面防焊層2的膜減。 A process (A) to a process (D) were performed in the same manner as in Example 1 except that the exposure amount of the process (C3) was 1000 mJ / cm ² . As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the bonding pads 3 for electronic component connection on the first surface to 5.0 μm below the surface of the bonding pads 3 for electronic component connection. The film reduction of the first-side solder resist layer 2 caused by the oxygen polymerization obstruction of the process (C3) was not confirmed.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10.0μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and the connection for adjacent electronic component connection was performed. Between the pads 3, a solder resist layer 2 having a thickness of 10.0 μm is filled. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.30μm。 Next, the surface roughness of the solder resist layer 2 between the connection pads 3 for connecting adjacent electronic components was measured, and the surface roughness Ra was 0.30 μm.

(實施例5) (Example 5)

除了在氧環境下，利用直接描繪裝置(商品名稱：LI-8500、Dainippon Screen Mfg.Co.,Ltd.製)以曝光量400mJ/cm²實施製程(C3)之曝光以外，以與實施例1相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.5μm為止，防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光，電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。 Except that in the oxygen environment, a direct drawing device (trade name: LI-8500, manufactured by Dainippon Screen Mfg. Co., Ltd.) was used to perform exposure in the process (C3) at an exposure amount of 400 mJ / cm ^2. In the same way, process (A) to process (D) are performed. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the connection pads 3 for connecting electronic components on the first surface up to 5.5 μm below the surface of the connection pads 3 for connecting electronic components. By the non-contact exposure under the oxygen environment of the process (C3), the photopolymerization of the surface of the solder resist layer 2 between the bonding pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm.

其次，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.40μm。 Next, the number of connection pads 3 for connecting adjacent electronic components is measured. The surface roughness of the intermediate solder resist layer 2 was 0.40 μm.

(實施例6) (Example 6)

製程(C3)時，除了以接觸曝光方式來實施曝光以外，以與實施例1相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.0μm為止，防焊層2充填於電子構件連結用連結墊3之間。製程(C3)時，藉由充份執行接觸曝光時之排氣，而在非氧環境下實施曝光，故防焊層2表面未粗面化，結果，防焊層2的厚度未減少。 In the process (C3), except that the exposure is performed by the contact exposure method, the process (A) to the process (D) are performed in the same manner as in Example 1. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the bonding pads 3 for electronic component connection on the first surface to 5.0 μm below the surface of the bonding pads 3 for electronic component connection. During the manufacturing process (C3), the exposure is performed in a non-oxygen environment by fully performing exhaust gas during contact exposure, so that the surface of the solder resist layer 2 is not roughened, and as a result, the thickness of the solder resist layer 2 is not reduced.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，導體墊4露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and the connection for adjacent electronic component connections Between the pads 3, a solder resist layer 2 with a thickness of 10 μm is filled. Further, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the conductive pad 4 was exposed.

其次，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.10μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.10 μm.

實施例1~6時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。此外，因為防焊層2之殘渣不存在於外部連結用連結墊4上，安裝於外部電氣基板時，也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例1~6的話，相較於電子構件連結用連結墊3之間之防焊層2表面平滑的實施例6所製造的配線基板，實施例1~5所製造的配線基板，填膠之黏著性高，連結信賴性優良。 In Examples 1 to 6, since there is a sufficient thickness of the solder resist layer 2 between the connecting pads 3 for connecting adjacent electronic components, it is possible to surely prevent electrical shorts caused by soldering when the electronic components are mounted. In addition, since the residue of the solder resist layer 2 does not exist on the connection pad 4 for external connection, when mounted on an external electrical substrate, a highly reliable wiring substrate can be produced without causing electrical insulation failure. Comparing Examples 1 to 6, the wiring substrate manufactured in Example 6 has a smooth surface compared to the wiring substrate manufactured in Example 6 with a smooth surface of the solder resist layer 2 between the connection pads 3 for electronic component connection. High adhesion and excellent connection reliability.

(比較例1) (Comparative example 1) <製程(A)> <Process (A)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此，形成防焊層2。第一面之防焊層2時，從絕緣層8表面之厚度為30μm，電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面，相較於導體配線密度較大之第二面，防焊層2之厚度為較薄之8μm。 A circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm) with a conductor wiring 7 formed on both surfaces was produced by a semi-additive method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm, which is used as the connection pad 4 for external connection, is formed. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 25 μm was vacuum thermocompression bonded (lamination temperature 75 ° C, suction time 30 seconds) (Pressurizing time: 10 seconds) on both surfaces of the circuit board 1. Thereby, the solder resist layer 2 is formed. In the case of the solder resist layer 2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm, and the thickness on the connection pad 3 for electronic component connection is 15 μm. When the solder mask 2 on the second side, The thickness of the surface of the insulating layer 8 is 38 μm, and the thickness on the connection pad 4 for external connection is 23 μm. The thickness of the solder resist layer 2 is 8 μm thinner on the first surface where the conductor wiring density is smaller than the second surface where the conductor wiring density is larger.

<製程(C1)> <Process (C1)>

<製程(C2)> <Process (C2)>

<製程(B)> <Process (B)>

剝離第一面及第二面之防焊層2上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液50秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3 之表面下5.0μm為止，實施平均20μm之防焊層2的薄膜化。以光學顯微鏡進行觀察，第一面之防焊層2表面沒有處理不均，而得到良好的面內均一性。另一方面，第二面之防焊層2也被實施平均20μm之薄膜化，薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約3μm之防焊層2的殘渣。 After peeling off the supporting layer film on the solder resist layer 2 on the first and second sides, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as a thin film treatment solution with the first side facing upward, and The circuit board 1 is immersed in a thin film-forming treatment liquid for 50 seconds, and is then subjected to a micellization process (thinning process). Thereafter, a micellar removal treatment using a micellar removal solution (liquid temperature 25 ° C) is sprayed, a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed to make the solder resist 2 on the non-exposed part of the first surface Thickness becomes the connection pad for connecting electronic components 3 Up to 5.0 μm below the surface, the thickness of the solder resist layer 2 is reduced to an average of 20 μm. Observation with an optical microscope showed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the second surface of the solder resist layer 2 is also thinned to an average thickness of 20 μm. Bubbles in the thin film treatment liquid are adhered to the solder resist layer 2 of the non-exposed part on the second surface, and the film thickness is uneven. . In addition, residues of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10.0μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，然而，於外部連結用連結墊4上殘留著厚度3μm之防焊層2的殘渣。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and the connection for adjacent electronic component connection was performed. Between the pads 3, a solder resist layer 2 having a thickness of 10.0 μm is filled. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, but remained on the external connection bonding pad 4. The residue of the solder resist layer 2 having a thickness of 3 μm was hit.

安裝電子構件時，於相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2，可確實防止焊劑所導致的電氣短路，然而，安裝於外部電氣基板時，殘留於外部連結用連結墊4上之防焊層2的殘渣，導致焊劑凸塊連結發生電氣絕緣不良。 When mounting electronic components, there is a sufficient thickness of solder resist layer 2 between adjacent electronic component connection pads 3 to reliably prevent electrical shorts caused by solder. However, when mounted on external electrical substrates, it remains for external connection. The residue of the solder resist layer 2 on the bonding pad 4 causes the solder bump connection to be electrically insulated.

測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度時，表面粗細度Ra為0.03μm。相較於電子構件連結用連結墊3之間之防焊表面平滑的比較例1所製造的配線基板，實施例1~5所製造的配線基板，填膠之黏著性高，連結信賴性優良。 Measure the resistance between connecting pads 3 for connecting adjacent electronic components When the surface thickness of the solder layer 2 is 0.03 μm, the surface roughness Ra is 0.03 μm. Compared with the wiring board manufactured in Comparative Example 1 in which the solder resist surface between the connection pads 3 for electronic component connection is smooth, the wiring boards manufactured in Examples 1 to 5 have high adhesiveness and excellent connection reliability.

實施例7~11，係第5-1圖、第5-2圖及第5-3圖所示之配線基板的製造方法(2)的相關例。 Examples 7 to 11 are related examples of the manufacturing method (2) of the wiring substrate shown in FIGS. 5-1, 5-2, and 5-3.

(實施例7) (Example 7) <製程(A)> <Process (A)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此，形成防焊層2。第一面之防焊層2時，從絕緣層8表面之厚度為30μm，電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面，相較於導體配線密度較大之第二面，防焊層2之厚度為較薄之8μm。 A circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm) with a conductor wiring 7 formed on both surfaces was produced by a semi-additive method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm, which is used as the connection pad 4 for external connection, is formed. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 25 μm was vacuum thermocompression bonded (lamination temperature 75 ° C, suction time 30 seconds) (Pressurizing time: 10 seconds) on both surfaces of the circuit board 1. Thereby, the solder resist layer 2 is formed. In the case of the solder resist layer 2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm, and the thickness on the connection pad 3 for electronic component connection is 15 μm. In the case of the solder resist layer 2 on the second side, the thickness from the surface of the insulating layer 8 is 38 μm, and the thickness on the external connection pad 4 is 23 μm. The thickness of the solder resist layer 2 is 8 μm thinner on the first surface where the conductor wiring density is smaller than the second surface where the conductor wiring density is larger.

<製程(C1)> <Process (C1)>

對第一面之防焊層2，使用對比距離複數電子構件連結用連結墊3之端部為400μm之外周更為外側的區域照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 For the solder mask layer 2 on the first side, a photomask 5 irradiated with a pattern of active light 6 is used at a distance of 400 μm from the outer edge of the connecting pad 3 for connecting multiple electronic components with a contrast distance of 200 mJ / cm. ² Implement contact exposure.

<製程(C2)> <Process (C2)>

<製程(B1)> <Process (B1)>

剝離第一面及第二面之防焊層2上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，至第一面之非曝光部的防焊層2的厚度成為電子構件連結用連結墊3之表面上5.0μm為止，實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察，第一面之防焊層2表面沒有處理不均，而得到良好的面內均一性。另一方面，第二面之防焊層2也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約13μm之防焊層2的殘渣。 After peeling off the supporting layer film on the solder resist layer 2 on the first and second sides, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as a thin film treatment solution with the first side facing upward, and The circuit board 1 is immersed in a thin film-forming treatment liquid for 25 seconds, and is subjected to a micellization process (thinning process). Thereafter, a micellar removal treatment using a micellar removal liquid (liquid temperature 25 ° C), a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed to the solder resist 2 of the non-exposed portion on the first side. The thickness of the solder resist layer 2 is reduced to 5.0 μm on the surface of the bonding pad 3 for electronic component connection, and an average thickness of 10 μm is applied. Observation with an optical microscope showed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand The solder resist layer 2 is also formed into a thin film with an average thickness of 10 μm. However, the bubbles in the thin film-forming treatment solution adhere to the solder resist layer 2 in the non-exposed portion on the second surface, and the film thickness is uneven. In addition, residues of the solder resist layer 2 of about 13 μm remained on the connection pad 4 for external connection.

<製程(C4)> <Process (C4)>

對第一面之防焊層2，使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5，利用氧環境下之非接觸曝光，以曝光量400mJ/cm²實施曝光。 For the solder mask layer 2 on the first side, a photomask 5 irradiated with a pattern of active light 6 is used in the area where the end portion of the connecting pad 3 for connecting multiple electronic components is 200 μm away from the outer periphery. In contact exposure, exposure was performed at an exposure amount of 400 mJ / cm ² .

<製程(B2)> <Process (B2)>

使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3之表面下5.0μm為止，實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察，第一面之防焊層2表面沒有處理不均，而得到良好的面內均一性。藉由製程(C4)之氧環境下的非接觸曝光，從距離配置於第一面之電子構件連結用連結墊3端部200μm的外周至距離400μm之外周為止之區域之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。另一方面，第二面之防焊層2也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約3μm之防焊層2的殘渣。 A 10% by mass sodium metasilicate aqueous solution (liquid temperature: 25 ° C) was used as a thin film treatment liquid, with the first side facing upward, and the circuit board 1 was immersed in the thin film treatment liquid for 25 seconds to perform a micellization treatment (thin film).化处理). Thereafter, a micellar removal treatment using a micellar removal solution (liquid temperature 25 ° C) is sprayed, a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed, so that The thickness of the solder resist layer 2 is reduced to an average of 10 μm until the thickness is 5.0 μm below the surface of the bonding pad 3 for electronic component connection. Observation with an optical microscope showed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. By non-contact exposure under the oxygen environment of the process (C4), the surface of the solder resist layer 2 from the outer periphery of the end of 200 μm to the end of the outer periphery of 400 μm from the end of the bonding pad 3 of the electronic component connection pad 3 arranged on the first surface Photopolymerization As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm. On the other hand, the solder mask layer 2 on the second surface is also thinned to an average thickness of 10 μm. However, the bubbles in the thin film treatment liquid adhere to the solder mask layer 2 on the non-exposed portion of the second surface, and the thickness is uneven. The location. In addition, residues of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.

<製程(C5)> <Process (C5)>

對第一面之防焊層2，使用對製程(B2)被薄膜化之區域部分及從該薄膜化區域之境界部至200μm外側為止之區域照射活性光線6之圖案的光罩5，利用氧環境下之非接觸曝光，以曝光量400mJ/cm²實施曝光。 For the solder mask layer 2 on the first surface, a mask 5 irradiated with a pattern of active light 6 is applied to the area of the thin filmed area in the manufacturing process (B2) and the area from the boundary portion of the thinned area to the outside of 200 μm. For non-contact exposure in an environment, exposure was performed at an exposure amount of 400 mJ / cm ² .

<製程(D)> <Process (D)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影，除去第二面之非曝光部的防焊層2。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.5μm為止，防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C4)及(C5)之氧環境下的非接觸曝光，在第一面，製程(C1)之接觸曝光所照射活性光線6之區域以外之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。 Development was performed for 30 seconds using a 1% by mass sodium carbonate aqueous solution (liquid temperature 30 ° C., spray pressure 0.15 MPa) to remove the solder resist layer 2 of the non-exposed portion on the second surface. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the connection pads 3 for connecting electronic components on the first surface up to 5.5 μm below the surface of the connection pads 3 for connecting electronic components. By the non-contact exposure under the oxygen environment of the process (C4) and (C5), on the first side, the photopolymerization on the surface of the solder mask layer 2 outside the area of the active light 6 irradiated by the contact exposure of the process (C1) is suppressed As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及19.5μm之防焊層2所覆蓋，形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.5μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19.5 μm to form a bank with a thickness of 10.5 μm corresponding to the step difference. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and a solder resist layer 2 having a thickness of 9.5 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19.5μm之防焊層2的表面粗細度，表面粗細度Ra為0.40μm。此外，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.40μm。 Next, the thickness of the surface of the solder resist layer 2 with a thickness of 19.5 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface and a distance of 400 μm from the outer periphery of the end portion was measured. The surface roughness Ra is 0.40 μm. In addition, the surface roughness of the solder resist layer 2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.40 μm.

(實施例8) (Example 8)

除了更替製程(C1)與製程(C2)之順序以外，以與實施例7相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止，充填著防焊層2。藉由製程(C4)及(C5)之氧環境下的非接觸曝光，在第一面，製程(C1)之接觸曝光所照射活性光線6之區域以外之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。 A process (A) to a process (D) were carried out in the same manner as in Example 7 except that the order of the process (C1) and the process (C2) was changed. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, it is connected to the electronic components arranged on the first side. The solder resist layer 2 is filled with 5.5 μm below the surface of the connection pad 3. By the non-contact exposure under the oxygen environment of the process (C4) and (C5), on the first side, the photopolymerization on the surface of the solder mask layer 2 outside the area of the active light 6 irradiated by the contact exposure of the process (C1) is suppressed As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm.

(實施例9) (Example 9)

除了製程(C4)及(C5)之曝光量為200mJ/cm²以外，以與實施例7相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止，充填著防焊層2。藉由製程(C4)及(C5)之氧環境下的非接觸曝光，在第一面，製程(C1)之接觸曝光所照射活性光線6之區域以外之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少1.0μm。 Except that the exposure amounts of processes (C4) and (C5) were 200 mJ / cm ² , processes (A) to (D) were performed in the same manner as in Example 7. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled until 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the process (C4) and (C5), on the first side, the photopolymerization on the surface of the solder mask layer 2 outside the area of the active light 6 irradiated by the contact exposure of the process (C1) is suppressed As a result, the thickness of the solder resist layer 2 was reduced by 1.0 μm.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及19μm之防焊層2所覆蓋，形成相當於該段差之厚度11μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.0μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19 μm, and a dam for filling dams with a thickness of 11 μm corresponding to the step was formed. In addition, the bonding pad 3 for connecting electronic components having a thickness of 15 μm is exposed, and a solder resist layer 2 having a thickness of 9.0 μm is filled between the bonding pads 3 for connecting electronic components adjacent to each other. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19μm之防焊層2的表面粗細度，表面粗細度Ra為0.50μm。此外，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.50μm。 Next, the surface of the solder resist layer 2 having a thickness of 19 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface and a thickness of 19 μm from the area between the outer periphery of the end portion and the outer periphery of 400 μm was measured. The thickness and the surface roughness Ra were 0.50 μm. In addition, the surface roughness of the solder resist layer 2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.50 μm.

(實施例10) (Example 10)

除了製程(C4)及(C5)之曝光量為1000mJ/cm²以外，以與實施例6相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著防焊層2，未確認到製程(C4)及(C5)之氧之聚合妨礙所導致之第一面之防焊層2的膜減。 Except that the exposure amounts of processes (C4) and (C5) were 1000 mJ / cm ² , processes (A) to (D) were performed in the same manner as in Example 6. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 was filled up to 5.0 μm below the surface of the connecting pad 3 for connecting electronic components arranged on the first surface, and the first caused by the polymerization inhibition of oxygen in the processes (C4) and (C5) was not confirmed. The surface of the solder mask 2 is reduced.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之防焊層2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10.0μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 20 μm, and a dam for filling the dam with a thickness of 10 μm corresponding to the step was formed. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and a solder resist layer 2 having a thickness of 10.0 μm was filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之防焊層2的表面粗細度，表面粗細度Ra為0.30μm。此外，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.30μm。 Next, measure the thickness of the surface of the solder resist layer 2 with a thickness of 20 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface and the area between the outer periphery of the end portion 400 μm and the thickness of 20 μm. The surface roughness Ra was 0.30 μm. In addition, the surface roughness of the solder resist layer 2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.30 μm.

(實施例11) (Example 11)

製程(C4)及(C5)時，除了以接觸曝光方式實施曝光以外，以與實施例7相同之方法，實施製程(A)~製程(D)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外，在第一面，至電子構件連結用連結墊3之表面下5.0μm為止，防焊層2充填於電子構件連結用連結墊3之間。製程(C4)及(C5)時，藉由充份執行接觸曝光時之排氣，而在非氧環境下實施曝光，故防焊層2表面未粗面化，結果，防焊層2的厚度未減少。 In processes (C4) and (C5), except that exposure is performed by contact exposure, processes (A) to (D) are performed in the same manner as in Example 7. As a result of observation with an optical microscope, as a result, no residue of the solder resist layer 2 was found on the first and second surfaces of the bonding pads 3 and 4 for external connection. In addition, the solder resist layer 2 is filled between the bonding pads 3 for electronic component connection on the first surface to 5.0 μm below the surface of the bonding pads 3 for electronic component connection. During the processes (C4) and (C5), the exposure is performed in a non-oxygen environment by fully performing the exhaust gas during the contact exposure, so the surface of the solder resist layer 2 is not roughened. As a result, the thickness of the solder resist layer 2 Not reduced.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之防焊層2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度 15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10.0μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 20 μm, and a dam for filling the dam with a thickness of 10 μm corresponding to the step was formed. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm was exposed, and a solder resist layer 2 having a thickness of 10.0 μm was filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm to expose a part of the external connection bonding pad 4. .

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之防焊層2的表面粗細度，表面粗細度Ra為0.10μm。此外，測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.10μm。 Next, measure the thickness of the surface of the solder resist layer 2 with a thickness of 20 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface and the area between the outer periphery of the end portion 400 μm and the thickness of 20 μm. The surface roughness Ra was 0.10 μm. In addition, the surface roughness of the solder resist layer 2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.10 μm.

實施例7~11時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為防焊層2之殘渣不存在於外部連結用連結墊4上，安裝於外部電氣基板時，也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例7~11的話，相較於電子構件連結用連結墊3之間及周圍之防焊層2表面平滑的實施例11所製造的配線基板，實施例7~10所製造的配線基板，填膠之黏著性高，連結信賴性優良。 In the seventh to eleventh embodiments, since there is a sufficient thickness of the solder resist layer 2 between the connection pads 3 for connecting adjacent electronic components, it is possible to reliably prevent electrical shorts caused by soldering when the electronic components are mounted. Since the residue of the solder resist layer 2 does not exist on the connection pad 4 for external connection, when mounted on an external electrical substrate, a highly reliable wiring substrate can be produced without causing electrical insulation failure. Comparing Examples 7 to 11, the wiring boards manufactured in Example 11 and the wiring boards manufactured in Examples 7 to 10 are smoother than the wiring boards manufactured in Example 11 between and around the bonding pads 3 for connecting electronic components. The adhesive has high adhesion and excellent connection reliability.

(比較例2) (Comparative example 2) <製程(A)> <Process (A)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此，形成防焊層2。第一面之防焊層2時，從絕緣層8表面之厚度為30μm，電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面，相較於導體配線密度較大之第二面，防焊層2之厚度為較薄之8μm。 A circuit with conductor wiring 7 formed on both surfaces by semi-addition Substrate 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm). On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm, which is used as the connection pad 4 for external connection, is formed. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 25 μm was vacuum thermocompression bonded (lamination temperature 75 ° C, suction time 30 seconds) (Pressurizing time: 10 seconds) on both surfaces of the circuit board 1. Thereby, the solder resist layer 2 is formed. In the case of the solder resist layer 2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm, and the thickness on the connection pad 3 for electronic component connection is 15 μm. In the case of the solder resist layer 2 on the second side, the thickness from the surface of the insulating layer 8 is 38 μm, and the thickness on the external connection pad 4 is 23 μm. The thickness of the solder resist layer 2 is 8 μm thinner on the first surface where the conductor wiring density is smaller than the second surface where the conductor wiring density is larger.

<製程(C1)> <Process (C1)>

<製程(C2)> <Process (C2)>

<製程(B1)> <Process (B1)>

剝離第一面及第二面之防焊層2上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，至第一面之非曝光部的防焊層2的厚度成為電子構件連結用連結墊3之表面上5.0μm為止，實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察，第一面之防焊層2表面沒有處理不均，而得到良好的面內均一性。另一方面，第二面之防焊層2也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約13μm之防焊層2的殘渣。 After peeling off the supporting layer film on the solder resist layer 2 on the first and second sides, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as a thin film treatment solution with the first side facing upward, and The circuit board 1 is immersed in a thin film-forming treatment liquid for 25 seconds, and is subjected to a micellization process (thinning process). Thereafter, a micellar removal treatment using a micellar removal liquid (liquid temperature 25 ° C), a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed to the solder resist 2 of the non-exposed portion on the first side. The thickness of the solder resist layer 2 is reduced to 5.0 μm on the surface of the bonding pad 3 for electronic component connection, and an average thickness of 10 μm is applied. Observation with an optical microscope showed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the solder mask layer 2 on the second surface is also thinned to an average thickness of 10 μm. However, the bubbles in the thin film treatment liquid adhere to the solder mask layer 2 on the non-exposed portion of the second surface, and the thickness is uneven. The location. In addition, residues of the solder resist layer 2 of about 13 μm remained on the connection pad 4 for external connection.

<製程(C4)> <Process (C4)>

對第一面之防焊層2，使用對距離複數電子構件連結用連結墊3之端部為200μm的外周、及距離該端部400μm之外周之間之區域照射活性光線6之圖案的光罩5，利用氧環境下之非接觸曝光，以曝光量400mJ/cm²實施曝光。 On the first surface of the solder resist layer 2, a mask having a pattern of active light 6 is irradiated to the outer periphery of 200 μm from the end of the connecting pad 3 for connecting plural electronic components and the area between the outer periphery of 400 μm from the end. 5. Use non-contact exposure under an oxygen environment to perform exposure at an exposure amount of 400 mJ / cm ² .

<製程(B2)> <Process (B2)>

使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3之表面下5.0μm為止，實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察，第一面之防焊層2表面沒有處理不均，而得到良好的面內均一性。藉由製程(C4)之氧環境下的非接觸曝光，從距離配置於第一面之電子構件連結用連結墊3之端部200μm的外周至距離400μm之外周為止之區域之防焊層2表面的光聚合獲得抑制，結果，防焊層2的厚度減少0.5μm。另一方面，第二面之防焊層2也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約3μm之防焊層2的殘渣。 A 10% by mass sodium metasilicate aqueous solution (liquid temperature: 25 ° C) was used as a thin film treatment liquid, with the first side facing upward, and the circuit board 1 was immersed in the thin film treatment liquid for 25 seconds to perform a micellization treatment (thin film).化处理). Thereafter, a micellar removal treatment using a micellar removal solution (liquid temperature 25 ° C) is sprayed, a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed to make the solder resist 2 on the non-exposed part of the first surface The thickness of the solder resist layer 2 is reduced to an average of 10 μm until the thickness is 5.0 μm below the surface of the bonding pad 3 for electronic component connection. Observation with an optical microscope showed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. By the non-contact exposure in the oxygen environment of the process (C4), the surface of the solder resist 2 from the outer periphery of the 200 μm end to the outer periphery of the 400 μm distance from the end of the electronic component connection pad 3 arranged on the first surface. Photopolymerization was suppressed, and as a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm. On the other hand, the solder mask layer 2 on the second surface is also thinned to an average thickness of 10 μm. However, the bubbles in the thin film treatment liquid adhere to the solder mask layer 2 on the non-exposed portion of the second surface, and the thickness is uneven. The location. In addition, residues of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.

其次，為了使第一面及第二面之防焊層2硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線 7為厚度30μm及19.5μm之防焊層2所覆蓋，形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.5μm之防焊層2。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之防焊層2的圓形開口部，然而，於外部連結用連結墊4上，殘留有3μm之防焊層2的殘渣。 Next, in order to harden the solder resist layer 2 on the first and second sides, full exposure was performed at an exposure amount of 1000 mJ / cm ² , and then a heat curing treatment was performed at 150 ° C. for 60 minutes to obtain a wiring substrate. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19.5 μm to form a bank with a thickness of 10.5 μm corresponding to the step difference. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and a solder resist layer 2 having a thickness of 9.5 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the external connection bonding pad 4 having a thickness of 15 μm. A residue of the solder resist layer 2 of 3 μm remained.

測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度，表面粗細度Ra為0.03μm。相較於電子構件連結用連結墊3之間之防焊表面平滑的比較例2所製造的配線基板，實施例7~11所製造的配線基板，填膠之黏著性高，連結信賴性優良。 The surface roughness of the solder resist layer 2 between the connection pads 3 for connecting adjacent electronic components was measured, and the surface roughness Ra was 0.03 μm. Compared with the wiring board manufactured in Comparative Example 2 in which the solder resist surface between the connection pads 3 for connecting electronic components is smooth, the wiring boards manufactured in Examples 7 to 11 have high adhesiveness and excellent connection reliability.

實施例12~16，係第6-1圖、第6-2圖及第6-3圖所示之配線基板的製造方法(3)的相關例。 Examples 12 to 16 are related examples of the manufacturing method (3) of the wiring substrate shown in FIGS. 6-1, 6-2, and 6-3.

(實施例12) (Example 12) <製程(A1)> <Process (A1)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於上述電路基板1之表面，並將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於上述電路基板1之背面(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此，形成第一防焊層2-1。第一面之第一防焊層2-1時，從絕緣層8表面之厚度為20μm，電子構件連結用連結墊3上之厚度為5μm。第二面之第一防焊層2-1時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上之厚度為23μm。 A circuit with conductor wiring 7 formed on both surfaces by semi-addition Substrate 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm). On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm, which is used as the connection pad 4 for external connection, is formed. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 15 μm was vacuum-welded to the surface of the circuit board 1 and the thickness was 25 μm solder mask (manufactured by TAIYO INK MFG.CO., LTD., Trade name: PFR-800 AUS410) is vacuum thermocompression bonded to the back surface of the circuit board 1 (stacking temperature 75 ° C, suction time 30 seconds, pressurization) Time 10 seconds). Thereby, the first solder resist layer 2-1 is formed. In the case of the first solder resist layer 2-1 on the first side, the thickness from the surface of the insulating layer 8 is 20 μm, and the thickness on the connection pad 3 for electronic component connection is 5 μm. In the case of the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 is 38 μm, and the thickness on the external connection pad 4 is 23 μm.

<製程(C1)> <Process (C1)>

對第一面之第一防焊層2-1，使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 The first solder resist layer 2-1 on the first side is exposed with a mask 5 having a pattern of active light rays 6 on the outer side of the outer periphery of 200 μm at the end of the connecting pad 3 for a plurality of electronic components. An amount of 200 mJ / cm ^{2 was used} for contact exposure.

<製程(C2)> <Process (C2)>

對第二面之第一防焊層2-1，於外部連結用連結墊4 上配設直徑500μm之圓形開口部區域，利用對圓形開口部區域以外照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 For the first solder resist layer 2-1 on the second surface, a circular opening area with a diameter of 500 μm is arranged on the external connection bonding pad 4, and a photomask irradiated with a pattern of active light 6 outside the circular opening area is used. 5. Contact exposure was performed at an exposure amount of 200 mJ / cm ² .

<製程(B)> <Process (B)>

剝離第一面及第二面之第一防焊層2-1上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，至第一面之非曝光部的第一防焊層2-1之厚度成為電子構件連結用連結墊3之表面下5.0μm為止，實施平均10μm之第一防焊層2-1的薄膜化。以光學顯微鏡進行觀察，第一面之第一防焊層2-1表面沒有處理不均，而得到良好的面內均一性。另一方面，第二面之第一防焊層2-1也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約13μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the first solder resist 2-1 on the first and second sides, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C) was used as a thin film treatment solution to make the first side The circuit board 1 was immersed in the thin film-forming treatment liquid for 25 seconds to perform a micellization treatment (thinning treatment). Thereafter, a micellar removal treatment using a micellar removal solution (liquid temperature 25 ° C) is sprayed, a water washing treatment (liquid temperature 25 ° C), and a drying treatment are performed to a first solder resist layer on the first side of the non-exposed portion The thickness of 2-1 is reduced to 5.0 μm below the surface of the connection pad 3 for electronic component connection, and the first solder resist layer 2-1 is thinned to an average of 10 μm. Observation with an optical microscope showed that the surface of the first solder resist 2-1 on the first surface was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface is also thinned to an average thickness of 10 μm. However, the bubbles in the thin film treatment liquid adhere to the first solder resist layer 2 on the non-exposed portion of the second surface. -1, where the film thickness is uneven. In addition, residues of the first solder resist layer 2-1 of about 13 μm remained on the connection pad 4 for external connection.

<製程(C3)> <Process (C3)>

對第一面之第一防焊層2-1，使用對於製程(B)被薄膜化區域照射活性光線6之圖案的光罩5，利用氧環境下之非接觸曝光，以曝光量400mJ/cm²實施曝光。 For the first solder mask layer 2-1 on the first side, a photomask 5 with a pattern irradiating the active light 6 on the thinned area of the manufacturing process (B) was used, and the exposure amount was 400 mJ / cm by non-contact exposure in an oxygen environment. ² embodiment of the exposure.

<製程(A2)> <Process (A2)>

使用真空層合機，將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於完成至製程(C3)為止之電路基板1之第一面之第一防焊層2-1上(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此，形成第一面之第二防焊層2-2。第一面之第二防焊層2-2時，從絕緣層8表面之厚度為30μm。 Using a vacuum laminator, a 15 μm-thick solder mask (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) was vacuum heat-bonded to the circuit board 1 until the process (C3) was completed. On the first solder resist 2-1 on the first side (overlap temperature 75 ° C, suction time 30 seconds, and pressing time 10 seconds). Thereby, the second solder resist layer 2-2 on the first surface is formed. In the case of the second solder resist layer 2-2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm.

<製程(C6)> <Process (C6)>

對第一面之第二防焊層2-2，使用對比距離電子構件連結用連結墊3之端部400μm之外周更為外側的區域照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 For the second solder resist layer 2-2 on the first side, a photomask 5 irradiated with a pattern of active light 6 using an area further outside the periphery of 400 μm from the end portion of the bonding pad 3 for connecting electronic components is used, and the exposure amount is 200 mJ / cm ² performs contact exposure.

<製程(D1)> <Process (D1)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影，除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1。藉此，形成填膠堰塞用堤壩，而且，再度使從被第二防焊層2-2所覆蓋之第一防焊層2-1露出之狀態的電子構件連結用連結墊3及其周圍之第一防焊層2-1露出。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一面之第一防焊層2-1的厚度減少0.5μm。 Development was performed using a 1% by mass sodium carbonate aqueous solution (liquid temperature 30 ° C, spray pressure 0.15 MPa) for 30 seconds to remove the second solder resist 2-2 of the non-exposed portion on the first side and the non-exposed portion on the second side The first solder mask 2-1. Thereby, the dam for filling the dam is formed, and the connection pad 3 for connecting electronic components and the surroundings are exposed again from the first solder resist layer 2-1 covered by the second solder resist layer 2-2. The first solder resist 2-1 is exposed. To light As a result of observation with a microscope, as a result, the first solder resist layer 2-1 and the second solder resist layer 2 were not found on the first and second faces of the bonding pads 3 and 4 for external connection. -2 residue. In addition, the first solder resist layer 2-1 was filled until 5.5 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the first first solder resist layer 2-1 is reduced by 0.5 μm.

其次，為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.5μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Secondly, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2 on the first surface, and the first solder resist layer 2-1 on the second surface, a full exposure was performed at an exposure of 1000 mJ / cm ² After exposure, heat-curing treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, and a step equivalent to this step was formed. Embankment for filling dams with a thickness of 10 μm. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1 的表面粗細度，表面粗細度Ra為0.05μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.40μm。 Next, the first solder resist 2-1 having a thickness of 20 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface at a distance of 200 μm and a distance from the outer periphery of the end portion at a distance of 400 μm was measured. The surface roughness Ra is 0.05 μm. In addition, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent connection pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.40 μm.

(實施例13) (Example 13)

除了更替製程(C1)與製程(C2)之順序以外，以與實施例12相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一防焊層2-1的厚減少0.5μm。 A process (A1) to a process (D1) were performed in the same manner as in Example 12, except that the order of the process (C1) and the process (C2) was changed. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 was filled until 5.5 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the solder resist 2-1 was reduced by 0.5 μm.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.05μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.40μm。 Next, the distance from the outer periphery of 200 μm of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface to the first solder resist layer 2-1 having a thickness of 20 μm from the area between the outer periphery of the end portion of 400 μm and the distance was measured. The surface roughness and the surface roughness Ra were 0.05 μm. In addition, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent connection pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.40 μm.

(實施例14) (Example 14)

除了製程(C3)之曝光量為200mJ/cm²以外，以與實施例12相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一防焊層2-1的厚度減少1.0μm。 A process (A1) to a process (D1) were performed in the same manner as in Example 12, except that the exposure amount of the process (C3) was 200 mJ / cm ² . Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the solder resist layer 2-1 was reduced by 1.0 μm.

其次，為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.0μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Secondly, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2 on the first surface, and the first solder resist layer 2-1 on the second surface, a full exposure was performed at an exposure of 1000 mJ / cm ² After exposure, heat-curing treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, and a step equivalent to this step was formed. Embankment for filling dams with a thickness of 10 μm. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.05μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.50μm。 Next, the distance from the outer periphery of 200 μm of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface to the first solder resist layer 2-1 having a thickness of 20 μm from the area between the outer periphery of the end portion of 400 μm and the distance was measured. The surface roughness and the surface roughness Ra were 0.05 μm. In addition, the surface roughness of the first solder resist layer 2-1 in a region between adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.50 μm.

(實施例15) (Example 15)

除了製程(C3)之曝光量為1000mJ/cm²以外，以與實施例12相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著第一防焊層2-1，未確認到製程(C3)之氧之聚合妨礙所導致之第一面之第一防焊層2-1的膜減。 A process (A1) to a process (D1) were performed in the same manner as in Example 12, except that the exposure amount of the process (C3) was 1000 mJ / cm ² . Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the bonding pad 3 for connecting electronic components arranged on the first surface, and the first caused by the polymerization inhibition of oxygen in the process (C3) was not confirmed. The surface of the first solder resist 2-1 is reduced.

其次，為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10.0μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Secondly, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2 on the first surface, and the first solder resist layer 2-1 on the second surface, a full exposure was performed at an exposure of 1000 mJ / cm ² After exposure, heat curing treatment was performed at 150 ° C for 60 minutes. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, and a step equivalent to this step was formed. Embankment for filling dams with a thickness of 10 μm. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and the first solder resist layer 2-1 with a thickness of 10.0 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.05μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.30μm。 Next, the distance from the outer periphery of 200 μm of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface to the first solder resist layer 2-1 having a thickness of 20 μm from the area between the outer periphery of the end portion of 400 μm and the distance was measured. The surface roughness and the surface roughness Ra were 0.05 μm. In addition, the surface roughness of the first solder resist layer 2-1 in the area between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.30 μm.

(實施例16) (Example 16)

製程(C3)時，除了以接觸曝光方式實施曝光以外，以與實施例12相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著第一防焊層2-1。製程(C3)時，藉由充份執行接觸曝光時之排氣，而在非氧環境下實施曝光，故第一防焊層2-1表面未粗面化，結果，第一防焊層2-1的厚度未減少。 In the process (C3), except that the exposure is performed by the contact exposure method, the process (A1) to the process (D1) are performed in the same manner as in Example 12. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. During the manufacturing process (C3), the exposure is performed in a non-oxygen environment by fully performing exhaust gas during contact exposure, so the surface of the first solder resist 2-1 is not roughened. As a result, the first solder resist 2 The thickness of -1 is not reduced.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.05μm。此外，測定相鄰電子構件連結用連結墊3之間之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.10μm。 Second, measure the number of electronic structures with the distances on the first side. The surface thickness of the first solder resist layer 2-1 and the surface roughness Ra of the first solder resist layer 2-1 with a thickness of 20 μm and a thickness of 20 μm from a region between the outer periphery of the 400 μm end of the connecting pad 3 of the connection pad 3 for connection of the pieces were 0.05 μm. The surface roughness of the first solder resist layer 2-1 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.10 μm.

實施例12~16時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之第一防焊層2-1，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為第一防焊層2-1之殘渣不存在於外部連結用連結墊4上，安裝於外部電氣基板時，也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例12~16的話，相較於電子構件連結用連結墊3之間之第一防焊層2-1之表面平滑的實施例16所製造的配線基板，實施例12~15所製造的配線基板，填膠之黏著性高，連結信賴性優良。 In Examples 12 to 16, since there is a sufficient thickness of the first solder resist layer 2-1 between the connecting pads 3 for connecting adjacent electronic components, it is possible to surely prevent electrical shorts caused by solder when mounting the electronic components. Since the residue of the first solder resist layer 2-1 does not exist on the connection pad 4 for external connection, even when mounted on an external electrical substrate, a highly reliable wiring substrate that does not cause poor electrical insulation can be produced. Comparing Examples 12 to 16, the wiring board manufactured in Example 16 is smoother than the wiring board manufactured in Example 16 in which the surface of the first solder resist layer 2-1 between the connection pads 3 for electronic component connection is smooth. The wiring substrate has high adhesiveness and excellent connection reliability.

實施例17~21，係第7-1圖、第7-2圖及第7-3圖所示之配線基板的製造方法(4)的相關例。 Examples 17 to 21 are examples related to the manufacturing method (4) of the wiring substrate shown in FIGS. 7-1, 7-2, and 7-3.

(實施例17) (Example 17) <製程(A1)> <Process (A1)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於上述電路基板1之表面，並將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於上述電路基板1之背面(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此，形成第一防焊層2-1。第一面之第一防焊層2-1時，從絕緣層8表面之厚度為20μm，電子構件連結用連結墊3上之厚度為5μm。第二面之第一防焊層2-1時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上之厚度為23μm。 A circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm) with a conductor wiring 7 formed on both surfaces was produced by a semi-additive method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back surface (second surface), a connection pad 4 for external connection is formed and used A circular conductor wiring having a diameter of 600 μm. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 15 μm was vacuum-welded to the surface of the circuit board 1 and the thickness was 25 μm solder mask (manufactured by TAIYO INK MFG.CO., LTD., Trade name: PFR-800 AUS410) is vacuum thermocompression bonded to the back surface of the circuit board 1 (stacking temperature 75 ° C, suction time 30 seconds, pressurization) Time 10 seconds). Thereby, the first solder resist layer 2-1 is formed. In the case of the first solder resist layer 2-1 on the first side, the thickness from the surface of the insulating layer 8 is 20 μm, and the thickness on the connection pad 3 for electronic component connection is 5 μm. In the case of the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 is 38 μm, and the thickness on the external connection pad 4 is 23 μm.

<製程(C1)> <Process (C1)>

<製程(C2)> <Process (C2)>

對第二面之第一防焊層2-1，於外部連結用連結墊4上配設直徑500μm之圓形開口部區域，利用對圓形開口部區域以外照射活性光線6之圖案的光罩5，以曝光量200mJ/cm²實施接觸曝光。 For the first solder resist layer 2-1 on the second surface, a circular opening area with a diameter of 500 μm is arranged on the external connection bonding pad 4, and a photomask irradiated with a pattern of active light 6 outside the circular opening area is used. 5. Contact exposure was performed at an exposure amount of 200 mJ / cm ² .

<製程(B)> <Process (B)>

<製程(C3)> <Process (C3)>

<製程(D)> <Process (D)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影，除去第二面之非曝光部的第一防焊層2-1。 Use 1% by mass sodium carbonate aqueous solution (liquid temperature 30 ° C, spray 0.15 MPa) for 30 seconds, and the first solder resist 2-1 of the non-exposed portion on the second surface is removed.

<製程(A2)> <Process (A2)>

使用真空層合機，將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於完成至製程(D)為止之電路基板1之第一面之第一防焊層2-1上(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此，形成第一面之第二防焊層2-2。第一面之第二防焊層2-2時，從絕緣層8表面之厚度為30μm。 Using a vacuum laminator, a 15 μm-thick solder mask (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) was vacuum heat-bonded to the circuit board 1 which was completed to the process (D). On the first solder resist 2-1 on the first side (overlap temperature 75 ° C, suction time 30 seconds, and pressing time 10 seconds). Thereby, the second solder resist layer 2-2 on the first surface is formed. In the case of the second solder resist layer 2-2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm.

<製程(C6)> <Process (C6)>

<製程(D2)> <Process (D2)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影，除去第一面之非曝光部的第二防焊層2-2。藉此，形成填膠堰塞用堤壩，而且，再度使從被第二防焊層2-2所覆蓋之第一防焊層2-1露出之狀態的電子構件連結用連結墊3及其周圍之第一防焊層 2-1露出。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一面之第一防焊層2-1的厚度減少0.5μm。 Development was performed for 30 seconds using a 1% by mass sodium carbonate aqueous solution (liquid temperature 30 ° C, spray pressure 0.15 MPa), and the second solder resist 2-2 of the non-exposed portion on the first surface was removed. Thereby, the dam for filling the dam is formed, and the connection pad 3 for connecting electronic components and the surroundings are exposed again from the first solder resist layer 2-1 covered by the second solder resist layer 2-2. First solder mask 2-1 is exposed. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 was filled until 5.5 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the first first solder resist layer 2-1 is reduced by 0.5 μm.

(實施例18) (Example 18)

除了更替製程(C1)與製程(C2)之順序以外，以與實施例17相同之方法，實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一面之第一防焊層2-1的厚度減少0.5μm。 A process (A1) to a process (D2) were performed in the same manner as in Example 17 except that the order of the process (C1) and the process (C2) was changed. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 was filled until 5.5 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the first first solder resist layer 2-1 is reduced by 0.5 μm.

(實施例19) (Example 19)

除了製程(C3)之曝光量為200mJ/cm²以外，以與實施例17相同之方法，實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一面之第一防焊層2-1的厚度減少1.0μm。 A process (A1) to a process (D2) were carried out in the same manner as in Example 17 except that the exposure amount of the process (C3) was 200 mJ / cm ² . Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the first first solder resist layer 2-1 is reduced by 1.0 μm.

(實施例20) (Example 20)

除了製程(C3)之曝光量為1000mJ/cm²以外，以與實施例17相同之方法，實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著第一防焊層2-1，未確認到製程(C3)之氧之聚合妨礙所導致之第一面之第一防焊層2-1的膜減。 A process (A1) to a process (D2) were performed in the same manner as in Example 17 except that the exposure amount of the process (C3) was 1000 mJ / cm ² . Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the bonding pad 3 for connecting electronic components arranged on the first surface, and the first caused by the polymerization inhibition of oxygen in the process (C3) was not confirmed. The surface of the first solder resist 2-1 is reduced.

其次，為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10.0μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Secondly, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2 on the first surface, and the first solder resist layer 2-1 on the second surface, a full exposure was performed at an exposure of 1000 mJ / cm ² After exposure, heat-curing treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, and a step equivalent to this step was formed. Embankment for filling dams with a thickness of 10 μm. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and the first solder resist layer 2-1 with a thickness of 10.0 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

(實施例21) (Example 21)

製程(C3)時，除了以接觸曝光方式實施曝光以外，以與實施例17相同之方法，實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著第一防焊層2-1。製程(C3)時，藉由充份執行接觸曝光時之排氣，而在非氧環境下實施曝光，故第一防焊層2-1表面未粗面化，結果，第一防焊層2-1的厚度未減少。 In the process (C3), except that the exposure is performed by the contact exposure method, the process (A1) to the process (D2) are performed in the same manner as in Example 17. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. During the manufacturing process (C3), the exposure is performed in a non-oxygen environment by fully performing exhaust gas during contact exposure, so the surface of the first solder resist 2-1 is not roughened. As a result, the first solder resist 2 The thickness of -1 is not reduced.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.05μm。此外，測定相鄰電子構件連結用連結墊3之間之第一防焊層2-2的表面粗細度，表面粗細度Ra為0.10μm。 Second, measure the number of electronic structures with the distances on the first side. The surface thickness of the first solder resist layer 2-1 and the surface roughness Ra of the first solder resist layer 2-1 with a thickness of 20 μm and a thickness of 20 μm from a region between the outer periphery of the 400 μm end of the connecting pad 3 of the connection pad 3 for connection of the pieces were 0.05 μm. In addition, the surface roughness of the first solder resist layer 2-2 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.10 μm.

實施例17~21時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之第一防焊層2-1，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為第一防焊層2-1之殘渣不存在於外部連結用連結墊4上，安裝於外部電氣基板時，也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例17~21的話，相較於電子構件連結用連結墊3之間之第一防焊層2-1之表面平滑的實施例21所製造的配線基板，實施例17~20所製造的配線基板，填膠之黏著性高，連結信賴性優良。 In the embodiments 17 to 21, since the first solder resist 2-1 having a sufficient thickness is provided between the adjacent pads 3 for connecting electronic components, it is possible to reliably prevent electrical shorts caused by soldering when the electronic components are mounted. Since the residue of the first solder resist layer 2-1 does not exist on the connection pad 4 for external connection, even when mounted on an external electrical substrate, a highly reliable wiring substrate that does not cause poor electrical insulation can be produced. Comparing Examples 17 to 21, the wiring board manufactured in Example 21 is smoother than the wiring board manufactured in Example 21 in which the surface of the first solder resist layer 2-1 between the bonding pads 3 for electronic component connection is smooth. The wiring substrate has high adhesiveness and excellent connection reliability.

實施例22~25，係第8-1圖、第8-2圖及第8-3圖所示之配線基板的製造方法(5)的相關例。 Examples 22 to 25 are examples related to the manufacturing method (5) of the wiring substrate shown in FIGS. 8-1, 8-2, and 8-3.

(實施例22) (Example 22) <製程(A1)> <Process (A1)>

利用半加法，製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)，有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)，形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次，使用真空層合機，將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於上述電路基板1之表面，並將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於上述電路基板1之背面(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此，形成第一防焊層2-1。第一面之第一防焊層2-1時，從絕緣層8表面之厚度為20μm，電子構件連結用連結墊3上之厚度為5μm。第二面之第一防焊層2-1時，從絕緣層8表面之厚度為38μm，外部連結用連結墊4上的厚度為23μm。 A circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, and substrate thickness 0.4 mm) with a conductor wiring 7 formed on both surfaces was produced by a semi-additive method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for electronic component connection. On the back surface (second surface), a connection pad 4 for external connection is formed and used A circular conductor wiring having a diameter of 600 μm. Next, using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 15 μm was vacuum-welded to the surface of the circuit board 1 and the thickness was 25 μm solder mask (manufactured by TAIYO INK MFG.CO., LTD., Trade name: PFR-800 AUS410) is vacuum thermocompression bonded to the back surface of the circuit board 1 (stacking temperature 75 ° C, suction time 30 seconds, pressurization) Time 10 seconds). Thereby, the first solder resist layer 2-1 is formed. In the case of the first solder resist layer 2-1 on the first side, the thickness from the surface of the insulating layer 8 is 20 μm, and the thickness on the connection pad 3 for electronic component connection is 5 μm. In the case of the first solder resist layer 2-1 on the second side, the thickness from the surface of the insulating layer 8 is 38 μm, and the thickness on the connection pad 4 for external connection is 23 μm.

<製程(C2)> <Process (C2)>

<製程(B)> <Process (B)>

剝離第一面及第二面之第一防焊層2-1上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，至第一面之非曝光部的第一防焊層2-1之厚度成為電子構件連結用連結墊3之表面下5.0μm為止，實施平均10μm之第一防焊層2-1的薄膜化。以光學顯微鏡進行觀察，第一面之第一防焊層2-1表面沒有處理不均，而得到良好的面內均一性。另一方面，第二面之第一防焊層2-1也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約13μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the first solder resist 2-1 on the first and second sides, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C) was used as a thin film treatment solution to make the first side The circuit board 1 was immersed in the thin film-forming treatment liquid for 25 seconds to perform a micellization treatment (thinning treatment). Thereafter, the micellar removal was carried out by spraying with a micellar removal solution (liquid temperature 25 ° C). De-treatment, water-washing treatment (liquid temperature 25 ° C.), and drying treatment until the thickness of the first solder resist 2-1 of the non-exposed part on the first surface becomes 5.0 μm below the surface of the connection pad 3 for electronic component connection, The thickness of the first solder resist 2-1 is reduced to an average of 10 μm. Observation with an optical microscope showed that the surface of the first solder resist 2-1 on the first surface was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface is also thinned to an average thickness of 10 μm. However, the bubbles in the thin film treatment liquid adhere to the first solder resist layer 2 on the non-exposed portion of the second surface. -1, where the film thickness is uneven. In addition, residues of the first solder resist layer 2-1 of about 13 μm remained on the connection pad 4 for external connection.

<製程(C3)> <Process (C3)>

<製程(A2)> <Process (A2)>

使用真空層合機，將厚度20μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱：PFR-800 AUS410)真空熱壓接合於完成至製程(C)為止之電路基板1之第一面之第一防焊層2-1上(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此，形成第一面之第二防焊層2-2。第一面之第二防焊層2-2時，從絕緣層8表面之厚度為30μm。 Using a vacuum laminator, a solder resist film (manufactured by TAIYO INK MFG.CO., LTD., Product name: PFR-800 AUS410) with a thickness of 20 μm was vacuum hot-press bonded to the circuit board 1 until the process (C) was completed. On the first solder resist 2-1 on the first side (overlap temperature 75 ° C, suction time 30 seconds, and pressing time 10 seconds). Thereby, the second solder resist layer 2-2 on the first surface is formed. In the case of the second solder resist layer 2-2 on the first side, the thickness from the surface of the insulating layer 8 is 30 μm.

<製程(C6)> <Process (C6)>

<製程(B3)> <Process (B3)>

剝離第一面之第二防焊層2-2上的支撐層膜後，使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液，使第一面朝上，將電路基板1浸漬於薄膜化處理液25秒鐘，實施膠束化處理(薄膜化處理)。其後，實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理，至第一面之非曝光部的第二防焊層2-2之厚度成為電子構件連結用連結墊3之表面上5.0μm為止，實施平均10μm之第二防焊層2-2的薄膜化。以光學顯微鏡進行觀察，第一面之第二防焊層2-2表面沒有處理不均，而得到良好的面內均一性。另一方面，第二面之第一防焊層2-1也被實施平均10μm之薄膜化，然而，薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1，出現膜厚不均一的部位。此外，於外部連結用連結墊4上，殘留有約3μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the second solder resist layer 2-2 on the first side, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C) was used as a thin film treatment solution, with the first side facing upward, and The circuit board 1 is immersed in a thin film-forming treatment liquid for 25 seconds, and is subjected to a micellization process (thinning process). Thereafter, a micellar removal process using a micellar removal solution (liquid temperature 25 ° C) for spraying, a water washing process (liquid temperature 25 ° C), and a drying process are performed to a second solder resist layer on the non-exposed portion on the first side. The thickness of 2-2 is reduced to 5.0 μm on the surface of the connection pad 3 for electronic component connection, and the second solder resist layer 2-2 is thinned to an average of 10 μm. Observation with an optical microscope showed that the surface of the second solder resist 2-2 on the first surface was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface is also thinned to an average thickness of 10 μm. However, the bubbles in the thin film treatment liquid adhere to the first solder resist layer 2 on the non-exposed portion of the second surface. -1, where the film thickness is uneven. In addition, a residue of the first solder resist layer 2-1 of about 3 μm remained on the connection pad 4 for external connection.

<製程(C7)> <Process (C7)>

對第一面之第二防焊層2-2，使用對比距離電子構件連結用連結墊3之端部200μm之外周更為外側的區域照射活性光線6之圖案的光罩5，利用氧環境下之非接觸曝光，以曝光量400mJ/cm²實施曝光。 For the second solder resist layer 2-2 on the first side, a photomask 5 irradiated with a pattern of active light 6 is used in a region further outside the periphery of 200 μm from the end portion of the connecting pad 3 for connecting electronic components. For non-contact exposure, exposure was performed at an exposure amount of 400 mJ / cm ² .

<製程(D1)> <Process (D1)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影，除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1。藉此，形成填膠堰塞用堤壩，而且，再度使從被第二防焊層2-2所覆蓋之第一防焊層2-1露出之狀態的電子構件連結用連結墊3及其周圍之第一防焊層2-1露出。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一面之第一防焊層2-1的厚度減少0.5μm。此外，藉由製程(C7)之氧環境下的非接觸曝光，距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2之表面的光聚合獲得抑制，結果，厚度20μm之第二防焊層2-2之表面厚度減少0.5μm。 Development was performed using a 1% by mass sodium carbonate aqueous solution (liquid temperature 30 ° C, spray pressure 0.15 MPa) for 30 seconds to remove the second solder resist 2-2 of the non-exposed portion on the first side and the non-exposed portion on the second side The first solder mask 2-1. Thereby, the dam for filling the dam is formed, and the connection pad 3 for connecting electronic components and the surroundings are exposed again from the first solder resist layer 2-1 covered by the second solder resist layer 2-2. The first solder resist 2-1 is exposed. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 was filled until 5.5 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the first first solder resist layer 2-1 is reduced by 0.5 μm. In addition, by the non-contact exposure under the oxygen environment of the manufacturing process (C7), the distance between the outer periphery of 200 μm and the outer periphery of 400 μm of the end portion of the plurality of electronic component connection connection pads 3 arranged on the first side 20 μm thickness The photopolymerization of the surface of the solder layer 2-2 was suppressed, and as a result, the surface thickness of the second solder mask layer 2-2 having a thickness of 20 μm was reduced by 0.5 μm.

其次，為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及19.5μm之第二防焊層2-2所覆蓋，形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.5μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Secondly, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2 on the first surface, and the first solder resist layer 2-1 on the second surface, a full exposure was performed at an exposure of 1000 mJ / cm ² After exposure, heat-curing treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. Observation with an optical microscope revealed that on the first side, the conductor wiring 7 having a thickness of 15 μm was covered with the second solder resist layer 2-2 having a thickness of 30 μm and 19.5 μm, and a filling weir corresponding to the step thickness of 10.5 μm was formed. Plugged with a dyke. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19.5μm之第二防焊層2-2的表面粗細度，表面粗細度Ra為0.40μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.40μm。 Next, the second solder resist 2-2 having a thickness of 19.5 μm from the outer periphery of the end portion of the plural pads of the plurality of electronic component connection connecting pads 3 arranged on the first surface and a distance of 400 μm from the outer periphery of the end portion was measured. The surface roughness Ra is 0.40 μm. In addition, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent connection pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.40 μm.

(實施例23) (Example 23)

除了製程(C3)及(C7)之曝光量為200mJ/cm²以外，以與實施例22相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止，充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光，配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制，結果，第一面之第一防焊層2-1的厚度減少1.0μm。此外，藉由製程(C7)之氧環境下的非接觸曝光，距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2之表面的光聚合獲得抑制，結果，厚度20μm之第二防焊層2-2之表面的厚度減少1.0μm。 Except that the exposure amounts of processes (C3) and (C7) were 200 mJ / cm ² , the processes (A1) to (D1) were performed in the same manner as in Example 22. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By the non-contact exposure under the oxygen environment of the manufacturing process (C3), the photopolymerization of the surface of the first solder resist layer 2-1 disposed between the bonding pads 3 for electronic component connection on the first surface is suppressed, and as a result, the first The thickness of the first first solder resist layer 2-1 is reduced by 1.0 μm. In addition, by the non-contact exposure under the oxygen environment of the manufacturing process (C7), the distance between the outer periphery of 200 μm and the outer periphery of 400 μm of the end portion of the plurality of electronic component connection pads 3 arranged on the first side Photopolymerization of the surface of the second solder resist layer 2-2 having a thickness of 20 μm in the region was suppressed, and as a result, the thickness of the surface of the second solder resist layer 2-2 having a thickness of 20 μm was reduced by 1.0 μm.

其次，為了使第一面之防焊層2-1及2-2、第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理，而得到配線基板。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及19μm之第一防焊層2-1及第二防焊層2-2所覆蓋，形成相當於該段差之厚度11μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度9.0μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Next, in order to harden the solder resist layers 2-1 and 2-2 on the first side, and perform a full exposure at an exposure amount of 1000 mJ / cm ² in order to harden the solder resist layers 2-1 on the second side and then at 150 ° C. A heat-curing treatment was performed for 60 minutes to obtain a wiring board. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 19 μm, and a step corresponding to this step was formed. Embankment for filling dams with a thickness of 11 μm. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19μm之第二防焊層2-2的表面粗細度，表面粗細度Ra為0.50μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.50μm。 Next, the distance between the outer periphery of 200 μm of the end portion of the plurality of electronic component connection pads 3 disposed on the first surface and the thickness of the second solder resist layer 2-2 of the area between the outer periphery of the end portion 400 μm and the thickness of the second solder resist layer 2-2 of 400 μm was measured. The surface roughness and the surface roughness Ra were 0.50 μm. In addition, the surface roughness of the first solder resist layer 2-1 in a region between adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.50 μm.

(實施例24) (Example 24)

除了製程(C3)及(C7)之曝光量為1000mJ/cm²以外，以與實施例22相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著第一防焊層2-1，未確認到製程(C3)及(C7)之氧之聚合妨礙所導致之第一面之第一防焊層2-1及第一面之第二防焊層2-2的膜減。 A process (A1) to a process (D1) were performed in the same manner as in Example 22 except that the exposure amounts of the processes (C3) and (C7) were 1000 mJ / cm ² . Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, the first solder resist 2-1 was filled up to 5.0 μm below the surface of the bonding pad 3 for connecting electronic components arranged on the first surface, and no oxygen hindrance was observed in the processes (C3) and (C7). The resulting film reduction of the first solder mask layer 2-1 on the first side and the second solder mask layer 2-2 on the first side.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2的表面粗細度，表面粗細度Ra為0.30μm。此外，測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.30μm。 Next, the distance between the outer periphery of 200 μm of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface and the thickness of the second solder resist layer 2-2 of 20 μm from the area between the outer periphery of the end portion 400 μm was measured. The surface roughness Ra was 0.30 μm. In addition, the surface roughness of the first solder resist layer 2-1 in the area between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.30 μm.

(實施例25) (Example 25)

製程(C3)及(C7)時，除了以接觸曝光方式實施曝光以外，以與實施例22相同之方法，實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察，結果，在第一面及第二面，於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外，至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止，充填著第一防焊層2-1。製程(C3)及(C7)時，藉由充份執行接觸曝光時之排氣，而在非氧環境下實施曝光，故防焊層2表面未粗面化，結果，第一面之第一防焊層2-1及第一面之第二防焊層2-2的厚度未減少。 In processes (C3) and (C7), except that exposure was performed by the contact exposure method, processes (A1) to (D1) were performed in the same manner as in Example 22. Observation with an optical microscope revealed that on the first and second surfaces, neither the first solder resist layer 2-1 nor the second solder resist layer was found on the bonding pad 3 for connecting electronic components and the bonding pad 4 for external connection. 2-2 residue. In addition, to the connecting pads 3 for connecting electronic components arranged on the first surface The first solder resist 2-1 is filled up to 5.0 μm below the surface. During the processes (C3) and (C7), the exposure is performed in a non-oxygen environment by fully performing the exhaust gas during the contact exposure, so the surface of the solder resist layer 2 is not roughened. As a result, the first surface is the first The thicknesses of the solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface are not reduced.

其次，為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化，以曝光量1000mJ/cm²實施全面曝光，接著，以150℃實施60分鐘之熱硬化處理。以光學顯微鏡進行觀察，結果，在第一面，厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋，形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外，厚度15μm之電子構件連結用連結墊3露出，於相鄰電子構件連結用連結墊3之間，充填著厚度10μm之第一防焊層2-1。此外，在第二面，於厚度15μm之外部連結用連結墊4上的一部分，形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部，而使外部連結用連結墊4之一部分露出。 Secondly, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2 on the first surface, and the first solder resist layer 2-1 on the second surface, a full exposure was performed at an exposure of 1000 mJ / cm ² After exposure, heat curing treatment was performed at 150 ° C for 60 minutes. Observation with an optical microscope revealed that on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, and a step equivalent to this step was formed. Embankment for filling dams with a thickness of 10 μm. In addition, the bonding pad 3 for connecting electronic components with a thickness of 15 μm is exposed, and a first solder resist layer 2-1 having a thickness of 10 μm is filled between the bonding pads 3 for connecting with adjacent electronic components. In addition, on the second surface, a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm was formed on a part of the external connection bonding pad 4 having a thickness of 15 μm, and the external connection connection pad 4 was formed. One part of 4 is exposed.

其次，測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2的表面粗細度，表面粗細度Ra為0.10μm。此外，測定相鄰電子構件連結用連結墊3之間之第一防焊層2-1的表面粗細度，表面粗細度Ra為0.10μm。 Next, the distance between the outer periphery of 200 μm of the end portion of the plurality of electronic component connection connecting pads 3 arranged on the first surface and the thickness of the second solder resist layer 2-2 of 20 μm from the area between the outer periphery of the end portion 400 μm was measured. The surface roughness and the surface roughness Ra were 0.10 μm. The surface roughness of the first solder resist layer 2-1 between the adjacent bonding pads 3 for connecting electronic components was measured, and the surface roughness Ra was 0.10 μm.

實施例22~25時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之第一防焊層2-1，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為第一防焊層2-1之殘渣不存在於外部連結用連結墊4上，安裝於外部電氣基板時，也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例22~25的話，相較於電子構件連結用連結墊3之間之第一防焊層2-1及電子構件連結用連結墊3周圍之第二防焊層2-2之表面平滑的實施例25所製造的配線基板，實施例22~24所製造的配線基板，填膠之黏著性高，連結信賴性優良。 In the embodiments 22 to 25, since the first solder resist 2-1 with a sufficient thickness is provided between the connecting pads 3 for connecting adjacent electronic components, it is possible to surely prevent electrical shorts caused by soldering when the electronic components are mounted. Since the residue of the first solder resist layer 2-1 does not exist on the connection pad 4 for external connection, even when mounted on an external electrical substrate, a highly reliable wiring substrate that does not cause poor electrical insulation can be produced. Compared with Examples 22 to 25, the surface of the first solder resist layer 2-1 between the connection pads 3 for electronic component connection and the second solder resist layer 2-2 around the connection pad 3 for electronic component connection was smoother. The wiring board manufactured in Example 25 and the wiring boards manufactured in Examples 22 to 24 have high adhesiveness and excellent connection reliability.

如上述說明所示，實施例1~6所製造之配線基板，第一面之電子構件連結用連結墊3的一部分從防焊層2露出。使用該配線基板進行覆晶連結時，即使為以高密度配置電子構件連結用連結墊3之配線基板時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。此外，絕緣層8與電子構件連結用連結墊3之接著強度、及電子構件連結用連結墊3與焊劑之接著強度增大，得到高連結信賴性。此外，以氧環境下之非接觸曝光方式來實施製程(C3)之曝光時，因為電子構件連結用連結墊3周圍之防焊層2的表面被充份粗面化，填膠之黏著性良好，而得到高連結信賴性。此外，因為第二面之外部連結用連結墊4之表面上也沒有防焊層2之殘渣，安裝於外部基板時，得到不會發生焊劑連結之電氣絕緣不良的高連結信賴性。 As described above, in the wiring substrates manufactured in Examples 1 to 6, a part of the connection pad 3 for electronic component connection on the first surface is exposed from the solder resist layer 2. When this wiring substrate is used for flip-chip bonding, even when the wiring substrate 3 is used to arrange the bonding pads 3 for connecting electronic components at a high density, there is a sufficient thickness of the solder resist layer 2 between the bonding pads 3 for bonding electronic components. It is sure to prevent the electric short circuit caused by the flux when mounting the electronic components. In addition, the bonding strength between the insulating layer 8 and the connection pad 3 for electronic component connection and the bonding strength between the connection pad 3 for electronic component connection and the solder are increased, and high connection reliability is obtained. In addition, when the exposure of the manufacturing process (C3) is performed by a non-contact exposure method in an oxygen environment, the surface of the solder resist layer 2 around the bonding pad 3 for electronic component connection is sufficiently roughened, and the adhesiveness of the filler is good. And get high link reliability. In addition, there is no residue of the solder resist 2 on the surface of the connection pad 4 for external connection on the second surface, so that when mounted on an external substrate, it has a high connection reliability that does not cause defective electrical insulation of the solder connection. Sex.

如上述說明所示，實施例7~26所製造之配線基板，電子構件連結用連結墊3之一部分從防焊層2(第一防焊層2-1)露出，此外，具有由二段構造之防焊層2(第一防焊層2-1及第二防焊層2-2)所形成的填膠堰塞用堤壩。使用該配線基板進行覆晶連結時，可以防止充填於電子構件與配線基板之間之填膠溢至周圍而對電氣連結信賴性產生的不良影響。此外，即使為以高密度配置電子構件連結用連結墊3之配線基板時，因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2(第一防焊層2-1)，可以確實防止安裝電子構件時之焊劑所導致的電氣短路。絕緣層8與電子構件連結用連結墊3之接著強度、及電子構件連結用連結墊3與焊劑之接著強度增大，得到高連結信賴性。此外，配線基板的製造方法(2)之製程(C4)及(C5)、配線基板的製造方法(3)、(4)、(5)之製程(C3)、以及配線基板的製造方法(5)之製程(C7)之曝光以氧環境下之非接觸曝光方式來實施時，因為電子構件連結用連結墊3之間、及周圍之防焊層2(第一防焊層2-1、第二防焊層2-2)表面被充份粗面化，填膠之黏著性良好，得到高連結信賴性。此外，因為第二面之外部連結用連結墊4之表面上也沒有防焊層2(第一防焊層2-1)之殘渣，安裝於外部基板時，得到不會發生焊劑連結之電氣絕緣不良的高連結信賴性。 As described above, the wiring substrates manufactured in Examples 7 to 26 have a part of the connection pad 3 for connecting electronic components exposed from the solder mask layer 2 (the first solder mask layer 2-1), and have a two-stage structure. Embankment for filling dam formed by the solder resist layer 2 (the first solder resist layer 2-1 and the second solder resist layer 2-2). When this wiring substrate is used for flip-chip connection, it is possible to prevent the filler filled between the electronic component and the wiring substrate from overflowing to the surroundings, thereby adversely affecting the reliability of the electrical connection. In addition, even in the case of a wiring board in which the connection pads 3 for connecting electronic components are arranged at a high density, there is a sufficient thickness of the solder resist layer 2 between the connection pads 3 for connecting electronic components (first solder resist layer 2-1). , Can reliably prevent electrical short circuit caused by solder when mounting electronic components. The bonding strength between the insulating layer 8 and the connection pad 3 for electronic component connection and the bonding strength between the connection pad 3 for electronic component connection and the solder are increased, and high connection reliability is obtained. In addition, the manufacturing method (C4) and (C5) of the wiring substrate manufacturing method, the manufacturing method (3), (4), (5) of the wiring substrate manufacturing method (C3), and the manufacturing method of the wiring substrate (5) When the exposure of the manufacturing process (C7) is performed by a non-contact exposure method in an oxygen environment, the solder resist layer 2 (the first solder resist layer 2-1, The surface of the second solder resist layer 2-2) is sufficiently roughened, and the adhesiveness of the filler is good, and high connection reliability is obtained. In addition, since there is no residue of the solder resist layer 2 (first solder resist layer 2-1) on the surface of the second-side connection pad 4 for external connection, it is possible to obtain electrical insulation that does not cause solder connection when mounted on an external substrate. Poor high link reliability.

[產業上的可利用性] [Industrial availability]

本發明之配線基板的製造方法，例如，適用於用以製造具有以連結半導體晶片及其他印刷線路板等電子構件為目的之複數連結墊之配線基板的用途。 The manufacturing method of the wiring board of the present invention is suitable for use in manufacturing a wiring board having a plurality of connection pads for the purpose of connecting electronic components such as semiconductor wafers and other printed wiring boards.

Claims

一種配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之防焊層的製程(A)；對厚度薄於第二面之防焊層的第一面之防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之防焊層，實施於製程(B)被薄膜化之區域部分之曝光的製程(C3)；以及以顯影液除去第二面之非曝光部之防焊層的製程(D)。A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer. The two surfaces of the circuit substrate are provided with a solder resist layer, so that part of the connecting pad is removed from the solder resist layer. The exposed wiring substrate manufacturing method is characterized by comprising a process (A) of forming a solder resist layer having different thicknesses on both surfaces of a circuit substrate having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer; For the solder mask on the first side, which is thinner than the solder mask on the second side, the process (C1) of exposing the part other than the thinned area in the post-process (B1); the solder mask on the second side Layer, which is implemented in the post-process (D) process (C2) for exposing parts other than the area being developed; on the first side, a thin film treatment solution is used to make the solder resist layer of the non-exposed part less than the thickness of the bonding pad. A process (B) for exposing a part of the connection pad to a thin film so far; a process (C3) for exposing a solder resist layer on the first surface to a part of the filmed area (C3); and a development process Remove the non-exposed part of the second surface Process solder layer (D).

一種配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之防焊層的製程(A)；對厚度薄於第二面之防焊層的第一面之防焊層，實施後製程之製程(B1)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；對第一面，在連結墊未露出之範圍，以薄膜化處理液，實施非曝光部之防焊層之薄膜化的製程(B1)；於第一面之防焊層，實施於後製程之製程(B2)被薄膜化區域以外部分之曝光的製程(C4)；於第一面，以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B2)；對第一面之防焊層，實施於製程(B2)被薄膜化之區域部分之曝光的製程(C5)；以及以顯影液除去第二面之非曝光部之防焊層的製程(D)。A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer. The two surfaces of the circuit substrate are provided with a solder resist layer, so that part of the connecting pad is removed from the solder resist layer. The exposed wiring substrate manufacturing method is characterized by comprising a process (A) of forming a solder resist layer having different thicknesses on both surfaces of a circuit substrate having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer; For the solder mask on the first side, which is thinner than the solder mask on the second side, perform the post-process (B1) process (C1) where the part other than the thin film area is exposed; the solder mask on the second side In the post-processing process (D), the exposure process (C2) is performed outside of the developed area; on the first side, in a range where the connection pad is not exposed, a thin film is used to implement a solder mask for the non-exposed part. (B1); the solder mask on the first side is implemented in the post-process (B2); the process (C4) is exposed outside the filmed area; on the first side, the film is formed into a thin film. The treatment liquid is applied to make the solder resist of the non-exposed part into A process (B2) where the thickness of the junction pad is less than the thickness to expose a part of the bonding pad (B2); the first side of the solder mask is implemented in the process (B2) where the area where the film is thinned is exposed (C5) ); And a process (D) of removing a solder resist layer of a non-exposed portion of the second surface with a developing solution.

一種配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之第一防焊層的製程(A1)；對厚度薄於第二面之第一防焊層的第一面之第一防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之第一防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之第一防焊層，實施於製程(B)被薄膜化區域部分之曝光的製程(C3)；於完成至(C3)製程為止之電路基板之第一面的第一防焊層上，形成第二防焊層之製程(A2)；對第一面之第二防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C6)；以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer. The two surfaces of the circuit substrate are provided with a solder resist layer, so that part of the connecting pad is removed from the solder resist layer. The method for manufacturing an exposed wiring board includes a process of forming first solder resist layers having different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer (A1). ); For the first solder mask having a thickness smaller than the first solder mask on the second surface, the process (C1) of exposing the portion other than the thinned area in the post-process (B) of the first process is performed; The first solder mask layer on the second side is implemented in the process (C2) of exposing the part other than the developed area in the post-process (D1); on the first side, a thin film treatment liquid is used to implement the first non-exposed part. The process (B) of forming a solder resist layer into a thin film to a thickness less than the thickness of the bonding pad to expose a part of the bonding pad; the first solder resist layer on the first side is applied to the part of the filmed area of the manufacturing process (B) Exposure process (C3); after completion to (C3) The process (A2) of forming a second solder resist layer on the first solder resist layer on the first side of the circuit board so far; the second solder resist layer on the first face is developed in a process (D1) implemented in a later process Process (C6) for exposing parts outside the area; and process (D1) for removing the second solder resist layer of the non-exposed part on the first side and the first solder resist layer of the non-exposed part on the second side with a developing solution.

一種配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之第一防焊層的製程(A1)；對厚度薄於第二面之第一防焊層的第一面之第一防焊層，實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1)；對第二面之第一防焊層，實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之第一防焊層，實施於製程(B)被薄膜化區域部分之曝光的製程(C3)；以顯影液除去第二面之非曝光部之第一防焊層的製程(D)；於完成至(D)製程為止之電路基板之第一面的第一防焊層上，形成第二防焊層之製程(A2)；對第一面之第二防焊層，實施於後製程之製程(D2)被顯影區域以外部分之曝光的製程(C6)；以及以顯影液除去第一面之非曝光部之第二防焊層的製程(D2)。A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer. The two surfaces of the circuit substrate are provided with a solder resist layer, so that part of the connecting pad is removed from the solder resist layer. The method for manufacturing an exposed wiring board includes a process of forming first solder resist layers having different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer (A1). ); For the first solder mask having a thickness smaller than the first solder mask on the second surface, the process (C1) of exposing the portion other than the thinned area in the post-process (B) of the first process is performed; The first solder resist layer on the second side is implemented in the process (C2) of exposing the part other than the developed area in the post-process (D); on the first side, the first non-exposed part is implemented with a thin film treatment solution. A process (B) in which a solder resist layer is thinned to a thickness of the bonding pad to expose a part of the bonding pad; the first solder resist layer on the first side is applied to the portion of the filmed region of the manufacturing process (B) Exposure process (C3); remove with developer Manufacturing process (D) of the first solder resist layer of the non-exposed part on the second side; forming the second solder resist layer on the first solder resist layer on the first side of the circuit substrate until completion of the (D) process (A2); for the second solder resist layer on the first side, the process (C6) of exposing the portion other than the developed area in the post-process (D2); and removing the non-exposed part of the first side with a developing solution Process (D2) of the second solder resist layer.

一種配線基板的製造方法，係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板，於電路基板之兩表面，具有防焊層，使連結墊之一部分從防焊層露出之配線基板的製造方法，其特徵為，含有：於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面，形成厚度不同之第一防焊層的製程(A1)；對第二面之第一防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2)；於第一面，以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化，來使連結墊之一部分露出的製程(B)；對第一面之第一防焊層，實施於製程(B)被薄膜化區域部分之曝光的製程(C3)；於完成至(C3)製程為止之電路基板之第一面的第一防焊層上，形成第二防焊層之製程(A2)；對第一面之第二防焊層，實施於後製程之製程(B3)被薄膜化區域以外部分之曝光的製程(C6)；於第一面，在連結墊未露出之範圍，以薄膜化處理液實施非曝光部之第二防焊層之薄膜化的製程(B3)；對第一面之第二防焊層，實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C7)；以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。A method for manufacturing a wiring substrate is a circuit substrate having an insulating layer on both surfaces and a connecting pad formed on the surface of the insulating layer. The two surfaces of the circuit substrate are provided with a solder resist layer, so that part of the connecting pad is removed from the solder resist layer. The method for manufacturing an exposed wiring board includes a process of forming first solder resist layers having different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer (A1). ); For the first solder resist layer on the second side, the process (C2) of exposing the portion other than the developed area in the post-process (D1) is performed; on the first side, the non-exposed portion is implemented with a thin film treatment liquid. The process (B) of forming the first solder resist layer to a thickness less than the thickness of the bonding pad to expose a part of the bonding pad; the first solder resist layer on the first side is thinned into the process (B). Process (C3) for area exposure; process (A2) for forming a second solder mask layer on the first solder resist layer on the first side of the circuit substrate up to (C3) process; for the first face Second solder mask, implemented in the post-process (B3) Process (C6) for exposing parts other than the thinned area; on the first side, in a range where the bonding pad is not exposed, a process for thinning the second solder resist layer of the non-exposed part with a thinning treatment liquid (B3) ; For the second solder resist layer on the first side, the process (C7) of exposing the portion other than the developed area in the post-process (D1); and the second resist for removing the non-exposed part of the first side with the developer The process (D1) of the solder layer and the first solder resist of the non-exposed part on the second surface.

如申請專利範圍第1~4項之其中任一項所記載之配線基板的製造方法，其中在製程(C1)之前，實施製程(C2)。The method for manufacturing a wiring board according to any one of claims 1 to 4 of the scope of patent application, wherein the manufacturing process (C2) is performed before the manufacturing process (C1).

如申請專利範圍第1~4項之其中任一項所記載之配線基板的製造方法，其中同時實施製程(C1)及製程(C2)。The method for manufacturing a wiring board according to any one of the claims 1 to 4 of the patent application scope, wherein the manufacturing process (C1) and manufacturing process (C2) are performed simultaneously.

如申請專利範圍第1、3、4項之其中任一項所記載之配線基板的製造方法，其中以氧環境下之非接觸曝光方式來實施製程(C3)之曝光。The method for manufacturing a wiring board according to any one of the claims 1, 3, and 4, wherein the exposure of the manufacturing process (C3) is performed by a non-contact exposure method in an oxygen environment.

如申請專利範圍第5項所記載之配線基板的製造方法，其中以氧環境下之非接觸曝光方式來實施製程(C3)及製程(C7)之曝光。The method for manufacturing a wiring board according to item 5 of the scope of patent application, wherein the exposure in the process (C3) and the process (C7) is performed by a non-contact exposure method under an oxygen environment.

如申請專利範圍第2項所記載之配線基板的製造方法，其中以氧環境下之非接觸曝光方式來實施製程(C4)及製程(C5)之曝光。The manufacturing method of the wiring board as described in the second item of the patent application scope, wherein the exposure in the process (C4) and the process (C5) is performed by a non-contact exposure method under an oxygen environment.

如申請專利範圍第1、3、4項之其中任一項所記載之配線基板的製造方法，其中製程(C3)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下。For example, the method for manufacturing a wiring board according to any one of the claims 1, 3, and 4, wherein the exposure amount of the manufacturing process (C3) is more than 1 to 5 times the exposure amount of the manufacturing process (C1).

如申請專利範圍第5或9項所記載之配線基板的製造方法，其中製程(C3)及製程(C7)之曝光量為製程(C6)之曝光量之1倍以上、5倍以下。The manufacturing method of the wiring board as described in the item 5 or 9 of the scope of the patent application, wherein the exposure amount of the manufacturing process (C3) and the manufacturing process (C7) is more than 1 to 5 times the exposure amount of the manufacturing process (C6).

如申請專利範圍第2或10項所記載之配線基板的製造方法，其中製程(C4)及製程(C5)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下。The manufacturing method of the wiring substrate as described in the second or tenth item of the scope of the patent application, wherein the exposure amount of the process (C4) and the process (C5) is more than 1 to 5 times the exposure amount of the process (C1).

如申請專利範圍第1、3、4項之其中任一項所記載之配線基板的製造方法，其中製程(B)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method for manufacturing a wiring board according to any one of claims 1, 3, and 4, wherein the thinning treatment of the solder resist layer in the process (B) is performed with the thinning treatment surface facing upward.

如申請專利範圍第5或9項所記載之配線基板的製造方法，其中製程(B)及製程(B3)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method for manufacturing a wiring board according to item 5 or 9 of the scope of application for a patent, wherein the thinning treatment of the solder resist layer in the process (B) and the process (B3) is performed with the thinning process surface facing upward.

如申請專利範圍第2或10項所記載之配線基板的製造方法，其中製程(B1)及製程(B2)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method for manufacturing a wiring board according to item 2 or 10 of the scope of patent application, wherein the thinning treatment of the solder resist layer in the manufacturing process (B1) and the manufacturing process (B2) is carried out with the thinning treatment surface facing upward.

如申請專利範圍第8項所記載之配線基板的製造方法，其中製程(C3)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下。The method for manufacturing a wiring board according to item 8 of the scope of application for a patent, wherein the exposure amount in the process (C3) is more than 1 to 5 times the exposure amount in the process (C1).

如申請專利範圍第8項所記載之配線基板的製造方法，其中製程(B)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method for manufacturing a wiring board according to item 8 of the scope of application for a patent, wherein the thinning treatment of the solder resist in the process (B) is performed with the thinning treatment surface facing upward.

如申請專利範圍第11項所記載之配線基板的製造方法，其中製程(B)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method of manufacturing a wiring board according to item 11 of the scope of application for a patent, wherein the thinning treatment of the solder resist in the process (B) is performed with the thinning treatment surface facing upward.

如申請專利範圍第12項所記載之配線基板的製造方法，其中製程(B)及製程(B3)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method for manufacturing a wiring board according to item 12 of the scope of the patent application, wherein the thinning treatment of the solder resist layer in the process (B) and the process (B3) is performed with the thinning process side facing up.

如申請專利範圍第13項所記載之配線基板的製造方法，其中製程(B1)及製程(B2)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。The method for manufacturing a wiring board according to item 13 of the scope of patent application, wherein the thinning treatment of the solder resist layer in the manufacturing process (B1) and the manufacturing process (B2) is performed with the thinning treatment surface facing upward.