1355222 0807005/0806006 29048twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種績 aa 里綠路基板的電鍍法，且特別是有 關於一種用以將金屬層電鲈认&妨# ^ 疋负 製程 ^ 於、.表路基板的接合墊上的電鍛 【先前技術】 二般:，線路基板主要·*多層線路層（patt_d clrcuiuayer)及多層介電層（dieiectri 疊 丨t 路層的接合塾上通常以層(：u 1^：)或其他統層力叫轉，職 響而氧化’造成接合塾的電性品質下降。 衣切 魚圖、—歸絲板魏方法的流程示 :美板Γο二’首先，提供一線路基板10，此線 20a^_ : 少 第—線路層20b。請參考圖1B，接著， „池與第—線路層2〇a上形成-第—導電層3〇a 電路），於下表面勘與第二線“繩 圖:接厂:!層，(做為電鍍用的線路）。請參考 十 者，>成—第一光阻層40a於第一導電声3()盥 第二導電層3〇〜請參如D，接著， ^進行曝光與顯影，以形成—第—圖案化光阻層4t j 份第二導電層鳥。請參考圖接著，移ΜΑ 1355222 0807005/0806006 29048twf.doc/n 案化光阻層wa覆蓋的第一導電層3〇a與第二導電層 30b，以暴露出部份上表面10a、部份下表面1%、部份第 一線路層20a與第二線路層2〇b。請參考圖卟，接著，移 除第-圖，化光阻層42a，以暴露位於第一圖案化光阻層 42a下之第一導電層30a與第二導電層3〇b。 清參考圖1G，接著，於第一線路層施、第二線路層 20b、第一導電層30a與第二導電層3〇上形 層働。請參考圖1H，接著，對第二光阻層.進行曝光、 顯影及光固化處理，以形成一第二圖案化光阻層桃，其 中第二圖案化光阻層42b覆蓋圖案化的第-導電層30a以 及圖案化的第二導電層3%，僅顯露出第—線路層挪愈 =二線路層勘的欲電鑛表面（即接合墊的表面）。請參 2二’ fr將上述步驟的線路基板10放置於電鍍液 化的Ϊ:導雷Μ並經由圖案化的第—導電層*以及圖案 I: 3%供電，以分別形成-第-金屬層50a 上（即接a墊_ 線路層咖與弟二線路層2〇b 接i 的表面上）’以防止線路氧化。請參考圖U， 第導光p且層42b、第—導電層3°a以及 = =1=考隨與圖1L，之後， 60a盥一第-_ 刀_成—第―®案化防銲層 .案‘層娜於線路基板10的上表面 眉屏in 、面1%’其中第—圖案化防銲層60a覆蓋第一金 屬層50a與第一線路戶20a，日+ I * ” m綠* 暴露出部份第—金屬層5〇a。 線路基板的電鍍製程中，第-線路層咖以同 1355222 0807005/0806006 29048twf.doc/n -表面上的第-導電層3加做為電鑛膜來電鐘第一金屬層 5〇a，但為了覆蓋圖案化的第一導電層3如（如圖ih所示）， 必須先去除第-圖案化光阻層42a，接著再形成第二圖案 化光阻層42b，等到完成第一金屬層伽之後，再去除第 二圖案化光阻層42b’因而多增加第二光阻層働形成及 去除步驟（見圖1H及圖1JT)。同樣，電鑛第二金屬層獅 於第二線路層2Gb上’與上述的製程相同，也多增加第二 光阻層働形成及去除步驟（見® 1H及圖U)。由於光 靖及㈣的時間長，且光罩的數量增加及光阻 曝光顯影的開口對準度必須不斷地調整、檢測，因而浪費 時^及f本。此外，光阻在電鑛過財若溶解於電 ，又、定，字5染電錢液，進而縮短了電鑛液的使用壽命。1355222 0807005/0806006 29048twf.doc/n IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to an electroplating method for a green road substrate of a grade aa, and particularly relates to a method for electroforming a metal layer & amp amp ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The joints of the 丨t road layer are usually transferred by layers (:u 1^:) or other layers of force, and the oxidation of the occupational rings causes the electrical quality of the joints to decrease. The cut-cut fish map, the silk-plate The flow of the method is shown as follows: First, a circuit substrate 10 is provided. This line 20a^_: a small first-circuit layer 20b. Please refer to FIG. 1B, and then, a cell and a first circuit layer 2a are formed. - the first - conductive layer 3 〇 a circuit), on the lower surface of the second line "rope diagram: factory:! layer, (as a circuit for electroplating). Please refer to the ten, > into the first photoresist layer 40a in the first conductive sound 3 () 盥 second conductive layer 3 〇 ~ please refer to D, then, ^ exposure and development to form - the first pattern The photoresist layer 4t j part of the second conductive layer bird. Referring to the figure, the first conductive layer 3〇a and the second conductive layer 30b covered by the photoresist layer wa are exposed to expose a portion of the upper surface 10a and a portion of the lower surface layer 10a. 1% of the surface, part of the first circuit layer 20a and the second circuit layer 2〇b. Referring to FIG. 2, next, the photoresist layer 42a is removed to expose the first conductive layer 30a and the second conductive layer 3b under the first patterned photoresist layer 42a. Referring to Fig. 1G, next, a layer is formed on the first wiring layer, the second wiring layer 20b, the first conductive layer 30a, and the second conductive layer 3?. Referring to FIG. 1H, the second photoresist layer is exposed, developed, and photocured to form a second patterned photoresist layer, wherein the second patterned photoresist layer 42b covers the patterned first. The conductive layer 30a and the patterned second conductive layer 3% only reveal the surface of the electrode layer (ie, the surface of the bonding pad) of the second circuit layer. Referring to the second step, the circuit substrate 10 of the above step is placed on the electroplated liquefied germanium: thunder and is supplied with power through the patterned first conductive layer* and the pattern I: 3% to form the -metal layer 50a, respectively. On (ie, connect a pad _ line layer coffee and brother two circuit layer 2 〇 b to the surface of i) to prevent line oxidation. Please refer to FIG. U, the light guide p and the layer 42b, the first conductive layer 3°a and the ==1= test with FIG. 1L, and then, the 60a盥- the first-_ knife_成—the first--------------------- The layer 'layer' is on the upper surface of the circuit substrate 10, and the surface 1%', wherein the first patterned solder mask 60a covers the first metal layer 50a and the first line household 20a, day + I * ” m green * Expose part of the metal layer 5〇a. In the electroplating process of the circuit substrate, the first-line layer is added to the first conductive layer 3 on the surface of the 1355222 0807005/0806006 29048twf.doc/n - as the electric ore. The film calls the first metal layer 5〇a, but in order to cover the patterned first conductive layer 3 (as shown in FIG. 1h), the first patterned photoresist layer 42a must be removed first, followed by the second patterning. The photoresist layer 42b waits until the first metal layer is completed, and then removes the second patterned photoresist layer 42b', thereby increasing the second photoresist layer formation and removal step (see FIG. 1H and FIG. 1JT). The second metal layer of the mine is on the second layer 2Gb', which is the same as the above process, and the second photoresist layer is formed and removed (see ® 1H and Figure U). Due to the long time of Guangjing and (4), and the increase in the number of reticle and the opening alignment of the photoresist exposure development, it must be constantly adjusted and detected, so that it is wasted and f. In addition, the photoresist is in the electric mine. Dissolved in electricity, and fixed, word 5 dyed money liquid, which shortens the service life of electric mineral liquid.
【發明内容J 本發明提供一種線路基板的表面電鑛製程。 月提種線路基板的表面電 供:線路基板’其中線路基板已於一上表 面形成一第二線路層。接著，分‘成 表面;;表面ΐΐ;第線，基_ :層:第防銲層暴露出部二:面出:::線： i声：ΐΐί:導電層於第—圖案化防銲層上，且第二導 Γ第—線路層。形成-第-光阻層於第 ν電層上。Μ弟—導電層為電鍍膜，形成一第—金“ 7 0807005/0806006 29048twf.d〇c/n 於第二線路層上。移除第—光 =第-線路層與第-圖案化防鲜層。第= 化防銲層與第—金屬層上，且第二導電層覆 皿被暴路出的下表面並包覆第一金 2第二導電層上。以第二導電層為電鍍膜，形阻 金屬層於被暴露出的第—線路層上 =二導電層，以暴露出部份下表面、第-且 二圖案化防銲層。 喝禮及弟 日在本發明之-實施财，上述之分獅成第一 防銲層與第二_化防銲層辑路 ^ ^驟，首先，分別形成-第-防銲層與—第二防 線路，板，其中第—防銲層覆蓋上表面與第-線路層:第 :防銲層覆盖下表面與第二線路層上。接著，對第— ^與第二防銲層進行曝光與顯影，以形成—第—圖案化 銲層與一第二圖案化防銲層。 ”方 在本發明之-實施例中’上述之形成第—圖案 層^與第二®案化防銲層之後，更包括進行騎—紫於 第一圖案化防銲層與第二圖案化防銲層上，簡化闻 案化防銲層與第二圖案化防銲層。 圖SUMMARY OF THE INVENTION The present invention provides a surface electrominening process for a circuit substrate. The surface power supply of the circuit substrate is as follows: the circuit substrate 'where the circuit substrate has formed a second circuit layer on an upper surface. Then, the surface is divided into; surface ΐΐ; the first line, the base _: layer: the first solder resist layer exposed part 2: face out::: line: i sound: ΐΐί: conductive layer in the first - patterned solder mask Up, and the second guide - the circuit layer. A -first photoresist layer is formed on the νth electrical layer. The younger brother—the conductive layer is a plating film, forming a first gold “7 0807005/0806006 29048twf.d〇c/n on the second circuit layer. Removing the first-light=first-line layer and the first-patterned anti-fresh The second conductive layer is coated on the second conductive layer and the second conductive layer is coated on the second conductive layer. The metal layer is formed on the exposed first circuit layer = two conductive layers to expose a portion of the lower surface, the first and second patterned solder resist layers. The gift and the diary are in the invention - the implementation of the The above-mentioned lions are formed into a first solder mask layer and a second solder mask layer. First, a -first solder mask layer and a second anti-solder layer are formed, respectively, wherein the first solder mask layer Covering the upper surface and the first-circuit layer: the: solder resist layer covers the lower surface and the second wiring layer. Then, the first and second solder resist layers are exposed and developed to form a -first patterned solder layer And a second patterned solder resist layer. In the embodiment of the present invention, the above-mentioned forming the first pattern layer and the second layer of the solder resist layer further includes Riding row - purple patterned on the first solder resist layer and the second patterned solder resist layer, a simplified smelling patterned solder resist layer and the second patterned solder resist layer. Figure
在本發明之一實施例中，上述之形成第—圖案化 層與第二_化防銲層之後，更包括進行—齡氣牛 驟’以固化第-圖案化防銲層與第二圖案化防銲層。V 在本發明之一實施例中，上述之形成第—導^ -圖案化防銲層上之前’更包括對第—_化時^進行 1355222 0807005/0806006 29〇48twf.doc/n 一第一粗化處理。 在本發明之一實施例中，上述之第—粗化處理包括物 理性的粗化處理或化學性的粗化處理。 在本發明之一實施例中，上述之形成第一導電層於第 一圖案化防銲層上的方法包括物理氣相沉積、化學^相沉 積或化學液相沉積。 在本發明之一實施例中，上述之形成第一光阻層於第 一導電層上之後，更包括照射一紫外光於第一光阻^上， 以固化第一光阻層。 在本發明之一實施例中，上述之照射紫外光於第一光 阻層之後，更包括進行一熱空氣烘烤步驟，以固化第一光 阻層。 在本發明之一實施例中，上述之移除第一光阻層及第 一導電層的方法包括去膜蝕刻製程。 在本發明之一實施例中，上述之形成第二導電層於第 二圖案化防銲層與第一金屬層上的方法包括物理氣相沉 積、化學氣相沉積或化學液相沉積。 一在本發明之一實施例中，上述之形成第二導電層於第 -圖案化防銲層上之前’更包括對第三圖案化防銲層進行 一第二粗化處理。 在本發明之一實施例中，上述之第二粗化處理包括物 理性的粗化處理或化學性的粗化處理。 在本發明之一實施例中，上述之形成第二光阻層於第 二導電層上之後，更包括照射一紫外光於第二光阻層上， 1355222 0807005/0806006 29048twf.doc/n 以固化第二光阻層。 在本發明之-實施例中，上述之照射紫外光於第二光 阻層上之後，更包括進行—熱空氣烘烤步驟， 光阻層。 K乐一 -道Ϊ本發明之—實關巾’域之移轉二光阻層及第 —導電層的方法包括去膜蝕刻製程。 在^㈣之—實補巾，上述之第―金屬層的 括錫、錫合金、金或鎳金。 、 上述之第二金屬層的材質包 在本發明之一實施例中 括錫、錫合金、金或鎳金。 命山ΛΛ* μ …上述之第一圖案化防銲 路的口 (Μ分第-線路層為-銲罩定義型的接合塾。；、 露中t本發日把—實施财，上述之第二_化_層暴 的弟一線路層為一非銲罩定義型的接合墊。 -、 先於基板的表面電錄製程是 形成導電二’再於圖案化防銲層上 進行光固化處理•因二 =二=;阻層 有超少練層在麵财巾崎量，其具 想的難成效’且為本領域中熟知該技術者所不易聯 在本發明之一實施例中 文特舉以例，並配合所_式作詳細說明如下。 1355222 0807005/0806006 29048twf.doc/n 【實施方式】 圖2A至圖2K為本發明之—實施例之一種線路基板 的表面電鍍製程的流程示意圖。請先參考圖2Α，關於本實 施例的線絲㈣表面賴製程，首先，提供—線路基板 100，其中此線路基板100已於—上表面1〇〇a形成一第一 線路層110a及於-下表面聽形成一第二線路層應。 在本實施例中，第-線路層⑽與第二線路層·的材 質例如是銅。 —明參考圖2B，接著，分別形成一第一防銲層12〇&與 一第二防銲層12〇b於線路基板1〇()上，其中第一防銲層 120a覆蓋線路基板100的上表面1〇〇a與第一線路層 110a第一防銲層i20b覆盍線路基板的下表面 與第二線路層110b上。 請參考圖2C，接著，對第—防銲層12〇a與第二防銲 層120b進行曝光與顯影，以分別形成一第一圖案化防銲層 122a與一第二圖案化防銲·層122b於線路基板1〇〇的上表 面100a與下表面i〇〇b，其中第一圖案化防銲層122a暴露 出部份第一線路層ll〇a，第二圖案化防銲層122b暴露出 部份下表面100b及第二線路層110b。 在本實施例中，完成前述之第一圖案化防銲層122a與第二 圖案化防銲層122b之後，更包括進行照射一紫外光於第一 圖案化防銲層122a與第二圖案化防銲層12孔上，以固化 第圖案化防銲層122a與第二圖案化防銲層122b。此外， 於其他實施例中，在進行完照射紫外光後，更可以選擇性 1355222 0807005/0806006 29048twf.doc/n 地包括進4亍熱空氣供烤步驟，以固化第一圖案化防銲層 122a與第二圖案化防銲層122b。另外，於其他未繪示實施 例中，完成前述之第一圖案化防銲層122&與第二圖案化防 銲層122b之後，更包括進行一熱空氣烘烤步驟，以固化第 一圖案化防銲層122a與第二圖案化防銲層122b。當然， 在進行完前述之熱空氣烘烤步驟後，更可以選擇性^包括 進行照射一紫外光以固化第一圖案化防銲層122a與第二 圖案化防鲜廣122b。In an embodiment of the invention, after the forming the first patterned layer and the second patterned solder resist layer, the method further comprises: performing an age-old gas bump to cure the first patterned solder resist layer and the second patterning layer. Solder mask. V In one embodiment of the present invention, before the forming of the first-patterned solder resist layer is performed, the first step is to include 1355222 0807005/0806006 29〇48twf.doc/n first Coarse processing. In an embodiment of the invention, the first roughening treatment includes a physical roughening treatment or a chemical roughening treatment. In one embodiment of the invention, the method of forming the first conductive layer on the first patterned solder resist layer comprises physical vapor deposition, chemical phase deposition or chemical liquid deposition. In an embodiment of the invention, after forming the first photoresist layer on the first conductive layer, the method further comprises irradiating an ultraviolet light on the first photoresist to cure the first photoresist layer. In an embodiment of the invention, after the irradiating the ultraviolet light to the first photoresist layer, the method further comprises performing a hot air baking step to cure the first photoresist layer. In an embodiment of the invention, the method for removing the first photoresist layer and the first conductive layer includes a stripping etching process. In an embodiment of the invention, the method of forming the second conductive layer on the second patterned solder resist layer and the first metal layer comprises physical vapor deposition, chemical vapor deposition or chemical liquid deposition. In one embodiment of the invention, the step of forming the second conductive layer on the first patterned solder resist layer further comprises performing a second roughening treatment on the third patterned solder resist layer. In an embodiment of the invention, the second roughening treatment includes a physical roughening treatment or a chemical roughening treatment. In an embodiment of the invention, after the forming the second photoresist layer on the second conductive layer, further comprising irradiating an ultraviolet light on the second photoresist layer, 1355222 0807005/0806006 29048 twf.doc/n to cure The second photoresist layer. In an embodiment of the invention, after the irradiating the ultraviolet light on the second photoresist layer, the method further comprises performing a hot air baking step, the photoresist layer. K Leyi - The method of transferring the two photoresist layers and the first conductive layer of the present invention - the actual sealing film field includes a film removing etching process. In the ^ (4) - solid patch, the above-mentioned - metal layer of tin, tin alloy, gold or nickel gold. The material of the second metal layer described above is included in one embodiment of the invention, including tin, tin alloy, gold or nickel gold.命山ΛΛ* μ ...the first patterned soldering-proof circuit port (the first-circuit layer is the solder-shield-type joint 塾;;, the dew-t is the day of the hair--the implementation of the above-mentioned The second circuit layer of the second layer is a non-weld mask-defined bonding pad. - The surface of the substrate is electrically formed before the surface is electrically formed and then cured on the patterned solder mask. Because the second = two =; the resist layer has a very small layer in the surface of the money, it is difficult to achieve 'and is well-known in the art, the technology is not easy to connect in one of the embodiments of the present invention For example, the following is a detailed description of the following: 1355222 0807005/0806006 29048twf.doc/n [Embodiment] FIG. 2A to FIG. 2K are schematic diagrams showing the surface plating process of a circuit substrate according to an embodiment of the present invention. Referring first to FIG. 2A, with respect to the wire (4) surface process of the present embodiment, first, a circuit substrate 100 is provided, wherein the circuit substrate 100 has a first circuit layer 110a and a lower surface formed on the upper surface 1a. The surface is formed to form a second circuit layer. In this embodiment, the first line (10) The material of the second circuit layer is, for example, copper. - Referring to FIG. 2B, respectively, a first solder resist layer 12A and a second solder resist layer 12b are formed on the circuit substrate 1 () The first solder resist layer 120a covers the upper surface 1a of the circuit substrate 100 and the first solder layer i20b of the first circuit layer 110a over the lower surface of the circuit substrate and the second circuit layer 110b. 2C, then, the first solder resist layer 12A and the second solder resist layer 120b are exposed and developed to form a first patterned solder resist layer 122a and a second patterned solder resist layer 122b, respectively. The upper surface 100a and the lower surface i〇〇b of the substrate 1 ,, wherein the first patterned solder resist layer 122a exposes a portion of the first wiring layer 11a, and the second patterned solder resist layer 122b exposes a portion under The surface 100b and the second wiring layer 110b. In this embodiment, after the first patterned solder resist layer 122a and the second patterned solder resist layer 122b are completed, the method further comprises: irradiating an ultraviolet light to the first patterning prevention Solder layer 122a and second patterned solder mask 12 holes to cure the first patterned solder resist layer 122a and the second pattern The solder resist layer 122b. In addition, in other embodiments, after the ultraviolet light is irradiated, the optional 1355222 0807005/0806006 29048 twf.doc/n includes 4 hot air for the baking step to cure the first The patterned solder resist layer 122a and the second patterned solder resist layer 122b. In addition, in the other unillustrated embodiments, after the first patterned solder resist layer 122 & and the second patterned solder resist layer 122 b are completed, The method further includes performing a hot air baking step to cure the first patterned solder resist layer 122a and the second patterned solder resist layer 122b. Of course, after the hot air baking step is performed, it is further possible to selectively irradiate an ultraviolet light to cure the first patterned solder resist layer 122a and the second patterned anti-fresh layer 122b.
值得-提的S ’在本實施例中，第―圖案化防鮮層 122a暴露出的部份第一線路層u〇a為銲罩定義型江 ]^吐0诏此(1’8]^)的接合墊112&(圖2(：中繪示三個）， 用以配置至少-銲球或其他導電結構（未繪示），而線路 基板100可透過此銲球與外界作電性連接，而第二圖案化 防銲層122b暴露出的第二線路層11%為非銲罩定義型 (Non-Solder Mask Defined，NSMD)的接合墊 ll2b (圖In the present embodiment, the portion of the first circuit layer u〇a exposed by the first-patterned anti-friction layer 122a is a solder mask-defined type of water]^ 吐0诏(1'8]^ The bonding pads 112 & (three in FIG. 2) are used to configure at least a solder ball or other conductive structure (not shown), and the circuit substrate 100 can be electrically connected to the outside through the solder ball And the second patterned layer exposed by the second patterned solder resist layer 122b is a non-Solder Mask Defined (NSMD) bond pad 11b (Fig.
2C中繪示三個），用以接合至少一晶片（未繪示），其中 銲罩定義雜合触非銲|域難合墊是㈣畴層是 否覆蓋接合墊的差異而有所區分。 接著，對第 圖案化防銲層122a進行一第 ------ 粗化, 理’以增加第-圖案化防銲層122a與後續所形成之一第 導電層130a (請參考圖2D)之間的結合力。在本實施 中，第一粗化處理包括物理性的粗化處理或化學性二^ 處理’其中化學性的粗化處理例如是以—化學藥劑對第 圖案化防銲層122a的表祕粗化，而物理性的粗化處理 1355222 0807005/0806006 29048twf.doc/n 括以研磨材研磨第一圖案化防銲層122a的表面或對第一 圖案倾制122a的表輯行電漿轟擊或喷砂處理。 凊參考圖2D，接著，形成第-導電層1施於第-圖 ，化防銲層122a上’且第—導電層1施覆蓋被暴露出的 弟-線路層ll〇a(即所謂的銲罩定義型的接合塾U2a)。 在本實&例巾’形成第導電層13Qa於第—圖案化防鲜層 22a上的方法包括物理氣相沉積（卩咖丨⑶卜叩。『吻⑽出⑽， PVD )、化學氣相沉積（chemical vapor deposition, CVD )、 ( Chemical liquid phase deposition, CLPD) ^ 電鍍法（plating)或無電電鍍法（electr〇lessplating)，其 中物理氣相"b積例如疋真空蒸鑛（⑶腿㈣pGrati〇n )或 =鍍（sputtering)。第-導電層挪的材質可選自於錫、 銅、鉻、鈀、鎳、鋅及其合金。 請參考® 2E，接著，形成一第一光阻層M〇a於第一 j層13〇a上。在本實施例中，於第一導電層13如上形 成弟-光阻層14Ga之後’接著對第—光阻層14Qa進行光 口化處理。光固化處理是於第—光阻層丨術上照射一紫外 光，藉此將第一光阻層14〇a固體化。由於第一光阻層▲ 、、二由光固化處理之後，其抗蝕刻性以及抗化學性相對增 加’且第一光阻層14〇a溶解於電鍍液中的溶解速度會因此 而變慢’故能有效避免第-光阻層丨術溶解於電錄液中， 因而減輕第一光阻層140a污染電鍍液的程度。值得一提的 是’在本實施例令，照射紫外光於第一光阻層14〇a之後， 更包括進行-熱空氣烘烤步驟，以提高第一光阻層M〇a U] 13 1355222 0807005/0806006 29048twf.doc/n 固化的程度。 請參考圖2F，接著，聪：μ、+、 於電鍍液中，冬上述步騍的線路基板1〇〇玫置 於舊液中，並以第—導電層13〇 第一金屬層150a於第二圖荦 ^賴$鍍形成一 ιιπκ rP 口木化防鋅層122b所暴露出的第 r -) _及線路基板!。。内的線;(;繪示 在第-線路層2 ^中’第-金屬層咖的材質包括;^ 金，而第-金屬層15Ga用以防止第錫°，錢鎳 謂的非銲衫義接合塾U2b)因譽a 即所 成其電性品質下降。 u 響而乳化’造 上覆 ί膜光成第一金屬層15〇a於第二線路】=ί電 換j f 能避免電鐘金屬於第—導電層130a上。 兴5之，弟—光阻層HOa可為一阻鍍層。 ^相2G，接著，移除第—級層咖及第 露出部f ί—線路層11Ga(即所謂的銲罩 除第|接口墊112&)與弟一圖案化防銲層122a，其中移 =程光㈣驗及第-導電们施吻钟括去酿 接著，對第二圖案化防銲層122b谁;^ 咕 疋订一第二粗化處 14 1355222 0807005/0806006 29048twf.d〇〇/n 導電12_後續所形成之一第二 ί =1;上考圖2H)之間的結合力。在本實施例 理性與第—粗化叙糊，其包括物 處理例如3、一2 ·ΐ性的粗化處理，其中化學性的粗化 面傲如彳卜疋以化學藥劑對第二圖案化防銲層122b的表3C is shown in FIG. 2C for bonding at least one wafer (not shown), wherein the solder mask defines a hybrid touch non-weld|domain hard mat to distinguish whether the (4) domain layer covers the difference of the bonding pads. Next, the first patterned solder resist layer 122a is subjected to a first coarsening process to increase the first patterned solder resist layer 122a and the subsequently formed one conductive layer 130a (please refer to FIG. 2D). The bond between the two. In the present embodiment, the first roughening treatment includes a physical roughening treatment or a chemical treatment, wherein the chemical roughening treatment is, for example, a chemical chemical treatment of the first patterned solder resist layer 122a. And the physical roughening treatment 1355222 0807005/0806006 29048twf.doc/n includes grinding the surface of the first patterned solder resist 122a with an abrasive or buffing or sandblasting the surface of the first pattern 120a. deal with. Referring to FIG. 2D, next, the formation of the first conductive layer 1 is applied to the first view, and the solder resist layer 122a is formed and the first conductive layer 1 is covered with the exposed wiring layer 11a (so-called soldering). Cover-type joint 塾U2a). The method of forming the first conductive layer 13Qa on the first patterned anti-fresh layer 22a in the present embodiment includes physical vapor deposition (卩咖丨(3) 叩. "Kiss (10) out (10), PVD), chemical vapor phase Chemical vapor deposition (CVD), (chemical liquid phase deposition, CLPD) ^ plating (electroplating) or electroless plating (electr〇lessplating), in which physical vapor phase "b product such as 疋 vacuum distillation ((3) leg (four) pGrati 〇n ) or = sputtering. The material of the first conductive layer may be selected from the group consisting of tin, copper, chromium, palladium, nickel, zinc, and alloys thereof. Please refer to ® 2E, and then form a first photoresist layer M〇a on the first j layer 13〇a. In the present embodiment, after the first conductive layer 13 is formed as described above, the photo-masking process is performed on the first photoresist layer 14Qa. The photocuring treatment irradiates an ultraviolet light on the first photoresist layer to solidify the first photoresist layer 14A. Since the first photoresist layers ▲ and 2 are photocured, their etching resistance and chemical resistance are relatively increased, and the dissolution rate of the first photoresist layer 14〇a dissolved in the plating solution is slowed down. Therefore, the first photoresist layer can be effectively prevented from being dissolved in the electro-acoustic liquid, thereby reducing the degree to which the first photoresist layer 140a contaminates the plating solution. It is worth mentioning that, in the present embodiment, after irradiating ultraviolet light to the first photoresist layer 14A, a step of performing a hot air baking step is further performed to increase the first photoresist layer M〇a U] 13 1355222 0807005/0806006 29048twf.doc/n Degree of curing. Please refer to FIG. 2F, and then, Cong: μ, +, in the plating solution, the circuit substrate 1 of the above-mentioned step is placed in the old liquid, and the first conductive layer 13 is used as the first metal layer 150a. The second figure 荦 ^ 赖 $ plated to form an ιιπκ rP mouth woodized zinc layer 122b exposed r -) _ and circuit substrate! . Inside the line; (; shown in the first - circuit layer 2 ^ 'the metal layer of the material of the metal layer includes; ^ gold, and the first - metal layer 15Ga to prevent the second tin, the nickel is said to be non-welded Bonding U2b) is a result of a decline in electrical quality. u 而 emulsified ' 覆 覆 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜 膜Xing 5, brother - the photoresist layer HOa can be a resist layer. ^ phase 2G, then, remove the first level layer coffee and the exposed portion f ί - circuit layer 11Ga (so-called solder mask except the first | interface pad 112 &) and the brother-patterned solder resist layer 122a, where shift = Cheng Guang (four) test and the first - conductive people kiss the bell to the brewing, followed by the second patterned solder mask 122b; ^ 咕疋 ordered a second roughening 14 1355222 0807005/0806006 29048twf.d〇〇 / n conductive 12 _ Subsequent formation of a second ί = 1; the test between Figure 2H). In the present embodiment, rational and first-roughening, including the treatment of, for example, 3, a 2, a roughening treatment, wherein the chemical roughening surface is proud of the second chemical patterning Table of solder resist layer 122b
幸㈣雜的粗化處理包括以研磨材研磨第二圖 ==層⑽的表面或對第二圖案化防卿 面進行電漿轟聲或噴砂處理。 凊參相2Η，縣’形成第二導電層働於第二圖 方銲層122b上’且第二導電層㈣覆蓋被暴露出的 :表面100b並包覆第二線路層腿及第—金屬層H =本實施例中’形成第二導電層丨勘於第二圖案化防鲜層 b上的方去包括物理氣相沉積、化學氣相沉積、化學液 相/儿積、魏法或無電電鑛法，其巾物理氣相沉積例如是 真空蒸錢或雜。第二導電@ 13%的材質可選自於錫、 鋼、鉻、鈀、鎳、鋅及其合金。 请參考圖21 ’接著，形成一第二光阻層14〇b於第二 導電層130b上。在本實施例中，於第二導電層13〇b上形 成第二光阻層140b之後，接著對第二光阻層140b進行光 固化處理。光固化處理是於第二光阻層14〇b上照射一紫外 光’藉此將第二光阻層140b固體化。由於第二光阻層14〇b 經由光固化處理之後，其抗蝕刻性以及抗化學性相對增 加，且第二光阻層140b溶解於電鍍液中的溶解速度會因此 而變慢，故能有效避免第二光阻層140b溶解於電鑛液中， ί 51 15 0807005/0806006 29048twf.doc/n 因而減輕第二光阻層14〇b污染電鏡液的程度。值得一提的 是’在本實施例中’照射紫外光於第二光阻層14〇b之後， 更包括進行-熱空氣烘烤步驟，以提高^^光阻層勵匕 固化的程度。 請參考圖2J’接著，將上述步驟的線路基板1〇〇放置 ^電鑛液中，並以第二導電層賺為電賴，電鑛形成一 第二金屬層150b於第-圖案化防銲層ma所暴露出的第 一線路層110a(即所謂的銲罩定義型的接合墊U2a)上。 值得注意的是，第二導電層13%是藉由第二線路層n〇b 及線路基板1GG内的線路（未繪示）與第—線路層n〇a 電性連接’與習知技術中在第二線路層2%的同—表面形 成第二導電層施的作法完全不同。在本實施例_，第二 金屬層150b的材質包括錫、錫合金、金或鎳金，而第二金 ^層150b用以防止第一線路層(即所謂的即所謂的 銲，定義型的接合墊112a)因環境影響而氧化，造成其電 性品質下降。 值得一提的是，在本實施例中，由於第二導電層13仙 亡覆蓋第二光阻層140b，因此當以第二導電層i3〇:為電 '广膜’電鍍形成第二金屬層l5Qb於第—線路層Η此時， 第二光阻層140b能避免電鍍金屬於第二導電層n〇b上。 換言之，第二光阻層14〇13可是為一阻鍍層。曰 、請參考圖2K，之後，移除第二光阻層14%及第二導 =13%’峰露出雜下表面腸、第—金屬層挪 弟一圖案化防銲層122b，其中移除第二光阻層M〇b及 1355222 0807005/0806006 29〇48twf.doc/n 第-導電層13Gb的方法包括去膜制製程。至此，已完成 線路基板的表面電鑛製程。 在後續的製程中，舉例而言，本實施例之線路基板1〇〇 可藉由打線接合（Wire Bonding，WB)或覆晶接合（Flip Chip Bonding ’ FC )的方式應用於晶片與封裝載板（package earner)之間。詳細而言，首先，經由多條銲線（wire)(未 繪示）將晶片（未繪示）電性連接至線路基板1〇〇的非銲 罩定義型的接合塾112b上。接著’將多個形成於線路基板 100之銲罩定義型賴合墊112a上的銲球電性及結構性地 連接至一封裝載板（例如是一印刷電路板）（未繪示）上， 使分別位於線路基板100及封裝載板之間的兩介面、兩元 =或兩端點均可經由上述之銲球來達成訊號傳遞的目的。 簡言之，當線路基板100欲與其他元件（例如封裝載板、 晶片等）構成躲連接時，即可直接透過線路基板100的 婷罩定義型的接合塾112a以及非銲罩定義型的接合塾 ⑽與其他元件進行電性連接，如此—來，可增加線ς基 板100使用上的便利性。 此外，在本實施例中，雖然本發明的線路基板的表面 電鍵製程是應用於上表面l〇〇a與下表面1〇〇b分別具有第 —線路層110a與第二線路層110b的線路基板且第 —線路層110a具有多個銲罩定義型的接合墊U2a，第二 線路層110b具有多個非銲罩定義型的接合墊U2b，粹I 於其他實施射’亦可以僅應祕單岭树路層的= 基板，且亦可僅具有單個接合塾。因此，本發_線路基 17 1355222 0807005/0806006 29048twf.doc/n 制之線路基板_，僅為舉例說 先於線路基板的表Μ鍵製程是 形成於圖案化防銲層上 驟’因此本發明除了可減少所二層光進二固量化= ==過程中溶解量，其具有超過預二== 2魏中熱知該技術者所不易聯想的難度克服。 一圖案化防銲層與第二圖案化防銲層進行 ;吉合；以Π:圖案化防銲層與第-導電層之間的 力。 及弟―®案化將層與第二導電叙間的結合 本已以實_揭露如上，然錢_以限定 =之=屬Γ領域中具有通常知識者，在不脫離 發明圍内’當可作些許之更動與潤飾，故本 X之保4抱圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 意圖圖1Α至圖江是習知一種線路基板電鍍方法的流程示 表:實綠-種線路基板的 1355222 0807005/0806006 29048twf.doc/n 【主要元件符號說明】 10、100 :線路基板 10a、100a :上表面 10b、100b :下表面 20a、110a :第一線路層 20b、110b :第二線路層 30a、130a :第一導電層 30b、130b :第二導電層 • 40a、140a :第一光阻層 40b、140b :第二光阻層 42a :第一圖案化光阻層 42b :第二圖案化光阻層 50a、150a :第一金屬層 50b、150b :第二金屬層 60a、122a :第一圖案化防銲層 60b、122b :第二圖案化防銲層 φ 112a :銲罩定義型的接合墊 112b :非銲罩定義型的接合墊 120a ··第一防銲層 120b :第二防銲層 i S1 19Fortunately, the (4) heterogeneous roughening treatment includes grinding the surface of the second image == layer (10) with an abrasive material or performing plasma bombing or sand blasting on the second patterned anti-frost surface.凊 相 phase 2Η, the county 'forms a second conductive layer on the second square solder layer 122b' and the second conductive layer (four) covers the exposed surface 100b and covers the second circuit layer leg and the first metal layer H = in the present embodiment, 'the second conductive layer is formed on the second patterned anti-fresh layer b, including physical vapor deposition, chemical vapor deposition, chemical liquid phase/child, Wei method or no electricity In the mining method, the physical vapor deposition of the towel is, for example, vacuum evaporation or miscellaneous. The second conductive @ 13% material may be selected from the group consisting of tin, steel, chromium, palladium, nickel, zinc, and alloys thereof. Referring to FIG. 21', a second photoresist layer 14b is formed on the second conductive layer 130b. In the present embodiment, after the second photoresist layer 140b is formed on the second conductive layer 13b, the second photoresist layer 140b is then photocured. The photocuring treatment irradiates an ultraviolet light on the second photoresist layer 14b to thereby solidify the second photoresist layer 140b. Since the etching resistance and chemical resistance of the second photoresist layer 14〇b are relatively increased after the photocuring treatment, the dissolution rate of the second photoresist layer 140b dissolved in the plating solution is slowed down, so that it can be effective. The second photoresist layer 140b is prevented from being dissolved in the electro-mineral solution, thereby reducing the extent to which the second photoresist layer 14b contaminates the electron-mirror solution. It is worth mentioning that, in the present embodiment, after irradiating ultraviolet light to the second photoresist layer 14b, a step of performing a hot air baking step is further included to improve the degree of curing of the photoresist layer. Please refer to FIG. 2J'. Next, the circuit substrate 1 of the above step is placed in the electro-mineral liquid, and the second conductive layer is used as an electric circuit, and the electric ore is formed into a second metal layer 150b for the first-patterned anti-welding. The first wiring layer 110a exposed by the layer ma (the so-called solder mask-defined bonding pad U2a). It should be noted that the second conductive layer 13% is electrically connected to the first circuit layer n〇a through the second circuit layer n〇b and the circuit (not shown) in the circuit substrate 1GG. The formation of the second conductive layer on the same surface of the second circuit layer is completely different. In this embodiment, the material of the second metal layer 150b includes tin, tin alloy, gold or nickel gold, and the second metal layer 150b is used to prevent the first circuit layer (so-called so-called soldering, defined type The bonding pad 112a) is oxidized due to environmental influences, causing a decrease in electrical quality. It is worth mentioning that, in this embodiment, since the second conductive layer 13 covers the second photoresist layer 140b, the second metal layer is formed by electroplating the second conductive layer i3: for the electric 'wide film' l5Qb is in the first layer, and the second photoresist layer 140b can avoid plating metal on the second conductive layer n〇b. In other words, the second photoresist layer 14A can be a resist layer.曰, please refer to FIG. 2K, after which the second photoresist layer 14% and the second guide=13%' peak are removed to expose the subsurface intestine, and the first metal layer is patterned to prevent the solder layer 122b from being removed. The second photoresist layer M〇b and 1355222 0807005/0806006 29〇48twf.doc/n The method of the first conductive layer 13Gb includes a stripping process. At this point, the surface electro-mineralization process of the circuit substrate has been completed. In the subsequent process, for example, the circuit substrate 1 of the present embodiment can be applied to the wafer and the package carrier by wire bonding (WB) or flip chip bonding (FC). Between (package earner). In detail, first, a wafer (not shown) is electrically connected to a non-solder-defining joint 塾 112b of the wiring substrate 1 via a plurality of wires (not shown). Then, the plurality of solder balls formed on the solder mask defining type pad 112a of the circuit substrate 100 are electrically and structurally connected to a loading board (for example, a printed circuit board) (not shown). The two interfaces, the two-element = or both end points respectively located between the circuit substrate 100 and the package carrier can achieve the purpose of signal transmission via the solder balls described above. In short, when the circuit substrate 100 is to be occluded with other components (for example, a package carrier, a wafer, etc.), it can directly pass through the junction-defining joint 112a of the circuit substrate 100 and the non-weld-shielded type joint. The 塾(10) is electrically connected to other components, so that the convenience of using the cymbal substrate 100 can be increased. Further, in the present embodiment, although the surface key routing process of the wiring substrate of the present invention is applied to the wiring substrate having the first wiring layer 110a and the second wiring layer 110b on the upper surface 10a and the lower surface 1b, respectively. The first circuit layer 110a has a plurality of solder mask-defined bonding pads U2a, and the second circuit layer 110b has a plurality of non-welding mask-type bonding pads U2b. The layer of the tree layer = the substrate, and may also have only a single joint. Therefore, the circuit substrate _ line base 17 1355222 0807005/0806006 29048 twf. doc / n made only by way of example, the surface key process prior to the circuit substrate is formed on the patterned solder resist layer. In addition to reducing the amount of dissolution in the process of the two layers of light into two solids ===, it has more than the difficulty of the pre-two == 2 Weizhong knowing that the technology is not easy to associate. A patterned solder mask is applied to the second patterned solder resist layer; the germanium is patterned to pattern the force between the solder resist layer and the first conductive layer. And the brother---the combination of the layer and the second conductive rehearsal has been revealed as above, but the money _ to limit = = belongs to the general knowledge in the field, without leaving the invention Make some changes and refinements, so the X-protection 4 is bounded by the scope of the patent application attached to it. [Simple description of the diagram] Intention Figure 1Α to Tujiang is a flow chart of a conventional circuit board plating method: 1352222 0807005/0806006 29048twf.doc/n of real green-type circuit board [Explanation of main component symbols] 10,100 : circuit substrate 10a, 100a: upper surface 10b, 100b: lower surface 20a, 110a: first wiring layer 20b, 110b: second wiring layer 30a, 130a: first conductive layer 30b, 130b: second conductive layer 40a, 140a: first photoresist layer 40b, 140b: second photoresist layer 42a: first patterned photoresist layer 42b: second patterned photoresist layer 50a, 150a: first metal layer 50b, 150b: second metal layer 60a, 122a: first patterned solder mask layer 60b, 122b: second patterned solder resist layer φ 112a: solder mask defined type bond pad 112b: non-solder cap definition type bond pad 120a · · first solder resist layer 120b: second solder mask i S1 19