TW200834841A - Package with a marking structure and method of the same - Google Patents
Package with a marking structure and method of the same Download PDFInfo
- Publication number
- TW200834841A TW200834841A TW097100207A TW97100207A TW200834841A TW 200834841 A TW200834841 A TW 200834841A TW 097100207 A TW097100207 A TW 097100207A TW 97100207 A TW97100207 A TW 97100207A TW 200834841 A TW200834841 A TW 200834841A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- substrate
- die
- dielectric layer
- metal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
200834841 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種封裝結構’尤其是一種板材級封 晶片尺寸級封裝結構製作方法,其標示結構封袈可保 °結構不受電磁輻射干擾且提供更好之散熱處理。 【先前技術】 处煢午采 “ 回料後電子製造業闻婼更小且更人性化
電子產品,快速發展之半導體技術致使半導體封裝面積I 小’以適應多腳位、高精密崎宫 、、 曰圓级私壯+ 门侑山、、泉見以及極小化電子零件需求 :r路徑,少寄生電容:::::本得= 雜比(SNR)。 丁』又野之彳 晶片級封裝(CSP),_般形成 切割成半導體晶片,接著于牛泠體- f疋:之位置並將之黏著,並將之密封於一樹r中, 者將此雄、封樹脂與基板切割 、曰 /件。另一僂絡方々一*…攻月成為一半導體晶片,
片)黏著於其Λ 體晶圓(尚未切割成為半導體E < 、土板上,接著此半導體晶圓盥, 割分離半導體晶片,並封穿封壯&基板被切割,且戈 更進-步因電路設計 響其操作性、性能與晶片壽命,:與晶圓封褒’皆會悬 裝技術。因為IC晶片之特性與性=敘述便針對晶片封 路之訊號延遲與衰減產生,益掩逮增加,晶片外部電 片封裝於一小面積1C晶片封、电拴i曰加之需求。一晶 x ,其需具良好之散熱以及 6 200834841 保漠,加上較高性能之特 之 目標。 此八為日日片封裝所需達到 ^更進步,因為傳統封裝技術須於晶圓上切〜上 粒,並個別封|曰 刀軎成晶 元件面技術於製程中較為耗時。當 電路a ' 1 /因素’因為晶片封裝技術高度影塑f體 電路開發,封裝技 又〜I知體 發展,由球閘陣=要二=p素’封裝技術之 •級封裝〜至今曰晶圓 :思二,其於個別化(切割)成為晶片(晶粒);;=個 封破以及晶圓内部雷彡 +正们 ’Μ性連結與其他之製 於所有組裴製程或 〇 取 叙而吕 衣柱70成,早獨的半導靜刼壯认曰 圓上被分離,使其具有多 π '衣;曰曰 士斤, 干命篮日日粒。晶圓級封梦苴且 有極小之尺寸,兼具極佳之電氣特性。 衣/ 於製造方法巾’晶圓尺寸級縣(w 裝方法,藉由於^先進封 ⑩並組衰成適合表面黏著生 妾者將-切剔 u Q 座深用因為晶圓級封H #闲敕 片日日圓作為標的,非使用| 正 前,測試也已^ 因此於施行切割製程 打線:曰^ 進一步WLP為今進封裝技術,致使
枯供i + 士 & & 于衣枉』被,略。错由使用WLP =術/、成本與製造時間可被降低,且其結構大 同,此技術可符合電子元件 /、子
1且古m制 '更進一步,WLCSP 為黏著點。此達成〜二糟由使用晶粒區域作 咬取/、日日粒表面上重佈一面陣列,並 此晶粒之整個表面。葬由曰 八 稭由幵y成覆a曰凸塊,此黏著點位於重 7 200834841 佈電路’而於其晶粒背面藉由微小黏著點,直接連結於印 刷電路板(PCB)。 雖然WLCSP可大大地降低訊號路徑長度,旦當其整 合晶粒與内部元件變多時,依然難以容納所有黏著點於晶 粒表面上。當於更高之整合中,腳位於晶粒上增加時,於 有限面積中增加重佈腳數變難以達成。縱使重佈腳數可 $計,其腳位間距將過小,亦將難以符合印刷電路板間距
而求。亦即此敘述之習知結構與製程,將有良率與可靠度 因素之困擾’進一步此製作方式之缺點為更高之製造成本 且更為耗時。 基於前述之觀點,本發明提出一面板尺寸封裝—晶 寸子衣之新結構與方法,其作為可防護電磁干擾並克 服上述缺點之技術。 【發明内容】 本發明前述之形式、目的、 以ΠΓ私A金 硯點、特徵及優點將隨著 乂么Λ施例中詳細的描 顯,1细筋扣n ^ 田义及其伴酼之圖式而愈見明 噚將i隨附之田= 以述明本發明。而本發明之範 通附之專利請求項來定義。 # > =考只月之目地,為藉由一 Psp-Csp製作桿亍钍; 裝之結構與方法,提供半導 構封 不受電磁(EJVO波干擾。、衣’以作為保護結構 本發明之另—目地,為藉由一 一 封裝之結構盘方半 ^ 1作標示結構 销万法’提供一半導 表面使具有較好之外觀。 、衣,於元件之上 8 200834841 本發明之又一目地,為藉由一 psp_c 封襄之結構與方法,提供一半導體元件封裝,構 線作為導熱路徑。 /、可連結地 地屏蔽效能r kw導體元件封裝,其可改進接 件之重佈:路一導體元件封襄’其可保護元 盆勺in提供—具有標示結構封裝之半導體封裝結構, 構形成具有一晶粒容内槽於其中之結 面之上,且其基板下表面上具有導電線路。= 晶粒容納槽中,且具有複數個焊墊於其上,;曰粒 作她妾此焊塾與此通孔結構;-第二介電層 :=Τ=線路之上;一金屬標示層形成於此第 一丨電層,且一散熱層形成於金屬標示層之上。 含-且有方法以作為半導體元件封裝,其結構包 日日粒谷納凹槽之基板,其形成於基板之上表面, 社禮之^孔結構通過此基板’其中具有—終端接點於通孔 '、:⑤方’且此基板包含一導電線路形成於此基板之下 =塾粒於此容納_中’其中晶粒上具有複數 二一介電層於此基板上耳此晶粒露出焊墊 认孔、、、口構;形成一重佈層於此第_介電層之上,以連結 9 200834841 焊墊與此通孔結構;形成—第二介電層於此重佈層. 形成一金屬標示層於此第二介電芦之 曰 ’ 於此金屬標示層之上。 θ 且形成一散熱層 【實施方式】 本發明將以較佳之實施例及觀點加以詳细 類敘述係解釋本發明之結構及程序, L、日日 _ 用以况明而非用以 限制本發明之中請專利範圍。因&,除說明書中之較 施例之外’本發明亦可廣泛實行於其他實施例。 土、 圖一為一根據本發明所述,半導體元件封裝,盆且 -標示結構100之基板尺寸晶片尺寸封褒(psp_cs^ 面圖’其具有-標示結構100之封裝中,其包含一^ 102、-晶粒容納凹槽114、—通孔124、—黏著材料^4、 -晶粒106、複數個焊墊108、一第一介電層11〇 導電層112、-重佈層(RDL)116、一第二介電層ιΐ8、一 金屬標示層120、一散熱層121、一導通線路122、保護声 126以及複數個焊料凸塊128。 曰 於圖-中此基板1〇2具有一晶粒容納凹槽114,其形 成於基板102之上表面以容納一晶粒1〇 二 構124被製成,由基板102之上表面至下表面 H)2。此複數個通孔結構124被填人導電物f以作為電性導 通,此終端接點125形成於基板1〇2下表面之下方,且藉 由此通孔結構124連結’此導通線路122(導線電路)被設^ 於此基板102之下表面之上。 叹 進一步,一晶粒106具有複數個焊墊1〇8黏著於晶粒 200834841 容納晶片114,且此焊墊108被形成於此晶粒1〇6上表面, 於形成重佈層(RDL)之前,此焊墊108之表面為露出。於 形成此第一介電層11 〇於此晶粒1 06以及此基板102上之 後,此第一介電層110之部分區域被移除,以露出焊墊1〇8 之表面與通孔結構124,其介面傳導層112被填入此焊墊 108與此通孔結構124之露出表面,以作為電性之相互連 結。接著此重佈層116被形成於介面導電層1丨2與此第一 肇介電層110之上。亦即此介面導電層112形成於焊墊ι〇8 與此通孔結構124之上表面,為此重佈層116覆蓋,且此 重佈層116可連結此介面導電層112其形成於焊墊1〇8與 通孔結構124之表面上。 下一步驟,一第二介電層118被形成於此第一介電層 110之上,以覆蓋此重佈層116。緊接著此金屬標示層12〇 被形成於此第二介電層118,且接著此散熱層121被形成 於此金屬標示層120之上。複數個焊料凸塊128被形成於 鲁終端接點120之上,且此複數個焊料凸塊1〇8可藉由連接 焊墊108經過通孔結構124形成電性導通。 於一實施例中,此封裝具有一標示結構〗〇〇,其進一 步包含一黏著材料104填入並覆蓋此晶粒容納凹槽114以 固著此晶粒10 6。 於一實施例中,此基板102之材料包含為環氧樹脂 型,FR5、FR4、B —三氮樹脂(Bismaleimide triazine,BT), 亦可為金屬、合金、矽、陶瓷或印刷電路板。其合金進一 步可包含合金42其為較佳例示,其成分為鐵、鎳合金,其 11 200834841 膨脹係數使其適合加人於具微小f子線路 組成成分為42%鎳與58%鐵。其合金成分亦可:丄其 (Kovar),其組成為29%鎳、17%鈷與54%鐵。'、、、。 。至 於一實施例中,此第一介電層u〇 二。入 之材料,可包含苯環丁稀(BCB) 二電€118 聚亞酿華)。此重佈…之材料 包含鈦/銅/金之合金或鈦/銅/鎳/金合金。 〃 於一實施例中’此金屬標示層12〇之材料包含 以作為電磁_干擾之保護。須知本發明所揭露之材料, 僅用於敘述而非用以限制本發明。 ^於一實施例中,此散熱層121之材料,其可包含分子 散熱風扇(molecular cooling fan)於金屬標示声〗 增強散熱。 "
茶照圖二,其為-根據本發明之半導體元件標示結構 封裝之上視圖,其中基板尺寸封裝_晶片尺寸封裝 (PSP-CSP) ’具有-標不金屬層1GG。標示結構⑽之封裝 進 步包含進一步可包含一字型 案或商標130 ’標志於此結構1 〇〇之上表面 文字、一字元 圖 於-實施例中,本發明進-步包含一訊號接地,其連 結至金屬標不層120上,作為接地屏蔽與散熱之用。 根據本發明所述之觀點,當完成psp_csp之增層結 構,一種子金屬層濺鍍於此第二介電層丨丨8之上,此亦即, 此種子金屬層濺鍍於此結構之上表面,此種子金屬層可包 含鈦/銅。下一步驟塗佈光阻(圖中未顯示)於此種子金屬層 12 200834841 上且對光阻作光微影以形成此複數個字元i3〇。一銅/金 電鍵於標示結構封請之表面,其銅/金薄膜厚度約為 2〇微米較佳。接著將光阻層自標示結構封裝1〇〇之 t表㈣去’此種子金屬層可/但不限㈣濕式㈣方式除 一。接者塗佈散熱材料121(分子散熱風扇較佳),於金屬標 不層120,其散熱層121之厚度約為1〇微米。 接著此金屬標示層120與散熱層121形成於標示結構 封裝100之上表面,換言之,具有標示結構之封裝100之 上表面為金屬標示層120與散熱層121所覆蓋,一金膜或 可錢於金屬標示層12G上’且不可覆蓋此複數個金屬標示 曰_ 〇 /員'主思者,其他之金屬材質亦可被用來鍍於金屬 標示層120之上。 於-實施例中’此複數個特徵字元、字、圖案或商標, 包含但不限定於,各種商標、圖案或標誌。 根據本發明之觀點,本發明進一步提供一方法,形成 一具有標示結構封t議’圖三顯示根據本發明所述之一 標示結構封裝1()()形成方式之流程圖,其步驟敘述如下。 於步驟200首先備妥一基板1〇2其具有一晶粒容納凹 槽114形成於此基板之上表面,且具一通孔結構以,其 中具有終端接點125形成於通孔結構124,且此基板1〇2 包含一導電㈣122形成於此基板之上表面。接著步驟2〇2 將一晶粒106粘著於此晶粒容納凹槽114,且此晶粒1〇6 具有複數個焊墊1〇8形成於上。於步驟2〇4將一第一介電 層no覆蓋於基板102與此晶粒106之上,並露出焊墊1〇8 13 200834841 以及通孔結構124。步驟2〇6將導電接觸面μ佈於 108與通孔結構124之露出面上。 、緊接著於步驟208,一重佈層116形成於焊墊1〇8與 L孔、.’σ構124之上,以相互連接。於步驟21 〇,一第二介 =層118形成此重佈層116之上。接著步驟犯,一金屬 標不層120與一散熱層121形成於此第二介電^ 118之 上。於步驟2U,一保護層126形成於此基板1〇2之下表 面’以覆蓋此導電線路122。接著步驟216 凸塊Π8焊接於終端接點⑵。 &數個㈣ 置,月中所示之結構,不限於上述之材料與佈 —構中材料與佈置,可根據不同之需求作調整。 可佯之觀點’本發明提供-金屬標示結構,其 保1“冓不受電磁輻射干擾 :::外觀。進-步本發明提供-扇二 =:作:散熱’且亦可增進接地辱蔽效能。本發: 面其具有微小化之晶片尺寸封裝結構 其供一金屬標示層結構與方法, ^專曰曰片尺寸封裝結構與方法,可获 工業,ft技#之問題,此方法可用於晶圓或面板 ^ 亦可經調整並實施於其他相關應用。 上述敘述係為本發明之較佳實 應得以領會1俜用以J此領域之技藝者 带夕奎… 明本發明而非用以限定本發明所主 張之專利權利範圍。其專利保護範圍當視後附二= 200834841 犯圍及其等同領域而定。凡熟悉此領域之技藝者,在不脫 離本專利精神或範圍内,所作之更動或潤飾,均屬於本發 明所揭示精神下所完成之等效改變或設計,且應包含在下 述之申晴專利範圍内。 【圖式簡單說明】 /本务月可藉由說明書中若干車父佳實施例及詳細敘述以 及後附圖式得以瞭解。然而,此領域之技藝者應得以領會 所有本發明之較佳實施例係用以說明而非用以限制本發明 之申晴專利範圍,其中: 一圖一為一根據本發明所述,半導體元件封裝具有一標 不結構封裝結構之基板尺寸晶片尺寸封裝(psp_csp)之剖 面圖; 一圖二為一根據本發明所述,半導體元件封裝具有一標 不結構之基板尺寸晶片尺寸封裝(PSP-CSP)之上視圖; ⑨圖三為一根據本發明所述方法,半導體元件封裝具有 _ 一標示結構之基板尺寸晶片尺寸封裝(PSP-CSP)之流程圖。 【主要元件符號說明】 標示結構100 基板102 黏著材料104 晶粒106 焊墊108 第一介電層110 接觸面導電層112 15 200834841 容納凹槽114 重佈層(RDL)116 第二介電層118 金屬標示層120 散熱層121 導通線路122 通孔124 終端接點125 ^保護層126 焊料凸塊128 字元130 步驟200(製備一基板於其上表面使具有一晶粒容納凹 槽) 步驟202(黏著一晶粒於晶粒容納凹槽内) 步驟204(形成一第一介電層於基板上) _ 步驟206(形成導電接觸面於焊墊表面上) 步驟208(形成一重佈層於焊墊上方) .步驟210(形成一第二介電層於重佈層之上) 步驟212(形成一標示層與散熱層於第二介電層之上) 步驟214(形成一保護層於基板下表面以覆蓋導電線 路) 步驟216(焊接一複數個焊料凸塊於終端接點) 16
Claims (1)
- 200834841 十、申請專利範圍: 1 · 一半導體元件封裝其具有—標示結構包含: -基板其具有-晶粒容納凹槽於其上表面,且其結構中 具有一通孔結構形成貫通,且呈右 *』 ,、有終端接點形成於此 基板之下表面,以及導電線路形成於此基板之下表面; 一晶粒黏著於此晶粒容納凹槽 、— · τ日且具有一稷數個焊墊於 , 了第-介電層形成於此晶粒與此基板上m此焊塾 與此通孔之表面; 一重佈層形成於此第一介電声 丨电層以耦合此焊墊與此通孔 結構; -第二介電層形成於此第一介電層與此重佈層線路;且 一金屬標示層形成於此第二介電層。 2‘如申請專利範圍第i項所提之結構,進—步包含複數個 馨肖料凸塊形成於此終端接點上,其中此複數個焊料凸塊 可猎由此通孔結構,作為此焊墊間電性傳導。 3·如申請專利範圍第1項所提之結構,進—步包含—保護 層,其形成於此基板之下表面上,以覆蓋此導電線路。 4·如申請專利範圍第i項所提之結構,進一步包含一散熱 層於此金屬標示層上。 17 200834841 5.如申請專利範圍第4項所提之結構,其中此散熱層包含 分子散熱風扇以增強散熱。 6·如申請專利範圍第1項所提之結構,進一步包含一黏著 材料包覆此晶粒容納凹槽以固著此晶粒。 7·如申請專利範圍第1項所提之結構,其中此基板之材料 包含環氧樹脂型態之FR5,FR或Β —三氮樹脂ΒΤ (Bismaleimide triazine)。 8·如申請專利範圍第1項所提之結構,其中此基板之材料 包含金屬、合金、玻璃、矽、陶瓷或印刷電路板。 9·如申請專利範圍第6項所提之結構,其中此合金包含合 金42(42%鎳與58%鐵)柯華合金(〖〇雨)(29%鎳_ π% 始-54%鐵)。 10·如申請專利範圍第丨項所提之結構,其中此通孔為導電 物質所填充。 11 ·如申請專利範圍第丨項所提之結構,其中此第一介電層 與此第二介電層之材料,包含苯環丁烯(BCB)、矽氧烷 向分子(SINR)或聚亞醯胺(pj)。 18 200834841 12·如申請專利範圍第1 金 員所楗之結構,其中此重佈層為合 衣,、匕3鈦/銅/金之合金或鈦/銅/鎳/金合金。 13·如申請專利範圍第1 ,big. ^ 員所棱之結構,其中此重佈層藉由 此通孔結構’向下與此終端接點傳導。 14·如申請專利範圍第1項所 之絲祖甘6人 貞所k之結構,其中此金屬標示層 ο 4其包含金屬以保護此封裝不受電磁輕射干擾。 15.如申請專職圍第1項所提之結構,其中可包含一種子 金屬層賤鑛於此第一與第二介電層之上。 圖案或商標鍍於此金屬標示層 16.如申請專利範圍第1項所提 型、一文字、一字元、 之結構,進一步可包含一字 17.=申請專利範圍第!項所提之結構,進 此孟屬4不|,以#為接地屏蔽與散熱。 1 8 · 一製作半導體元件封裝並一一 含·· ,、,、有一私不結構之方法其包 :備-具有晶粒容納凹槽之基板,其形成 面’以及-通孔結構通過此基板, 於通孔結構之下方,且—人 央〜知接點 基板之下表面;此基板包卜導電線路形成於此 19 200834841 黏著一晶粒於此容納凹槽中,其中 墊; 曰曰粒上具有複數個焊 形成一第一介電層於此基板上且此 孔結構; 晶粒露出焊墊與通 形成一重佈層於此第一介電層之上 孔結構; 以連結焊墊與此通形成一第二介電層於此重佈層之上; 形成一金屬標示層於此第二介電層之上。 19.如申請專利範圍第18項所提之方法,進 焊接複數個焊料凸塊與此終端接點之步驟 步可包含一 如申請專利範圍第18項所提之方法, 塗佈一散熱材料於此金屬標示層之步驟 步可包含 21·如申請專利範圍第18項所提之方法 黏著材料包覆此晶粒容納凹槽以固著 ,進一步可包含一 此晶粒之步驟。 22·如申請專利範圍第18項所提之方法, 訊號接地連接至此金屬標示層之步驟 進一步可包含一 23.如申請專利範圍 刑七〜 丨促及万法,進一步可包含^型、文字、字元、圖案或商棹铲# 匕3 一 知鍍於此金屬標示層之步驟 20 200834841 24.如申請專利範圍第18項所提之方法,其中可包含一種 子金屬層減:鍍於此第一與第二介電層上之步驟。21
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/648,829 US20080157342A1 (en) | 2007-01-03 | 2007-01-03 | Package with a marking structure and method of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200834841A true TW200834841A (en) | 2008-08-16 |
Family
ID=39582724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097100207A TW200834841A (en) | 2007-01-03 | 2008-01-03 | Package with a marking structure and method of the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US20080157342A1 (zh) |
CN (1) | CN101232002A (zh) |
TW (1) | TW200834841A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI681517B (zh) * | 2016-11-29 | 2020-01-01 | 台灣積體電路製造股份有限公司 | 封裝結構、在封裝中傳遞熱量的方法及積體電路晶片 |
TWI726867B (zh) * | 2015-02-23 | 2021-05-11 | 美商艾馬克科技公司 | 半導體封裝及製造其之方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI573201B (zh) * | 2008-07-18 | 2017-03-01 | 聯測總部私人有限公司 | 封裝結構性元件 |
TWI579995B (zh) | 2009-08-19 | 2017-04-21 | Xintex Inc | 晶片封裝體及其製造方法 |
KR101179386B1 (ko) * | 2010-04-08 | 2012-09-03 | 성균관대학교산학협력단 | 패키지 기판의 제조방법 |
CN102237482A (zh) * | 2010-05-07 | 2011-11-09 | 陈一璋 | 高散热led非金属基板与高散热led元件及其制法 |
US20120126399A1 (en) * | 2010-11-22 | 2012-05-24 | Bridge Semiconductor Corporation | Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry |
US8368202B2 (en) * | 2010-11-24 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package having the same |
EP2613349B1 (en) * | 2012-01-05 | 2019-11-20 | Nxp B.V. | Semiconductor package with improved thermal properties |
TWI465163B (zh) * | 2012-04-20 | 2014-12-11 | Bridge Semiconductor Corp | 具有內建加強層之凹穴基板及其製造方法 |
CN105428327B (zh) * | 2014-08-28 | 2018-03-23 | 联华电子股份有限公司 | 扇出型晶片级封装结构 |
TWI571983B (zh) * | 2014-11-25 | 2017-02-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
CN107093593B (zh) * | 2017-03-14 | 2019-08-13 | 深圳市江波龙电子股份有限公司 | 一种封装芯片及封装方法 |
US10644046B2 (en) * | 2017-04-07 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out sensor package and optical fingerprint sensor module including the same |
CN107564872A (zh) * | 2017-08-25 | 2018-01-09 | 广东工业大学 | 一种具备高散热扇出型封装结构的芯片及其制作方法 |
CN107369663A (zh) * | 2017-08-25 | 2017-11-21 | 广东工业大学 | 一种具备正面凸点的扇出型封装结构的芯片及其制作方法 |
US10347574B2 (en) * | 2017-09-28 | 2019-07-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out packages |
CN108091616A (zh) * | 2017-12-15 | 2018-05-29 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装方法以及封装结构 |
CN109564905A (zh) * | 2018-10-30 | 2019-04-02 | 长江存储科技有限责任公司 | Ic封装 |
CN109494163A (zh) * | 2018-11-20 | 2019-03-19 | 苏州晶方半导体科技股份有限公司 | 芯片的封装结构以及封装方法 |
US11978722B2 (en) * | 2021-08-27 | 2024-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and formation method of package containing chip structure with inclined sidewalls |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6448632B1 (en) * | 2000-08-28 | 2002-09-10 | National Semiconductor Corporation | Metal coated markings on integrated circuit devices |
JP4012496B2 (ja) * | 2003-09-19 | 2007-11-21 | カシオ計算機株式会社 | 半導体装置 |
US6984876B2 (en) * | 2004-05-27 | 2006-01-10 | Semiconductor Components Industries, L.L.C. | Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof |
TWI301660B (en) * | 2004-11-26 | 2008-10-01 | Phoenix Prec Technology Corp | Structure of embedding chip in substrate and method for fabricating the same |
US7327030B2 (en) * | 2005-12-16 | 2008-02-05 | Atmel Corporation | Apparatus and method incorporating discrete passive components in an electronic package |
-
2007
- 2007-01-03 US US11/648,829 patent/US20080157342A1/en not_active Abandoned
-
2008
- 2008-01-03 CN CNA2008100000260A patent/CN101232002A/zh not_active Withdrawn
- 2008-01-03 TW TW097100207A patent/TW200834841A/zh unknown
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI726867B (zh) * | 2015-02-23 | 2021-05-11 | 美商艾馬克科技公司 | 半導體封裝及製造其之方法 |
TWI681517B (zh) * | 2016-11-29 | 2020-01-01 | 台灣積體電路製造股份有限公司 | 封裝結構、在封裝中傳遞熱量的方法及積體電路晶片 |
Also Published As
Publication number | Publication date |
---|---|
US20080157342A1 (en) | 2008-07-03 |
CN101232002A (zh) | 2008-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200834841A (en) | Package with a marking structure and method of the same | |
US10157900B2 (en) | Semiconductor structure and manufacturing method thereof | |
TWI600129B (zh) | 玻璃覆晶接合結構 | |
CN206976325U (zh) | 电子装置 | |
TWI377630B (en) | Semiconductor device and fabricating method thereof | |
CN102637608B (zh) | 半导体器件和形成用于3d fo‑wlcsp的垂直互连结构的方法 | |
TWI360188B (en) | A semiconductor package assembly and methods of fo | |
CN102543923B (zh) | 半导体器件及其制造方法 | |
TWI453840B (zh) | 半導體元件的製造方法 | |
TWI260079B (en) | Micro-electronic package structure and method for fabricating the same | |
US20090127702A1 (en) | Package, subassembly and methods of manufacturing thereof | |
TW200836311A (en) | Semiconductor device package with multi-chips and method of the same | |
US7498203B2 (en) | Thermally enhanced BGA package with ground ring | |
TW200843055A (en) | Semiconductor device package to improve functions of heat sink and ground shield | |
TW201138041A (en) | Semiconductor die and method for forming a conductive feature | |
TW200529384A (en) | Semiconductor device and method of manufacturing the same | |
US6781221B2 (en) | Packaging substrate for electronic elements and electronic device having packaged structure | |
TWI297941B (en) | Semiconductor device with electroless plating metal connecting layer and method for fabricating the same | |
CN105206588B (zh) | 半导体封装件及其制造方法 | |
CN108962764A (zh) | 半导体结构的形成方法、半导体芯片、封装方法及结构 | |
US20080290502A1 (en) | Integrated circuit package with soldered lid for improved thermal performance | |
CN114464581A (zh) | 封装结构及其制造方法 | |
TW200901396A (en) | Semiconductor device package having chips | |
US6818475B2 (en) | Wafer level package and the process of the same | |
CN106887420A (zh) | 凸块构造与其构成的内连结构 |