TWI571983B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- TWI571983B TWI571983B TW103140748A TW103140748A TWI571983B TW I571983 B TWI571983 B TW I571983B TW 103140748 A TW103140748 A TW 103140748A TW 103140748 A TW103140748 A TW 103140748A TW I571983 B TWI571983 B TW I571983B
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- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 238000000034 method Methods 0.000 title claims description 29
- 238000005553 drilling Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 238000004891 communication Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 92
- 238000005253 cladding Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 238000010329 laser etching Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 239000007795 chemical reaction product Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
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- 229920002577 polybenzoxazole Polymers 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000001273 butane Substances 0.000 description 1
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- 238000005272 metallurgy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- IJDNQMDRQITEOD-UHFFFAOYSA-N n-butane Chemical compound CCCC IJDNQMDRQITEOD-UHFFFAOYSA-N 0.000 description 1
- OFBQJSOFQDEBGM-UHFFFAOYSA-N n-pentane Natural products CCCCC OFBQJSOFQDEBGM-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/147—Semiconductor insulating substrates
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- H01L23/15—Ceramic or glass substrates
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description
本發明係有關一種封裝製程,特別是關於一種能改善封裝製程良率之電子封裝件及其製法。
貫穿膠體(Through molding via,簡稱TMV)之技術,目前已廣泛運用於半導體領域,其主要技術係利用雷射燒灼方式於封裝膠體表面進行開孔製程,以增加佈線空間。例如,製作扇出型(Fan-Out,簡稱FO)封裝堆疊(Package on Package,簡稱POP)結構時,便會使用該技術。
第1A至1F圖係為習知封裝堆疊裝置之其中一電子封裝件1之製法之剖面示意圖。
如第1A圖所示,設置一如半導體晶片之電子元件10於一第一承載件11之離形層110上,再形成一包覆層13於該離形層110上以覆蓋該電子元件10。
如第1B圖所示,將具有銅箔120之第二承載件12設於該包覆層13上。
如第1C圖所示,移除該第一承載件11及其離形層110,以露出該電子元件10與包覆層13。
如第1D圖所示,以雷射方式或反應性離子蝕刻
(Reactive Ion Etching,簡稱RIE)形成複數通孔130於該電子元件10周邊之包覆層13上。
如第1E圖所示,填入導電材料於該些通孔130中,以形成導電柱14,再於該包覆層13上形成複數線路重佈層(redistribution layer,簡稱RDL)15,以令該線路重佈層15電性連接該導電柱14與電子元件10。
如第1F圖所示,移除該第二承載件12,再利用該銅箔120進行圖案化線路製程,以形成線路結構16,之後再進行切單製程。
惟,習知電子封裝件1之製程中,以封膠材料(即包覆層13)完全包覆該電子元件10,因封膠材料與半導體晶片兩者間的熱膨脹係數(Coefficient of thermal expansion,簡稱CTE)差異過大,故製作過程中或是終端切單產品,皆會有翹曲過大的現象發生,而造成後續製程及最終產品可靠度不佳等問題。
再者,因一次製作該通孔130之深度極深,所需之雷射或反應性離子蝕刻之能量太強,因而會直接破壞該銅箔120,使該導電柱14無法有效電性連接至預定之電路(即該線路結構16),亦即容易損害該銅箔120而影響後續製作該線路結構16之良率,故會造成終端產品之可靠度不佳的問題。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明提供一種電子封裝件,係包括:板體,係具有相對之第一側與第二側,且該板體之第一側上具有凹部與至少一第一開孔,並於該板體之第二側上具有與該第一開孔相通之至少一第二開孔,令該第一開孔與第二開孔構成通孔;電子元件,係設於該凹部中;介電層,係形成於該板體之第一側與該電子元件上;線路層,係形成於該介電層上並電性連接該電子元件;以及導電體,係設於該通孔中,且具有設於該第一開孔中並電性連接該線路層之第一導電部、及設於該第二開孔中並電性連接該第一導電部之第二導電部。
前述之電子封裝件中,該第一導電部與第二導電部之間係具有交界面。
本發明復提供一種電子封裝件之製法,係包括:提供一具有相對之第一側與第二側之板體,該板體之第一側上具有凹部與至少一第一開孔;置放一電子元件於該凹部中;形成介電層於該板體之第一側與該電子元件上;形成線路層於該介電層上,且該線路層電性連接該電子元件,又該線路層具有延伸至該第一開孔中之第一導電部;形成至少一第二開孔於該板體之第二側上,且該第二開孔與該第一開孔相通,令該第一開孔與第二開孔構成通孔;以及形成第二導電部於該第二開孔中,使該第二導電部電性連接該第一導電部,以於該通孔中形成導電體。
前述之製法中,該凹部係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
前述之製法中,該第一開孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
前述之製法中,該凹部之深度係大於該第一開孔之深度。
前述之製法中,該第二開孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
前述之電子封裝件及其製法中,該板體係為半導體板材。
前述之電子封裝件及其製法中,該介電層復形成於該第一開孔之孔壁上,使該第一導電部形成於該介電層上。
前述之電子封裝件及其製法中,復包括形成止蝕層於該第一開孔中,使該第一導電部形成於該止蝕層上。例如,於形成該第二導電部之前,先移除該通孔中之止蝕層,令該第一導電部外露於該通孔。
前述之電子封裝件及其製法中,復包括於形成該線路層之前,形成導電塊體於該第一開孔中,令該第一導電部形成於該導電塊體上,故該導電體復具有導電塊體,係設於該第一開孔中並位於該第一導電部與該第二導電部之間,使該第一導電部藉由該導電塊體電性連接該第二導電部。
前述之電子封裝件及其製法中,復包括形成絕緣層於該第二開孔之孔壁上,使該第二導電部形成於該絕緣層上。
另外,前述之電子封裝件及其製法中,復包括形成線路重佈結構於該板體之第二側上,且該線路重佈結構電性
連接該第二導電部。
由上可知,本發明之電子封裝件及其製法中,藉由該板體與該電子元件之間的熱膨脹係數相似,故可避免該板體於部分製作過程中因升溫降溫而發生翹曲的現象,以提升製程中及終端產品之良率。
再者,藉由兩階段製程製作該通孔,使每一次所需製作的孔深減小,故所需之雷射或反應性離子蝕刻之能量不需太強,以避免破壞該第一導電部,故能避免終端產品之可靠度不佳的問題。
1、2、3‧‧‧電子封裝件
10、21‧‧‧電子元件
11‧‧‧第一承載件
110‧‧‧離形層
12‧‧‧第二承載件
120‧‧‧銅箔
13、22‧‧‧包覆層
130、260‧‧‧通孔
14‧‧‧導電柱
15、291‧‧‧線路重佈層
16‧‧‧線路結構
20‧‧‧板體
20a‧‧‧第一側
20b、20b’‧‧‧第二側
200‧‧‧凹部
201‧‧‧第一開孔
202‧‧‧第二開孔
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
211‧‧‧結合層
212‧‧‧保護層
23‧‧‧介電層
24‧‧‧止蝕層
25‧‧‧線路層
250‧‧‧導電盲孔
26、36‧‧‧導電體
261‧‧‧第一導電部
262‧‧‧第二導電部
27a、27b‧‧‧絕緣保護層
28a、28b‧‧‧導電元件
280‧‧‧凸塊底下金屬層
29‧‧‧線路重佈結構
290‧‧‧絕緣層
34‧‧‧導電塊體
h、d‧‧‧深度
w、r‧‧‧寬度
X‧‧‧交界面
第1A至1F圖係為習知電子封裝件之製法之剖面示意圖;第2A至2H圖係為本發明電子封裝件之製法之剖視示意圖;以及第3A至3C圖係為本發明電子封裝件之製法之另一實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例
關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明電子封裝件2之製法之剖視示意圖。
如第2A圖所示,提供一具有相對之第一側20a與第二側20b之板體20,該板體20之第一側20a上具有凹部200與複數第一開孔201。
於本實施例中,該板體20係為半導體板材,如矽板材或玻璃板材,且該凹部200與該第一開孔201係以雷射鑽孔、機械鑽孔或蝕刻方式(如反應性離子蝕刻)形成者。
再者,該凹部200之深度h係大於該第一開孔201之深度d,且各該第一開孔201係位於該凹部200周邊區域。
如第2B圖所示,藉由一結合層211置放一電子元件21於該凹部200中。
於本實施例中,該電子元件21係為主動元件、被動元件或其組合者,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於此,該電子元件21係為半導體晶片,其具有相對之作用面21a與非作用面21b,且該作用面21a具有一保護層212與複數電極墊210,
而該非作用面21b藉由該結合層211結合至該凹部200中。
如第2C圖所示,先形成一包覆層22於該板體20之第一側20a上及該凹部200中以包覆該電子元件21周圍,再形成一介電層23於該第一開孔201之孔壁、該包覆層22與該電子元件21之作用面21a上。接著,形成一止蝕層24於該介電層23上。
於本實施例中,形成該包覆層22之材質係為絕緣材,例如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
再者,形成該介電層23之材質係為無機材質,如氧化矽(SiO2)、氮化矽(SixNy)等、或有機材質,如聚醯亞胺(Polyimide,PI)、聚對二唑苯(Polybenzoxazole,PBO)、苯環丁烯(Benzocyclclobutene,BCB)等。
又,形成該止蝕層24之材質係為氮化矽,以供蝕刻液於矽材與氮化矽之間具有高選擇性。
如第2D圖所示,進行線路重佈層(redistribution layer,簡稱RDL)製程,即形成一線路層25於該介電層23上之止蝕層24上,且該線路層25具有貫穿該介電層23與該止蝕層24之複數導電盲孔250以電性連接該電子元件21之部分電極墊210,又該線路層25具有延伸至該第一開孔201中之第一導電部261,使該第一導電部261形成於該介電層23上之止蝕層24上。
於本實施例中,該線路層25(含第一導電部261)可利用電鍍、沉積或其它習知技術形成如含銅、鋁、鈦或導
電膠之方式進行製作。具體地,該第一導電部261係為金屬柱,例如銅柱。
如第2E圖所示,形成一絕緣保護層27a於該止蝕層24與線路層25上,以令該線路層25之部分表面外露於該絕緣保護層27a,供結合如銲球之導電元件28a。
如第2F圖所示,先移除該板體20之第二側20b之部分材質,再形成複數第二開孔202於該板體20之第二側20b’上,且該第二開孔202與該第一開孔201相通,令該第一開孔201與第二開孔202構成通孔260。
於本實施例中,於本實施例中,該第二開孔202係以雷射鑽孔、機械鑽孔或蝕刻方式(如反應性離子蝕刻)形成者。
如第2G圖所示,先移除該通孔260中之止蝕層24與介電層23,令該第一導電部261外露於該通孔260,再形成一線路重佈結構29於該板體20之第二側20b’上,且形成第二導電部262於該第二開孔202中,使該第二導電部262電性連接該第一導電部261,以於該通孔260中形成由該第一導電部261與第二導電部262構成之導電體26。
於本實施例中,該線路重佈結構29係包含一設於該板體20之第二側20b’上之絕緣層290、及一設於該絕緣層290上之線路重佈層(RDL)291,且該線路重佈層291電性連接該第二導電部262。具體地,該線路重佈層291與第二導電部262可利用電鍍、沉積或其它習知技術形成如含銅、鋁、鈦或導電膠之方式一體製作。
再者,該絕緣層290復延伸至該第二開孔202之孔壁上,使該第二導電部262形成於該絕緣層290上。
又,該第一導電部261之寬度w小於該第二導電部262之寬度r。
如第2H圖所示,形成一絕緣保護層27b於該線路重佈結構29上,以令該線路重佈層291之部分表面外露於該絕緣保護層27b,供結合如銲球之導電元件28b,其中,可依需求,形成凸塊底下金屬層(Under Bump Metallurgy,簡稱UBM)280於該線路重佈層291與該導電元件28b之間。之後進行切單製程。
於另一實施例中,如第3A至3B圖所示,於形成該線路層25之前,形成導電塊體34於該第一開孔201中之介電層23上,令該第一導電部261形成於該導電塊體34上,以於後續形成第二開孔202時,供蝕刻液於矽材與該導電塊體34之間具有高選擇性,因此,無需形成止蝕層。
於本實施例中,該導電塊體34係為銲錫材料。
再者,後續如第3C圖所示,該導電塊體34係位於該第一導電部261與該第二導電部262之間,使該第一導電部261藉由該導電塊體34電性連接該第二導電部262,亦即該導電體36復包含該導電塊體34。
又,該第一導電部261之寬度等於該第二導電部262之寬度。
本發明之製法中,由於該板體20係為半導體板材,使其與該電子元件21之間的熱膨脹係數(CTE)相似,故相
較於習知以封膠材料包覆該電子元件,本發明可避免該板體20於部分製作過程中因升溫降溫而發生翹曲(warpage)的現象,因而能避免該導電盲孔250與該電極墊210間之對位不準確,或因翹曲度過大而造成該電子元件21破裂之問題發生,因此,可提升製程中及終端產品之良率。
再者,藉由兩階段製程(即製作第一開孔201與第二開孔202)製作該通孔260,使所需製作的孔深減小(即該第一開孔201與第二開孔202之深度),故所需之雷射或反應性離子蝕刻之能量不需太強,因而於製作該第二開孔202時,不會破壞該第一導電部261,使該導電體26能有效電性連接該線路層25與該線路重佈層291,故能避免終端產品之可靠度不佳的問題。
又,藉由佈設一止蝕層24、或填入導電塊體34以當作蝕刻(乾式蝕刻)或雷射用之停止層(Stop layer),故能避免於製作該第二開孔202時破壞該第一導電部261之問題。
本發明提供一種電子封裝件2,3,係包括:一板體20、一電子元件21、一介電層23、一線路層25以及複數導電體26,36。
所述之板體20係為半導體板材,其具有相對之第一側20a與第二側20b’,且該板體20之第一側20a上具有一凹部200與複數第一開孔201,並於該板體20之第二側20b’上具有與各該第一開孔201相通之複數第二開孔202,令該些第一開孔201與該些第二開孔202構成複數通孔260。
所述之電子元件21係設於該凹部200中。
所述之介電層23係形成於該板體20之第一側20a、該第一開孔201之孔壁與該電子元件21上。
所述之線路層25係形成於該介電層23上並電性連接該電子元件21。
所述之導電體26,36係設於該通孔260中,且該導電體26具有設於該第一開孔201中並電性連接該線路層25之第一導電部261、及設於該第二開孔202中並電性連接該第一導電部261之第二導電部262,使該第一導電部261形成於該介電層23上。
於一實施例中,各該第一導電部261與各該第二導電部262之間係具有一交界面X。
於一實施例中,所述之電子封裝件2復包括一止蝕層24,係設於各該第一開孔201之孔壁之介電層23上,使各該第一導電部261形成於該止蝕層24上。
於一實施例之電子封裝件3中,該導電體36復具有導電塊體34,係設於各該第一開孔201中並位於各該第一導電部261與各該第二導電部262之間,使各該第一導電部261藉由該些導電塊體34電性連接各該第二導電部262。
於一實施例中,所述之電子封裝件2,3復包括一絕緣層290,係形成於各該第二開孔202之孔壁上,使該些第二導電部262形成於該絕緣層290上。
於一實施例中,所述之電子封裝件2,3復包括一線路重佈結構29,係形成於該板體20之第二側20b’上並電性
連接各該第二導電部262。
綜上所述,本發明之電子封裝件及其製法中,藉由該板體與該電子元件之間的熱膨脹係數相似,故可避免該板體於部分製作過程中因升溫降溫而發生翹曲的現象,以提升製程中及終端產品之良率。
再者,藉由兩階段製程製作該通孔,使每一次所需製作的孔深減小,故所需之雷射或反應性離子蝕刻之能量不需太強,以避免破壞該第一導電部,故能避免終端產品之可靠度不佳的問題。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧板體
20a‧‧‧第一側
20b’‧‧‧第二側
200‧‧‧凹部
201‧‧‧第一開孔
202‧‧‧第二開孔
22‧‧‧包覆層
23‧‧‧介電層
24‧‧‧止蝕層
25‧‧‧線路層
26‧‧‧導電體
261‧‧‧第一導電部
262‧‧‧第二導電部
27a、27b‧‧‧絕緣保護層
28a、28b‧‧‧導電元件
280‧‧‧凸塊底下金屬層
29‧‧‧線路重佈結構
290‧‧‧絕緣層
291‧‧‧線路重佈層
260‧‧‧通孔
Claims (15)
- 一種電子封裝件,係包括:板體,係具有相對之第一側與第二側,且該板體之第一側上具有凹部與至少一第一開孔,並於該板體之第二側上具有與該第一開孔相通之至少一第二開孔,令該第一開孔與第二開孔構成通孔;電子元件,係設於該凹部中;介電層,係形成於該板體之第一側上並覆蓋於該電子元件上;線路層,係形成於該介電層上並電性連接該電子元件;以及導電體,係設於該通孔中,且具有設於該第一開孔中並電性連接該線路層之第一導電部、設於該第二開孔中並電性連接該第一導電部之第二導電部、及設於該第一開孔中並位於該第一導電部與該第二導電部之間的導電塊體,使該第一導電部藉由該導電塊體電性連接該第二導電部,其中,該導電塊體未設於該第二開孔中。
- 如申請專利範圍第1項所述之電子封裝件,其中,該板體係為半導體板材。
- 如申請專利範圍第1項所述之電子封裝件,其中,該介電層復形成於該第一開孔之孔壁上,使該第一導電部形成於該介電層上。
- 如申請專利範圍第1項所述之電子封裝件,其中,該第一導電部與第二導電部之間係具有交界面。
- 如申請專利範圍第1項所述之電子封裝件,復包括絕緣層,係形成於該第二開孔之孔壁上,使該第二導電部形成於該絕緣層上。
- 如申請專利範圍第1項所述之電子封裝件,復包括線路重佈結構,係形成於該板體之第二側上並電性連接該第二導電部。
- 一種電子封裝件之製法,係包括:提供一具有相對之第一側與第二側之板體,該板體之第一側上具有凹部與至少一第一開孔;置放一電子元件於該凹部中;形成介電層於該板體之第一側上,以令該介電層覆蓋於該電子元件上;形成導電塊體於該第一開孔中;形成線路層於該介電層上,且該線路層電性連接該電子元件,又該線路層具有延伸至該第一開孔中之第一導電部,令該第一導電部形成於該導電塊體上;形成至少一第二開孔於該板體之第二側上,且該第二開孔與該第一開孔相通,令該第一開孔與第二開孔構成通孔;以及形成第二導電部於該第二開孔中,使該導電塊體位於該第一導電部與該第二導電部之間,且該第二導電部藉由該導電塊體電性連接該第一導電部,以於該通孔中形成導電體,其中,該導電塊體未設於該第二開孔中。
- 如申請專利範圍第7項所述之電子封裝件之製法,其 中,該板體係為半導體板材。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該凹部係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該第一開孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該凹部之深度係大於該第一開孔之深度。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該介電層復形成於該第一開孔之孔壁上,使該第一導電部形成於該介電層上。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該第二開孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
- 如申請專利範圍第7項所述之電子封裝件之製法,復包括形成絕緣層於該第二開孔之孔壁上,使該第二導電部形成於該絕緣層上。
- 如申請專利範圍第7項所述之電子封裝件之製法,復包括形成線路重佈結構於該板體之第二側上,且該線路重佈結構電性連接該第二導電部。
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TW103140748A TWI571983B (zh) | 2014-11-25 | 2014-11-25 | 電子封裝件及其製法 |
CN201410763563.6A CN105742273A (zh) | 2014-11-25 | 2014-12-11 | 电子封装件及其制法 |
US14/833,586 US20160148873A1 (en) | 2014-11-25 | 2015-08-24 | Electronic package and fabrication method thereof |
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US10566261B2 (en) | 2017-11-15 | 2020-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out packages with embedded heat dissipation structure |
US10504841B2 (en) * | 2018-01-21 | 2019-12-10 | Shun-Ping Huang | Semiconductor package and method of forming the same |
US11031345B2 (en) * | 2018-08-14 | 2021-06-08 | Medtronic, Inc. | Integrated circuit package and method of forming same |
US11270920B2 (en) * | 2018-08-14 | 2022-03-08 | Medtronic, Inc. | Integrated circuit package and method of forming same |
US11004816B2 (en) | 2018-08-28 | 2021-05-11 | Industrial Technology Research Institute | Hetero-integrated structure |
CN110211931A (zh) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | 一种三维封装结构及其制造方法 |
CN110620053B (zh) * | 2019-09-06 | 2021-09-03 | 广东佛智芯微电子技术研究有限公司 | 具有激光开孔阻挡层的扇出型封装结构及其制备方法 |
TWI714269B (zh) * | 2019-09-19 | 2020-12-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
CN110867429A (zh) * | 2019-12-09 | 2020-03-06 | 上海先方半导体有限公司 | 一种tsv转接板互连结构 |
CN111312697B (zh) * | 2020-02-28 | 2022-02-22 | 西安微电子技术研究所 | 一种三维堆叠集成结构及其多芯片集成结构和制备方法 |
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