CN107369663A - 一种具备正面凸点的扇出型封装结构的芯片及其制作方法 - Google Patents
一种具备正面凸点的扇出型封装结构的芯片及其制作方法 Download PDFInfo
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Abstract
本申请公开了一种具备正面凸点的扇出型封装结构的芯片,包括散热基板,所述散热基板的正面开设有至少一个芯片槽,所述芯片槽中粘接有芯片本体,所述芯片本体的正面和侧面、所述散热基板的正面均覆盖有介电层,所述芯片本体的正面连接有铜凸点,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球,所述金属线路的正面除了所述金属球的位置之外均设置有保护层。上述具备正面凸点的扇出型封装结构的芯片及其制作方法,能够在低成本的基础上有效提高芯片的散热效果,优化线路布局,且无需引线框架。
Description
技术领域
本发明属于芯片封装技术领域,特别是涉及一种具备正面凸点的扇出型封装结构的芯片及其制作方法。
背景技术
目前,电子信息技术已经深入到国民经济的各个领域,与我们的日常生活息息相关。微电子IC芯片封装技术是指把构成电子组件、模块的各个元件和芯片,按规定的电路要求合理布置、组装、键合、互联,并与外部环境隔离,从而达到保护的一种综合设计与制造技术。不同的封装技术在制造工序和工艺方面差异很大,封装后对内存芯片自身性能的发挥也起到至关重要的作用。随着光电、微电制造工艺技术的飞速发展,电子产品始终在朝着更小、更轻和更便宜的方向发展,因此芯片元件的封装形式也不断得到改进。
现有的芯片封装结构中,芯片大多被包裹在注塑体中,主要通过与芯片连接的金属与外界进行热传递,散热能力有限,这疾苦会影响芯片运行的稳定性。一种现有技术是塑料基板材质为芯片承载底板的封装,特别是球型阵列封装多采用塑料基板材质,但由于塑料基板本身的导热性能较差,导致散热效果不佳,还有现有技术采用金属线实现电互联的封装结构,多通过高分子环氧树脂材料将芯片粘结在承载板上,树脂本身的散热效果较差,芯片主要透过树脂中添加的金属颗粒进行热传导,为了达到更好的散热效果而选用金属颗粒所占比例较高的合成树脂,造成树脂比例的相对下降,降低了其与芯片、承载板之间的粘结力,进而出现因粘结力不强、金属颗粒高比例带来的高应力残留而导致的分层等可靠性问题,还有受本身的封装结构限制而散热不佳的半导体封装,也有采用高导热塑封料的方式来提高散热效果,但高导热塑封料除了本身高昂的***格外,对产品塑封工艺的控制也提出了更高的要求,且散热效果不明显。
发明内容
为解决上述问题,本发明提供了一种具备正面凸点的扇出型封装结构的芯片及其制作方法,能够在低成本的基础上有效提高芯片的散热效果,优化线路布局,且无需引线框架。
本发明提供的一种具备正面凸点的扇出型封装结构的芯片,包括散热基板,所述散热基板的正面开设有至少一个芯片槽,所述芯片槽中粘接有芯片本体,所述芯片本体的正面和侧面、所述散热基板的正面均覆盖有介电层,所述芯片本体的正面连接有铜凸点,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球,所述金属线路的正面除了所述金属球的位置之外均设置有保护层。
优选的,在上述具备正面凸点的扇出型封装结构的芯片中,所述散热基板为铜基板或陶瓷基板。
优选的,在上述具备正面凸点的扇出型封装结构的芯片中,所述芯片本体利用Die-Attach胶与所述芯片槽粘接。
优选的,在上述具备正面凸点的扇出型封装结构的芯片中,所述散热基板的厚度范围为0.5毫米至5.0毫米。
优选的,在上述具备正面凸点的扇出型封装结构的芯片中,所述介电层为ABF层、BCB层或PI层。
优选的,在上述具备正面凸点的扇出型封装结构的芯片中,所述金属线路为铜线或银线。
本发明提供的一种具备正面凸点的扇出型封装结构的芯片的制作方法,包括:
在散热基板的正面开设至少一个芯片槽;
所述芯片槽中粘接芯片本体,在所述芯片本体的正面植入铜凸点;
所述芯片本体的正面和侧面、所述散热基板的正面均覆盖介电层;
在所述介电层表面制作金属种子层,并电镀金属线路;
在所述金属线路需要保护的部分覆盖光阻膜,刻蚀掉不需要保护的区域的金属线路和金属种子层,并去除所述光阻膜;
在所述金属线路的正面设置保护层,在所述散热基板的正面预留出植球区域,并在所述植球区域植入金属球,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球;
去除多余的介电层,切割出单个芯片。
优选的,在上述具备正面凸点的扇出型封装结构的芯片的制作方法中,所述在散热基板的正面开设至少一个芯片槽为:
在铜基板或陶瓷基板的正面开设至少一个芯片槽。
通过上述描述可知,本发明提供的上述具备正面凸点的扇出型封装结构的芯片及其制作方法,由于该芯片包括散热基板,所述散热基板的正面开设有至少一个芯片槽,所述芯片槽中粘接有芯片本体,所述芯片本体的正面和侧面、所述散热基板的正面均覆盖有介电层,所述芯片本体的正面连接有铜凸点,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球,所述金属线路的正面除了所述金属球的位置之外均设置有保护层,因此能够在低成本的基础上有效提高芯片的散热效果,优化线路布局,且无需引线框架。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1为本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片的示意图;
图2为本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片的制作方法的示意图。
具体实施方式
本发明的核心思想在于提供一种具备正面凸点的扇出型封装结构的芯片及其制作方法,能够在低成本的基础上有效提高芯片的散热效果,优化线路布局,且无需引线框架。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片如图1所示,图1为本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片的示意图,该芯片包括散热基板1,该散热基板1的材质可以是但不限于铜或者陶瓷,只要具有足够高的散热性能即可,所述散热基板1的正面开设有至少一个芯片槽2,这里开设的芯片槽2可以是二个以上,这是根据实际需要而定的,此处并不限制,且芯片槽的深度和宽度并不限制,所述芯片槽2中粘接有芯片本体3,这种在散热基板上开槽直接粘接芯片本体的方式能够实现更好的散热效果,而且需要重点说明的是,采用本方案,就能够在同一个基板上开设具有不同尺寸的芯片槽,从而放置不同种类的芯片本体,实现多种芯片本体的同时封装,大大提高封装效率,也能缩小封装结构整体的体积,所述芯片本体3的正面和侧面、所述散热基板1的正面均覆盖有介电层4,所述芯片本体1的正面连接有铜凸点5,所述铜凸点5利用经过所述介电层4的正面的金属线路连接至位于所述散热基板1正面的金属球6,所述金属线路的正面除了所述金属球6的位置之外均设置有保护层7,在这种情况下,芯片本体产生的热量可以直接传导到散热基板上,再通过散热基板传导到外部,没有环氧树脂或其他隔热材料的阻挡,实现更加快速的散热。
通过上述描述可知,本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片,由于包括散热基板,所述散热基板的正面开设有至少一个芯片槽,所述芯片槽中粘接有芯片本体,所述芯片本体的正面和侧面、所述散热基板的正面均覆盖有介电层,所述芯片本体的正面连接有铜凸点,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球,所述金属线路的正面除了所述金属球的位置之外均设置有保护层,因此能够在低成本的基础上有效提高芯片的散热效果,优化线路布局,且无需引线框架。
本申请实施例提供的第二种具备正面凸点的扇出型封装结构的芯片,是在上述第一种具备正面凸点的扇出型封装结构的芯片的基础上,还包括如下技术特征:
所述散热基板为铜基板或陶瓷基板。
由于铜和陶瓷的导热性能极佳,因此采用铜基板或陶瓷基板对芯片的散热效果会大大提高,且将芯片直接贴装在铜基板或陶瓷基板上,不需要定制引线框架,且可以根据需求进行多个同一型芯片,甚至多个不同型号芯片的混装,降低制造成本,提高芯片的生产效率。
本申请实施例提供的第三种具备正面凸点的扇出型封装结构的芯片,是在上述第一种具备正面凸点的扇出型封装结构的芯片的基础上,还包括如下技术特征:
所述芯片本体利用Die-Attach胶与所述芯片槽粘接。
需要说明的是,这种优选方案采用的DA胶(Die-Attach胶)是芯片贴装用胶,其主要成分为环氧树脂、银粉和其他添加剂,主要起到的作用是粘接芯片与基板,其导电和导热性能更好,从而进一步实现芯片良好的散热效果。
本申请实施例提供的第四种具备正面凸点的扇出型封装结构的芯片,是在上述第一种具备正面凸点的扇出型封装结构的芯片的基础上,还包括如下技术特征:
所述散热基板的厚度范围为0.5毫米至5.0毫米。
需要说明的是,散热基板不能太厚,这样就最大限度降低对热量的阻挡,也不能太薄,这样就保证能够在其上设置芯片槽,因此这种方案一般优选为0.5毫米至5.0毫米,兼顾散热和加工两方面。
本申请实施例提供的第五种具备正面凸点的扇出型封装结构的芯片,是在上述第一种具备正面凸点的扇出型封装结构的芯片的基础上,还包括如下技术特征:
所述介电层为ABF层、BCB层或PI层。
其中,所述ABF层为积层板用绝缘树脂材料,所述BCB层为苯并环丁烯绝缘树脂材料,所述PI层为聚酰亚胺复合绝缘材料。
本申请实施例提供的第六种具备正面凸点的扇出型封装结构的芯片,是在上述第一种至第五种具备正面凸点的扇出型封装结构的芯片中任一种的基础上,还包括如下技术特征:
所述金属线路为铜线或银线。
需要说明的是,这种铜线或银线具有更好的散热性能,因此这里可以优选为这两种,当然还可以选用其他种类的散热性能好的金属线路,此处并不限制。
本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片的制作方法如图2所示,图2为本申请实施例提供的第一种具备正面凸点的扇出型封装结构的芯片的制作方法的示意图,该方法包括如下步骤:
S1:在散热基板的正面开设至少一个芯片槽;
其中,芯片槽深度为芯片高度加上粘合胶的厚度,这里开设的芯片槽可以是二个以上,根据实际需要而定,还可以同时具有不同尺寸的芯片槽,以适应不同尺寸的芯片本体,以提高制作效率。
S2:所述芯片槽中粘接芯片本体,在所述芯片本体的正面植入铜凸点;
具体的,在芯片槽内涂上DA粘和胶,将芯片本体贴装在芯片槽中,使得芯片本体的上表面与散热基板的上表面相平齐。
S3:所述芯片本体的正面和侧面、所述散热基板的正面均覆盖介电层;
具体的,可以用激光将铜凸点上方的介电层去除,露出铜凸点。
S4:在所述介电层表面制作金属种子层,并电镀金属线路;
首先对基板的上下表面进行金属化处理,制作金属种子层,使得后续能够对其进行电镀金属线路,金属种子层表面电镀一层导电材料(如铜、银等),然后覆盖光阻膜,在需要保护的上下金属线路部分覆盖一层光阻膜;蚀刻掉多余的铜,蚀刻掉光阻膜之外未保护的金属;快速蚀刻金属化层,对基板表面进行快速蚀刻,去掉除金属线路以外的金属化层;去除光阻膜。
S6:在所述金属线路的正面设置保护层,在所述散热基板的正面预留出植球区域,并在所述植球区域植入金属球,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球;
需要说明的是,这种保护层可以是热固型聚合物,能够对线路实行有效的保护。
S7:去除多余的介电层,切割出单个芯片。
这样就形成了一个个的单一芯片产品。
本申请实施例提供的第二种具备正面凸点的扇出型封装结构的芯片的制作方法,是在上述第一种具备正面凸点的扇出型封装结构的芯片的制作方法的基础上,还包括如下技术特征:
所述在散热基板的正面开设至少一个芯片槽为:
在铜基板或陶瓷基板的正面开设至少一个芯片槽。
由于铜和陶瓷的导热性能极佳,因此采用铜基板或陶瓷基板对芯片的散热效果会大大提高,且将芯片本体直接贴装在铜基板或陶瓷基板上,不需要定制引线框架,且可以根据需求进行多个同一型芯片本体,甚至多个不同型号芯片本体的混装,降低制造成本,提高芯片的生产效率。
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims (8)
1.一种具备正面凸点的扇出型封装结构的芯片,其特征在于,包括散热基板,所述散热基板的正面开设有至少一个芯片槽,所述芯片槽中粘接有芯片本体,所述芯片本体的正面和侧面、所述散热基板的正面均覆盖有介电层,所述芯片本体的正面连接有铜凸点,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球,所述金属线路的正面除了所述金属球的位置之外均设置有保护层。
2.根据权利要求1所述的具备正面凸点的扇出型封装结构的芯片,其特征在于,所述散热基板为铜基板或陶瓷基板。
3.根据权利要求1所述的具备正面凸点的扇出型封装结构的芯片,其特征在于,所述芯片本体利用Die-Attach胶与所述芯片槽粘接。
4.根据权利要求1所述的具备正面凸点的扇出型封装结构的芯片,其特征在于,所述散热基板的厚度范围为0.5毫米至5.0毫米。
5.根据权利要求1所述的具备正面凸点的扇出型封装结构的芯片,其特征在于,所述介电层为ABF层、BCB层或PI层。
6.根据权利要求1-5任一项所述的具备正面凸点的扇出型封装结构的芯片,其特征在于,所述金属线路为铜线或银线。
7.一种具备正面凸点的扇出型封装结构的芯片的制作方法,其特征在于,包括:
在散热基板的正面开设至少一个芯片槽;
所述芯片槽中粘接芯片本体,在所述芯片本体的正面植入铜凸点;
所述芯片本体的正面和侧面、所述散热基板的正面均覆盖介电层;
在所述介电层表面制作金属种子层,并电镀金属线路;
在所述金属线路需要保护的部分覆盖光阻膜,刻蚀掉不需要保护的区域的金属线路和金属种子层,并去除所述光阻膜;
在所述金属线路的正面设置保护层,在所述散热基板的正面预留出植球区域,并在所述植球区域植入金属球,所述铜凸点利用经过所述介电层的正面的金属线路连接至位于所述散热基板正面的金属球;
去除多余的介电层,切割出单个芯片。
8.根据权利要求7所述的具备正面凸点的扇出型封装结构的芯片的制作方法,其特征在于,所述在散热基板的正面开设至少一个芯片槽为:
在铜基板或陶瓷基板的正面开设至少一个芯片槽。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111430326A (zh) * | 2020-03-05 | 2020-07-17 | 广东工业大学 | 一种嵌入式高散热扇出型封装结构及封装方法 |
CN117471134A (zh) * | 2023-12-28 | 2024-01-30 | 成都天成电科科技有限公司 | 一种芯片测试夹具 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6544812B1 (en) * | 2000-11-06 | 2003-04-08 | St Assembly Test Service Ltd. | Single unit automated assembly of flex enhanced ball grid array packages |
CN1543675A (zh) * | 2000-12-15 | 2004-11-03 | ض� | 具有无凸块的叠片互连层的微电子组件 |
US20050280141A1 (en) * | 2004-06-21 | 2005-12-22 | Broadcom Corporation | Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same |
US20070231953A1 (en) * | 2006-03-31 | 2007-10-04 | Yoshihiro Tomita | Flexible interconnect pattern on semiconductor package |
CN101232002A (zh) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | 一具有标示结构之封装及其方法 |
CN104882416A (zh) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | 具有堆叠式封装能力的半导体封装件及其制作方法 |
CN105957845A (zh) * | 2016-07-11 | 2016-09-21 | 华天科技(昆山)电子有限公司 | 一种带有电磁屏蔽的芯片封装结构及其制作方法 |
-
2017
- 2017-08-25 CN CN201710742257.8A patent/CN107369663A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6544812B1 (en) * | 2000-11-06 | 2003-04-08 | St Assembly Test Service Ltd. | Single unit automated assembly of flex enhanced ball grid array packages |
CN1543675A (zh) * | 2000-12-15 | 2004-11-03 | ض� | 具有无凸块的叠片互连层的微电子组件 |
US20050280141A1 (en) * | 2004-06-21 | 2005-12-22 | Broadcom Corporation | Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same |
US20070231953A1 (en) * | 2006-03-31 | 2007-10-04 | Yoshihiro Tomita | Flexible interconnect pattern on semiconductor package |
CN101232002A (zh) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | 一具有标示结构之封装及其方法 |
CN104882416A (zh) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | 具有堆叠式封装能力的半导体封装件及其制作方法 |
CN105957845A (zh) * | 2016-07-11 | 2016-09-21 | 华天科技(昆山)电子有限公司 | 一种带有电磁屏蔽的芯片封装结构及其制作方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111430326A (zh) * | 2020-03-05 | 2020-07-17 | 广东工业大学 | 一种嵌入式高散热扇出型封装结构及封装方法 |
CN111430326B (zh) * | 2020-03-05 | 2022-02-11 | 广东工业大学 | 一种嵌入式高散热扇出型封装结构及封装方法 |
CN117471134A (zh) * | 2023-12-28 | 2024-01-30 | 成都天成电科科技有限公司 | 一种芯片测试夹具 |
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