CN105428327B - 扇出型晶片级封装结构 - Google Patents

扇出型晶片级封装结构 Download PDF

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CN105428327B
CN105428327B CN201410430514.0A CN201410430514A CN105428327B CN 105428327 B CN105428327 B CN 105428327B CN 201410430514 A CN201410430514 A CN 201410430514A CN 105428327 B CN105428327 B CN 105428327B
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fan
wafer level
level packaging
type wafer
packaging structure
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CN105428327A (zh
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林钜富
郭建利
陈国明
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种扇出型晶片级封装结构。扇出型晶片级封装结构包括一半导体元件、一封胶、一第一扇出结构、一导电散热板以及多个焊接球。半导体元件包括多个接合垫。封胶包覆半导体元件。第一扇出结构形成于半导体元件上，其中第一扇出结构具有多个扇出接触点，此些扇出接触点电连接于此些接合垫。导电散热板形成于第一扇出结构上，其中导电散热板具有多个填充一导电材料的穿孔。焊接球形成于导电散热板上，其中焊接球经由填充导电材料的穿孔电连接至第一扇出结构。

Description

扇出型晶片级封装结构
技术领域
本发明内容涉及一种扇出型晶片级封装结构，且特别是涉及一种具有良好散热效果的扇出型晶片级封装结构。
背景技术
近年来，由于扇出型晶片级封装结构(fan-out wafer level packages，FOWLP)具有高效能及低成本的特点，已经被广泛地应用于半导体芯片的制作。举例而言，扇出型晶片级封装结构的技术，已经作为一种采用28纳米规格的晶片制作行动式产品的方式。
然而，仍然有一些课题需要解决，例如是散热效率以及结构脱层(structuraldelamination)。因此，对于具有可靠效能的改良的扇出型晶片级封装结构仍一直有需求。
发明内容
本发明的目的在于提供一种扇出型晶片级封装结构，在该扇出型晶片级封装结构中，导电散热板形成于第一扇出结构上，有助于提高整体的散热效果，进而提高扇出型晶片级封装结构的整体稳定性。
为达上述目的，根据本发明内容的一实施例，提出一扇出型晶片级封装结构。扇出型晶片级封装结构包括一半导体元件、一封胶、一第一扇出结构、一导电散热板以及多个焊接球。半导体元件包括多个接合垫。封胶包覆半导体元件。第一扇出结构形成于半导体元件上，其中第一扇出结构具有多个扇出接触点，此些扇出接触点电连接于此些接合垫。导电散热板形成于第一扇出结构上，其中导电散热板具有多个填充一导电材料的穿孔。焊接球形成于导电散热板上，其中焊接球经由填充导电材料的穿孔电连接至第一扇出结构。
为了对本发明的上述及其他方面有更佳的了解，下文特举优选实施例，并配合所附的附图，作详细说明如下：
附图说明
图1为本发明内容一实施例的扇出型晶片级封装结构的示意图；
图2为本发明内容一实施例的导电散热板的局部示意图；
图3为本发明内容再一实施例的扇出型晶片级封装结构的示意图；
图4为本发明内容又一实施例的扇出型晶片级封装结构的示意图；
图5为本发明内容还一实施例的扇出型晶片级封装结构的示意图。
符号说明
10、20、30、40：扇出型晶片级封装结构
100：半导体元件
110：接合垫
120：介电结构
200：封胶
200T：封胶穿孔
300：第一扇出结构
310：扇出接触点
320：有机介电层
330：扇出导线
400：导电散热板
400s：侧壁
400T：穿孔
410：导电材料
420：绝缘层
430：导电层
430s：表面
440：氧化层
500：焊接球
2300：第二扇出结构
3300：第三扇出结构
W1：第一线宽
W2：第二线宽
具体实施方式
根据本发明内容的实施例，扇出型晶片级封装结构中，导电散热板形成于第一扇出结构上，有助于提高整体的散热效果，进而提高扇出型晶片级封装结构的整体稳定性。附图中相同的标号用以标示相同或类似的部分。需注意的是，附图已简化以利清楚说明实施例的内容，实施例所提出的细部结构仅为举例说明之用，并非对本发明内容欲保护的范围做限缩。具有通常知识者当可依据实际实施态样的需要对该些结构加以修饰或变化。
图1绘示根据本发明内容一实施例的扇出型晶片级封装结构10的示意图。扇出型晶片级封装结构10包括一半导体元件100、一封胶200、一第一扇出结构300、一导电散热板400以及多个焊接球500。图1中所示的两个半导体元件100可以是两个相同的半导体元件或是两个不同的半导体元件。此处所指的相同或不同指其功能或面积或厚度或制作工艺世代(如90nm、65nm、28nm的制作工艺世代)。半导体元件100包括多个接合垫110，封胶200包覆半导体元件100。第一扇出结构300形成于半导体元件100上，其中第一扇出结构300具有多个扇出接触点310，扇出接触点310电连接于接合垫110。导电散热板400形成于第一扇出结构300上，其中导电散热板400具有多个填充导电材料410的穿孔400T。焊接球500形成于导电散热板400上，其中焊接球500经由填充导电材料410的穿孔400T电连接至第一扇出结构300。
根据本发明内容的实施例，导电散热板400形成于第一扇出结构300上，有助于提高整体的散热效果。当散热效果获得有效的提升，扇出型晶片级封装结构中，多个层结构便不容易发生因受热而发生变形程度不同导致的脱层(delamination)。如此一来，能够进而提高扇出型晶片级封装结构的整体稳定性。
再者，第一扇出结构300具有多个电性接触点，用以电连接至第一扇出结构300之外的元件，例如是扇出接触点310。此些电性接触点是制作工艺中的弱点(weak point)，当此些电性接触点的结构直接连接至外部元件时，例如是焊接球500，容易在制作工艺中发生故障的情形，而影响到整个扇出型晶片级封装结构的制作工艺良率。然而，根据本发明内容的实施例，焊接球500经由填充导电材料410的穿孔400T电连接至第一扇出结构300，如此一来，可以避免第一扇出结构300以结构弱点连接至焊接球500的情形，有效增加结构的强度与稳定性。
实施例中，穿孔400T例如是经由激光钻孔(laser drilling)、机械钻孔(mechanical drilling)和/或蚀刻制作工艺(etching process)制作，之后再填入导电材料410于穿孔400T中。导电材料410可以经由例如是电镀(electroplating)制作工艺来填入穿孔400T中，导电材料410电连接至焊接球500和接合垫110。
一实施例中，导电散热板400例如是硅中介层(silicon interposer)，填充导电材料410的穿孔400T例如是硅穿孔(through silicon via，TSV)。
图2绘示根据本发明内容一实施例的导电散热板400的局部示意图。如图2所示，实施例中，导电散热板400可包括多个绝缘层420。绝缘层420形成于填充导电材料410的穿孔400T的侧壁400s和导电材料410之间。实施例中，绝缘层420例如是氧化物层或氮化物层。
如图2所示，实施例中，导电散热板400可包括一导电层430。导电层430可包括硅、铜、铝及上述者的合金的至少其中之一。
如图2所示，实施例中，导电散热板400可还包括二氧化层440。两个氧化层440分别形成于导电层430的两个相对表面430s上。两个氧化层440与侧壁400s上的绝缘层可以是由相同制作工艺所形成的同一绝缘膜层。
如图1所示，实施例中，第一扇出结构300还可包括一有机介电层320以及多个扇出导线330。扇出导线330形成于有机介电层320中。第一扇出结构300的扇出导线330向***展开，可以有助于令多个焊接球500之间的节距(pitch)放大，节距的放大可以增加整个结构和空气接触的空间，因而使得导热效果也会更好。
一些实施例中，第一扇出结构300还可包括至少一被动元件(未绘示)，被动元件形成于有机介电层320中。实施例中，被动元件例如是电容、电阻、电感…等。
实施例中，有机介电层320的材质包括有机介电材料，有机介电层320可经由例如化学气相沉积制作工艺(CVD process)、喷涂制作工艺(spray coating process)或成型制作工艺(molding process)而制作。
如图1所示，扇出导线330具有一第一线宽W1，填充导电材料410的穿孔400T具有一第二线宽W2。实施例中，第二线宽W2例如是大于第一线宽W1。第一扇出结构300的扇出导线330在有机介电层320中具有绕线图案，所以具有的第一线宽W1比较细；而填充导电材料410的穿孔400T是垂直的，不具有横向延展的结构，所以具有的第二线宽W2可以比较粗。如此一来，不仅穿孔400T的制作工艺可以不用非常精准，且因为截面积大(也就是第二线宽W2较大)，所以可以提供优选的散热效果。
一些实施例中，接合垫的材质为导电材料，例如可包括铝。一实施例中，多个焊接球500可形成一球栅阵列(ball grid array，BGA)。
图3绘示根据本发明内容再一实施例的扇出型晶片级封装结构20的示意图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
如图3所示，扇出型晶片级封装结构20还可包括至少一封胶穿孔200T。封胶穿孔200T形成于封胶200中，封胶穿孔200T电连接至该些焊接球500的至少其中之一。实施例中，封胶穿孔200T填充导电材料。当扇出型晶片级封装结构20与额外的封装结构堆叠连接时，封胶穿孔200T可以用作多个封装结构之间的电连接。本实施例中，如图3所示，两个封胶穿孔200T穿过封胶200、第一扇出结构300及导电散热板400以分别电连接至两个不同的焊接球500。
如图3所示，半导体元件100还可包括一内连线结构120。内连线结构120形成于接合垫110上。如图3所示，内连线结构120例如是直接接触接合垫110，且接合垫110位于内连线结构120和第一扇出结构300之间。实施例中，内连线结构120可具有多层电连线(未绘示)及介电材料，介电材料将该些电连线电性隔离开来。
图4绘示根据本发明内容又一实施例的扇出型晶片级封装结构30的示意图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
如图4所示，扇出型晶片级封装结构30还可包括一第二扇出结构2300。第二扇出结构2300形成于导电散热板400上，第一扇出结构300电连接于第二扇出结构2300。
本实施例中，第二扇出结构2300电连接至焊接球500。经由额外设置第二扇出结构2300，可以使得多个焊接球500之间的节距更进一步放大，且进一步于横向上延伸放大线宽与线距，也可进一步提高整体结构的散热效果。
图5绘示根据本发明内容更一实施例的扇出型晶片级封装结构40的示意图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
如图5所示，扇出型晶片级封装结构40还可包括一第三扇出结构3300。第三扇出结构3300形成于导电散热板400上。
本实施例中，第二扇出结构2300和第三扇出结构3300分别形成于导电散热板400的两个相对表面上，第三扇出结构3300电连接于第二扇出结构2300。
综上所述，虽然结合以上优选实施例公开了本发明，然而其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (14)

1.一种扇出型晶片级封装结构，包括：
半导体元件，包括多个接合垫；
封胶，包覆该半导体元件；
第一扇出结构，形成于该半导体元件上，其中该第一扇出结构具有多个扇出接触点，该些扇出接触点电连接于该些接合垫；
导电散热板，形成于该第一扇出结构上，其中该导电散热板具有多个填充一导电材料的穿孔；
多个焊接球，形成于该导电散热板上，其中该些焊接球经由填充该导电材料的该些穿孔电连接至该第一扇出结构；以及
第二扇出结构，形成于该导电散热板上，其中该第一扇出结构电连接于该第二扇出结构。
2.如权利要求1所述的扇出型晶片级封装结构，其中该导电散热板包括多个绝缘层，形成于该些填充该导电材料的穿孔的侧壁和该导电材料之间。
3.如权利要求1所述的扇出型晶片级封装结构，其中该导电散热板包括导电层，该导电层包括硅、铜或铝的至少其中之一。
4.如权利要求3所述的扇出型晶片级封装结构，其中该导电散热板还包括两层绝缘的氧化层，分别形成于该导电层的两个相对表面上。
5.如权利要求1所述的扇出型晶片级封装结构，其中该第一扇出结构包括：
有机介电层；以及
多个扇出导线，形成于该有机介电层中。
6.如权利要求5所述的扇出型晶片级封装结构，其中该些扇出导线电连接于该第一扇出结构的该些扇出接触点。
7.如权利要求5所述的扇出型晶片级封装结构，其中该些扇出导线具有第一线宽，该些填充该导电材料的穿孔具有第二线宽，该第二线宽大于该第一线宽。
8.如权利要求5所述的扇出型晶片级封装结构，其中该第一扇出结构还包括：
至少一被动元件，形成于该有机介电层中。
9.如权利要求1所述的扇出型晶片级封装结构，其中该第二扇出结构电连接至该些焊接球。
10.如权利要求1所述的扇出型晶片级封装结构，还包括：
第三扇出结构，形成于该导电散热板上，其中该第二扇出结构和该第三扇出结构分别形成于该导电散热板的两个相对表面上，该第三扇出结构电连接于该第二扇出结构。
11.如权利要求1所述的扇出型晶片级封装结构，其中该些接合垫包括铝。
12.如权利要求1所述的扇出型晶片级封装结构，其中该些焊接球形成一球栅阵列。
13.如权利要求1所述的扇出型晶片级封装结构，还包括：
至少一封胶穿孔，形成于该封胶中，其中该封胶穿孔电连接至该些焊接球的至少其中之一。
14.如权利要求1所述的扇出型晶片级封装结构，其中该半导体元件还包括一介电结构，形成于该些接合垫上。
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