TW200816379A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
TW200816379A
TW200816379A TW096128890A TW96128890A TW200816379A TW 200816379 A TW200816379 A TW 200816379A TW 096128890 A TW096128890 A TW 096128890A TW 96128890 A TW96128890 A TW 96128890A TW 200816379 A TW200816379 A TW 200816379A
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Taiwan
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layer
conductive layer
insulating film
film
copper
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TW096128890A
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Chinese (zh)
Inventor
Yoshiyuki Ohba
Toshihiko Hayashi
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Sony Corp
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Publication of TW200816379A publication Critical patent/TW200816379A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed herein is a method for manufacturing a semiconductor device, the method including the steps of: forming a recess in an insulating film provided over a substrate; forming a plating seed layer in such a way that an inner wall of the recess is covered, the plating seed layer arising from sequential deposition of an alloy layer composed of copper and a metal other than copper and a conductive layer composed mainly of copper; burying a conductive layer composed mainly of copper by plating in the recess on which the plating seed layer is provided; and carrying out heat treatment to cause the metal in the alloy layer to react with a constituent in the insulating film, to thereby form a barrier film composed of a metal compound having a copper diffusion barrier function at an interface between the alloy layer and the insulating film.

Description

200816379 九、發明說明： 【發明所屬之技術領域】 波置之方法；且更明確地 構之半導體裝置之方法， 間絕緣膜之間提供一自形 本發明係關於一種製造半導體 說，係關於一種製造具有鑲嵌結 其中，會在一互連或通道及一層 成阻障膜。 【先前技術】200816379 IX. Description of the invention: [Technical field of the invention] Wave-forming method; and a method for more clearly configuring a semiconductor device, providing a self-shape between the insulating films. The present invention relates to a method for manufacturing a semiconductor, relating to a Manufactured with a damascene junction where it will form a barrier film in an interconnect or via and a layer. [Prior Art]

在半導體裝置中形成一鋼（ClI、万、查 UL^U)互連的通用程序中會運用 到鑲散方法，I中會藉由填充設置在—層間絕緣膜之中的 互連溝渠來形成一互連圖案。在使用鑲礙方法來形成Cu互 連中，通常會以在埋置Cu之前先沉積一阻障膜（例如钽（Ta) 或氮化鉅（TaN)膜）使其具有約10 11〇1的膜厚度之方式，以 便覆蓋一互連溝渠的内壁，以達防止Cu擴散至層間絕緣膜 之中的目的。在藉由電解電鍍沉積該阻障膜之後，便會在 其上設置著該阻障膜的互連溝渠之中埋置一 Cu層。 不過，隨著互連間距變小時，Cu的埋置也變得更為困 難。此外，該阻障膜與總互連體積的體積比會變高，其會 提高互連電阻。為解決該些問題，已經有人提出一種解決 技術（參見 2005 IEEE International Interconnect Technology Conference 第 188 至 190 頁的 ’’Low Resistive and HighlyIn the general procedure for forming a steel (ClI, 10,000, check UL) interconnection in a semiconductor device, a splicing method is used, and I is formed by filling interconnected trenches provided in the interlayer insulating film. An interconnect pattern. In the use of the embedding method to form a Cu interconnect, a barrier film (for example, a tantalum (Ta) or a tantalum nitride (TaN) film) is usually deposited to have a thickness of about 10 11 〇 1 before the Cu is buried. The film thickness is so as to cover the inner wall of an interconnected trench for the purpose of preventing Cu from diffusing into the interlayer insulating film. After depositing the barrier film by electrolytic plating, a Cu layer is buried in the interconnect trench in which the barrier film is disposed. However, as the interconnection pitch becomes smaller, the embedding of Cu becomes more difficult. In addition, the volume ratio of the barrier film to the total interconnect volume becomes higher, which increases the interconnect resistance. In order to solve these problems, a solution technique has been proposed (see ¡’Low Resistive and Highly on page 188 to 190 of the IEEE International Interconnect Technology Conference 2005).

Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier Layer’’）。於此項技術 中並未沉積一阻障膜，不過卻會形成一由含Μη的Cu層所 形成的晶種層。再者，Μη會透過熱處置而擴散，從而會 120673.doc 200816379 在一層間絕緣膜與一 Cu互連間之介面處形成一由化合 物組成且膜厚度約2至3 nm的自形成阻障膜。 下文將參考圖3 A至3 C來說明此自形成阻障製程。首先 參考圖3 A，在由石夕晶圓所形成的基板i i之上會形成一由二 氧化矽（si〇2)所組成的層間絕緣膜12。而後，便會在該層 間絕緣膜12之中形成一抵達基板丨丨的通道孔丨3，並且接著 會在該通道孔13之中埋置一（例如）由嫣（w)所組成的通道 14 〇 接著，便會在該層間絕緣膜12與該通道14之上形成一由 Si〇2所組成層間絕緣膜15。接著’便會在該層間絕緣膜^ 之中形成一會抵達層間絕緣膜丨2與通道丨4的互連溝渠丨6。 而後，便會在該層間絕緣膜15之上形成一由CuMn層所形 成的電鍍晶種層17f。 接著參考圖3B，藉由電解電鍍，會以在該電鍍晶種層 17’之上形成一由純以所構成的導電層18之方式，以便填 充該互連溝渠1 6。 接著參考圖3C，其會進行熱處置，用以讓該電鍍晶種層 17'中内含的Μη與該等層間絕緣膜12與15中的成分進行反 應，從而在該電鍍晶種層17’與該等層間絕緣膜12與15之間 的介面處形成一由Μη化合物所組成的自形成阻障膜丨9。 升y成此自形成阻p早膜19以具有一 2 nm至3 nm之膜厚度。透 過熱處置還會在該導電層18表面側上離析出Μη，因而會 形成氧化猛（ΜηΟ)層Μ。 而後，圖中雖然並未顯示，不過藉由化學機械拋光法 120673.doc 200816379 便▲會移除不需要作為互連圖案的導電層is部分虚自 :成且_ 19並且向下拋光曝露的層間 側，以便在該互連溝渠此中形成—互連。 在為導電層18提供良好覆蓋方面’上面所述的製造方法 k於運用Ta或TaN阻障膜的典型埋置程序，因為透過該電 鍍b曰種層17中的Mn與該等層間絕緣膜以與15中的成分進Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier Layer''). A barrier film is not deposited in this technique, but a seed layer formed of a Cu layer containing Μη is formed. Furthermore, Μη will diffuse through heat treatment, thereby forming a self-forming barrier film composed of a compound and having a film thickness of about 2 to 3 nm at the interface between the interlayer insulating film and a Cu interconnection. . This self-forming barrier process will be described below with reference to FIGS. 3A to 3C. Referring first to Fig. 3A, an interlayer insulating film 12 made of ruthenium dioxide (si〇2) is formed on the substrate i i formed by the Shihwa wafer. Then, a via hole 抵达3 which reaches the substrate 丨丨 is formed in the interlayer insulating film 12, and then a channel 14 composed of, for example, 嫣(w) is buried in the via hole 13 Then, an interlayer insulating film 15 composed of Si 〇 2 is formed over the interlayer insulating film 12 and the via 14 . Then, an interconnected trench 6 which reaches the interlayer insulating film 2 and the via 4 is formed in the interlayer insulating film ^. Then, a plating seed layer 17f formed of a CuMn layer is formed on the interlayer insulating film 15. Referring next to Fig. 3B, by electrolytic plating, a conductive layer 18 of pure shape is formed over the plated seed layer 17' to fill the interconnecting trenches 16. Referring next to FIG. 3C, heat treatment is performed to cause the Mn contained in the plating seed layer 17' to react with the components in the interlayer insulating films 12 and 15, so that the plating seed layer 17' A self-forming barrier film 9 composed of a Μn compound is formed at an interface between the interlayer insulating films 12 and 15. The y is formed into the resistive film early film 19 to have a film thickness of from 2 nm to 3 nm. The heat treatment also causes the Μη to be separated on the surface side of the conductive layer 18, thereby forming an oxidized layer. Then, although not shown in the figure, by chemical mechanical polishing 120673.doc 200816379 ▲ will remove the conductive layer is not required as an interconnection pattern is partially virtual: _ 19 and polished down the exposed layer Side to form an interconnection in the interconnected trench. The manufacturing method described above is a typical embedding procedure using a Ta or TaN barrier film in order to provide good coverage for the conductive layer 18 because the Mn in the plating layer 17 and the interlayer insulating film are With the ingredients in 15

:反應會形成具有較小厚度的自形成阻障膜Μ。再者，此 製造方法還進-步提供達成具有低電阻之互連的優點，因 為°亥自形成阻障臈1 9的膜厚度小於Ta或TaN阻障膜的厚 度。 ' 【發明内容】 然而’上面所述的製造方法卻涉及下面的問題。明確地 δ兒’倘若電鍍晶種層1 7’中Μη的濃度不足的話，那麼圖3c 中所述步驟便無法形成如圖4中所示之連續的自形成阻障 膜19。這會因在該熱處置之初始階段處的劇烈應力變化導 致該導電層1 8與該等層間絕緣膜丨2與1 5之間的黏著性下降 的關係’而造成導電層1 8分離。為防止此情形，可以有效 提高該電鍍晶種層17彳參見圖3C)中的Μη濃度，促成該自 形成阻障膜19的形成。不過，因為Μη的電阻高於Cu，所 以’提高Μη濃度會造成電鑛晶種層17’具有較高的薄片電 阻。這會導致必須在該電鍍步驟中應用龐大的電流，且因 而會提高該電鍍步驟的負擔。這會導致橫跨基板11平面上 之導電層18的電鍍成長不均勻，其會造成導電層18具有很 低的覆蓋均勻性。再者，電鐘晶種層1 7’之表面側上的Μη 120673.doc 200816379 很合易各析在電鍍溶液中，其會導致的問題係，被溶析在 忒電鍍溶液中的％11會連同該導電層18一起被埋置在該互 連溝渠16之中，並且因而提高互連電阻。 斤乂本發明必須提供一種製造半導體裝置的方法，用 以防止導電層分離，同時抑制電鍍步驟上的負擔，並且允 許增強橫跨該基板平面上之導電層的覆蓋均勻性，同時抑 制互連電阻提高。 在根據本發明具體實施例的製造半導體裝置之方法中會 依序實行下面步驟。首先，會在位於_基板上方的絕㈣ 成凹邛。接著會已依序沉積一由銅（Cu)及非Cu金 屬所組成的合金層以及一主要由〜所組成的導電層來產生: The reaction forms a self-forming barrier film crucible having a small thickness. Furthermore, this manufacturing method further provides the advantage of achieving an interconnection having a low resistance because the film thickness of the barrier 臈1 is less than the thickness of the Ta or TaN barrier film. [Summary of the Invention] However, the manufacturing method described above involves the following problems. Specifically, if the concentration of Μη in the electroplated seed layer 1 7' is insufficient, the step described in Fig. 3c cannot form the continuous self-forming barrier film 19 as shown in Fig. 4. This causes the conductive layer 18 to separate due to the relationship between the conductive layer 18 and the adhesion between the interlayer insulating films 丨2 and 15 due to the severe stress change at the initial stage of the heat treatment. In order to prevent this, the plating concentration of the plating seed layer 17 (see Fig. 3C) can be effectively increased to contribute to the formation of the self-forming barrier film 19. However, since the resistance of Μη is higher than that of Cu, increasing the concentration of Μη causes the electrodeide seed layer 17' to have a higher sheet resistance. This causes a large current to be applied in the plating step, and thus the burden of the plating step is increased. This causes uneven plating growth across the conductive layer 18 on the plane of the substrate 11, which causes the conductive layer 18 to have a low coverage uniformity. Furthermore, the Μη 120673.doc 200816379 on the surface side of the seed crystal layer 1 7' is easily separated into the plating solution, which causes problems, and the %11 which is dissolved in the ruthenium plating solution will Together with the conductive layer 18, it is buried in the interconnect trench 16, and thus the interconnect resistance is increased. The present invention must provide a method of fabricating a semiconductor device for preventing separation of a conductive layer while suppressing a burden on a plating step, and allowing uniformity of coverage of a conductive layer across a plane of the substrate to be enhanced while suppressing interconnection resistance. improve. The following steps are sequentially performed in the method of fabricating a semiconductor device in accordance with an embodiment of the present invention. First, it will be a concave (four) on the top of the _ substrate. Then, an alloy layer composed of copper (Cu) and non-Cu metal and a conductive layer mainly composed of ~ are sequentially deposited.

*電錢曰曰種層之方式來形成，用以覆蓋該凹部的内壁。接 者，便會藉由電鍍將主要由Cu所組成的導電層埋置在其上 會设置該電錢晶種層的凹部之中。接著便會進行熱處置， 以便:襄該合金層中的金屬與該絕緣膜之中的成分進行反 應攸而形成一由金屬化合物所組成的阻障膜，其在該合 金層與該絕緣膜間的介面處具有Cu擴散阻障功能。 根據此製造半導體裝置的方法，即使該合金層中内含的 非Cu金屬的電阻很高，該電鑛晶種層的薄片電阻仍會低於 僅由该合金層所構成之電鑛晶種層17,的薄片電阻，因為該 電：曰曰種層係藉由依序沉積該合金層及該主要由α所組成 產生而形成的。所以，即使將該合金層中該金 電一連續阻障膜的程度，仍可抑制該 曰4片電阻的提高。這便無需在電鍍步驟中應 120673.doc 200816379 用魔大的電流，且因而會抑制電鑛步驟的負擔。因此，抑 制包銀步驟的負擔，便能夠藉由提高該合金層中該金屬的 濃度而在該合金層與該絕緣膜間的介面處形成-連續的阻 障膜。這會提高該導電層與該絕緣膜之間的黏著性，其能 夠防止4導電層/刀离•。此外，由於該電鍍晶種層之低薄片 電阻的關係、，所以會抑制橫跨該基板平面上該導電層之電 鍍成長不均勻性並且提高該導電層之覆蓋均勻⑯。再者， Ο u 因為該電鍍晶種層中的合金層受到主要由Cu所組成之導電 層覆蓋，戶斤以Μ更可在該電錢步驟中防止該合金金屬之表 面側上的金屬溶析在電㈣液之中。這可防止在藉由電鍵 以該導電層來填出該凹部時因連同該導電層將被溶析在該 電鍍洛液中的金屬埋置在該凹部之中而提高該導電層的電 阻。 如上所述，根據本發明具體實施例之製造半導體裝置的 方法能夠防止導電層分離，且因而能夠提高該半導體裝置 的產量。再者，還會提高橫跨該基板平面上該導電層之覆 蓋均勻性，其能夠抑制利用（例如）CMP來進行該導電層之 拋光中會出現的淺碟（dishing)與侵|虫（erosi〇n)。再者，還 可防止導電層之電阻提高。結果，當該凹部係一互連溝渠 而該導電層係一互連時，便能夠防止互連電阻提高且能夠 提高互連可靠度。 【實施方式】 以下將參考附圖來詳細說明本發明之具體實施例。 (第一具體實施例） 120673.doc 10 200816379 根據本發明第一纟體實施例之製造半導體裝置的方法係 和形成單一鑲嵌互連結構有關。下文將參考圖以至”作為 製造步驟斷面圖來說明帛—具體實施例。在下面說明中， 和相關技術中相同的組件會給定相同的符號。 首先參考圖1A，在由矽晶圓所構成的基板！丨（其上會構 成各種元件例如電晶體）之上會構成一（例如）由；§i〇2所植 成的層間絕緣膜12。而後’便會形成—抵達基板u的通道 ( 1* The electric money is formed in a layered manner to cover the inner wall of the recess. Then, a conductive layer mainly composed of Cu is buried by plating on the recess in which the seed crystal layer is disposed. Then, heat treatment is performed to: react the metal in the alloy layer with the components in the insulating film to form a barrier film composed of a metal compound between the alloy layer and the insulating film. The interface has a Cu diffusion barrier function. According to the method of manufacturing a semiconductor device, even if the resistance of the non-Cu metal contained in the alloy layer is high, the sheet resistance of the electromineral seed layer is lower than that of the electromineral seed layer composed only of the alloy layer. The sheet resistance of 17, because the electricity layer is formed by sequentially depositing the alloy layer and the composition mainly composed of α. Therefore, even if the gold layer is a continuous barrier film in the alloy layer, the improvement of the resistance of the ruthenium plate can be suppressed. This eliminates the need for a large current in the electroplating step and thus inhibits the burden of the electromineralization step. Therefore, by suppressing the burden of the silver-coated step, a continuous barrier film can be formed at the interface between the alloy layer and the insulating film by increasing the concentration of the metal in the alloy layer. This improves the adhesion between the conductive layer and the insulating film, which prevents the 4 conductive layer/knife from being removed. Further, due to the low sheet resistance of the plating seed layer, plating growth unevenness of the conductive layer across the substrate plane is suppressed and the uniform coverage of the conductive layer is improved. Furthermore, Ο u because the alloy layer in the electroplated seed layer is covered by a conductive layer mainly composed of Cu, and it is possible to prevent metal elution on the surface side of the alloy metal in the electric money step. In the electricity (four) liquid. This prevents the electric resistance of the conductive layer from being increased by embedding the metal which is to be eluted in the plating solution together with the conductive layer in the recess when the recess is filled with the conductive layer by a key. As described above, the method of manufacturing a semiconductor device according to an embodiment of the present invention can prevent the separation of the conductive layer, and thus can increase the yield of the semiconductor device. Moreover, the coverage uniformity of the conductive layer across the plane of the substrate is also improved, which can suppress the dishing and invasiveness (erosi) which may occur in the polishing of the conductive layer by, for example, CMP. 〇n). Furthermore, the resistance of the conductive layer can be prevented from increasing. As a result, when the recesses are interconnected to the trench and the conductive layers are interconnected, the interconnection resistance can be prevented from being improved and the interconnection reliability can be improved. [Embodiment] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. (First Embodiment) 120673.doc 10 200816379 A method of fabricating a semiconductor device in accordance with a first embodiment of the present invention is related to forming a single damascene interconnect structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the same components as those in the related art will be given the same reference numerals in the following description. Referring first to FIG. 1A, The substrate 丨 (which will constitute various elements such as a transistor) will constitute, for example, an interlayer insulating film 12 formed of §i〇2, and then will form a channel for reaching the substrate u. ( 1

孔13，並且接著會在該通道孔13之中埋置一（例如）由w所 組成的通道1 4。 而後，便會使用矽烷（SiH4)作為沉積氣體利用（例如）電 襞增強化學氣相沉積（PECVD)在該層間絕緣膜㈣該通道 14之上形成—由Si〇2所組成的層間絕緣膜丨5。 而後，便會在該層間絕緣膜15之上形成一具有互連溝渠 圖案的光P且圖案(圖中並未顯示)，並且接$會利用此光阻 圖案作為遮罩來進行㈣而於該層間絕緣膜Η之中形成一 互連溝渠叫凹部）。此互連溝渠16的孔徑寬度係75_。 現在蒼考圖1B，（例如）葬由％ U JJ猎由物理矾相沉積（pvD)，例如 使用CiiMn合金目標進行濺鍍，合 / 数 θ以在忒層間絕緣膜15之 上形成一由CuMn所組成之合金声 、、 孟滑1 /a之方式，用以覆蓋該 互連溝渠16的内壁。Μη的電p且古於Γι AA兩 J电丨且同於Cii的電阻。再者，在 稍後步驟中藉由熱處置，該八 〇孟層1 7a中的Μη便會與該等 層間絕緣膜12與1 5中的成分彳隹c虚 進仃反應，從而形成一自形成 阻障膜。 所以 該合金層17a中Μη的 濃度及該合金層1 7a的膜厚 120673.doc 200816379 度會被疋義在特定範圍内。明確地說，Μη濃度及膜厚度 等數值會等於或大於在稍後步驟中透過熱處置用以在該合 金層17a及該等層間絕緣膜12與15間的介面處形成一連續 自形成阻障膜的下限。此外，Μη濃度及膜厚度等數值還 • 纟等於或小於用以產生形成在該互連溝渠16之中且含有剩 • 餘Mn的互連之互連電阻以及因將主要由Cu所組成之導電 層堆疊在該合金層17a之上（稍後會作說明）而產生的電鍍晶 f) 種層薄片電阻之允許上限的上限。 明確地說，合金層17a中Mn濃度係在1原子百分比至1〇 原子百分比之範圍，且較佳的係，該Mn濃度係在2原子百 分比至6原子百分比之範圍。再者，該合金層17&的膜厚度 會被定義為不大於一特定值，俾使藉由稍後的電鍍以導電 層來進行填充的品質不會受到破壞且至多為上面所述之上 限。明確地說，在不具有互連溝渠圖案的平滑部分中，合 金層17a的膜厚度係在丨〇 nm至50 nm之範圍。舉例來說， 在本範例中，该合金層1 7a形成以具有一 30 nm之膜厚度。 接著參考圖1C，在合金層l7a之上，會形成一（例如）由 純Cu所組成的導電層17b，其膜厚度（例如）為3〇 。這會 藉由依序沉積該合金層17a與該導電層17b所產生而形成一 電鍍晶種層17。這會讓由純Cii所組成的導電層17b覆蓋該 合金層17a的表面側。所以，相較於僅由CuMn所組成之合 金層17a所形成的電鍍晶種層，電鍍晶種層17會具有較低 的薄>1電阻。這會抑制稍後要說明之用於將一導電層埋置 在互連溝渠1 6的電鍍步驟的負擔。 120673.doc -12- 200816379 在本範例中，導電層17b係由純Cu所組成的。不過，導 電層17b的材料可為任何材料，只要其係包含作為其主 成分即可。舉例來$，亦可使用CuAg合金，其僅會小幅 提南電阻率。 «亥V電層1 7b的膜厚度會被設定成讓該電鍍晶種層口的 薄片電阻會被抑制在允許範圍内且藉由電鍍以導電層以來 進行填充的。口夤如上述並不會遭到破壞。明確地說，在不 具有互連溝渠圖案的平滑部分中，導電層17b的膜厚度係 在10 nm至50 nm之範圍。在本範例中，該導電層i7b形成 以具有一 30 nm之膜厚度。 接著麥考圖1D，（例如）藉由電解電鍍，以會在該導電層 17b之上形成一（例如）由純Cu所構成的導電層18直到膜厚 度為800 ^或更大之方式，以便填充該互連溝_。在此 =置中，橫跨基板U之平面上該導電層18的覆蓋均勻性非 常南，因為如上所述，該電鍍晶種層17的薄片電阻非常 低。再者，藉由純（^所組成的導電層i7b覆蓋該合金層Pa 的表面側。這會防止該合金層17a之表面側上的Μη溶析在 電鍍/合液之中，並且從而防止連同該導電層Μ將被溶析在 該電鍍溶液中的]^11埋置在該互連溝渠16之中。因此便會 防止互連電阻提高。再者，還可避免因被溶析在該電鑛溶 液中的Μη的關係而對電鍍步驟造成負面效應。 在本乾例中，導電層1 8係由純Cu所組成的。不過，導電 層1口8的材料可為任何材料，只要其^包含Cu作為其主成分 即可。舉例來說，亦、可使用CuAg合金，其僅會小幅提高 120673.doc 200816379 電阻率。 接著簽考圖1E，舉例來說，其會在3〇〇。(：處進行3〇分鐘 的熱處置。此熱處置會瓖合金層17a中的Mn(參見圖1〇)與 該等層間絕緣膜12與15中的成分進行反應，從而在該合金 層17a與該等層間絕緣膜12與15間的介面處形成一具有防 止Cu擴散功能的自形成阻障膜19。較佳的係，用以形成該 自形成阻障膜19之熱處置的溫度及處置時間分別為2〇〇。〇 Ο 至40〇t及60秒至兩小時，以促成確保形成該自形成阻障 膜19且防止因該熱處置而在該裝置上造成負面效應。更佳 的係，處置時間係為60秒與3〇分鐘之間。該等層間絕緣膜 12與15中的”成分’’同樣涵蓋會從環境中被料層間絕緣膜 12與1 5表面吸收的氧、水等。 在本具體實施例中，該等層㈤絕緣膜12與15係由叫所 組成’所以該自形成阻障膜19係由Mn化合物所組成，例 如含石夕的Μη氧化物（MnSix〇y)或是施氧化物（Mn办）。該 ， 自形成阻障膜19的膜厚度係2 至3 nm。合金層17a含有 具有此一高濃度的Mn ’以便形成連續的自形成阻障膜 19。相較於現存的方法，這允許供應較大量的Mn至該合 金層17a與該等層間絕緣膜12與15間的介面處，其允許形 成堅韋刃的連續自形成阻障膜19並且提供極高的黏著性。這 會防止因在該熱處置之初始階段處的急據應力變化而出現 j導電層18分離。再者’還可確保該熱處置的條件會具有 ' κ勺邊限自於此熱處置的關係，同樣會在該導電8 表面側上離析出Mn，其會形成Mn〇層m。 田 120673.doc -14- 200816379 接著 > 考圖1F，其會藉由（例如）CMp來進行雙級抛光。 在第一級拋光中，會移除乂的層叫參見圖1E)及不必作為 互連圖案的導電層18的部分（參見圖1E)。接著，在第二級 抛光中，會移除該自形成阻障膜j 9，並且會將曝露的層間 絕緣膜15向下拋光⑽nm。這會在該互連溝渠“之中形成 由Cu所、，且成的互連丨8,。因為上述的自形成阻障膜1 9係 位在该導電層18與該等層間絕緣膜12與15間的介面處，所 以可防止因該CMP步驟而造成該導電層18分離，且因而可 確保該CMP的條件會具有寬廣的邊限。 在該CMP步驟之後會使用檸檬酸水溶液、草酸水溶液等 來進行有機酸清洗，從而移除該互連18，之上的氧化物膜以 及在該CMP步驟之後仍殘留在該以表面上之Cu的抗腐蝕 劑（例如苯并三㈣生物）。而&，便會使用含石夕的材料（例 如三甲基矽烷（3MS)、氨（NH3)等）作為沉積氣體，利用 CVD在該互連18,與該層間絕緣膜15之上沉積一（例如）由碳 氮化矽（SiCN)所組成的覆蓋膜20至膜厚度為5〇 nm。 在上面所述的製造半導體裝置的方法中，會如配合圖 所述般地依序沉積該合金層17a及由純以所組成的導電層 17b所產生而形成該電鍍晶種層17。這能夠在合金層 提供增加的Μη濃度，同時抑制電鍍步驟的負擔。因此 便可在該合金層17a與該等層間絕緣膜12與15間的介面# 形成連續的自形成阻障膜19。這會提高該導電層18與咳= 層間絕緣膜12與15之間的黏著性，其能夠防止該導電層u 分離。結果，便能夠提高半導體裝置的產量。 #节’逛可 120673.doc -15· 200816379 確保用於形成該自形成阻障膜19的熱處置的條件及用於抛 光該導電層1 8的CMP的條件會具有寬廣的邊限。 此外，電鍍晶種層17的薄片電阻亦可設定為較低，其能 夠提面橫跨基板11之平面上該導電層18的覆蓋均勻性。所 以，便能夠抑制利用CMP來進行該導電層18之拋光中的淺 碟與侵蝕，其能夠提高互連可靠度。 再者，因為該合金層17&會被由純Cu所組成的導電層17b 〇 覆蓋，所以便可防止在該電鍍步驟中讓Μη溶析在電錢溶 液中。這可防止因連同該導電層18將]^11埋置在該互連溝 渠16之中而提高該互連18，的電阻。 表1顯示電鍍晶種層（1)(其會被套用根據本發明具體實施 例之製ie半導體裝置的方法）以及電鑛晶種層（2)與（3)(它們 並不會被套用本發明具體實施例）之薄片電阻數值的比較 結果。The hole 13 and then a channel 14 of, for example, w, is embedded in the channel hole 13. Then, decane (SiH4) is used as a deposition gas to form an interlayer insulating film composed of Si〇2 on the interlayer insulating film (4) by using, for example, electro-time-enhanced chemical vapor deposition (PECVD). 5. Then, a light P having an interconnected trench pattern and a pattern (not shown) are formed on the interlayer insulating film 15, and the photoresist pattern is used as a mask to perform (4). An interconnecting trench is formed in the interlayer insulating film to form a recess. The interconnected trench 16 has an aperture width of 75_. Now, Fig. 1B, for example, is buried by physical 矾 phase deposition (pvD) by % U JJ, for example, sputtering using a CiiMn alloy target, and θ is formed to form a CuMn on the 忒 interlayer insulating film 15. The alloy sound and the Meng slip 1 / a are formed to cover the inner wall of the interconnected trench 16 . Μη的电p and ancient Γι AA two J electric and the same as the resistance of Cii. Furthermore, in the later step, by thermal treatment, the Μn in the 〇 〇 层 layer 1 7a reacts with the 彳隹c 彳隹c in the interlayer insulating films 12 and 15 to form a self. A barrier film is formed. Therefore, the concentration of Μη in the alloy layer 17a and the film thickness of the alloy layer 17a are 120673.doc 200816379 degrees, which are derogated within a specific range. Specifically, values such as Μη concentration and film thickness may be equal to or greater than a thermal self-disposal in a later step for forming a continuous self-forming barrier at the interface between the alloy layer 17a and the interlayer insulating films 12 and 15. The lower limit of the membrane. In addition, the values of Μη concentration and film thickness are also equal to or less than the interconnect resistance used to create the interconnect formed in the interconnected trench 16 and containing residual Mn and the conductive layer which will be mainly composed of Cu. The layer is stacked on the alloy layer 17a (described later) to produce an upper limit of the allowable upper limit of the plating crystal f). Specifically, the concentration of Mn in the alloy layer 17a is in the range of 1 atomic percent to 1 atomic percent, and preferably, the Mn concentration is in the range of 2 atomic percent to 6 atomic percent. Further, the film thickness of the alloy layer 17 & will be defined to be not more than a specific value so that the quality of the filling by the electroplating layer by later plating is not deteriorated and is at most the upper limit described above. Specifically, in the smooth portion having no interconnected trench pattern, the film thickness of the alloy layer 17a is in the range of 丨〇 nm to 50 nm. For example, in the present example, the alloy layer 17a is formed to have a film thickness of 30 nm. Referring next to Fig. 1C, on the alloy layer 17a, a conductive layer 17b composed of, for example, pure Cu is formed, which has a film thickness of, for example, 3 Å. This forms an electroplated seed layer 17 by sequentially depositing the alloy layer 17a and the conductive layer 17b. This causes the conductive layer 17b composed of pure Cii to cover the surface side of the alloy layer 17a. Therefore, the plated seed layer 17 has a lower thin > 1 resistance than the plated seed layer formed of only the alloy layer 17a composed of CuMn. This suppresses the burden of the plating step for embedding a conductive layer in the interconnect trench 16 to be described later. 120673.doc -12- 200816379 In this example, the conductive layer 17b is composed of pure Cu. However, the material of the conductive layer 17b may be any material as long as it contains as its main component. For example, a CuAg alloy can also be used, which only slightly increases the south resistivity. The film thickness of the "Hi-V layer 1 7b" is set such that the sheet resistance of the plated seed layer layer is suppressed to an allowable range and filled by electroplating with a conductive layer. The above words will not be destroyed. Specifically, in the smooth portion having no interconnected trench pattern, the film thickness of the conductive layer 17b is in the range of 10 nm to 50 nm. In this example, the conductive layer i7b is formed to have a film thickness of 30 nm. Next, in the McCaw chart 1D, by electroplating, a conductive layer 18 made of, for example, pure Cu is formed on the conductive layer 17b until the film thickness is 800^ or more, so that Fill the interconnect trench _. In this = centering, the coverage uniformity of the conductive layer 18 across the plane of the substrate U is very south because the sheet resistance of the plated seed layer 17 is very low as described above. Furthermore, the surface side of the alloy layer Pa is covered by a pure conductive layer i7b. This prevents the Μη on the surface side of the alloy layer 17a from being eluted in the plating/liquid mixture, and thus prevents the The conductive layer 埋 is deposited in the plating solution and buried in the interconnected trench 16. Therefore, the interconnection resistance is prevented from increasing. Further, it is also prevented from being dissolved in the electric ore. The relationship of Μ in the solution has a negative effect on the plating step. In the present example, the conductive layer 18 is composed of pure Cu. However, the material of the conductive layer 1 can be any material as long as it contains Cu can be used as its main component. For example, CuAg alloy can also be used, which only slightly increases the resistivity of 120673.doc 200816379. Then, check Figure 1E, for example, it will be at 3〇〇. The heat treatment is performed for 3 minutes. This heat treatment reacts Mn (see FIG. 1A) in the alloy layer 17a with the components in the interlayer insulating films 12 and 15, so that the alloy layer 17a and the like Forming an interface between the interlayer insulating films 12 and 15 to prevent Cu diffusion. The barrier film 19 is formed. Preferably, the temperature and the treatment time for forming the heat treatment of the self-forming barrier film 19 are respectively 2 〇〇 〇Ο to 40 〇 t and 60 seconds to 2 hours, respectively. It is ensured that the self-forming barrier film 19 is formed and prevents a negative effect on the device due to the heat treatment. More preferably, the treatment time is between 60 seconds and 3 minutes. The interlayer insulating films 12 and 15 The "component" in the same also covers oxygen, water, etc. which are absorbed from the surface of the interlayer insulating film 12 and 15 in the environment. In the present embodiment, the layers (5) of the insulating film 12 and 15 are composed of Therefore, the self-forming barrier film 19 is composed of a Mn compound, for example, a cerium oxide containing cerium oxide (MnSix〇y) or an oxide (Mn). The film thickness of the self-forming barrier film 19 is formed. 2 to 3 nm. The alloy layer 17a contains Mn' having such a high concentration to form a continuous self-forming barrier film 19. This allows a larger amount of Mn to be supplied to the alloy layer 17a as compared to the existing method. At the interface between the interlayer insulating films 12 and 15, which allows the formation of a continuous self-shape of the firm blade The barrier film 19 also provides an extremely high adhesion. This prevents the separation of the j-conducting layer 18 from occurring due to changes in the critical stress at the initial stage of the thermal treatment. Furthermore, it is also ensured that the condition of the heat treatment will have ' The κ spoon margin is derived from the heat treatment relationship, and Mn is also precipitated on the surface side of the conductive layer 8, which forms a Mn layer m. Field 120673.doc -14- 200816379 Next > Figure 1F, which will Two-stage polishing is performed by, for example, CMp. In the first-stage polishing, the layer that removes germanium is referred to as FIG. 1E) and the portion of conductive layer 18 that does not have to be an interconnect pattern (see FIG. 1E). Next, in the second-stage polishing, the self-forming barrier film j 9 is removed and the exposed interlayer insulating film 15 is polished downward (10) nm. This forms an interconnect 丨8 formed of Cu in the interconnect trench. Because the self-forming barrier film 19 is located in the conductive layer 18 and the interlayer insulating films 12 and 15 The intervening interface prevents the separation of the conductive layer 18 due to the CMP step, and thus ensures that the conditions of the CMP have a wide margin. After the CMP step, an aqueous solution of citric acid, an aqueous solution of oxalic acid, or the like is used. An organic acid cleaning is performed to remove the oxide film on the interconnect 18 and the anti-corrosive agent (such as benzotri(III)) remaining on the surface after the CMP step. And & A material containing a stellite (for example, trimethyl decane (3MS), ammonia (NH3), etc.) is used as a deposition gas, and CVD is used on the interconnection 18 to deposit a (for example) on the interlayer insulating film 15 The cover film 20 composed of tantalum carbonitride (SiCN) has a film thickness of 5 〇 nm. In the above method for fabricating a semiconductor device, the alloy layer 17a is sequentially deposited as described in conjunction with the drawings. Purely formed by the conductive layer 17b formed to form the plating The seed layer 17. This can provide an increased concentration of Μη in the alloy layer while suppressing the burden of the plating step. Therefore, a continuous self-forming barrier can be formed between the alloy layer 17a and the interface # between the interlayer insulating films 12 and 15. The film 19. This improves the adhesion between the conductive layer 18 and the cough interlayer insulating film 12 and 15, which can prevent the conductive layer u from being separated. As a result, the yield of the semiconductor device can be improved. #节'逛可120673. Doc -15·200816379 It is ensured that the conditions for forming the heat treatment of the self-forming barrier film 19 and the conditions for polishing the CMP of the conductive layer 18 have a wide margin. Further, the thin plate of the seed layer 17 is plated. The resistance can also be set lower, which can cover the uniformity of coverage of the conductive layer 18 across the plane of the substrate 11. Therefore, it is possible to suppress the shallow dish and erosion in the polishing of the conductive layer 18 by CMP. It is possible to improve the reliability of the interconnection. Further, since the alloy layer 17 & is covered by the conductive layer 17b composed of pure Cu, it is possible to prevent the Μη from being eluted in the electricity money solution in the plating step. This prevents the cause The electrical resistance of the interconnect 18 is increased by embedding the conductive layer 18 with the conductive layer 18. Table 1 shows an electroplated seed layer (1) which will be applied in accordance with an embodiment of the present invention. The method of fabricating the semiconductor device and the comparison of the sheet resistance values of the electro-mineral seed layers (2) and (3) which are not applied to the specific embodiment of the present invention.

n層（d金層17 a)之上沉積一膜厚度30 nm之純Cu層（導 電層17b)所獲得的。電鍍晶種層（2)係由膜厚度6〇 A%-含MiU^CuMn層所形成的。如表中所示，可以確定的 係，電鍍晶種層（1)的薄片電阻會遠低於電鍍晶種層（2)的 120673.doc -16- 200816379 薄片電阻。電鍍晶種層（3)係由膜厚度6〇 nm之A%_含 CuMn層所形成的，所以，Μη濃度為電鍍晶種層（2)Mn濃 度的一半。如表中所示，可以確定的係，電鍍晶種層（1)的 薄片電阻會低於電鍍晶種層（3)的薄片電阻，不過，電鍍晶 種層（3)的總Μη濃度則會等於電鍍晶種層（1)的總Mn濃度。 結果，可以確定的係，相較於僅由該合金層17a來形成該 電鍍晶種層1 7的情況，透過在由CuMn所組成的合金層丨 Ο 之上沉積由純〜所組成的導電層17b便會大幅地降低該電 鐘晶種層17的薄片電阻。 (第二具體實施例） 下文將參考圖2A至2K作為製造步驟斷面圖來說明根據 本發明第二具體實施例之製造半導體裝置的方法。為說明 根據本發明第二具體實施例的方法，現在將說明會在第一 具體實施例中所述之覆蓋膜上方形成一雙镶欲互連結構的 範例。 〇 首先參考圖2A，在覆盍膜20之上，（例如）會藉由pE_ CVD來’儿積一（例如）由Si〇2所組成的層間絕緣膜2 1至膜厚 度為350 nm。接著，便會在該層間絕緣膜^之上形成一具 ㈣道孔圖案的光阻圖案（圖中並未顯示），並且接著㈣ 此光阻®案作為遮罩來進行似彳而形成—會抵達該覆蓋 膜20的通道孔22a。 接著參考圖2B，以在層間絕緣膜21之上會塗敷一光阻r 之方式’用以填充該通道孔22a。接著便會在該光阻r之上 形成一旋塗玻璃（S0G)膜，並且接著會在該s〇g膜之上形 120673.doc 17 200816379 成一具有互連溝渠圖案的光阻圖案（圖中並未顯示）。而 後，便會利用該光阻圖案作為遮罩來進行_以處理該 SOG膜’從而形成一硬遮罩23。 /接著參考圖2C，其會利用該硬遮罩23作為#刻遮罩來進 行蝕刻以處理該光阻R(參見圖π)，從而形成—具有互連A layer of a pure Cu layer (conductive layer 17b) having a film thickness of 30 nm was deposited on the n layer (d gold layer 17a). The electroplated seed layer (2) is formed by a film thickness of 6 Å A% - containing a MiU^CuMn layer. As shown in the table, the sheet resistance of the plated seed layer (1) is much lower than that of the plated layer (2) of 120673.doc -16-200816379 sheet resistance. The plating seed layer (3) is formed of A%_CuMn-containing layer having a film thickness of 6 Å, so that the Μη concentration is half of the Mn concentration of the plating seed layer (2). As shown in the table, the determined sheet resistance, the sheet resistance of the plated seed layer (1) will be lower than the sheet resistance of the plated seed layer (3), but the total Μη concentration of the plated seed layer (3) will Equal to the total Mn concentration of the plated seed layer (1). As a result, a system which can be determined is formed by depositing a conductive layer composed of pure ~ on the alloy layer 由 composed of CuMn as compared with the case where the plating seed layer 17 is formed only by the alloy layer 17a. 17b greatly reduces the sheet resistance of the seed layer 17 of the electric clock. (Second Embodiment) A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described below with reference to Figs. 2A to 2K as sectional views of manufacturing steps. In order to explain the method according to the second embodiment of the present invention, an example in which a double-embedded interconnect structure is formed over the cover film described in the first embodiment will now be described. Referring first to Fig. 2A, on the overlying film 20, for example, an interlayer insulating film 21 composed of, for example, Si〇2 is deposited by pE_CVD to a film thickness of 350 nm. Then, a photoresist pattern (not shown) having a (four) via pattern is formed on the interlayer insulating film, and then (4) the photoresist film is formed as a mask to form a mask. The passage hole 22a of the cover film 20 is reached. Referring next to Fig. 2B, a photoresist r is applied over the interlayer insulating film 21 to fill the via hole 22a. Then, a spin-on-glass (S0G) film is formed on the photoresist r, and then a photoresist pattern having an interconnected trench pattern is formed on the s〇g film 120673.doc 17 200816379 (in the figure) Not shown). Then, the photoresist pattern is used as a mask to process the SOG film to form a hard mask 23. / Next, referring to FIG. 2C, the hard mask 23 is used as a #etch mask to etch to process the photoresist R (see FIG. π), thereby forming an interconnection.

溝渠圖案的光阻圖案R、覆蓋該通道孔22a之底部的光阻R 會被留下。 η ο 接著參考圖2D，其會利用該硬遮罩23(參見圖2C)與該光 阻圖案R，作為㈣遮罩來進行㈣，在該層間絕緣膜21的 上方側之中形成一會與該通道孔22a通連的互連溝渠。 這S幵y成一雙鑲肷孔徑22(凹部），其係由該互連溝渠22b及 與該互連溝渠22b之底部通連的通道孔22a所組成。該互連 溝渠22b的深度會透過控制蝕刻時間來控制。該通道孔22& 的孔徑寬度與深度分別為75 11111與11〇 nm。該互連溝渠22b 的孔徑寬度與深度分別為75 11]11至1〇〇 nm&15〇 nm。因為 光阻R會留在通道孔22a内部，所以可防止蝕刻該通道孔 22a的側壁’並且從而保持側壁的垂直性。 接著餐考圖4E，其會藉由灰化與化學清洗來移除光阻圖 案R’（參見圖2D)與光阻R(參見圖2〇)，以便曝露出該通道 孔22a底部處的覆蓋膜2〇。 接著’如圖2F中所示，該通道孔22a底部處的覆蓋膜2〇 會被移除’從而曝露出該互連，的表面。 接著參考圖2G，其會（例如）藉由濺鍍而在該層間絕緣膜 ry 1 p , 形成一由CuMn合金所組成的合金層24a，用以覆蓋 120673.doc -18- 200816379 该雙鑲嵌孔徑22的内壁。和第一具體實施例雷目，合金層 24a中Μη濃度係在1原子百分比至1〇原子百分比之範圍， 且較佳的係，該Μη濃度係在2原子百分比至6原子百分比 之範圍。在不具有任何互連溝渠圖案的平滑部分中，合金 層24a的膜厚度係在1〇11]11至5〇11111之範圍。 接著參考圖2H，其會在合金層24a之上形成一（例如）由 純Cu所組成的導電層24b。這會藉由依序沉積該合金層2乜 〇 與該導電層24b所產生而形成一電鍍晶種層24。和第一具 體實施例雷同，在不具有任何互連溝渠圖案的平滑部分 中’此導電層24b的膜厚度係在1〇ηηι至50 nm之範圍。 接著參考圖21，以在該（^層2413之上會形成一由純⑸所 組成的導電層25之方式，以便填充該雙鑲嵌孔徑22。 接著參考圖2J，舉例來說，其會在3〇(rc處進行3〇分鐘 的熱處置。此熱處置會讓合金層24a中的Mn(參見圖21)與 該層間絕緣膜21的成分進行反應，從而在該合金層2牦與 L) 該層間絕緣膜21間的介面處形成一具有防止Cu擴散功能由 Μη化合物所組成的自形成阻障膜26。和第一具體實施例 雷同’該層間絕緣膜2 1係由Si〇2所組成，所以該自形成阻 障膜26係由含矽的Mn氧化物（MnSix〇y)或是Mn氧化物 (Mnx〇y)所組成。該自形成阻障膜26的膜厚度係2 nm至3 nm ° 接著參考圖2K，其會（例如）藉由CMP來進行雙級拋光。 在第一級拋光中，會移除MnO層M(參見圖2J)及不必作為 互連圖案的導電層25部分（參見圖2J)。接著，在第二級拋 120673.doc -19- 200816379 光中，會移除該自形成阻障膜26，並且會將外露的層間絕 緣膜21向下拋光100 nm。這會導致在該通道孔22&之中形 成會與該互連18’通連的通道25a，以及在該互連溝渠2孔之 中形成一互連25b’。 接著，便會使用檸檬酸水溶液、草酸水溶液等來進行有 機酸清洗，從而移除該互連25b，之上的氧化物膜以及在該 CMP步驟之後仍殘留在該Cu表面上之以的抗腐蝕劑。而 〇 後便會在該互連25b，與該層間絕緣膜21之上沉積一（例如） 由SiCN所組成的覆蓋膜27至膜厚度為5〇 。 在此製造半導體裝置的方法中，會如配合圖2(}與2]^所 述般地依序沉積由CuMn所組成的合金層24a及由純Cu所組 成的導電層24b以產生而形成該電鍍晶種層24。此能夠提 供和第一具體實施例所提供者相同的優點。 在上面所述之根據第一與第二具體實施例的範例中，該 等合金層17a與24a係由CuMn所組成。除了 Μη以外，該等 j 合金層1化與24&中内含的非Cu金屬範例包含：鋁（Α1)、鋅 (Ζη)、鉻（Cr)、釩（V)、鈦（Ti)、以及鈕（Ta)。舉例來說， 當合金層17a與24a係由CuAl所組成時，那麼便會形成（例 如）έ石夕的A1氧化物（AlSixOy)或A1氧化物（Alx〇y)作為自形 成阻障膜19。當合金層17a與24a係由CuZnm組成時，那麼 便會形成（例如）含矽的Ζη氧化物（ZnSix〇y)或Zn氧化物 (ZnxOy)作為自形成阻障膜19。同樣地，對上面所述的其它 金屬來說，亦可形成雷同的矽化合物或氧化物。 在上面所述的具體實施例中，係以含矽的氧化物 120673.doc -20- 200816379 (MnSixOy)或Μη氧化物（Mnx〇y)作為該等自形成阻障膜μ與 26的Μη化合物。不過，於特定的情況中，倘若該等層間 絕緣膜12、15、以及21係由含碳的絕緣膜（例如有機絕緣 膜）所構成的活，那麼便會形成Μη碳化物（MnxCy)作為該等 自形成阻障膜19與26 WMn化合物。再者，於特定情況 中，倘若使用上面所述CuAi4CuTi作為合金層17a的話， 那麼便會形成A1奴化物（AixCy)或碳化鈦（TixCy)。同樣地，The photoresist pattern R of the trench pattern, and the photoresist R covering the bottom of the via hole 22a are left. Next, referring to FIG. 2D, the hard mask 23 (see FIG. 2C) and the photoresist pattern R are used as (4) masks to perform (4), and a layer is formed in the upper side of the interlayer insulating film 21. The via hole 22a is connected to the interconnected trench. This S幵y is formed into a double-inserted aperture 22 (recess) which is composed of the interconnecting trench 22b and a via hole 22a which is connected to the bottom of the interconnected trench 22b. The depth of the interconnect trench 22b is controlled by controlling the etch time. The aperture width and depth of the channel holes 22& are 75 11111 and 11 〇 nm, respectively. The interconnect trench 22b has an aperture width and depth of 75 11]11 to 1 〇〇 nm & 15 〇 nm, respectively. Since the photoresist R remains inside the via hole 22a, the side wall ' of the via hole 22a can be prevented from being etched and thus the verticality of the sidewall can be maintained. Next, the sample is shown in FIG. 4E, which removes the photoresist pattern R' (see FIG. 2D) and the photoresist R (see FIG. 2A) by ashing and chemical cleaning to expose the coverage at the bottom of the via hole 22a. Membrane 2 〇. Next, as shown in Fig. 2F, the cover film 2 at the bottom of the via hole 22a is removed' to expose the surface of the interconnect. Referring next to FIG. 2G, an alloy layer 24a composed of a CuMn alloy is formed on the interlayer insulating film ry 1 p by sputtering, for example, to cover 120673.doc -18-200816379. The inner wall of 22. As in the first embodiment, the concentration of Μη in the alloy layer 24a is in the range of 1 atomic percent to 1 atomic percent, and preferably, the Μη concentration is in the range of 2 atomic percent to 6 atomic percent. In the smooth portion having no interconnected trench pattern, the film thickness of the alloy layer 24a is in the range of 1 〇 11] 11 to 5 〇 11111. Referring next to Figure 2H, a conductive layer 24b of, for example, pure Cu is formed over the alloy layer 24a. This forms an electroplated seed layer 24 by sequentially depositing the alloy layer 2乜 and the conductive layer 24b. Similar to the first specific embodiment, the film thickness of the conductive layer 24b is in the range of 1 〇ηη to 50 nm in a smooth portion having no interconnected trench pattern. Referring next to Fig. 21, a conductive layer 25 composed of pure (5) is formed over the layer 2413 to fill the dual damascene aperture 22. Referring next to Fig. 2J, for example, it will be at 〇 (3 minutes of heat treatment at rc. This heat treatment causes Mn in the alloy layer 24a (see Fig. 21) to react with the composition of the interlayer insulating film 21, thereby in the alloy layer 2牦 and L) A self-forming barrier film 26 having a function of preventing Cu diffusion from being composed of a ΜN compound is formed at the interface between the interlayer insulating films 21. Like the first embodiment, the interlayer insulating film 2 1 is composed of Si 〇 2 Therefore, the self-forming barrier film 26 is composed of Mn-containing Mn oxide (MnSix〇y) or Mn oxide (Mnx〇y). The film thickness of the self-forming barrier film 26 is 2 nm to 3 nm. ° Next, referring to FIG. 2K, it is possible to perform two-stage polishing, for example, by CMP. In the first-stage polishing, the MnO layer M (see FIG. 2J) and the portion of the conductive layer 25 that does not have to be an interconnection pattern are removed (see FIG. 2J) ( See Fig. 2J). Next, in the second stage throwing 120673.doc -19-200816379 light, the self-forming barrier film 2 is removed. 6, and the exposed interlayer insulating film 21 is polished downward by 100 nm. This causes a channel 25a to be connected to the interconnect 18' to be formed in the via hole 22& and a hole in the interconnect trench 2 Forming an interconnection 25b'. Next, an organic acid cleaning is performed using an aqueous citric acid solution, an aqueous oxalic acid solution, or the like, thereby removing the oxide film on the interconnection 25b, and remaining in the CMP step. An anti-corrosion agent on the surface of the Cu, and a coating film 27 composed of, for example, SiCN is deposited on the interconnection 25b and the interlayer insulating film 21 to a film thickness of 5 Å. In the method of fabricating a semiconductor device, an alloy layer 24a composed of CuMn and a conductive layer 24b composed of pure Cu are sequentially deposited as described in conjunction with FIG. 2 (} and 2) to form the plating crystal. The layer 24. This can provide the same advantages as those provided by the first embodiment. In the examples according to the first and second embodiments described above, the alloy layers 17a and 24a are composed of CuMn. In addition to Μη, these j alloy layers are 1 & 24& Examples of non-Cu metals contained in amp include: aluminum (Α1), zinc (Ζη), chromium (Cr), vanadium (V), titanium (Ti), and button (Ta). For example, when the alloy layer When 17a and 24a are composed of CuAl, then, for example, A1 oxide (AlSixOy) or Al oxide (Alx〇y) of the ruthenium is formed as the self-forming barrier film 19. When the alloy layers 17a and 24a When it is composed of CuZnm, for example, yttrium-containing yttrium oxide (ZnSix〇y) or Zn oxide (ZnxOy) is formed as the self-forming barrier film 19. Similarly, similar bismuth compounds or oxides may be formed for the other metals described above. In the specific examples described above, the ruthenium-containing oxides 120673.doc -20-200816379 (MnSixOy) or Μη oxides (Mnx〇y) are used as the Μη compounds of the self-forming barrier films μ and 26. . However, in a specific case, if the interlayer insulating films 12, 15, and 21 are made of a carbon-containing insulating film (for example, an organic insulating film), then Μn carbide (MnxCy) is formed as the The self-forming barrier film 19 and 26 WMn compounds. Further, in a specific case, if CuAi4CuTi as described above is used as the alloy layer 17a, A1Cy (AixCy) or titanium carbide (TixCy) is formed. Similarly,

對上面所述的其它金屬來說，亦可形成雷同的金屬碳化 物0 热悉本技術人士應瞭解，於隨附申請專利範圍或宜等嗖 範圍之範相，可依據料需求與其它因素來進行錄修 改、組合、子組合、以及變更。 【圖式簡單說明】 圖1A至1F係解釋根據發明第—具體實施例之製造半導 體裝置之方法的製造步驟之斷面圖； 至⑽解釋用於根據本發明第二具體實施例之製 仏半¥體裝置之方法的製造步驟之斷面圖； 驟之斷面圖；A <見存方法的製造步 圖4係解釋和製造半導體 斷面圖。 破置之現存方法有關的問題之 【主要元件符號說明】 11 基板 層間絕緣膜 120673.doc 200816379For the other metals mentioned above, the same metal carbides can be formed. 0 It should be understood by those skilled in the art that the scope of the accompanying patent application or the range of the equivalent range can be based on material requirements and other factors. Make changes, combinations, sub-combinations, and changes. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1F are cross-sectional views explaining a manufacturing step of a method of manufacturing a semiconductor device according to a first embodiment of the present invention; and (10) are explained for a half of a second embodiment according to the present invention. Sectional view of the manufacturing steps of the method of the body device; sectional view of the step; A < Manufacturing step of the method of storage. Fig. 4 is a sectional view of the semiconductor. Problems related to existing methods of breaking [Major component symbol description] 11 Substrate Interlayer insulating film 120673.doc 200816379

Ο 13 通道孔 14 通道 15 層間絕緣膜 16 互連溝渠 17 電鍍晶種層 17a 合金層 17b 導電層 171 電鍍晶種層 18 導電層 181 互連 19 自形成屏障阻障膜 20 覆蓋膜 21 層間絕緣膜 22 雙鑲嵌孔徑 22a 通道子L 22b 互連溝渠 23 硬遮罩 24 電鍍晶種層 24a 合金層 24b 導電層 25 導電層 25a， 通道 25bf 互連層互連 26 自動形成自形成屏障阻障膜 120673.doc -22- 200816379 27 蓋膜覆蓋膜 Μ 氧化猛層 R 光阻 R’ 光阻圖案 120673.doc -23Ο 13 channel hole 14 channel 15 interlayer insulating film 16 interconnection trench 17 plating seed layer 17a alloy layer 17b conductive layer 171 plating seed layer 18 conductive layer 181 interconnection 19 self-forming barrier film 20 cover film 21 interlayer insulating film 22 Double mosaic aperture 22a Channel sub-L 22b Interconnect trench 23 Hard mask 24 Plating seed layer 24a Alloy layer 24b Conductive layer 25 Conductive layer 25a, Channel 25bf Interconnect layer interconnection 26 Automatic formation of self-forming barrier barrier film 120673. Doc -22- 200816379 27 Cover film Μ Oxidation blasting R photoresist R'resist pattern 120673.doc -23

Claims (1)

種製造半導體裝置的方法，該方法包括下面步輝 在位於一基板上方的絕緣膜之中形成一凹部；' ’該電 成的合 上會設A method of fabricating a semiconductor device, the method comprising the steps of forming a recess in an insulating film over a substrate; ''the electrical junction is set Ο 200816379 十、申請專利範圍·· 以覆蓋該凹部内壁之方式來形成一電錢晶種層 鍍晶種層係藉由依序沉積一由銅與一非銅金屬結 金層以及—主要由Cu所組成的導電層而產生的，· 藉由電鑛將主要由銅所組成的導電層埋置在其 置該電鑛晶種層的凹部之中；以及 進行熱處置，以便讓該合金層中的金屬與該絕緣膜之 中：成分進行反應，從而形成—由金屬化合物所組成的 阻p早膜，其在該合金層與該絕緣膜間的介面處具有銅擴 散阻障功能。 〃 2·如請求項丨之製造半導體裝置的方法，其中 該非鋼金屬係錳，而該金屬化合物則係氧化錳。 3·如請求項丨之製造半導體裝置的方法，其中 该非鋼金屬係猛，而該金屬化合物則係含矽的氧化 !孟〇 120673.docΟ 200816379 X. Patent Application Scope · To form an electro-money seed layer plating seed layer by covering the inner wall of the concave portion by depositing a layer of copper and a non-copper metal gold layer and - mainly by Cu Produced by a conductive layer, by electrically depositing a conductive layer mainly composed of copper in a recess in which the seed layer of the electric ore is placed; and performing heat treatment so as to be in the alloy layer The metal reacts with the component of the insulating film to form a resistive early film composed of a metal compound having a copper diffusion barrier function at the interface between the alloy layer and the insulating film. A method of manufacturing a semiconductor device according to claim 2, wherein the non-steel metal is manganese, and the metal compound is manganese oxide. 3. A method of manufacturing a semiconductor device according to claim 1, wherein the non-steel metal is fierce, and the metal compound is oxidized by lanthanum! Meng Meng 120673.doc
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