JP5255198B2 - Method for manufacturing a conductor-dielectric interconnect structure - Google Patents

Method for manufacturing a conductor-dielectric interconnect structure Download PDF

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JP5255198B2
JP5255198B2 JP2006310984A JP2006310984A JP5255198B2 JP 5255198 B2 JP5255198 B2 JP 5255198B2 JP 2006310984 A JP2006310984 A JP 2006310984A JP 2006310984 A JP2006310984 A JP 2006310984A JP 5255198 B2 JP5255198 B2 JP 5255198B2
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seed layer
layer
plating
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JP2007150298A (en
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デビッド・エル・ラス
チン・チャオ・ヤン
ショム・ポノス
キース・ウォン・ホン・ウォン
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers

Description

本開示は、導体−誘電体構造およびこの導体−誘電体構造を作成するための方法に関する。詳細には本開示は、ＢＥＯＬ（Back End of the Line）相互接続構造を作成するための方法に関する。本開示は一般に、メタライゼーション内のボイディング（voiding）、シーム（seam）などの不連続部の発生を低減させる新規のプロセスに関する。本開示によれば、犠牲シード層を使用して、その下のめっきシード層の酸化を防ぐ。   The present disclosure relates to a conductor-dielectric structure and a method for making the conductor-dielectric structure. In particular, this disclosure relates to a method for creating a BEOL (Back End of the Line) interconnect structure. The present disclosure generally relates to a novel process for reducing the occurrence of discontinuities such as voiding and seams in metallization. According to the present disclosure, a sacrificial seed layer is used to prevent oxidation of the underlying plating seed layer.

半導体技術の製造中には、シリコン基板などの半導体基板上に様々な材料の膜が順番に付着され、パターン形成される。バック−エンド−オブ−ライン（ＢＥＯＬ）処理について言えば、これらの材料には、相互接続構造のためのメタライゼーション・レベル、絶縁およびキャッピング（capping）のために使用される誘電体レベル、ならびに相互接続の拡散および酸化を防ぐための障壁層が含まれる。相互接続メタライゼーション向けには現在、デュアル・ダマシン法で製作された銅メタライゼーションが選択されている。誘電体材料には、シラン（ＳｉＨ４）またはオルトケイ酸テトラエチル（ＴＥＯＳ）前駆物質を使用したプラズマ化学蒸着（ＰＥＣＶＤ）によって付着させた酸化シリコン、あるいは、化学蒸着（ＣＶＤ）によって付着させた、高性能相互接続応用向けの有機ケイ酸塩ガラス（organosilicateglass）またはホウリンケイ酸塩ガラス（borophosphosilicate glass：ＢＰＳＧ）が含まれる。有機ケイ酸塩ガラスは、高密度の形態または微細孔を含む形態として付着させることができる。 During the manufacture of semiconductor technology, films of various materials are sequentially deposited and patterned on a semiconductor substrate such as a silicon substrate. For back-end-of-line (BEOL) processing, these materials include metallization levels for interconnect structures, dielectric levels used for insulation and capping, and mutual A barrier layer is included to prevent connection diffusion and oxidation. For interconnect metallization, copper metallization fabricated by the dual damascene method is currently selected. For dielectric materials, silicon oxide deposited by plasma enhanced chemical vapor deposition (PECVD) using silane (SiH 4 ) or tetraethyl orthosilicate (TEOS) precursor, or high performance deposited by chemical vapor deposition (CVD) Organosilicate glass or borophosphosilicate glass (BPSG) for interconnect applications is included. The organosilicate glass can be deposited as a high density form or a form containing micropores.

障壁層の選択肢には、タンタル、窒化タンタル、窒化タングステン、ルテニウム、イリジウムおよびチタン、ならびにこれらの金属の合金が含まれる。   Barrier layer options include tantalum, tantalum nitride, tungsten nitride, ruthenium, iridium and titanium, and alloys of these metals.

クリティカル・ディメンジョン（critical dimension：ＣＤ）が低下するにつれ、拡散障壁およびＣｕめっきシードの付着に関し、物理蒸着（ＰＶＤ）技法に起因する共形性および被覆率の問題はいっそう深刻になる。これらの問題は、図９に示すような中心および縁のボイドなど、めっき中の充填の問題を引き起こし、この充填の問題は、信頼性に対する懸念および歩留りの低下を引き起こす。この問題を回避する１つの方法は、ＰＶＤ材料の全厚を低減させ、拡散障壁とめっきシードの両方の役目を果たす単一のライナ材料層を利用する方法である。前述の問題を克服する他の方法は、従来のＰＶＤ技法に比べて良好なステップ・カバレージおよび共形性を提供する化学蒸着（ＣＶＤ）または原子層付着（ＡＬＤ）を使用する方法である。   As the critical dimension (CD) decreases, the conformality and coverage problems due to physical vapor deposition (PVD) techniques become more serious with respect to diffusion barrier and Cu plating seed deposition. These problems cause filling problems during plating, such as center and edge voids as shown in FIG. 9, which cause reliability concerns and yield loss. One way to avoid this problem is to reduce the overall thickness of the PVD material and utilize a single liner material layer that acts as both a diffusion barrier and a plating seed. Another way to overcome the aforementioned problems is to use chemical vapor deposition (CVD) or atomic layer deposition (ALD) which provides better step coverage and conformality compared to conventional PVD techniques.

このような材料の一例がルテニウムである（O. Chyan et al.,"Electrodeposition of Coper Thin Film on Ruthenium: A Potential DiffusionBarrier for Copper Interconnects," J. Electrochem. Soc., 150(5), p. C347,2003）。しかし、Ｒｕの表面にＣｕをめっきすることの問題は、Ｒｕ表面が、空気にさらされると酸化しやすいことであり、表面が酸化すると導電率（およびおそらくは付着力）が低下し、その結果めっきが不良となる。パターン形成された構造の極めて不良な充填とは別に、表面酸化物へのＣｕの不十分な付着力は、エレクトロマイグレーションおよび応力信頼性の懸念を引き起こす。めっき前にフォーミング・ガスおよび水素プラズマに暴露してこの表面酸化物を還元するなどのプロセスの使用によって、この問題に対処することが提案されている。これらの技法の欠点は、１）表面酸化物が再び成長する前に還元されたウェハをめっきしなければならない時間枠（キュー・タイム（Queuetime））が存在すること、ならびに２）還元プロセスに必要な機械類による製造コストの増大および未処理の（raw）プロセス時間の増大などである。
米国特許出願公開 2004/178078 A1 米国特許 No. 5,486,282 米国特許出願 No. 09/348,632 米国特許 No. 6,331,237 B1 O. Chyan et al.,"Electrodeposition of Coper Thin Film on Ruthenium: A Potential DiffusionBarrier for Copper Interconnects," J. Electrochem. Soc., 150(5), p. C347,2003 An example of such a material is ruthenium (O. Chyan et al., “Electrodeposition of Coper Thin Film on Ruthenium: A Potential Diffusion Barrier for Copper Interconnects,” J. Electrochem. Soc., 150 (5), p. C347. , 2003). However, the problem with plating Cu on the surface of Ru is that the Ru surface is susceptible to oxidation when exposed to air, and the conductivity (and possibly adhesion) decreases when the surface is oxidized, resulting in plating. Becomes defective. Apart from the very poor filling of the patterned structure, the poor adhesion of Cu to the surface oxide causes electromigration and stress reliability concerns. It has been proposed to address this problem by using processes such as exposure to forming gas and hydrogen plasma prior to plating to reduce this surface oxide. The disadvantages of these techniques are: 1) there is a time frame (Queuetime) in which the reduced wafer must be plated before the surface oxide is grown again, and 2) required for the reduction process. Such as increased manufacturing costs due to complex machinery and increased raw process time.
U.S. Patent Application Publication 2004/178078 A1 U.S. Patent No. 5,486,282 US Patent Application No. 09 / 348,632 U.S. Patent No. 6,331,237 B1 O. Chyan et al., "Electrodeposition of Coper Thin Film on Ruthenium: A Potential Diffusion Barrier for Copper Interconnects," J. Electrochem. Soc., 150 (5), p. C347,2003

相互接続内のめっきボイドを排除しまたは少なくとも最小限に抑えることができ、現在のめっきツールおよびめっきプロセスと両立する方法が望ましい。   A method that eliminates or at least minimizes plating voids in the interconnect and is compatible with current plating tools and plating processes is desirable.

本開示は、相互接続フィーチャ内のめっきボイドを少なくとも最小限に抑えることを可能にする。   The present disclosure makes it possible to at least minimize plating voids in interconnect features.

具体的には本開示の一態様は相互接続構造を作成するための方法に関し、この方法は、パターン形成されたフィーチャをその内部に有する誘電体層を含む構造を用意するステップと、パターン形成されたフィーチャ内またはバイア内の誘電体層の表面にめっきシード層を付着させるステップと、パターン形成されたフィーチャ内またはバイア内のめっきシード層の表面に犠牲シード層を付着させるステップと、犠牲シード層の厚さを逆めっき（reverse plating）によって低減させるステップと、パターン形成されたフィーチャ内の犠牲シード層の表面に導電性金属をめっきするステップとを含む。   Specifically, one aspect of the present disclosure relates to a method for creating an interconnect structure, the method comprising: providing a structure including a dielectric layer having patterned features therein; Depositing a plating seed layer on the surface of the dielectric layer in the feature or via, depositing a sacrificial seed layer on the surface of the plating seed layer in the patterned feature or via, and sacrificial seed layer Reducing the thickness of the sacrificial seed layer by reverse plating and plating the surface of the sacrificial seed layer in the patterned feature with a conductive metal.

本開示の他の態様は構造に関し、この構造は、パターン形成されたフィーチャをその内部に有する誘電体層と、パターン形成されたフィーチャ内の誘電体層の表面のめっきシード層と、パターン形成されたフィーチャ内のめっきシード層の表面に位置する不連続な犠牲シード層とを含む。   Another aspect of the present disclosure relates to a structure, which is patterned with a dielectric layer having a patterned feature therein, a plating seed layer on the surface of the dielectric layer within the patterned feature, and And a discontinuous sacrificial seed layer located on the surface of the plating seed layer in the feature.

企図される最良の形態を例示することによって好ましい実施形態だけを示し説明した以下の詳細な説明を読めば、本開示の他の目的および利点が当業者には明白となろう。この開示は他の異なる実施形態を収容することができ、そのいくつか詳細は、この開示から逸脱することなく、明白な様々な点の変更を収容することができることを理解されたい。したがって以下の説明は単に例示を目的としたものあって、限定を意図したものではない。   Other objects and advantages of the present disclosure will become apparent to those skilled in the art after reading the following detailed description, which illustrates and describes only the preferred embodiments by way of illustration of the best mode contemplated. It should be understood that this disclosure can accommodate other different embodiments, and that some details can accommodate various obvious changes without departing from this disclosure. Accordingly, the following description is for illustrative purposes only and is not intended to be limiting.

新規の特徴であると考えられる本開示の諸特徴および本開示を特徴付ける諸要素は、添付の請求項に詳細に記載されている。図面は単に例示を目的にしたものである。しかし本開示は、その構成と機能方法の両方に関して、添付図面に関する以下の詳細な説明を参照することによって最もよく理解されることができる。   The features of this disclosure believed to be novel and the elements that characterize this disclosure are set forth with particularity in the appended claims. The drawings are for illustrative purposes only. However, the present disclosure can be best understood by referring to the following detailed description in conjunction with the accompanying drawings, both in terms of its construction and method of function.

本開示の理解を容易にするために図面を参照する。   To facilitate an understanding of the present disclosure, reference is made to the drawings.

従来技術の上記の問題および欠陥に留意し、本開示は、メタライゼーション内のボイディング、シームなどの不連続部の発生を低減することを可能にする構造を提供する。   Noting the above problems and deficiencies of the prior art, the present disclosure provides a structure that allows to reduce the occurrence of discontinuities such as voiding, seams, etc. in metallization.

図１に、層間誘電体１６、誘電体１６のトラフ（trough）の中に位置する障壁層１８、および障壁層１８の上に位置する導電層１７を含む構造を示す。符号１０および２０はそれぞれ、層間誘電体材料１４の中に位置するシングル・ダマシン・エッチング断面およびデュアル・ダマシン・エッチング断面を表す。符号１１は、シングル・ダマシン・エッチング断面１０内のトレンチを表す。符号１２は、デュアル・ダマシン・エッチング断面２０内のトレンチを表し、符号１３はバイアを表す。層間誘電体１６の表面、障壁層１８の上および導電層１７の一部分の上にはキャッピング層１５がある。   FIG. 1 shows a structure including an interlayer dielectric 16, a barrier layer 18 located in the trough of the dielectric 16, and a conductive layer 17 located on the barrier layer 18. Reference numerals 10 and 20 represent a single damascene etch section and a dual damascene etch section, respectively, located in the interlayer dielectric material 14. Reference numeral 11 represents a trench in the single damascene etch section 10. Reference numeral 12 represents a trench in the dual damascene etch section 20 and reference numeral 13 represents a via. A capping layer 15 is on the surface of the interlayer dielectric 16, on the barrier layer 18 and on a portion of the conductive layer 17.

一般的な絶縁または誘電体材料１４および１６は、二酸化シリコン（ＳｉＯ２）、リンケイ酸塩ガラス（ＰＳＧ）、ホウ素ドープ（boron doped）ＰＳＧ（ＢＤＰＳＧ）またはオルトケイ酸テトラエチル（ＴＥＯＳ）を含み、より一般的には誘電率３．９未満の低ｋ誘電体、例えばＳＩＬＫ（ダウ・ケミカル（DowChemical）社から入手可能）、ＳｉＣＨ（ＢＬＯＫの商品名でＡＭＡＴ社から入手可能）、ＳｉＣＯＨ（Ｃｏｒａｌの商品名でＮｏｖｅｌｌｕｓ社から、Ｂｌａｃｋ Ｄｉａｍｏｎｄの商品名でＡＭＡＴ社から、Ａｕｏｒａの商品名でＡＳＭ社から入手可能）、ＳｉＣＨＮ（Ｎ Ｂｌｏｋの商品名でＩＢＭ社から入手可能）、ＣＶＤ炭素ドープ酸化物、多孔質ＣＶＤ炭素ドープ酸化物、多孔質および無孔有機ケイ酸塩、多孔質および無孔有機スピンオン・ポリマーを含む。 Common insulating or dielectric materials 14 and 16 include silicon dioxide (SiO 2 ), phosphosilicate glass (PSG), boron doped PSG (BDPSG) or tetraethyl orthosilicate (TEOS), more commonly Low k dielectrics with a dielectric constant of less than 3.9, eg SILK (available from Dow Chemical), SiCH (available from AMAT under the name BLOK), SiCOH (Coral product) From Novellus, under the trade name Black Diamond, available from AMAT, under the trade name Aura, from ASM, SiCHN (available from IBM under the trade name N Block), CVD carbon-doped oxide, porous CVD carbon doped oxide, porous and nonporous organosilicate, porous and nonporous Including the spin-on polymer.

一般的なキャッピング層の例は、ＳｉＣＯＨ、Ｂｌｏｋ、ＳｉＯ２、ＮＢｌｏｋ、Ｓｉ３Ｎ４およびスピンオン・シルセスキオキサンである。キャッピング層の厚さは約１０ｎｍから約６０ｎｍである。キャッピング層１５の機能は、誘電体層１４中への相互接続材料１７の拡散を防ぐことである。 Examples of typical capping layer, SiCOH, Blok, a SiO 2, NBlok, Si 3 N 4 and spin-silsesquioxane. The thickness of the capping layer is about 10 nm to about 60 nm. The function of the capping layer 15 is to prevent the diffusion of the interconnect material 17 into the dielectric layer 14.

障壁層１８の例は、タンタル、窒化タンタル、チタン、窒化チタン、タングステン、窒化タングステン、ルテニウム、レニウム、コバルト、モリブデン、クロム、イリジウム、白金、シリコン、炭素、ジルコニウム、ニオブ、ロジウム、パラジウム、これらの混合物およびこれらの合金である。上記の金属の合金は、Ｏ、Ｓ、Ｎ、Ｂ、Ｐなどの様々な合金材料を含むことができる。ただし合金材料はこれらに限定されるわけではない。障壁層１８はまた、同じ組成の複数の層または異なる組成の複数の層、あるいはその両方を含むことができる。   Examples of the barrier layer 18 are tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, ruthenium, rhenium, cobalt, molybdenum, chromium, iridium, platinum, silicon, carbon, zirconium, niobium, rhodium, palladium, these Mixtures and their alloys. The above metal alloys can include various alloy materials such as O, S, N, B, and P. However, the alloy material is not limited to these. The barrier layer 18 can also include multiple layers of the same composition, multiple layers of different compositions, or both.

より一般的な障壁層は、タングステン、チタン、タンタル、これらの窒化物、Ｒｕ、およびこれらの合金である。障壁層１８は一般に、化学蒸着（ＣＶＤ）によって、または物理蒸着（ＰＶＤ）、イオン化物理蒸着（ＩＰＶＤ）などのスパッタリングによって付着される。   More common barrier layers are tungsten, titanium, tantalum, their nitrides, Ru, and their alloys. The barrier layer 18 is typically deposited by chemical vapor deposition (CVD) or by sputtering such as physical vapor deposition (PVD), ionized physical vapor deposition (IPVD).

障壁層の厚さは一般に約８ｎｍから８０ｎｍである。   The thickness of the barrier layer is generally about 8 to 80 nm.

導電材料は一般に、Ｃｕ、Ｃｕ合金、Ａｌ、Ａｌ合金、Ａｇ、Ａｇ合金、Ａｕ、Ａｕ合金、ＷまたはＷ合金であり、より一般的にはＣｕを含む導電材料（例えばＣｕおよびＣｕ合金）である。ＣｕおよびＣｕ合金用の一般的なめっき浴は、その開示が参照によって本明細書で組み込まれる米国特許出願公開2004/178078 A1に開示されている。   The conductive material is generally Cu, Cu alloy, Al, Al alloy, Ag, Ag alloy, Au, Au alloy, W or W alloy, and more generally a conductive material containing Cu (for example, Cu and Cu alloy). is there. Common plating baths for Cu and Cu alloys are disclosed in US Patent Application Publication No. 2004/178078 A1, the disclosure of which is incorporated herein by reference.

図２を参照する。この図では、構造の表面に、層間誘電体（ＩＬＤ）１４および導電層１７の露出部分を覆う拡散障壁／めっきシード層２１が付着されている。拡散障壁／めっきシード層２１は一般にルテニウムまたはイリジウムあるいはその両方を含む。層２１は複数の層、例えばＲｕとＴａもしくはＲｕとＴａＮ、またはＲｕとＴａとＴａＮ、ＩｒとＴａもしくはＩｒとＴａＮ、またはＩｒとＴａとＴａＮ、ＲｕとＴｉＳｉＮ、ＩｒとＴｉＳｉＮなどの複数の層を含むこともできる。   Please refer to FIG. In this figure, a diffusion barrier / plating seed layer 21 covering the exposed portion of the interlayer dielectric (ILD) 14 and conductive layer 17 is deposited on the surface of the structure. The diffusion barrier / plating seed layer 21 generally comprises ruthenium and / or iridium. Layer 21 is a plurality of layers such as Ru and Ta or Ru and TaN, or Ru and Ta and TaN, Ir and Ta or Ir and TaN, Ir and Ta and TaN, Ru and TiSiN, Ir and TiSiN, etc. Can also be included.

Ｒｕ、ＩｒおよびＴａＮに関して層２１は一般にＣＶＤまたはＡＬＤによって付着される。とはいえＲｕ、ＩｒおよびＴａＮの付着についてはＰＶＤ付着技術も使用可能である。   For Ru, Ir and TaN, layer 21 is typically deposited by CVD or ALD. Nevertheless, PVD deposition techniques can also be used for Ru, Ir and TaN deposition.

層２１の厚さは一般に約２ｎｍから８０ｎｍ、より一般的には約４ｎｍから２０ｎｍである。   The thickness of layer 21 is generally about 2 nm to 80 nm, more typically about 4 nm to 20 nm.

次に、めっきシード層２１の上に、図３に示すような比較的に厚い犠牲シード層３１を付着させる。犠牲シード層３１は一般にＣｕまたはＣｕ合金であり、一般にＰＶＤによって付着される。   Next, a relatively thick sacrificial seed layer 31 as shown in FIG. 3 is deposited on the plating seed layer 21. The sacrificial seed layer 31 is typically Cu or a Cu alloy and is typically deposited by PVD.

層３１を付着させるのは、層２１の酸化を防ぎまたは少なくとも最小限に抑えるためである。犠牲シード層３１は、めっきシード層２１と同じ真空中で操作されるプラットホームで付着され、そのためこれらの２つの膜の付着と付着の間に空気への暴露は起こらず、付着された層２１の表面は酸素を含まない。プラットホームはいくつかの付着チャンバを含み、これらのチャンバとチャンバの間のウェハの輸送は真空で実施され、その間に空気への暴露は生じない。   The layer 31 is deposited in order to prevent or at least minimize the oxidation of the layer 21. The sacrificial seed layer 31 is deposited on a platform operated in the same vacuum as the plating seed layer 21, so that no exposure to air occurs between the deposition of these two films, and the deposition of the deposited layer 21. The surface does not contain oxygen. The platform includes several deposition chambers, and wafer transfer between these chambers is performed in a vacuum, during which no exposure to air occurs.

犠牲シード層３１の厚さは一般に約３ｎｍから約１００ｎｍ、より一般的には約５ｎｍから約５０ｎｍである。この層は、下層２１を酸化の危険にさらす可能性がある不連続部またはピン・ホールあるいはその両方の可能性を最小限に抑えるため十分に厚い必要がある。   The thickness of the sacrificial seed layer 31 is generally about 3 nm to about 100 nm, more typically about 5 nm to about 50 nm. This layer should be thick enough to minimize the possibility of discontinuities and / or pin holes that could expose the lower layer 21 to oxidation hazard.

単一のプラットホーム内で層２１および３１を付着させた後、犠牲層３１の厚さ低減プロセス（thickness thinning process）およびパターン形成されたフィーチャ内への導電材料の付着のため、ウェハを別のプラットホームに移す。この厚さ低減プロセスおよび導電材料付着プロセスの間、ウェハはその全体がめっき浴の中に完全に浸される。   After depositing layers 21 and 31 within a single platform, the wafer is separated from another platform for the thickness thinning process of sacrificial layer 31 and the deposition of conductive material within the patterned features. Move to. During this thickness reduction process and conductive material deposition process, the entire wafer is completely immersed in the plating bath.

図４に示すように、逆めっきプロセスを使用することによって犠牲シード３１の厚さを低減させ、薄くされた層４１を作成する。この逆めっきプロセスは電気めっき浴中の電流を反転させることを含む。一般的な逆めっきプロセスは、本出願の譲受人であるＩＢＭ社（International Business Machines Corporation）に譲渡された、ダッタ（Datta）の米国特許No.5,486,282に記載されている。この厚さ低減プロセスは化学エッチングを含み、一例では第二銅イオンが銅と反応して第一銅イオンを形成する化学エッチングを含む。犠牲シード層３１の厚さ低減プロセスと導電層７１の付着プロセスは同じめっき浴中で実施され、これらのプロセスの間、ウェハはめっき浴中に完全に浸されるので、その下の層２１が空気にさらされることは完全に防止される。   As shown in FIG. 4, the thickness of the sacrificial seed 31 is reduced by using a reverse plating process to create a thinned layer 41. This reverse plating process involves reversing the current in the electroplating bath. A typical reverse plating process is described in U.S. Pat. No. 5,486,282 to Datta, assigned to IBM (International Business Machines Corporation), the assignee of the present application. This thickness reduction process includes chemical etching, and in one example includes chemical etching in which cupric ions react with copper to form cuprous ions. The sacrificial seed layer 31 thickness reduction process and the conductive layer 71 deposition process are performed in the same plating bath, and during these processes the wafer is fully immersed in the plating bath so that the underlying layer 21 is Exposure to air is completely prevented.

薄くされた犠牲層の厚さは一般に層３１の厚さの５０％未満、より一般的には層３１の厚さの２０％未満である。   The thickness of the thinned sacrificial layer is generally less than 50% of the thickness of layer 31, and more typically less than 20% of the thickness of layer 31.

よりいっそう一般的なプロセスでは、この逆めっきプロセスを継続して図５に示すような不連続な犠牲シード層５１を作成する。この不連続な犠牲シード層５１の厚さは一般に１ｎｍから約１０ｎｍであり、この層はその下の層２１の少なくとも約３０％を覆う。   In a more general process, the reverse plating process is continued to create a discontinuous sacrificial seed layer 51 as shown in FIG. The thickness of the discontinuous sacrificial seed layer 51 is generally from 1 nm to about 10 nm, and this layer covers at least about 30% of the underlying layer 21.

所望の厚さの層４１が得られたときを決定するため、図６に示すように、この逆めっきプロセスの間、ウェハの抵抗率を監視することができる。   To determine when the desired thickness of layer 41 is obtained, the resistivity of the wafer can be monitored during this reverse plating process, as shown in FIG.

次に、図７に示すように、一般に無電解めっきまたは電気めっきによって、導電性相互接続７１をブランケット付着させて、開口１１、１２および１３を埋める。一般的な相互接続材料７１は、Ｃｕ、ＣｕＡｌなどのＣｕ合金、Ａｌ、ＡｌＣｕなどのＡｌ合金、Ａｇ、Ａｇ合金、Ａｕ、Ａｕ合金、ＷおよびＷ合金であり、ＣｕおよびＣｕ合金がより一般的である。適当な無電解めっき浴および電気めっき浴は知られており、本明細書で説明する必要はない（とはいえ可能ならば何らかの文献を参照されたい）。一般的な技法は、米国特許出願No. 09/348,632およびアンドリカコス（Andricacos）他の米国特許No. 6,331,237 B1に開示されている。犠牲シード層３１の厚さ低減プロセスと導電層７１の付着プロセスは同じめっき浴中で実施され、これらのプロセスの間、ウェハはめっき浴中に完全に浸されるので、その下の層２１が空気にさらされることは完全に防止される。   Next, as shown in FIG. 7, conductive interconnects 71 are blanket deposited, typically by electroless plating or electroplating, to fill openings 11, 12, and 13. Common interconnect materials 71 are Cu alloys such as Cu and CuAl, Al alloys such as Al and AlCu, Ag, Ag alloys, Au, Au alloys, W and W alloys, with Cu and Cu alloys being more common It is. Suitable electroless and electroplating baths are known and need not be described herein (although, if possible, see some literature). General techniques are disclosed in US Patent Application No. 09 / 348,632 and Andricacos et al., US Patent No. 6,331,237 B1. The sacrificial seed layer 31 thickness reduction process and the conductive layer 71 deposition process are performed in the same plating bath, and during these processes the wafer is fully immersed in the plating bath so that the underlying layer 21 is Exposure to air is completely prevented.

次いで、図８に示すように、この構造を化学機械研磨（ＣＭＰ）などによって平坦化して、過剰な相互接続材料７１を除去する。ＣＭＰ用の一般的なスラリは、アルミナ、シリカ、セリア、ジルコニア、二酸化チタンなどの研磨粒子、および硝酸第二鉄、ヨウ素酸カリウム、硝酸アンモニウムセリウム、フェリシアン化カリウム、硝酸銀、次亜塩素酸ナトリウム、過塩素酸カリウム、過マンガン酸カリウム、過酸化水素などの酸化剤を含む。   Next, as shown in FIG. 8, the structure is planarized by chemical mechanical polishing (CMP) or the like to remove excess interconnect material 71. Typical slurry for CMP is abrasive particles such as alumina, silica, ceria, zirconia, titanium dioxide, and ferric nitrate, potassium iodate, cerium ammonium nitrate, potassium ferricyanide, silver nitrate, sodium hypochlorite, perchlorine Contains oxidizing agents such as potassium acid, potassium permanganate, and hydrogen peroxide.

以上の記述は本開示を示し説明したものである。さらに、本開示は好ましい実施形態だけを示し説明したものであるが、前述のとおり本開示は、他の様々な組合せ、変更および環境での使用を収容することができ、上記の教示または関連技術の技能もしくは知識あるいはその両方に対応する、本明細書に表現された本発明のコンセプトの範囲内の変更または修正を収容することができる。さらに、本明細書に説明した実施形態は、出願人が知る最良の形態を説明すること、ならびに、このような実施形態または他の実施形態において、およびその特定の応用または使用が要求する様々な修正を加えて、当業者が本開示を利用することができるようにすることを意図したものである。したがって以上の記述は、本明細書に開示された形態に本発明を限定することを意図したものではない。または、添付の請求項は代替の実施形態を含むものと解釈されたい。   The above description illustrates and describes the present disclosure. Further, although the present disclosure has shown and described only preferred embodiments, as described above, the present disclosure can accommodate various other combinations, modifications, and uses in the environment, and the above teachings or related techniques. Changes or modifications within the scope of the inventive concept expressed herein may be accommodated which correspond to the skills and / or knowledge of the present invention. Further, the embodiments described herein describe the best mode known to the applicant, as well as the various applications required in such and other embodiments and for their particular application or use. The modifications are intended to enable those skilled in the art to utilize the present disclosure. Accordingly, the above description is not intended to limit the invention to the form disclosed herein. Alternatively, the appended claims should be construed to include alternative embodiments.

本明細書に引用された出版物および特許出願はすべて、あたかもこれらが参照によって本明細書に組み込まれると個別かつ明確に示されたかのように、あらゆる目的のため参照によって本明細書に組み込まれる。   All publications and patent applications cited herein are hereby incorporated by reference for all purposes as if they were individually and clearly indicated as incorporated herein by reference.

本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 抵抗率のｉｎ−ｓｉｔｕ監視を示すグラフである。It is a graph which shows the in-situ monitoring of resistivity. 本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 本開示の製造プロセスの一段階における構造の概略断面図である。It is a schematic sectional drawing of the structure in one step of the manufacturing process of this indication. 将来のノードにおけるＣＤの低下に起因するボイドを示す概略断面図である。It is a schematic sectional drawing which shows the void resulting from the fall of CD in a future node.

符号の説明Explanation of symbols

１０ シングル・ダマシン・エッチング断面
１１ トレンチ
１２ トレンチ
１３ バイア
１４ 層間誘電体
１５ キャッピング層
１６ 層間誘電体
１７ 導電層
１８ 障壁層
２０ デュアル・ダマシン・エッチング断面
２１ めっきシード層
３１ 犠牲シード層
４１ 薄くされた層
５１ 不連続な犠牲シード層
７１ 導電層 10 Single Damascene Etched Section 11 Trench 12 Trench 13 Via 14 Interlayer Dielectric 15 Capping Layer 16 Interlayer Dielectric 17 Conductive Layer 18 Barrier Layer 20 Dual Damascene Etched Section 21 Plating Seed Layer 31 Sacrificial Seed Layer 41 Thinned Layer 51 Discontinuous sacrificial seed layer 71 Conductive layer

Claims (7)

導体−誘電体相互接続構造を製造するための方法であって、
パターン形成された凹部をその内部に有する誘電体層を含む構造を用意するステップと、
前記パターン形成された凹部内の前記誘電体層の表面にＲｕまたはＩｒあるいはその両方を含むめっきシード層を付着するステップと、
前記パターン形成された凹部内の前記めっきシード層の表面にＣｕまたはＣｕ合金を含む犠牲シード層を付着するステップと、
前記犠牲シード層の厚さをめっき浴中での逆めっきによって元の厚さの少なくとも５０％まで低減させるステップと、
前記パターン形成された凹部内の厚さが減少された前記犠牲シード層の表面に前記めっき浴中でＣｕ、Ａｌ、Ａｇ、Ａｕ、Ｗおよびこれらの合金からなるグループから選択される導電材料をめっきするステップと、
を含む方法。 A method for manufacturing a conductor-dielectric interconnect structure comprising:
Providing a structure including a dielectric layer having patterned recesses therein;
Depositing a plating seed layer comprising Ru or Ir or both on the surface of the dielectric layer in the patterned recess;
Depositing a sacrificial seed layer comprising Cu or a Cu alloy on the surface of the plating seed layer in the patterned recess;
Reducing the thickness of the sacrificial seed layer to at least 50% of its original thickness by reverse plating in a plating bath;
A conductive material selected from the group consisting of Cu, Al, Ag, Au, W and alloys thereof is plated in the plating bath on the surface of the sacrificial seed layer having a reduced thickness in the patterned recess. And steps to
Including methods. 前記構造の前記パターン形成された凹部が、シングル・ダマシン構造またはデュアル・ダマシン構造あるいはその両方を含む、請求項１に記載の方法。   The method of claim 1, wherein the patterned recess of the structure comprises a single damascene structure, a dual damascene structure, or both. 前記めっきシード層が、ＲｕとＴａもしくはＲｕとＴａＮ、またはＲｕとＴａとＴａＮ、あるいはＩｒとＴａもしくはＩｒとＴａＮ、またはＩｒとＴａとＴａＮ、あるいはＲｕとＴｉＳｉＮ、あるいはＩｒとＴｉＳｉＮを含む、請求項１に記載の方法。   The plating seed layer includes Ru and Ta or Ru and TaN, Ru and Ta and TaN, Ir and Ta or Ir and TaN, Ir and Ta and TaN, Ru and TiSiN, or Ir and TiSiN. Item 2. The method according to Item 1. 前記犠牲シード層の厚さが３ｎｍから１００ｎｍである、請求項１に記載の方法。   The method of claim 1, wherein the sacrificial seed layer has a thickness of 3 nm to 100 nm. 前記犠牲シード層の厚さを低減させるステップは、前記犠牲シード層の厚さを低減させて不連続な犠牲シード層を形成することを含む、請求項１に記載の方法。   The method of claim 1, wherein reducing the thickness of the sacrificial seed layer includes reducing the thickness of the sacrificial seed layer to form a discontinuous sacrificial seed layer. 前記導電材料を平坦化するステップをさらに含む、請求項１に記載の方法。   The method of claim 1, further comprising planarizing the conductive material. 前記めっきシード層が、化学蒸着（ＣＶＤ）または原子層付着（ＡＬＤ）技法によって付着される、請求項１に記載の方法。   The method of claim 1, wherein the plating seed layer is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques.
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US20080284019A1 (en) 2008-11-20
CN100481384C (en) 2009-04-22

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