CN109216265B - Method for forming metal diffusion barrier layer - Google Patents
Method for forming metal diffusion barrier layer Download PDFInfo
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- CN109216265B CN109216265B CN201811015325.1A CN201811015325A CN109216265B CN 109216265 B CN109216265 B CN 109216265B CN 201811015325 A CN201811015325 A CN 201811015325A CN 109216265 B CN109216265 B CN 109216265B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
Abstract
The invention provides a method for forming a metal diffusion barrier layer, which comprises the following steps of providing a substrate, wherein the substrate sequentially comprises a metal interconnection layer, an insulating layer, a low-K dielectric layer and a hard mask layer from bottom to top; further comprising the steps of: forming a through hole penetrating through the hard mask layer, the low-K dielectric layer and the insulating layer, exposing the metal interconnection layer at the bottom of the through hole, forming a groove at the top of the through hole, and positioning the bottom of the groove in the low-K dielectric layer; forming a first metal layer on the hard mask layer, the hole wall and the hole bottom of the through hole, and the groove wall and the groove bottom of the groove; reacting the wall of the through hole, the first metal layer on the wall and the bottom of the groove with the low-K dielectric layer to form an alloy barrier layer; forming a metal seed layer on the alloy barrier layer and the surface of the residual first metal layer; and filling metal in the groove and the through hole. The method has the beneficial effects that the alloy barrier layer is formed before the metal seed layer is deposited, so that copper is more effectively prevented from being diffused before the barrier layer is formed.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a copper diffusion barrier layer.
Background
The metal interconnection layer is a structure for interconnecting mutually isolated elements in an integrated circuit into a required circuit according to a certain requirement, the problem that metal materials diffuse into a dielectric layer can occur in the metal interconnection layer process in the prior art, so that the metal interconnection layer has defects, at present, a TaN/Ta double-layer structure is usually deposited by adopting a PVD method to be used as a metal diffusion barrier layer, or an ALD TaN + PVD Ta double-layer structure is used as a metal diffusion barrier layer, and the two methods can lead the contact resistance value in a through hole to be higher, and lead the step coverage capability of PVD (physical vapor deposition) to be poorer.
Disclosure of Invention
In view of the above problems in the prior art, a method for forming a metal diffusion barrier layer is provided to more effectively prevent diffusion of metal before formation of the barrier layer by forming an alloy barrier layer before deposition of a metal seed layer.
A method for forming a metal diffusion barrier layer is provided, wherein a substrate is provided, and the substrate sequentially comprises a metal interconnection layer, an insulating layer, a low-K dielectric layer and a hard mask layer from bottom to top;
further comprising the steps of:
step 1: forming a through hole penetrating through the hard mask layer, the low-K dielectric layer and the insulating layer, exposing the metal interconnection layer at the bottom of the through hole, forming a groove at the top of the through hole, and positioning the bottom of the groove in the low-K dielectric layer;
step 2: forming a first metal layer on the hard mask layer, the hole wall and the hole bottom of the through hole, and the groove wall and the groove bottom of the groove;
and step 3: reacting the wall of the through hole, the first metal layer on the wall and the bottom of the groove with the low-K dielectric layer to form an alloy barrier layer;
and 4, step 4: forming a metal seed layer on the alloy barrier layer and the surface of the residual first metal layer;
and 5: and filling metal in the groove and the through hole.
Preferably, the method of forming a metal diffusion barrier layer, wherein the first metal layer is manganese metal; and/or
The low-K dielectric layer is made of silicon oxide; and/or
The alloy barrier layer is made of Mn-Si-O.
Preferably, the method of forming a metal diffusion barrier layer, wherein the thickness of the first metal layer is not less than 1 nm.
Preferably, the method for forming the metal diffusion barrier layer is chemical vapor deposition.
Preferably, the method for forming the metal diffusion barrier layer, wherein the first metal layer on the wall of the via hole, the wall of the trench and the bottom of the trench reacts with the low-K dielectric layer to form the alloy barrier layer in step 3 by annealing.
Preferably, the method for forming the metal diffusion barrier layer is characterized in that the annealing temperature in the step 3 is between 300 and 400 ℃; and/or an annealing time between 5 minutes and 20 minutes.
Preferably, the method for forming a metal diffusion barrier layer further comprises, before step 4:
and when the wall of the through hole, the wall of the groove and the first metal layer at the bottom of the groove are completely reacted, forming a second metal layer on the alloy barrier layer and the surface of the rest first metal layer.
Preferably, the method of forming a metal diffusion barrier layer, wherein the thickness of the second metal layer is not less than 1 nm.
Preferably, the method for forming the metal diffusion barrier layer, wherein the second metal layer is one of manganese, tantalum, titanium, cobalt and ruthenium; and/or
The second metal layer is formed by chemical vapor deposition.
Preferably, the method for forming the metal diffusion barrier layer is a method in which the material of the metal seed layer in step 4 is pure copper or a copper alloy.
The technical scheme has the following advantages or beneficial effects: by forming the alloy barrier layer before depositing the metal seed layer, diffusion of metal before forming the barrier layer is more effectively prevented.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a schematic cross-sectional view of a composite structure of a method of forming a metal diffusion barrier of the present invention;
FIG. 2 is a schematic cross-sectional view corresponding to step 1 of an embodiment of a method of forming a metal diffusion barrier layer according to the invention;
FIG. 3 is a schematic cross-sectional view corresponding to step 2 of an embodiment of a method of forming a metal diffusion barrier layer according to the invention;
FIG. 4 is a schematic cross-sectional view corresponding to step 3 of an embodiment of the method of forming a metal diffusion barrier layer according to the invention;
FIG. 5 is a schematic cross-sectional view corresponding to step 4 of an embodiment of the method of forming a metal diffusion barrier layer according to the invention;
FIG. 6 is a schematic cross-sectional view corresponding to step 5 of an embodiment of the method of forming a metal diffusion barrier layer of the present invention;
FIG. 7 is an enlarged view of a portion of FIG. 6A illustrating a method of forming a metal diffusion barrier layer in accordance with the present invention;
fig. 8 is a schematic cross-sectional view of a second metal layer formed in an embodiment of the method for forming a metal diffusion barrier layer of the present invention.
Reference numerals: 10. via hole, 11, trench, 20, substrate, 21, metal interconnection layer, 22, insulating layer, 23, low-K dielectric layer, 24, hard mask layer, 31, first metal layer, 32, alloy barrier layer, 331, second metal layer, 332, metal seed layer, 34, metal layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
A method for forming a metal diffusion barrier layer is an improvement of a metal interconnection process, as shown in fig. 1 to 7, and fig. 1 to 6 are schematic cross-sectional views corresponding to respective steps in the method for forming a metal diffusion barrier layer provided by the present invention, as shown in fig. 1, a substrate 20 is provided first, and the substrate 20 sequentially includes a metal interconnection layer 21, an insulating layer 22, a low-K dielectric layer 23 and a hard mask layer 24 from bottom to top, and further includes the following steps:
step 1: forming a through hole 10 penetrating through the hard mask layer 24, the low-K dielectric layer 23 and the insulating layer 22 on the substrate, exposing the metal interconnection layer 21 at the bottom of the through hole 10, and forming a trench 11 at the top of the through hole 10, wherein the bottom of the trench 11 is located in the low-K dielectric layer 23; the cross-section of the composite structure after this step is completed is shown in fig. 2; it should be noted that the content of the "and" connection in this step is not limited by the existing order, that is, the order of forming the via 10 and forming the trench 11 is not limited, and the via 10 may be formed first and then the trench 11 may be formed, or the trench 11 may be formed first and then the via 10 may be formed. Since the formation of a damascene structure having via holes and trenches is a conventional technique in the art, a detailed description of the formation method is omitted.
Step 2: forming a first metal layer 31 on the hard mask layer 24, the hole wall and the hole bottom of the through hole 10, and the groove wall and the groove bottom of the groove 11; the cross-section of the composite structure after this step is completed is shown in figure 3.
And step 3: the first metal layer 31 on the wall of the via 10 and on the walls and bottom of the trench 11 is reacted with the low-K dielectric layer 23 to form an alloy barrier layer 32. This step prevents the resistance in the via 10 from rising while performing the metal diffusion function by directly reacting the first metal layer 31 with the low-K dielectric layer 23 to form the alloy barrier layer 32, and the cross section of the composite structure after this step is completed is shown in fig. 4. And 4, step 4: forming a metal seed layer 332 on the alloy barrier layer 32 and the remaining surface of the first metal layer 31; the cross-section of the composite structure after this step is complete is shown in figure 5.
And 5: after the step of filling the trench 11 and the via hole 10 with metal, i.e. forming the metal layer 34, the cross section of the composite structure is shown in fig. 6, and it should be noted that the metal of the metal layer 34 is the same as the metal of the metal seed layer 332, and is metal copper.
On the basis of the technical scheme, the redundant metal on the surface of the substrate can be removed through a polishing process.
As an alternative embodiment, the above polishing process may be achieved by CMP (Chemical-mechanical polishing).
As an alternative embodiment, the first metal layer 31 may employ manganese metal; furthermore, the material of the low-K dielectric layer 23 may be silicon oxide, and in step 3, the manganese metal of the first metal layer 31 and the silicon oxide material of the low-K dielectric layer 23 may react to form Mn-Si-O, i.e., the material of the alloy barrier layer 32 is Mn-Si-O.
In the above embodiment, the manganese metal of the first metal layer 31 and the silicon oxide material of the low-K dielectric layer 23 may react to form Mn-Si-O in step 3 through an annealing process, wherein the Mn-Si-O may be formed by reacting the manganese metal with the silicon oxide through controlling the annealing conditions, i.e., the annealing temperature and the annealing time.
Further, in the above-described embodiment, the thickness of the first metal layer 31 is not less than 1 nm.
Further, in the above embodiments, the method of forming the first metal layer 31 may employ chemical vapor deposition.
Further, in the above embodiment, the first metal layer 31 on the wall of the via 10, and on the walls and bottom of the trench 11, and the low-K dielectric layer 23 react to form the alloy barrier layer 32 by annealing in step 3. Wherein, as an optional embodiment, the annealing temperature can be controlled between 300 ℃ and 400 ℃; further alternatively, the annealing time may be controlled between 5 minutes and 20 minutes.
Further, in the above embodiment, before step 4, the method further includes:
when the wall of the via 10 and the first metal layer 31 on the wall and bottom of the trench 11 are fully reacted, a second metal layer 331 may be formed on the surface of the alloy barrier layer 32 and the remaining first metal layer 31, and the cross-section of the composite structure after this step is completed is shown in fig. 8.
When the thickness of the first metal layer 31 is greater than 2nm, judging whether the hole wall of the through hole 10 and the first metal layer 31 on the groove wall and the groove bottom of the groove 11 completely react in the annealing process, if so, forming a second metal layer 331 on the surface of the alloy barrier layer 32 and the rest of the first metal layer 31, wherein the second metal layer 331 is used for enhancing the bonding force between the alloy barrier layer 32 and the metal seed layer 332; if the first metal layer 31 is not fully reacted, the second metal layer 331 does not have to be deposited.
Further, in the above embodiment, the thickness of the second metal layer 331 is not less than 1 nm.
Further, in the above embodiment, the second metal layer 331 is one of manganese, tantalum, titanium, cobalt, and ruthenium.
Further, in the above embodiment, the second metal layer 331 is formed by chemical vapor deposition.
Further, in the above embodiment, the material of the metal seed layer 332 in step 4 is pure copper or a copper alloy. Therefore, the sequence of forming the barrier layer and copper diffusion is not required to be considered, the operation is simpler, and the copper diffusion is more effectively avoided before the barrier layer is formed.
Further, in the above embodiment, step 5 may use an electroplating process to complete the metal filling.
The invention has the advantages that the Mn-Si-O structure is adopted as the alloy barrier layer 32, so that the contact resistance value in the through hole 10 can be effectively reduced, and further, the alloy barrier layer 32 is formed before the metal seed layer 332 is deposited, so that the copper is more effectively prevented from being diffused before the barrier layer is formed.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. A method for forming a metal diffusion barrier layer is characterized in that a substrate is provided, and the substrate sequentially comprises a metal interconnection layer, an insulating layer, a low-K dielectric layer and a hard mask layer from bottom to top;
further comprising the steps of:
step 1: forming a through hole penetrating through the hard mask layer, the low-K dielectric layer and the insulating layer, wherein the metal interconnection layer is exposed at the bottom of the through hole, a groove is formed at the top of the through hole, and the bottom of the groove is positioned in the low-K dielectric layer;
step 2: forming a first metal layer on the hard mask layer, the hole wall and the hole bottom of the through hole, and the groove wall and the groove bottom of the groove;
and step 3: reacting the wall of the through hole, the first metal layer on the wall and the bottom of the groove with the low-K dielectric layer to form an alloy barrier layer;
and 4, step 4: forming a metal seed layer on the alloy barrier layer and the surface of the rest first metal layer;
and 5: filling metal in the groove and the through hole;
before the step 4, the method further comprises the following steps:
judging whether the hole wall of the through hole, the groove wall of the groove and the first metal layer at the groove bottom completely react or not:
if the reaction is complete, forming a second metal layer on the alloy barrier layer and the surface of the rest first metal layer;
if not, the second metal layer need not be deposited.
2. The method of forming a metal diffusion barrier of claim 1 wherein said first metal layer is manganese metal; and/or
The low-K dielectric layer is made of silicon oxide; and/or
The alloy barrier layer is made of Mn-Si-O.
3. The method of forming a metal diffusion barrier of claim 1 wherein said first metal layer has a thickness of not less than 1 nm.
4. The method of forming a metal diffusion barrier of claim 1 wherein the method of forming said first metal layer is chemical vapor deposition.
5. The method of forming a metal diffusion barrier layer of claim 1 wherein said annealing in step 3 causes said first metal layer on the walls of said via and on the walls and bottom of said trench to react with said low K dielectric layer to form an alloy barrier layer.
6. The method of forming a metal diffusion barrier of claim 5 wherein the annealing temperature in step 3 is between 300 degrees celsius and 400 degrees celsius; and/or an annealing time between 5 minutes and 20 minutes.
7. The method of forming a metal diffusion barrier of claim 1 wherein said second metal layer has a thickness of not less than 1 nm.
8. The method of forming a metal diffusion barrier of claim 1 wherein said second metal layer is one of manganese, tantalum, titanium, cobalt and ruthenium; and/or
The second metal layer is formed by chemical vapor deposition.
9. The method for forming a metal diffusion barrier of claim 1 wherein the material of the metal seed layer in step 4 is pure copper or a copper alloy.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427040A (en) * | 2011-07-01 | 2012-04-25 | 上海华力微电子有限公司 | Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer |
| CN102446812A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnecting method |
| CN105575798A (en) * | 2014-10-29 | 2016-05-11 | 应用材料公司 | System and method for removing contamination from surface of seed layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4236201B2 (en) * | 2005-08-30 | 2009-03-11 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP2008047719A (en) * | 2006-08-17 | 2008-02-28 | Sony Corp | Method for manufacturing semiconductor device |
| CN103606532A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method for improving filling capability of copper interconnection trench |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446812A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnecting method |
| CN102427040A (en) * | 2011-07-01 | 2012-04-25 | 上海华力微电子有限公司 | Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer |
| CN105575798A (en) * | 2014-10-29 | 2016-05-11 | 应用材料公司 | System and method for removing contamination from surface of seed layer |
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