TW200610455A - Single row bond pad arrangement - Google Patents
Single row bond pad arrangementInfo
- Publication number
- TW200610455A TW200610455A TW094113432A TW94113432A TW200610455A TW 200610455 A TW200610455 A TW 200610455A TW 094113432 A TW094113432 A TW 094113432A TW 94113432 A TW94113432 A TW 94113432A TW 200610455 A TW200610455 A TW 200610455A
- Authority
- TW
- Taiwan
- Prior art keywords
- package
- pads
- die
- chip
- accept
- Prior art date
Links
Classifications
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/835,212 US20050245062A1 (en) | 2004-04-29 | 2004-04-29 | Single row bond pad arrangement |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200610455A true TW200610455A (en) | 2006-03-16 |
Family
ID=34967037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094113432A TW200610455A (en) | 2004-04-29 | 2005-04-27 | Single row bond pad arrangement |
Country Status (7)
Country | Link |
---|---|
US (1) | US20050245062A1 (zh) |
JP (1) | JP2007535821A (zh) |
KR (1) | KR20070053660A (zh) |
CN (1) | CN1998078A (zh) |
DE (1) | DE112005000980T5 (zh) |
TW (1) | TW200610455A (zh) |
WO (1) | WO2005112115A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7721238B2 (en) * | 2004-09-22 | 2010-05-18 | Digi International Inc. | Method and apparatus for configurable printed circuit board circuit layout pattern |
US7667321B2 (en) * | 2007-03-12 | 2010-02-23 | Agere Systems Inc. | Wire bonding method and related device for high-frequency applications |
JP6541991B2 (ja) * | 2015-03-04 | 2019-07-10 | エイブリック株式会社 | 半導体素子および半導体装置 |
CN114442010A (zh) * | 2020-10-31 | 2022-05-06 | 迈来芯电子科技有限公司 | 电流传感器*** |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2859360B2 (ja) * | 1990-02-27 | 1999-02-17 | 株式会社日立製作所 | 半導体装置、半導体装置の製造方法及び半導体装置の実装構造 |
JP2634516B2 (ja) * | 1991-10-15 | 1997-07-30 | 三菱電機株式会社 | 反転型icの製造方法、反転型ic、icモジュール |
JPH0637136A (ja) * | 1992-05-22 | 1994-02-10 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
EP0595021A1 (en) * | 1992-10-28 | 1994-05-04 | International Business Machines Corporation | Improved lead frame package for electronic devices |
US5567655A (en) * | 1993-05-05 | 1996-10-22 | Lsi Logic Corporation | Method for forming interior bond pads having zig-zag linear arrangement |
US5453583A (en) * | 1993-05-05 | 1995-09-26 | Lsi Logic Corporation | Interior bond pad arrangements for alleviating thermal stresses |
JP2972486B2 (ja) * | 1993-06-10 | 1999-11-08 | 日本電気アイシーマイコンシステム株式会社 | 半導体装置 |
JP2647001B2 (ja) * | 1994-05-31 | 1997-08-27 | 日本電気株式会社 | テープキャリアならびに半導体デバイスの実装構造およびその製造方法 |
US5719436A (en) * | 1995-03-13 | 1998-02-17 | Intel Corporation | Package housing multiple semiconductor dies |
JPH0927512A (ja) * | 1995-07-10 | 1997-01-28 | Mitsubishi Electric Corp | 半導体装置 |
US5637916A (en) * | 1996-02-02 | 1997-06-10 | National Semiconductor Corporation | Carrier based IC packaging arrangement |
US6140708A (en) * | 1996-05-17 | 2000-10-31 | National Semiconductor Corporation | Chip scale package and method for manufacture thereof |
JP2871608B2 (ja) * | 1996-08-02 | 1999-03-17 | 日本電気株式会社 | 半導体記憶装置及びその製造方法 |
US6064116A (en) * | 1997-06-06 | 2000-05-16 | Micron Technology, Inc. | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
JP2970755B2 (ja) * | 1997-12-01 | 1999-11-02 | 日本電気株式会社 | 半導体装置 |
US6351040B1 (en) * | 1998-01-22 | 2002-02-26 | Micron Technology, Inc. | Method and apparatus for implementing selected functionality on an integrated circuit device |
KR100259359B1 (ko) * | 1998-02-10 | 2000-06-15 | 김영환 | 반도체 패키지용 기판 및 반도체 패키지, 그리고 그 제조방법 |
US6075710A (en) * | 1998-02-11 | 2000-06-13 | Express Packaging Systems, Inc. | Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips |
US6414391B1 (en) * | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
US6091140A (en) * | 1998-10-23 | 2000-07-18 | Texas Instruments Incorporated | Thin chip-size integrated circuit package |
US6437436B2 (en) * | 2000-01-20 | 2002-08-20 | Ang Technologies Inc. | Integrated circuit chip package with test points |
US6531784B1 (en) * | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
JP2003258178A (ja) * | 2002-02-27 | 2003-09-12 | Sanyo Electric Co Ltd | 半導体装置 |
JP2003258179A (ja) * | 2002-02-28 | 2003-09-12 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US7276802B2 (en) * | 2002-04-15 | 2007-10-02 | Micron Technology, Inc. | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
US7323767B2 (en) * | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
-
2004
- 2004-04-29 US US10/835,212 patent/US20050245062A1/en not_active Abandoned
-
2005
- 2005-04-25 KR KR1020067025056A patent/KR20070053660A/ko not_active Application Discontinuation
- 2005-04-25 JP JP2007510890A patent/JP2007535821A/ja active Pending
- 2005-04-25 WO PCT/US2005/014285 patent/WO2005112115A1/en active Application Filing
- 2005-04-25 DE DE112005000980T patent/DE112005000980T5/de not_active Withdrawn
- 2005-04-25 CN CNA2005800183529A patent/CN1998078A/zh active Pending
- 2005-04-27 TW TW094113432A patent/TW200610455A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
JP2007535821A (ja) | 2007-12-06 |
US20050245062A1 (en) | 2005-11-03 |
WO2005112115A1 (en) | 2005-11-24 |
DE112005000980T5 (de) | 2007-03-29 |
CN1998078A (zh) | 2007-07-11 |
KR20070053660A (ko) | 2007-05-25 |
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